1 /*-
2 * Copyright (c) 1996, by Steve Passe
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
28
29 #include "opt_apic.h"
30 #include "opt_cpu.h"
31 #include "opt_kstack_pages.h"
32 #include "opt_mp_watchdog.h"
33 #include "opt_pmap.h"
34 #include "opt_sched.h"
35 #include "opt_smp.h"
36
37 #if !defined(lint)
38 #if !defined(SMP)
39 #error How did you get here?
40 #endif
41
42 #ifndef DEV_APIC
43 #error The apic device is required for SMP, add "device apic" to your config file.
44 #endif
45 #if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT)
46 #error SMP not supported with CPU_DISABLE_CMPXCHG
47 #endif
48 #endif /* not lint */
49
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/bus.h>
53 #include <sys/cons.h> /* cngetc() */
54 #ifdef GPROF
55 #include <sys/gmon.h>
56 #endif
57 #include <sys/kernel.h>
58 #include <sys/ktr.h>
59 #include <sys/lock.h>
60 #include <sys/malloc.h>
61 #include <sys/memrange.h>
62 #include <sys/mutex.h>
63 #include <sys/pcpu.h>
64 #include <sys/proc.h>
65 #include <sys/sched.h>
66 #include <sys/smp.h>
67 #include <sys/sysctl.h>
68
69 #include <vm/vm.h>
70 #include <vm/vm_param.h>
71 #include <vm/pmap.h>
72 #include <vm/vm_kern.h>
73 #include <vm/vm_extern.h>
74
75 #include <machine/apicreg.h>
76 #include <machine/cputypes.h>
77 #include <machine/mca.h>
78 #include <machine/md_var.h>
79 #include <machine/mp_watchdog.h>
80 #include <machine/pcb.h>
81 #include <machine/psl.h>
82 #include <machine/smp.h>
83 #include <machine/specialreg.h>
84
85 #define WARMBOOT_TARGET 0
86 #define WARMBOOT_OFF (KERNBASE + 0x0467)
87 #define WARMBOOT_SEG (KERNBASE + 0x0469)
88
89 #define CMOS_REG (0x70)
90 #define CMOS_DATA (0x71)
91 #define BIOS_RESET (0x0f)
92 #define BIOS_WARM (0x0a)
93
94 /*
95 * this code MUST be enabled here and in mpboot.s.
96 * it follows the very early stages of AP boot by placing values in CMOS ram.
97 * it NORMALLY will never be needed and thus the primitive method for enabling.
98 *
99 #define CHECK_POINTS
100 */
101
102 #if defined(CHECK_POINTS) && !defined(PC98)
103 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
104 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
105
106 #define CHECK_INIT(D); \
107 CHECK_WRITE(0x34, (D)); \
108 CHECK_WRITE(0x35, (D)); \
109 CHECK_WRITE(0x36, (D)); \
110 CHECK_WRITE(0x37, (D)); \
111 CHECK_WRITE(0x38, (D)); \
112 CHECK_WRITE(0x39, (D));
113
114 #define CHECK_PRINT(S); \
115 printf("%s: %d, %d, %d, %d, %d, %d\n", \
116 (S), \
117 CHECK_READ(0x34), \
118 CHECK_READ(0x35), \
119 CHECK_READ(0x36), \
120 CHECK_READ(0x37), \
121 CHECK_READ(0x38), \
122 CHECK_READ(0x39));
123
124 #else /* CHECK_POINTS */
125
126 #define CHECK_INIT(D)
127 #define CHECK_PRINT(S)
128 #define CHECK_WRITE(A, D)
129
130 #endif /* CHECK_POINTS */
131
132 /* lock region used by kernel profiling */
133 int mcount_lock;
134
135 int mp_naps; /* # of Applications processors */
136 int boot_cpu_id = -1; /* designated BSP */
137
138 extern struct pcpu __pcpu[];
139
140 /*
141 * CPU topology map datastructures for HTT.
142 */
143 static struct cpu_group mp_groups[MAXCPU];
144 static struct cpu_top mp_top;
145
146 /* AP uses this during bootstrap. Do not staticize. */
147 char *bootSTK;
148 static int bootAP;
149
150 /* Free these after use */
151 void *bootstacks[MAXCPU];
152
153 /* Hotwire a 0->4MB V==P mapping */
154 extern pt_entry_t *KPTphys;
155
156 struct pcb stoppcbs[MAXCPU];
157
158 /* Variables needed for SMP tlb shootdown. */
159 vm_offset_t smp_tlb_addr1;
160 vm_offset_t smp_tlb_addr2;
161 volatile int smp_tlb_wait;
162
163 #ifdef STOP_NMI
164 volatile cpumask_t ipi_nmi_pending;
165
166 static void ipi_nmi_selected(u_int32_t cpus);
167 #endif
168
169 #ifdef COUNT_IPIS
170 /* Interrupt counts. */
171 static u_long *ipi_preempt_counts[MAXCPU];
172 static u_long *ipi_ast_counts[MAXCPU];
173 u_long *ipi_invltlb_counts[MAXCPU];
174 u_long *ipi_invlrng_counts[MAXCPU];
175 u_long *ipi_invlpg_counts[MAXCPU];
176 u_long *ipi_invlcache_counts[MAXCPU];
177 u_long *ipi_rendezvous_counts[MAXCPU];
178 u_long *ipi_lazypmap_counts[MAXCPU];
179 #endif
180
181 /*
182 * Local data and functions.
183 */
184
185 #ifdef STOP_NMI
186 /*
187 * Provide an alternate method of stopping other CPUs. If another CPU has
188 * disabled interrupts the conventional STOP IPI will be blocked. This
189 * NMI-based stop should get through in that case.
190 */
191 static int stop_cpus_with_nmi = 1;
192 SYSCTL_INT(_debug, OID_AUTO, stop_cpus_with_nmi, CTLTYPE_INT | CTLFLAG_RW,
193 &stop_cpus_with_nmi, 0, "");
194 TUNABLE_INT("debug.stop_cpus_with_nmi", &stop_cpus_with_nmi);
195 #else
196 #define stop_cpus_with_nmi 0
197 #endif
198
199 static u_int logical_cpus;
200
201 /* used to hold the AP's until we are ready to release them */
202 static struct mtx ap_boot_mtx;
203
204 /* Set to 1 once we're ready to let the APs out of the pen. */
205 static volatile int aps_ready = 0;
206
207 /*
208 * Store data from cpu_add() until later in the boot when we actually setup
209 * the APs.
210 */
211 struct cpu_info {
212 int cpu_present:1;
213 int cpu_bsp:1;
214 int cpu_disabled:1;
215 int cpu_hyperthread:1;
216 } static cpu_info[MAX_APIC_ID + 1];
217 int cpu_apic_ids[MAXCPU];
218
219 /* Holds pending bitmap based IPIs per CPU */
220 static volatile u_int cpu_ipi_pending[MAXCPU];
221
222 static u_int boot_address;
223
224 static void assign_cpu_ids(void);
225 static void install_ap_tramp(void);
226 static void set_interrupt_apic_ids(void);
227 static int start_all_aps(void);
228 static int start_ap(int apic_id);
229 static void release_aps(void *dummy);
230
231 static int hlt_logical_cpus;
232 static u_int hyperthreading_cpus;
233 static cpumask_t hyperthreading_cpus_mask;
234 static int hyperthreading_allowed = 1;
235 static struct sysctl_ctx_list logical_cpu_clist;
236
237 static void
238 mem_range_AP_init(void)
239 {
240 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
241 mem_range_softc.mr_op->initAP(&mem_range_softc);
242 }
243
244 void
245 mp_topology(void)
246 {
247 struct cpu_group *group;
248 int apic_id;
249 int groups;
250 int cpu;
251
252 /* Build the smp_topology map. */
253 /* Nothing to do if there is no HTT support. */
254 if (hyperthreading_cpus <= 1)
255 return;
256 group = &mp_groups[0];
257 groups = 1;
258 for (cpu = 0, apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) {
259 if (!cpu_info[apic_id].cpu_present ||
260 cpu_info[apic_id].cpu_disabled)
261 continue;
262 /*
263 * If the current group has members and we're not a logical
264 * cpu, create a new group.
265 */
266 if (group->cg_count != 0 &&
267 (apic_id % hyperthreading_cpus) == 0) {
268 group++;
269 groups++;
270 }
271 group->cg_count++;
272 group->cg_mask |= 1 << cpu;
273 cpu++;
274 }
275
276 mp_top.ct_count = groups;
277 mp_top.ct_group = mp_groups;
278 smp_topology = &mp_top;
279 }
280
281
282 /*
283 * Calculate usable address in base memory for AP trampoline code.
284 */
285 u_int
286 mp_bootaddress(u_int basemem)
287 {
288
289 boot_address = trunc_page(basemem); /* round down to 4k boundary */
290 if ((basemem - boot_address) < bootMP_size)
291 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */
292
293 return boot_address;
294 }
295
296 void
297 cpu_add(u_int apic_id, char boot_cpu)
298 {
299
300 if (apic_id > MAX_APIC_ID) {
301 panic("SMP: APIC ID %d too high", apic_id);
302 return;
303 }
304 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
305 apic_id));
306 cpu_info[apic_id].cpu_present = 1;
307 if (boot_cpu) {
308 KASSERT(boot_cpu_id == -1,
309 ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
310 boot_cpu_id));
311 boot_cpu_id = apic_id;
312 cpu_info[apic_id].cpu_bsp = 1;
313 }
314 if (mp_ncpus < MAXCPU)
315 mp_ncpus++;
316 if (bootverbose)
317 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
318 "AP");
319 }
320
321 void
322 cpu_mp_setmaxid(void)
323 {
324
325 mp_maxid = MAXCPU - 1;
326 }
327
328 int
329 cpu_mp_probe(void)
330 {
331
332 /*
333 * Always record BSP in CPU map so that the mbuf init code works
334 * correctly.
335 */
336 all_cpus = 1;
337 if (mp_ncpus == 0) {
338 /*
339 * No CPUs were found, so this must be a UP system. Setup
340 * the variables to represent a system with a single CPU
341 * with an id of 0.
342 */
343 mp_ncpus = 1;
344 return (0);
345 }
346
347 /* At least one CPU was found. */
348 if (mp_ncpus == 1) {
349 /*
350 * One CPU was found, so this must be a UP system with
351 * an I/O APIC.
352 */
353 return (0);
354 }
355
356 /* At least two CPUs were found. */
357 return (1);
358 }
359
360 /*
361 * Initialize the IPI handlers and start up the AP's.
362 */
363 void
364 cpu_mp_start(void)
365 {
366 int i;
367 u_int threads_per_cache, p[4];
368
369 /* Initialize the logical ID to APIC ID table. */
370 for (i = 0; i < MAXCPU; i++) {
371 cpu_apic_ids[i] = -1;
372 cpu_ipi_pending[i] = 0;
373 }
374
375 /* Install an inter-CPU IPI for TLB invalidation */
376 setidt(IPI_INVLTLB, IDTVEC(invltlb),
377 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
378 setidt(IPI_INVLPG, IDTVEC(invlpg),
379 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
380 setidt(IPI_INVLRNG, IDTVEC(invlrng),
381 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
382
383 /* Install an inter-CPU IPI for cache invalidation. */
384 setidt(IPI_INVLCACHE, IDTVEC(invlcache),
385 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
386
387 /* Install an inter-CPU IPI for lazy pmap release */
388 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap),
389 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
390
391 /* Install an inter-CPU IPI for all-CPU rendezvous */
392 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous),
393 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
394
395 /* Install generic inter-CPU IPI handler */
396 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
397 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
398
399 /* Install an inter-CPU IPI for CPU stop/restart */
400 setidt(IPI_STOP, IDTVEC(cpustop),
401 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
402
403
404 /* Set boot_cpu_id if needed. */
405 if (boot_cpu_id == -1) {
406 boot_cpu_id = PCPU_GET(apic_id);
407 cpu_info[boot_cpu_id].cpu_bsp = 1;
408 } else
409 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
410 ("BSP's APIC ID doesn't match boot_cpu_id"));
411
412 /* Setup the initial logical CPUs info. */
413 logical_cpus = logical_cpus_mask = 0;
414 if (cpu_feature & CPUID_HTT)
415 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
416
417 /*
418 * Work out if hyperthreading is *really* enabled. This
419 * is made really ugly by the fact that processors lie: Dual
420 * core processors claim to be hyperthreaded even when they're
421 * not, presumably because they want to be treated the same
422 * way as HTT with respect to per-cpu software licensing.
423 * At the time of writing (May 12, 2005) the only hyperthreaded
424 * cpus are from Intel, and Intel's dual-core processors can be
425 * identified via the "deterministic cache parameters" cpuid
426 * calls.
427 */
428 /*
429 * First determine if this is an Intel processor which claims
430 * to have hyperthreading support.
431 */
432 if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_INTEL) {
433 /*
434 * If the "deterministic cache parameters" cpuid calls
435 * are available, use them.
436 */
437 if (cpu_high >= 4) {
438 /* Ask the processor about the L1 cache. */
439 for (i = 0; i < 1; i++) {
440 cpuid_count(4, i, p);
441 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1;
442 if (hyperthreading_cpus < threads_per_cache)
443 hyperthreading_cpus = threads_per_cache;
444 if ((p[0] & 0x1f) == 0)
445 break;
446 }
447 }
448
449 /*
450 * If the deterministic cache parameters are not
451 * available, or if no caches were reported to exist,
452 * just accept what the HTT flag indicated.
453 */
454 if (hyperthreading_cpus == 0)
455 hyperthreading_cpus = logical_cpus;
456 }
457
458 assign_cpu_ids();
459
460 /* Start each Application Processor */
461 start_all_aps();
462
463 set_interrupt_apic_ids();
464
465 /* Last, setup the cpu topology now that we have probed CPUs */
466 mp_topology();
467 }
468
469
470 /*
471 * Print various information about the SMP system hardware and setup.
472 */
473 void
474 cpu_mp_announce(void)
475 {
476 const char *hyperthread;
477 int i;
478
479 /* List active CPUs first. */
480 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
481 for (i = 1; i < mp_ncpus; i++) {
482 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
483 hyperthread = "/HT";
484 else
485 hyperthread = "";
486 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
487 cpu_apic_ids[i]);
488 }
489
490 /* List disabled CPUs last. */
491 for (i = 0; i <= MAX_APIC_ID; i++) {
492 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
493 continue;
494 if (cpu_info[i].cpu_hyperthread)
495 hyperthread = "/HT";
496 else
497 hyperthread = "";
498 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
499 i);
500 }
501 }
502
503 /*
504 * AP CPU's call this to initialize themselves.
505 */
506 void
507 init_secondary(void)
508 {
509 struct pcpu *pc;
510 vm_offset_t addr;
511 int gsel_tss;
512 int x, myid;
513 u_int cr0;
514
515 /* bootAP is set in start_ap() to our ID. */
516 myid = bootAP;
517
518 /* Get per-cpu data */
519 pc = &__pcpu[myid];
520
521 /* prime data page for it to use */
522 pcpu_init(pc, myid, sizeof(struct pcpu));
523 pc->pc_apic_id = cpu_apic_ids[myid];
524 pc->pc_prvspace = pc;
525 pc->pc_curthread = 0;
526
527 gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
528 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
529
530 for (x = 0; x < NGDT; x++) {
531 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
532 }
533
534 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
535 r_gdt.rd_base = (int) &gdt[myid * NGDT];
536 lgdt(&r_gdt); /* does magic intra-segment return */
537
538 lidt(&r_idt);
539
540 lldt(_default_ldt);
541 PCPU_SET(currentldt, _default_ldt);
542
543 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
544 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
545 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
546 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
547 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
548 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
549 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
550 ltr(gsel_tss);
551
552 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd);
553
554 /*
555 * Set to a known state:
556 * Set by mpboot.s: CR0_PG, CR0_PE
557 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
558 */
559 cr0 = rcr0();
560 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
561 load_cr0(cr0);
562 CHECK_WRITE(0x38, 5);
563
564 /* Disable local APIC just to be sure. */
565 lapic_disable();
566
567 /* signal our startup to the BSP. */
568 mp_naps++;
569 CHECK_WRITE(0x39, 6);
570
571 /* Spin until the BSP releases the AP's. */
572 while (!aps_ready)
573 ia32_pause();
574
575 /* BSP may have changed PTD while we were waiting */
576 invltlb();
577 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE)
578 invlpg(addr);
579
580 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
581 lidt(&r_idt);
582 #endif
583
584 /* Initialize the PAT MSR if present. */
585 pmap_init_pat();
586
587 /* set up CPU registers and state */
588 cpu_setregs();
589
590 /* set up FPU state on the AP */
591 npxinit();
592
593 /* set up SSE registers */
594 enable_sse();
595
596 #ifdef PAE
597 /* Enable the PTE no-execute bit. */
598 if ((amd_feature & AMDID_NX) != 0) {
599 uint64_t msr;
600
601 msr = rdmsr(MSR_EFER) | EFER_NXE;
602 wrmsr(MSR_EFER, msr);
603 }
604 #endif
605
606 /* A quick check from sanity claus */
607 if (PCPU_GET(apic_id) != lapic_id()) {
608 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid));
609 printf("SMP: actual apic_id = %d\n", lapic_id());
610 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
611 panic("cpuid mismatch! boom!!");
612 }
613
614 /* Initialize curthread. */
615 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
616 PCPU_SET(curthread, PCPU_GET(idlethread));
617
618 mca_init();
619
620 mtx_lock_spin(&ap_boot_mtx);
621
622 /* Init local apic for irq's */
623 lapic_setup(1);
624
625 /* Set memory range attributes for this CPU to match the BSP */
626 mem_range_AP_init();
627
628 smp_cpus++;
629
630 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid));
631 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid));
632
633 /* Determine if we are a logical CPU. */
634 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0)
635 logical_cpus_mask |= PCPU_GET(cpumask);
636
637 /* Determine if we are a hyperthread. */
638 if (hyperthreading_cpus > 1 &&
639 PCPU_GET(apic_id) % hyperthreading_cpus != 0)
640 hyperthreading_cpus_mask |= PCPU_GET(cpumask);
641
642 /* Build our map of 'other' CPUs. */
643 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
644
645 if (bootverbose)
646 lapic_dump("AP");
647
648 if (smp_cpus == mp_ncpus) {
649 /* enable IPI's, tlb shootdown, freezes etc */
650 atomic_store_rel_int(&smp_started, 1);
651 smp_active = 1; /* historic */
652 }
653
654 mtx_unlock_spin(&ap_boot_mtx);
655
656 /* wait until all the AP's are up */
657 while (smp_started == 0)
658 ia32_pause();
659
660 /* enter the scheduler */
661 sched_throw(NULL);
662
663 panic("scheduler returned us to %s", __func__);
664 /* NOTREACHED */
665 }
666
667 /*******************************************************************
668 * local functions and data
669 */
670
671 /*
672 * We tell the I/O APIC code about all the CPUs we want to receive
673 * interrupts. If we don't want certain CPUs to receive IRQs we
674 * can simply not tell the I/O APIC code about them in this function.
675 * We also do not tell it about the BSP since it tells itself about
676 * the BSP internally to work with UP kernels and on UP machines.
677 */
678 static void
679 set_interrupt_apic_ids(void)
680 {
681 u_int i, apic_id;
682
683 for (i = 0; i < MAXCPU; i++) {
684 apic_id = cpu_apic_ids[i];
685 if (apic_id == -1)
686 continue;
687 if (cpu_info[apic_id].cpu_bsp)
688 continue;
689 if (cpu_info[apic_id].cpu_disabled)
690 continue;
691
692 /* Don't let hyperthreads service interrupts. */
693 if (hyperthreading_cpus > 1 &&
694 apic_id % hyperthreading_cpus != 0)
695 continue;
696
697 intr_add_cpu(i);
698 }
699 }
700
701 /*
702 * Assign logical CPU IDs to local APICs.
703 */
704 static void
705 assign_cpu_ids(void)
706 {
707 u_int i;
708
709 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
710 &hyperthreading_allowed);
711
712 /* Check for explicitly disabled CPUs. */
713 for (i = 0; i <= MAX_APIC_ID; i++) {
714 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
715 continue;
716
717 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
718 cpu_info[i].cpu_hyperthread = 1;
719 #if defined(SCHED_ULE)
720 /*
721 * Don't use HT CPU if it has been disabled by a
722 * tunable.
723 */
724 if (hyperthreading_allowed == 0) {
725 cpu_info[i].cpu_disabled = 1;
726 continue;
727 }
728 #endif
729 }
730
731 /* Don't use this CPU if it has been disabled by a tunable. */
732 if (resource_disabled("lapic", i)) {
733 cpu_info[i].cpu_disabled = 1;
734 continue;
735 }
736 }
737
738 /*
739 * Assign CPU IDs to local APIC IDs and disable any CPUs
740 * beyond MAXCPU. CPU 0 is always assigned to the BSP.
741 *
742 * To minimize confusion for userland, we attempt to number
743 * CPUs such that all threads and cores in a package are
744 * grouped together. For now we assume that the BSP is always
745 * the first thread in a package and just start adding APs
746 * starting with the BSP's APIC ID.
747 */
748 mp_ncpus = 1;
749 cpu_apic_ids[0] = boot_cpu_id;
750 for (i = boot_cpu_id + 1; i != boot_cpu_id;
751 i == MAX_APIC_ID ? i = 0 : i++) {
752 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
753 cpu_info[i].cpu_disabled)
754 continue;
755
756 if (mp_ncpus < MAXCPU) {
757 cpu_apic_ids[mp_ncpus] = i;
758 mp_ncpus++;
759 } else
760 cpu_info[i].cpu_disabled = 1;
761 }
762 KASSERT(mp_maxid >= mp_ncpus - 1,
763 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
764 mp_ncpus));
765 }
766
767 /*
768 * start each AP in our list
769 */
770 static int
771 start_all_aps(void)
772 {
773 #ifndef PC98
774 u_char mpbiosreason;
775 #endif
776 uintptr_t kptbase;
777 u_int32_t mpbioswarmvec;
778 int apic_id, cpu, i;
779
780 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
781
782 /* install the AP 1st level boot code */
783 install_ap_tramp();
784
785 /* save the current value of the warm-start vector */
786 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
787 #ifndef PC98
788 outb(CMOS_REG, BIOS_RESET);
789 mpbiosreason = inb(CMOS_DATA);
790 #endif
791
792 /* set up temporary P==V mapping for AP boot */
793 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
794 kptbase = (uintptr_t)(void *)KPTphys;
795 for (i = 0; i < NKPT; i++)
796 PTD[i] = (pd_entry_t)(PG_V | PG_RW |
797 ((kptbase + i * PAGE_SIZE) & PG_FRAME));
798 invltlb();
799
800 /* start each AP */
801 for (cpu = 1; cpu < mp_ncpus; cpu++) {
802 apic_id = cpu_apic_ids[cpu];
803
804 /* allocate and set up a boot stack data page */
805 bootstacks[cpu] = (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
806
807 /* setup a vector to our boot code */
808 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
809 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
810 #ifndef PC98
811 outb(CMOS_REG, BIOS_RESET);
812 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
813 #endif
814
815 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4;
816 bootAP = cpu;
817
818 /* attempt to start the Application Processor */
819 CHECK_INIT(99); /* setup checkpoints */
820 if (!start_ap(apic_id)) {
821 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id);
822 CHECK_PRINT("trace"); /* show checkpoints */
823 /* better panic as the AP may be running loose */
824 printf("panic y/n? [y] ");
825 if (cngetc() != 'n')
826 panic("bye-bye");
827 }
828 CHECK_PRINT("trace"); /* show checkpoints */
829
830 all_cpus |= (1 << cpu); /* record AP in CPU map */
831 }
832
833 /* build our map of 'other' CPUs */
834 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask));
835
836 /* restore the warmstart vector */
837 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
838
839 #ifndef PC98
840 outb(CMOS_REG, BIOS_RESET);
841 outb(CMOS_DATA, mpbiosreason);
842 #endif
843
844 /* Undo V==P hack from above */
845 for (i = 0; i < NKPT; i++)
846 PTD[i] = 0;
847 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1);
848
849 /* number of APs actually started */
850 return mp_naps;
851 }
852
853 /*
854 * load the 1st level AP boot code into base memory.
855 */
856
857 /* targets for relocation */
858 extern void bigJump(void);
859 extern void bootCodeSeg(void);
860 extern void bootDataSeg(void);
861 extern void MPentry(void);
862 extern u_int MP_GDT;
863 extern u_int mp_gdtbase;
864
865 static void
866 install_ap_tramp(void)
867 {
868 int x;
869 int size = *(int *) ((u_long) & bootMP_size);
870 vm_offset_t va = boot_address + KERNBASE;
871 u_char *src = (u_char *) ((u_long) bootMP);
872 u_char *dst = (u_char *) va;
873 u_int boot_base = (u_int) bootMP;
874 u_int8_t *dst8;
875 u_int16_t *dst16;
876 u_int32_t *dst32;
877
878 KASSERT (size <= PAGE_SIZE,
879 ("'size' do not fit into PAGE_SIZE, as expected."));
880 pmap_kenter(va, boot_address);
881 pmap_invalidate_page (kernel_pmap, va);
882 for (x = 0; x < size; ++x)
883 *dst++ = *src++;
884
885 /*
886 * modify addresses in code we just moved to basemem. unfortunately we
887 * need fairly detailed info about mpboot.s for this to work. changes
888 * to mpboot.s might require changes here.
889 */
890
891 /* boot code is located in KERNEL space */
892 dst = (u_char *) va;
893
894 /* modify the lgdt arg */
895 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
896 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base);
897
898 /* modify the ljmp target for MPentry() */
899 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
900 *dst32 = ((u_int) MPentry - KERNBASE);
901
902 /* modify the target for boot code segment */
903 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
904 dst8 = (u_int8_t *) (dst16 + 1);
905 *dst16 = (u_int) boot_address & 0xffff;
906 *dst8 = ((u_int) boot_address >> 16) & 0xff;
907
908 /* modify the target for boot data segment */
909 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
910 dst8 = (u_int8_t *) (dst16 + 1);
911 *dst16 = (u_int) boot_address & 0xffff;
912 *dst8 = ((u_int) boot_address >> 16) & 0xff;
913 }
914
915 /*
916 * This function starts the AP (application processor) identified
917 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
918 * to accomplish this. This is necessary because of the nuances
919 * of the different hardware we might encounter. It isn't pretty,
920 * but it seems to work.
921 */
922 static int
923 start_ap(int apic_id)
924 {
925 int vector, ms;
926 int cpus;
927
928 /* calculate the vector */
929 vector = (boot_address >> 12) & 0xff;
930
931 /* used as a watchpoint to signal AP startup */
932 cpus = mp_naps;
933
934 /*
935 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
936 * and running the target CPU. OR this INIT IPI might be latched (P5
937 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
938 * ignored.
939 */
940
941 /* do an INIT IPI: assert RESET */
942 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
943 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
944
945 /* wait for pending status end */
946 lapic_ipi_wait(-1);
947
948 /* do an INIT IPI: deassert RESET */
949 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
950 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
951
952 /* wait for pending status end */
953 DELAY(10000); /* wait ~10mS */
954 lapic_ipi_wait(-1);
955
956 /*
957 * next we do a STARTUP IPI: the previous INIT IPI might still be
958 * latched, (P5 bug) this 1st STARTUP would then terminate
959 * immediately, and the previously started INIT IPI would continue. OR
960 * the previous INIT IPI has already run. and this STARTUP IPI will
961 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
962 * will run.
963 */
964
965 /* do a STARTUP IPI */
966 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
967 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
968 vector, apic_id);
969 lapic_ipi_wait(-1);
970 DELAY(200); /* wait ~200uS */
971
972 /*
973 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
974 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
975 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
976 * recognized after hardware RESET or INIT IPI.
977 */
978
979 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
980 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
981 vector, apic_id);
982 lapic_ipi_wait(-1);
983 DELAY(200); /* wait ~200uS */
984
985 /* Wait up to 5 seconds for it to start. */
986 for (ms = 0; ms < 5000; ms++) {
987 if (mp_naps > cpus)
988 return 1; /* return SUCCESS */
989 DELAY(1000);
990 }
991 return 0; /* return FAILURE */
992 }
993
994 #ifdef COUNT_XINVLTLB_HITS
995 u_int xhits_gbl[MAXCPU];
996 u_int xhits_pg[MAXCPU];
997 u_int xhits_rng[MAXCPU];
998 SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
999 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
1000 sizeof(xhits_gbl), "IU", "");
1001 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
1002 sizeof(xhits_pg), "IU", "");
1003 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
1004 sizeof(xhits_rng), "IU", "");
1005
1006 u_int ipi_global;
1007 u_int ipi_page;
1008 u_int ipi_range;
1009 u_int ipi_range_size;
1010 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
1011 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
1012 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
1013 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
1014 0, "");
1015
1016 u_int ipi_masked_global;
1017 u_int ipi_masked_page;
1018 u_int ipi_masked_range;
1019 u_int ipi_masked_range_size;
1020 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
1021 &ipi_masked_global, 0, "");
1022 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
1023 &ipi_masked_page, 0, "");
1024 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
1025 &ipi_masked_range, 0, "");
1026 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
1027 &ipi_masked_range_size, 0, "");
1028 #endif /* COUNT_XINVLTLB_HITS */
1029
1030 /*
1031 * Flush the TLB on all other CPU's
1032 */
1033 static void
1034 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1035 {
1036 u_int ncpu;
1037
1038 ncpu = mp_ncpus - 1; /* does not shootdown self */
1039 if (ncpu < 1)
1040 return; /* no other cpus */
1041 if (!(read_eflags() & PSL_I))
1042 panic("%s: interrupts disabled", __func__);
1043 mtx_lock_spin(&smp_ipi_mtx);
1044 smp_tlb_addr1 = addr1;
1045 smp_tlb_addr2 = addr2;
1046 atomic_store_rel_int(&smp_tlb_wait, 0);
1047 ipi_all_but_self(vector);
1048 while (smp_tlb_wait < ncpu)
1049 ia32_pause();
1050 mtx_unlock_spin(&smp_ipi_mtx);
1051 }
1052
1053 static void
1054 smp_targeted_tlb_shootdown(u_int mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
1055 {
1056 int ncpu, othercpus;
1057
1058 othercpus = mp_ncpus - 1;
1059 if (mask == (u_int)-1) {
1060 ncpu = othercpus;
1061 if (ncpu < 1)
1062 return;
1063 } else {
1064 mask &= ~PCPU_GET(cpumask);
1065 if (mask == 0)
1066 return;
1067 ncpu = bitcount32(mask);
1068 if (ncpu > othercpus) {
1069 /* XXX this should be a panic offence */
1070 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n",
1071 ncpu, othercpus);
1072 ncpu = othercpus;
1073 }
1074 /* XXX should be a panic, implied by mask == 0 above */
1075 if (ncpu < 1)
1076 return;
1077 }
1078 if (!(read_eflags() & PSL_I))
1079 panic("%s: interrupts disabled", __func__);
1080 mtx_lock_spin(&smp_ipi_mtx);
1081 smp_tlb_addr1 = addr1;
1082 smp_tlb_addr2 = addr2;
1083 atomic_store_rel_int(&smp_tlb_wait, 0);
1084 if (mask == (u_int)-1)
1085 ipi_all_but_self(vector);
1086 else
1087 ipi_selected(mask, vector);
1088 while (smp_tlb_wait < ncpu)
1089 ia32_pause();
1090 mtx_unlock_spin(&smp_ipi_mtx);
1091 }
1092
1093 void
1094 smp_cache_flush(void)
1095 {
1096
1097 if (smp_started)
1098 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
1099 }
1100
1101 void
1102 smp_invltlb(void)
1103 {
1104
1105 if (smp_started) {
1106 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
1107 #ifdef COUNT_XINVLTLB_HITS
1108 ipi_global++;
1109 #endif
1110 }
1111 }
1112
1113 void
1114 smp_invlpg(vm_offset_t addr)
1115 {
1116
1117 if (smp_started) {
1118 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
1119 #ifdef COUNT_XINVLTLB_HITS
1120 ipi_page++;
1121 #endif
1122 }
1123 }
1124
1125 void
1126 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
1127 {
1128
1129 if (smp_started) {
1130 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
1131 #ifdef COUNT_XINVLTLB_HITS
1132 ipi_range++;
1133 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
1134 #endif
1135 }
1136 }
1137
1138 void
1139 smp_masked_invltlb(u_int mask)
1140 {
1141
1142 if (smp_started) {
1143 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
1144 #ifdef COUNT_XINVLTLB_HITS
1145 ipi_masked_global++;
1146 #endif
1147 }
1148 }
1149
1150 void
1151 smp_masked_invlpg(u_int mask, vm_offset_t addr)
1152 {
1153
1154 if (smp_started) {
1155 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
1156 #ifdef COUNT_XINVLTLB_HITS
1157 ipi_masked_page++;
1158 #endif
1159 }
1160 }
1161
1162 void
1163 smp_masked_invlpg_range(u_int mask, vm_offset_t addr1, vm_offset_t addr2)
1164 {
1165
1166 if (smp_started) {
1167 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
1168 #ifdef COUNT_XINVLTLB_HITS
1169 ipi_masked_range++;
1170 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
1171 #endif
1172 }
1173 }
1174
1175 void
1176 ipi_bitmap_handler(struct trapframe frame)
1177 {
1178 int cpu = PCPU_GET(cpuid);
1179 u_int ipi_bitmap;
1180
1181 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
1182
1183 if (ipi_bitmap & (1 << IPI_PREEMPT)) {
1184 struct thread *running_thread = curthread;
1185 #ifdef COUNT_IPIS
1186 (*ipi_preempt_counts[cpu])++;
1187 #endif
1188 thread_lock(running_thread);
1189 if (running_thread->td_critnest > 1)
1190 running_thread->td_owepreempt = 1;
1191 else
1192 mi_switch(SW_INVOL | SW_PREEMPT, NULL);
1193 thread_unlock(running_thread);
1194 }
1195
1196 if (ipi_bitmap & (1 << IPI_AST)) {
1197 #ifdef COUNT_IPIS
1198 (*ipi_ast_counts[cpu])++;
1199 #endif
1200 /* Nothing to do for AST */
1201 }
1202 }
1203
1204 /*
1205 * send an IPI to a set of cpus.
1206 */
1207 void
1208 ipi_selected(u_int32_t cpus, u_int ipi)
1209 {
1210 int cpu;
1211 u_int bitmap = 0;
1212 u_int old_pending;
1213 u_int new_pending;
1214
1215 if (IPI_IS_BITMAPED(ipi)) {
1216 bitmap = 1 << ipi;
1217 ipi = IPI_BITMAP_VECTOR;
1218 }
1219
1220 #ifdef STOP_NMI
1221 if (ipi == IPI_STOP && stop_cpus_with_nmi) {
1222 ipi_nmi_selected(cpus);
1223 return;
1224 }
1225 #endif
1226 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi);
1227 while ((cpu = ffs(cpus)) != 0) {
1228 cpu--;
1229 cpus &= ~(1 << cpu);
1230
1231 KASSERT(cpu_apic_ids[cpu] != -1,
1232 ("IPI to non-existent CPU %d", cpu));
1233
1234 if (bitmap) {
1235 do {
1236 old_pending = cpu_ipi_pending[cpu];
1237 new_pending = old_pending | bitmap;
1238 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending));
1239
1240 if (old_pending)
1241 continue;
1242 }
1243
1244 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
1245 }
1246
1247 }
1248
1249 /*
1250 * send an IPI INTerrupt containing 'vector' to all CPUs, including myself
1251 */
1252 void
1253 ipi_all(u_int ipi)
1254 {
1255
1256 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) {
1257 ipi_selected(all_cpus, ipi);
1258 return;
1259 }
1260 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1261 lapic_ipi_vectored(ipi, APIC_IPI_DEST_ALL);
1262 }
1263
1264 /*
1265 * send an IPI to all CPUs EXCEPT myself
1266 */
1267 void
1268 ipi_all_but_self(u_int ipi)
1269 {
1270
1271 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) {
1272 ipi_selected(PCPU_GET(other_cpus), ipi);
1273 return;
1274 }
1275 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1276 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
1277 }
1278
1279 /*
1280 * send an IPI to myself
1281 */
1282 void
1283 ipi_self(u_int ipi)
1284 {
1285
1286 if (IPI_IS_BITMAPED(ipi) || (ipi == IPI_STOP && stop_cpus_with_nmi)) {
1287 ipi_selected(PCPU_GET(cpumask), ipi);
1288 return;
1289 }
1290 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
1291 lapic_ipi_vectored(ipi, APIC_IPI_DEST_SELF);
1292 }
1293
1294 #ifdef STOP_NMI
1295 /*
1296 * send NMI IPI to selected CPUs
1297 */
1298
1299 #define BEFORE_SPIN 1000000
1300
1301 void
1302 ipi_nmi_selected(u_int32_t cpus)
1303 {
1304 int cpu;
1305 register_t icrlo;
1306
1307 icrlo = APIC_DELMODE_NMI | APIC_DESTMODE_PHY | APIC_LEVEL_ASSERT
1308 | APIC_TRIGMOD_EDGE;
1309
1310 CTR2(KTR_SMP, "%s: cpus: %x nmi", __func__, cpus);
1311
1312 atomic_set_int(&ipi_nmi_pending, cpus);
1313
1314 while ((cpu = ffs(cpus)) != 0) {
1315 cpu--;
1316 cpus &= ~(1 << cpu);
1317
1318 KASSERT(cpu_apic_ids[cpu] != -1,
1319 ("IPI NMI to non-existent CPU %d", cpu));
1320
1321 /* Wait for an earlier IPI to finish. */
1322 if (!lapic_ipi_wait(BEFORE_SPIN))
1323 panic("ipi_nmi_selected: previous IPI has not cleared");
1324
1325 lapic_ipi_raw(icrlo, cpu_apic_ids[cpu]);
1326 }
1327 }
1328
1329 int
1330 ipi_nmi_handler(void)
1331 {
1332 int cpumask = PCPU_GET(cpumask);
1333
1334 if (!(ipi_nmi_pending & cpumask))
1335 return 1;
1336
1337 atomic_clear_int(&ipi_nmi_pending, cpumask);
1338 cpustop_handler();
1339 return 0;
1340 }
1341
1342 #endif /* STOP_NMI */
1343
1344 /*
1345 * Handle an IPI_STOP by saving our current context and spinning until we
1346 * are resumed.
1347 */
1348 void
1349 cpustop_handler(void)
1350 {
1351 int cpu = PCPU_GET(cpuid);
1352 int cpumask = PCPU_GET(cpumask);
1353
1354 savectx(&stoppcbs[cpu]);
1355
1356 /* Indicate that we are stopped */
1357 atomic_set_int(&stopped_cpus, cpumask);
1358
1359 /* Wait for restart */
1360 while (!(started_cpus & cpumask))
1361 ia32_pause();
1362
1363 atomic_clear_int(&started_cpus, cpumask);
1364 atomic_clear_int(&stopped_cpus, cpumask);
1365
1366 if (cpu == 0 && cpustop_restartfunc != NULL) {
1367 cpustop_restartfunc();
1368 cpustop_restartfunc = NULL;
1369 }
1370 }
1371
1372 /*
1373 * This is called once the rest of the system is up and running and we're
1374 * ready to let the AP's out of the pen.
1375 */
1376 static void
1377 release_aps(void *dummy __unused)
1378 {
1379
1380 if (mp_ncpus == 1)
1381 return;
1382 atomic_store_rel_int(&aps_ready, 1);
1383 while (smp_started == 0)
1384 ia32_pause();
1385 }
1386 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
1387
1388 static int
1389 sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS)
1390 {
1391 u_int mask;
1392 int error;
1393
1394 mask = hlt_cpus_mask;
1395 error = sysctl_handle_int(oidp, &mask, 0, req);
1396 if (error || !req->newptr)
1397 return (error);
1398
1399 if (logical_cpus_mask != 0 &&
1400 (mask & logical_cpus_mask) == logical_cpus_mask)
1401 hlt_logical_cpus = 1;
1402 else
1403 hlt_logical_cpus = 0;
1404
1405 if (! hyperthreading_allowed)
1406 mask |= hyperthreading_cpus_mask;
1407
1408 if ((mask & all_cpus) == all_cpus)
1409 mask &= ~(1<<0);
1410 hlt_cpus_mask = mask;
1411 return (error);
1412 }
1413 SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW,
1414 0, 0, sysctl_hlt_cpus, "IU",
1415 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2.");
1416
1417 static int
1418 sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS)
1419 {
1420 int disable, error;
1421
1422 disable = hlt_logical_cpus;
1423 error = sysctl_handle_int(oidp, &disable, 0, req);
1424 if (error || !req->newptr)
1425 return (error);
1426
1427 if (disable)
1428 hlt_cpus_mask |= logical_cpus_mask;
1429 else
1430 hlt_cpus_mask &= ~logical_cpus_mask;
1431
1432 if (! hyperthreading_allowed)
1433 hlt_cpus_mask |= hyperthreading_cpus_mask;
1434
1435 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1436 hlt_cpus_mask &= ~(1<<0);
1437
1438 hlt_logical_cpus = disable;
1439 return (error);
1440 }
1441
1442 static int
1443 sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS)
1444 {
1445 int allowed, error;
1446
1447 allowed = hyperthreading_allowed;
1448 error = sysctl_handle_int(oidp, &allowed, 0, req);
1449 if (error || !req->newptr)
1450 return (error);
1451
1452 #ifdef SCHED_ULE
1453 /*
1454 * SCHED_ULE doesn't allow enabling/disabling HT cores at
1455 * run-time.
1456 */
1457 if (allowed != hyperthreading_allowed)
1458 return (ENOTSUP);
1459 return (error);
1460 #endif
1461
1462 if (allowed)
1463 hlt_cpus_mask &= ~hyperthreading_cpus_mask;
1464 else
1465 hlt_cpus_mask |= hyperthreading_cpus_mask;
1466
1467 if (logical_cpus_mask != 0 &&
1468 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask)
1469 hlt_logical_cpus = 1;
1470 else
1471 hlt_logical_cpus = 0;
1472
1473 if ((hlt_cpus_mask & all_cpus) == all_cpus)
1474 hlt_cpus_mask &= ~(1<<0);
1475
1476 hyperthreading_allowed = allowed;
1477 return (error);
1478 }
1479
1480 static void
1481 cpu_hlt_setup(void *dummy __unused)
1482 {
1483
1484 if (logical_cpus_mask != 0) {
1485 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus",
1486 &hlt_logical_cpus);
1487 sysctl_ctx_init(&logical_cpu_clist);
1488 SYSCTL_ADD_PROC(&logical_cpu_clist,
1489 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1490 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0,
1491 sysctl_hlt_logical_cpus, "IU", "");
1492 SYSCTL_ADD_UINT(&logical_cpu_clist,
1493 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1494 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD,
1495 &logical_cpus_mask, 0, "");
1496
1497 if (hlt_logical_cpus)
1498 hlt_cpus_mask |= logical_cpus_mask;
1499
1500 /*
1501 * If necessary for security purposes, force
1502 * hyperthreading off, regardless of the value
1503 * of hlt_logical_cpus.
1504 */
1505 if (hyperthreading_cpus_mask) {
1506 SYSCTL_ADD_PROC(&logical_cpu_clist,
1507 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO,
1508 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW,
1509 0, 0, sysctl_hyperthreading_allowed, "IU", "");
1510 if (! hyperthreading_allowed)
1511 hlt_cpus_mask |= hyperthreading_cpus_mask;
1512 }
1513 }
1514 }
1515 SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL);
1516
1517 int
1518 mp_grab_cpu_hlt(void)
1519 {
1520 u_int mask = PCPU_GET(cpumask);
1521 #ifdef MP_WATCHDOG
1522 u_int cpuid = PCPU_GET(cpuid);
1523 #endif
1524 int retval;
1525
1526 #ifdef MP_WATCHDOG
1527 ap_watchdog(cpuid);
1528 #endif
1529
1530 retval = mask & hlt_cpus_mask;
1531 while (mask & hlt_cpus_mask)
1532 __asm __volatile("sti; hlt" : : : "memory");
1533 return (retval);
1534 }
1535
1536 #ifdef COUNT_IPIS
1537 /*
1538 * Setup interrupt counters for IPI handlers.
1539 */
1540 static void
1541 mp_ipi_intrcnt(void *dummy)
1542 {
1543 char buf[64];
1544 int i;
1545
1546 for (i = 0; i < mp_maxid; i++) {
1547 if (CPU_ABSENT(i))
1548 continue;
1549 snprintf(buf, sizeof(buf), "cpu%d: invltlb", i);
1550 intrcnt_add(buf, &ipi_invltlb_counts[i]);
1551 snprintf(buf, sizeof(buf), "cpu%d: invlrng", i);
1552 intrcnt_add(buf, &ipi_invlrng_counts[i]);
1553 snprintf(buf, sizeof(buf), "cpu%d: invlpg", i);
1554 intrcnt_add(buf, &ipi_invlpg_counts[i]);
1555 snprintf(buf, sizeof(buf), "cpu%d: preempt", i);
1556 intrcnt_add(buf, &ipi_preempt_counts[i]);
1557 snprintf(buf, sizeof(buf), "cpu%d: ast", i);
1558 intrcnt_add(buf, &ipi_ast_counts[i]);
1559 snprintf(buf, sizeof(buf), "cpu%d: rendezvous", i);
1560 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
1561 snprintf(buf, sizeof(buf), "cpu%d: lazypmap", i);
1562 intrcnt_add(buf, &ipi_lazypmap_counts[i]);
1563 }
1564 }
1565 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);
1566 #endif
Cache object: f87a7c2f8b4cf481d7e62b40996ac574
|