Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/i386/i386/mp_machdep.c
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1 /*- 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26 #include <sys/cdefs.h> 27 __FBSDID("$FreeBSD: releng/8.1/sys/i386/i386/mp_machdep.c 205706 2010-03-26 18:54:25Z jhb $"); 28 29 #include "opt_apic.h" 30 #include "opt_cpu.h" 31 #include "opt_kstack_pages.h" 32 #include "opt_mp_watchdog.h" 33 #include "opt_pmap.h" 34 #include "opt_sched.h" 35 #include "opt_smp.h" 36 37 #if !defined(lint) 38 #if !defined(SMP) 39 #error How did you get here? 40 #endif 41 42 #ifndef DEV_APIC 43 #error The apic device is required for SMP, add "device apic" to your config file. 44 #endif 45 #if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT) 46 #error SMP not supported with CPU_DISABLE_CMPXCHG 47 #endif 48 #endif /* not lint */ 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/bus.h> 53 #include <sys/cons.h> /* cngetc() */ 54 #ifdef GPROF 55 #include <sys/gmon.h> 56 #endif 57 #include <sys/kernel.h> 58 #include <sys/ktr.h> 59 #include <sys/lock.h> 60 #include <sys/malloc.h> 61 #include <sys/memrange.h> 62 #include <sys/mutex.h> 63 #include <sys/pcpu.h> 64 #include <sys/proc.h> 65 #include <sys/sched.h> 66 #include <sys/smp.h> 67 #include <sys/sysctl.h> 68 69 #include <vm/vm.h> 70 #include <vm/vm_param.h> 71 #include <vm/pmap.h> 72 #include <vm/vm_kern.h> 73 #include <vm/vm_extern.h> 74 75 #include <machine/apicreg.h> 76 #include <machine/clock.h> 77 #include <machine/cputypes.h> 78 #include <machine/mca.h> 79 #include <machine/md_var.h> 80 #include <machine/mp_watchdog.h> 81 #include <machine/pcb.h> 82 #include <machine/psl.h> 83 #include <machine/smp.h> 84 #include <machine/specialreg.h> 85 86 #define WARMBOOT_TARGET 0 87 #define WARMBOOT_OFF (KERNBASE + 0x0467) 88 #define WARMBOOT_SEG (KERNBASE + 0x0469) 89 90 #define CMOS_REG (0x70) 91 #define CMOS_DATA (0x71) 92 #define BIOS_RESET (0x0f) 93 #define BIOS_WARM (0x0a) 94 95 /* 96 * this code MUST be enabled here and in mpboot.s. 97 * it follows the very early stages of AP boot by placing values in CMOS ram. 98 * it NORMALLY will never be needed and thus the primitive method for enabling. 99 * 100 #define CHECK_POINTS 101 */ 102 103 #if defined(CHECK_POINTS) && !defined(PC98) 104 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 105 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 106 107 #define CHECK_INIT(D); \ 108 CHECK_WRITE(0x34, (D)); \ 109 CHECK_WRITE(0x35, (D)); \ 110 CHECK_WRITE(0x36, (D)); \ 111 CHECK_WRITE(0x37, (D)); \ 112 CHECK_WRITE(0x38, (D)); \ 113 CHECK_WRITE(0x39, (D)); 114 115 #define CHECK_PRINT(S); \ 116 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 117 (S), \ 118 CHECK_READ(0x34), \ 119 CHECK_READ(0x35), \ 120 CHECK_READ(0x36), \ 121 CHECK_READ(0x37), \ 122 CHECK_READ(0x38), \ 123 CHECK_READ(0x39)); 124 125 #else /* CHECK_POINTS */ 126 127 #define CHECK_INIT(D) 128 #define CHECK_PRINT(S) 129 #define CHECK_WRITE(A, D) 130 131 #endif /* CHECK_POINTS */ 132 133 /* lock region used by kernel profiling */ 134 int mcount_lock; 135 136 int mp_naps; /* # of Applications processors */ 137 int boot_cpu_id = -1; /* designated BSP */ 138 139 extern struct pcpu __pcpu[]; 140 141 /* AP uses this during bootstrap. Do not staticize. */ 142 char *bootSTK; 143 static int bootAP; 144 145 /* Free these after use */ 146 void *bootstacks[MAXCPU]; 147 static void *dpcpu; 148 149 /* Hotwire a 0->4MB V==P mapping */ 150 extern pt_entry_t *KPTphys; 151 152 struct pcb stoppcbs[MAXCPU]; 153 154 /* Variables needed for SMP tlb shootdown. */ 155 vm_offset_t smp_tlb_addr1; 156 vm_offset_t smp_tlb_addr2; 157 volatile int smp_tlb_wait; 158 159 #ifdef COUNT_IPIS 160 /* Interrupt counts. */ 161 static u_long *ipi_preempt_counts[MAXCPU]; 162 static u_long *ipi_ast_counts[MAXCPU]; 163 u_long *ipi_invltlb_counts[MAXCPU]; 164 u_long *ipi_invlrng_counts[MAXCPU]; 165 u_long *ipi_invlpg_counts[MAXCPU]; 166 u_long *ipi_invlcache_counts[MAXCPU]; 167 u_long *ipi_rendezvous_counts[MAXCPU]; 168 u_long *ipi_lazypmap_counts[MAXCPU]; 169 #endif 170 171 /* 172 * Local data and functions. 173 */ 174 175 static u_int logical_cpus; 176 static volatile cpumask_t ipi_nmi_pending; 177 178 /* used to hold the AP's until we are ready to release them */ 179 static struct mtx ap_boot_mtx; 180 181 /* Set to 1 once we're ready to let the APs out of the pen. */ 182 static volatile int aps_ready = 0; 183 184 /* 185 * Store data from cpu_add() until later in the boot when we actually setup 186 * the APs. 187 */ 188 struct cpu_info { 189 int cpu_present:1; 190 int cpu_bsp:1; 191 int cpu_disabled:1; 192 int cpu_hyperthread:1; 193 } static cpu_info[MAX_APIC_ID + 1]; 194 int cpu_apic_ids[MAXCPU]; 195 int apic_cpuids[MAX_APIC_ID + 1]; 196 197 /* Holds pending bitmap based IPIs per CPU */ 198 static volatile u_int cpu_ipi_pending[MAXCPU]; 199 200 static u_int boot_address; 201 static int cpu_logical; 202 static int cpu_cores; 203 204 static void assign_cpu_ids(void); 205 static void install_ap_tramp(void); 206 static void set_interrupt_apic_ids(void); 207 static int start_all_aps(void); 208 static int start_ap(int apic_id); 209 static void release_aps(void *dummy); 210 211 static int hlt_logical_cpus; 212 static u_int hyperthreading_cpus; 213 static cpumask_t hyperthreading_cpus_mask; 214 static int hyperthreading_allowed = 1; 215 static struct sysctl_ctx_list logical_cpu_clist; 216 217 static void 218 mem_range_AP_init(void) 219 { 220 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 221 mem_range_softc.mr_op->initAP(&mem_range_softc); 222 } 223 224 static void 225 topo_probe_0xb(void) 226 { 227 int logical; 228 int p[4]; 229 int bits; 230 int type; 231 int cnt; 232 int i; 233 int x; 234 235 /* We only support two levels for now. */ 236 for (i = 0; i < 3; i++) { 237 cpuid_count(0x0B, i, p); 238 bits = p[0] & 0x1f; 239 logical = p[1] &= 0xffff; 240 type = (p[2] >> 8) & 0xff; 241 if (type == 0 || logical == 0) 242 break; 243 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) { 244 if (!cpu_info[x].cpu_present || 245 cpu_info[x].cpu_disabled) 246 continue; 247 if (x >> bits == boot_cpu_id >> bits) 248 cnt++; 249 } 250 if (type == CPUID_TYPE_SMT) 251 cpu_logical = cnt; 252 else if (type == CPUID_TYPE_CORE) 253 cpu_cores = cnt; 254 } 255 if (cpu_logical == 0) 256 cpu_logical = 1; 257 cpu_cores /= cpu_logical; 258 } 259 260 static void 261 topo_probe_0x4(void) 262 { 263 u_int threads_per_cache, p[4]; 264 u_int htt, cmp; 265 int i; 266 267 htt = cmp = 1; 268 /* 269 * If this CPU supports HTT or CMP then mention the 270 * number of physical/logical cores it contains. 271 */ 272 if (cpu_feature & CPUID_HTT) 273 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 274 if (cpu_vendor_id == CPU_VENDOR_AMD && (amd_feature2 & AMDID2_CMP)) 275 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 276 else if (cpu_vendor_id == CPU_VENDOR_INTEL && (cpu_high >= 4)) { 277 cpuid_count(4, 0, p); 278 if ((p[0] & 0x1f) != 0) 279 cmp = ((p[0] >> 26) & 0x3f) + 1; 280 } 281 cpu_cores = cmp; 282 cpu_logical = htt / cmp; 283 284 /* Setup the initial logical CPUs info. */ 285 if (cpu_feature & CPUID_HTT) 286 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 287 288 /* 289 * Work out if hyperthreading is *really* enabled. This 290 * is made really ugly by the fact that processors lie: Dual 291 * core processors claim to be hyperthreaded even when they're 292 * not, presumably because they want to be treated the same 293 * way as HTT with respect to per-cpu software licensing. 294 * At the time of writing (May 12, 2005) the only hyperthreaded 295 * cpus are from Intel, and Intel's dual-core processors can be 296 * identified via the "deterministic cache parameters" cpuid 297 * calls. 298 */ 299 /* 300 * First determine if this is an Intel processor which claims 301 * to have hyperthreading support. 302 */ 303 if ((cpu_feature & CPUID_HTT) && cpu_vendor_id == CPU_VENDOR_INTEL) { 304 /* 305 * If the "deterministic cache parameters" cpuid calls 306 * are available, use them. 307 */ 308 if (cpu_high >= 4) { 309 /* Ask the processor about the L1 cache. */ 310 for (i = 0; i < 1; i++) { 311 cpuid_count(4, i, p); 312 threads_per_cache = ((p[0] & 0x3ffc000) >> 14) + 1; 313 if (hyperthreading_cpus < threads_per_cache) 314 hyperthreading_cpus = threads_per_cache; 315 if ((p[0] & 0x1f) == 0) 316 break; 317 } 318 } 319 320 /* 321 * If the deterministic cache parameters are not 322 * available, or if no caches were reported to exist, 323 * just accept what the HTT flag indicated. 324 */ 325 if (hyperthreading_cpus == 0) 326 hyperthreading_cpus = logical_cpus; 327 } 328 } 329 330 static void 331 topo_probe(void) 332 { 333 static int cpu_topo_probed = 0; 334 335 if (cpu_topo_probed) 336 return; 337 338 logical_cpus = logical_cpus_mask = 0; 339 if (cpu_high >= 0xb) 340 topo_probe_0xb(); 341 else if (cpu_high) 342 topo_probe_0x4(); 343 if (cpu_cores == 0) 344 cpu_cores = mp_ncpus > 0 ? mp_ncpus : 1; 345 if (cpu_logical == 0) 346 cpu_logical = 1; 347 cpu_topo_probed = 1; 348 } 349 350 struct cpu_group * 351 cpu_topo(void) 352 { 353 int cg_flags; 354 355 /* 356 * Determine whether any threading flags are 357 * necessry. 358 */ 359 topo_probe(); 360 if (cpu_logical > 1 && hyperthreading_cpus) 361 cg_flags = CG_FLAG_HTT; 362 else if (cpu_logical > 1) 363 cg_flags = CG_FLAG_SMT; 364 else 365 cg_flags = 0; 366 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) { 367 printf("WARNING: Non-uniform processors.\n"); 368 printf("WARNING: Using suboptimal topology.\n"); 369 return (smp_topo_none()); 370 } 371 /* 372 * No multi-core or hyper-threaded. 373 */ 374 if (cpu_logical * cpu_cores == 1) 375 return (smp_topo_none()); 376 /* 377 * Only HTT no multi-core. 378 */ 379 if (cpu_logical > 1 && cpu_cores == 1) 380 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags)); 381 /* 382 * Only multi-core no HTT. 383 */ 384 if (cpu_cores > 1 && cpu_logical == 1) 385 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags)); 386 /* 387 * Both HTT and multi-core. 388 */ 389 return (smp_topo_2level(CG_SHARE_L2, cpu_cores, 390 CG_SHARE_L1, cpu_logical, cg_flags)); 391 } 392 393 394 /* 395 * Calculate usable address in base memory for AP trampoline code. 396 */ 397 u_int 398 mp_bootaddress(u_int basemem) 399 { 400 401 boot_address = trunc_page(basemem); /* round down to 4k boundary */ 402 if ((basemem - boot_address) < bootMP_size) 403 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 404 405 return boot_address; 406 } 407 408 void 409 cpu_add(u_int apic_id, char boot_cpu) 410 { 411 412 if (apic_id > MAX_APIC_ID) { 413 panic("SMP: APIC ID %d too high", apic_id); 414 return; 415 } 416 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 417 apic_id)); 418 cpu_info[apic_id].cpu_present = 1; 419 if (boot_cpu) { 420 KASSERT(boot_cpu_id == -1, 421 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 422 boot_cpu_id)); 423 boot_cpu_id = apic_id; 424 cpu_info[apic_id].cpu_bsp = 1; 425 } 426 if (mp_ncpus < MAXCPU) 427 mp_ncpus++; 428 if (bootverbose) 429 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 430 "AP"); 431 } 432 433 void 434 cpu_mp_setmaxid(void) 435 { 436 437 mp_maxid = MAXCPU - 1; 438 } 439 440 int 441 cpu_mp_probe(void) 442 { 443 444 /* 445 * Always record BSP in CPU map so that the mbuf init code works 446 * correctly. 447 */ 448 all_cpus = 1; 449 if (mp_ncpus == 0) { 450 /* 451 * No CPUs were found, so this must be a UP system. Setup 452 * the variables to represent a system with a single CPU 453 * with an id of 0. 454 */ 455 mp_ncpus = 1; 456 return (0); 457 } 458 459 /* At least one CPU was found. */ 460 if (mp_ncpus == 1) { 461 /* 462 * One CPU was found, so this must be a UP system with 463 * an I/O APIC. 464 */ 465 return (0); 466 } 467 468 /* At least two CPUs were found. */ 469 return (1); 470 } 471 472 /* 473 * Initialize the IPI handlers and start up the AP's. 474 */ 475 void 476 cpu_mp_start(void) 477 { 478 int i; 479 480 /* Initialize the logical ID to APIC ID table. */ 481 for (i = 0; i < MAXCPU; i++) { 482 cpu_apic_ids[i] = -1; 483 cpu_ipi_pending[i] = 0; 484 } 485 486 /* Install an inter-CPU IPI for TLB invalidation */ 487 setidt(IPI_INVLTLB, IDTVEC(invltlb), 488 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 489 setidt(IPI_INVLPG, IDTVEC(invlpg), 490 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 491 setidt(IPI_INVLRNG, IDTVEC(invlrng), 492 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 493 494 /* Install an inter-CPU IPI for cache invalidation. */ 495 setidt(IPI_INVLCACHE, IDTVEC(invlcache), 496 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 497 498 /* Install an inter-CPU IPI for lazy pmap release */ 499 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap), 500 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 501 502 /* Install an inter-CPU IPI for all-CPU rendezvous */ 503 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), 504 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 505 506 /* Install generic inter-CPU IPI handler */ 507 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 508 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 509 510 /* Install an inter-CPU IPI for CPU stop/restart */ 511 setidt(IPI_STOP, IDTVEC(cpustop), 512 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 513 514 515 /* Set boot_cpu_id if needed. */ 516 if (boot_cpu_id == -1) { 517 boot_cpu_id = PCPU_GET(apic_id); 518 cpu_info[boot_cpu_id].cpu_bsp = 1; 519 } else 520 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 521 ("BSP's APIC ID doesn't match boot_cpu_id")); 522 523 /* Probe logical/physical core configuration. */ 524 topo_probe(); 525 526 assign_cpu_ids(); 527 528 /* Start each Application Processor */ 529 start_all_aps(); 530 531 set_interrupt_apic_ids(); 532 } 533 534 535 /* 536 * Print various information about the SMP system hardware and setup. 537 */ 538 void 539 cpu_mp_announce(void) 540 { 541 const char *hyperthread; 542 int i; 543 544 printf("FreeBSD/SMP: %d package(s) x %d core(s)", 545 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores); 546 if (hyperthreading_cpus > 1) 547 printf(" x %d HTT threads", cpu_logical); 548 else if (cpu_logical > 1) 549 printf(" x %d SMT threads", cpu_logical); 550 printf("\n"); 551 552 /* List active CPUs first. */ 553 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 554 for (i = 1; i < mp_ncpus; i++) { 555 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread) 556 hyperthread = "/HT"; 557 else 558 hyperthread = ""; 559 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread, 560 cpu_apic_ids[i]); 561 } 562 563 /* List disabled CPUs last. */ 564 for (i = 0; i <= MAX_APIC_ID; i++) { 565 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled) 566 continue; 567 if (cpu_info[i].cpu_hyperthread) 568 hyperthread = "/HT"; 569 else 570 hyperthread = ""; 571 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread, 572 i); 573 } 574 } 575 576 /* 577 * AP CPU's call this to initialize themselves. 578 */ 579 void 580 init_secondary(void) 581 { 582 struct pcpu *pc; 583 vm_offset_t addr; 584 int gsel_tss; 585 int x, myid; 586 u_int cr0; 587 588 /* bootAP is set in start_ap() to our ID. */ 589 myid = bootAP; 590 591 /* Get per-cpu data */ 592 pc = &__pcpu[myid]; 593 594 /* prime data page for it to use */ 595 pcpu_init(pc, myid, sizeof(struct pcpu)); 596 dpcpu_init(dpcpu, myid); 597 pc->pc_apic_id = cpu_apic_ids[myid]; 598 pc->pc_prvspace = pc; 599 pc->pc_curthread = 0; 600 601 gdt_segs[GPRIV_SEL].ssd_base = (int) pc; 602 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss; 603 604 for (x = 0; x < NGDT; x++) { 605 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 606 } 607 608 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 609 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 610 lgdt(&r_gdt); /* does magic intra-segment return */ 611 612 lidt(&r_idt); 613 614 lldt(_default_ldt); 615 PCPU_SET(currentldt, _default_ldt); 616 617 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 618 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 619 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 620 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 621 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 622 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 623 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 624 ltr(gsel_tss); 625 626 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd); 627 628 /* 629 * Set to a known state: 630 * Set by mpboot.s: CR0_PG, CR0_PE 631 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 632 */ 633 cr0 = rcr0(); 634 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 635 load_cr0(cr0); 636 CHECK_WRITE(0x38, 5); 637 638 /* Disable local APIC just to be sure. */ 639 lapic_disable(); 640 641 /* signal our startup to the BSP. */ 642 mp_naps++; 643 CHECK_WRITE(0x39, 6); 644 645 /* Spin until the BSP releases the AP's. */ 646 while (!aps_ready) 647 ia32_pause(); 648 649 /* BSP may have changed PTD while we were waiting */ 650 invltlb(); 651 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE) 652 invlpg(addr); 653 654 #if defined(I586_CPU) && !defined(NO_F00F_HACK) 655 lidt(&r_idt); 656 #endif 657 658 /* Initialize the PAT MSR if present. */ 659 pmap_init_pat(); 660 661 /* set up CPU registers and state */ 662 cpu_setregs(); 663 664 /* set up FPU state on the AP */ 665 npxinit(); 666 667 /* set up SSE registers */ 668 enable_sse(); 669 670 #ifdef PAE 671 /* Enable the PTE no-execute bit. */ 672 if ((amd_feature & AMDID_NX) != 0) { 673 uint64_t msr; 674 675 msr = rdmsr(MSR_EFER) | EFER_NXE; 676 wrmsr(MSR_EFER, msr); 677 } 678 #endif 679 680 /* A quick check from sanity claus */ 681 if (PCPU_GET(apic_id) != lapic_id()) { 682 printf("SMP: cpuid = %d\n", PCPU_GET(cpuid)); 683 printf("SMP: actual apic_id = %d\n", lapic_id()); 684 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 685 panic("cpuid mismatch! boom!!"); 686 } 687 688 /* Initialize curthread. */ 689 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 690 PCPU_SET(curthread, PCPU_GET(idlethread)); 691 692 mca_init(); 693 694 mtx_lock_spin(&ap_boot_mtx); 695 696 /* Init local apic for irq's */ 697 lapic_setup(1); 698 699 /* Set memory range attributes for this CPU to match the BSP */ 700 mem_range_AP_init(); 701 702 smp_cpus++; 703 704 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", PCPU_GET(cpuid)); 705 printf("SMP: AP CPU #%d Launched!\n", PCPU_GET(cpuid)); 706 707 /* Determine if we are a logical CPU. */ 708 if (logical_cpus > 1 && PCPU_GET(apic_id) % logical_cpus != 0) 709 logical_cpus_mask |= PCPU_GET(cpumask); 710 711 /* Determine if we are a hyperthread. */ 712 if (hyperthreading_cpus > 1 && 713 PCPU_GET(apic_id) % hyperthreading_cpus != 0) 714 hyperthreading_cpus_mask |= PCPU_GET(cpumask); 715 716 /* Build our map of 'other' CPUs. */ 717 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 718 719 if (bootverbose) 720 lapic_dump("AP"); 721 722 if (smp_cpus == mp_ncpus) { 723 /* enable IPI's, tlb shootdown, freezes etc */ 724 atomic_store_rel_int(&smp_started, 1); 725 smp_active = 1; /* historic */ 726 } 727 728 mtx_unlock_spin(&ap_boot_mtx); 729 730 /* wait until all the AP's are up */ 731 while (smp_started == 0) 732 ia32_pause(); 733 734 /* enter the scheduler */ 735 sched_throw(NULL); 736 737 panic("scheduler returned us to %s", __func__); 738 /* NOTREACHED */ 739 } 740 741 /******************************************************************* 742 * local functions and data 743 */ 744 745 /* 746 * We tell the I/O APIC code about all the CPUs we want to receive 747 * interrupts. If we don't want certain CPUs to receive IRQs we 748 * can simply not tell the I/O APIC code about them in this function. 749 * We also do not tell it about the BSP since it tells itself about 750 * the BSP internally to work with UP kernels and on UP machines. 751 */ 752 static void 753 set_interrupt_apic_ids(void) 754 { 755 u_int i, apic_id; 756 757 for (i = 0; i < MAXCPU; i++) { 758 apic_id = cpu_apic_ids[i]; 759 if (apic_id == -1) 760 continue; 761 if (cpu_info[apic_id].cpu_bsp) 762 continue; 763 if (cpu_info[apic_id].cpu_disabled) 764 continue; 765 766 /* Don't let hyperthreads service interrupts. */ 767 if (hyperthreading_cpus > 1 && 768 apic_id % hyperthreading_cpus != 0) 769 continue; 770 771 intr_add_cpu(i); 772 } 773 } 774 775 /* 776 * Assign logical CPU IDs to local APICs. 777 */ 778 static void 779 assign_cpu_ids(void) 780 { 781 u_int i; 782 783 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 784 &hyperthreading_allowed); 785 786 /* Check for explicitly disabled CPUs. */ 787 for (i = 0; i <= MAX_APIC_ID; i++) { 788 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp) 789 continue; 790 791 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) { 792 cpu_info[i].cpu_hyperthread = 1; 793 #if defined(SCHED_ULE) 794 /* 795 * Don't use HT CPU if it has been disabled by a 796 * tunable. 797 */ 798 if (hyperthreading_allowed == 0) { 799 cpu_info[i].cpu_disabled = 1; 800 continue; 801 } 802 #endif 803 } 804 805 /* Don't use this CPU if it has been disabled by a tunable. */ 806 if (resource_disabled("lapic", i)) { 807 cpu_info[i].cpu_disabled = 1; 808 continue; 809 } 810 } 811 812 /* 813 * Assign CPU IDs to local APIC IDs and disable any CPUs 814 * beyond MAXCPU. CPU 0 is always assigned to the BSP. 815 * 816 * To minimize confusion for userland, we attempt to number 817 * CPUs such that all threads and cores in a package are 818 * grouped together. For now we assume that the BSP is always 819 * the first thread in a package and just start adding APs 820 * starting with the BSP's APIC ID. 821 */ 822 mp_ncpus = 1; 823 cpu_apic_ids[0] = boot_cpu_id; 824 apic_cpuids[boot_cpu_id] = 0; 825 for (i = boot_cpu_id + 1; i != boot_cpu_id; 826 i == MAX_APIC_ID ? i = 0 : i++) { 827 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp || 828 cpu_info[i].cpu_disabled) 829 continue; 830 831 if (mp_ncpus < MAXCPU) { 832 cpu_apic_ids[mp_ncpus] = i; 833 apic_cpuids[i] = mp_ncpus; 834 mp_ncpus++; 835 } else 836 cpu_info[i].cpu_disabled = 1; 837 } 838 KASSERT(mp_maxid >= mp_ncpus - 1, 839 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid, 840 mp_ncpus)); 841 } 842 843 /* 844 * start each AP in our list 845 */ 846 /* Lowest 1MB is already mapped: don't touch*/ 847 #define TMPMAP_START 1 848 static int 849 start_all_aps(void) 850 { 851 #ifndef PC98 852 u_char mpbiosreason; 853 #endif 854 uintptr_t kptbase; 855 u_int32_t mpbioswarmvec; 856 int apic_id, cpu, i; 857 858 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 859 860 /* install the AP 1st level boot code */ 861 install_ap_tramp(); 862 863 /* save the current value of the warm-start vector */ 864 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 865 #ifndef PC98 866 outb(CMOS_REG, BIOS_RESET); 867 mpbiosreason = inb(CMOS_DATA); 868 #endif 869 870 /* set up temporary P==V mapping for AP boot */ 871 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 872 873 kptbase = (uintptr_t)(void *)KPTphys; 874 for (i = TMPMAP_START; i < NKPT; i++) 875 PTD[i] = (pd_entry_t)(PG_V | PG_RW | 876 ((kptbase + i * PAGE_SIZE) & PG_FRAME)); 877 invltlb(); 878 879 /* start each AP */ 880 for (cpu = 1; cpu < mp_ncpus; cpu++) { 881 apic_id = cpu_apic_ids[cpu]; 882 883 /* allocate and set up a boot stack data page */ 884 bootstacks[cpu] = 885 (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE); 886 dpcpu = (void *)kmem_alloc(kernel_map, DPCPU_SIZE); 887 /* setup a vector to our boot code */ 888 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 889 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 890 #ifndef PC98 891 outb(CMOS_REG, BIOS_RESET); 892 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 893 #endif 894 895 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4; 896 bootAP = cpu; 897 898 /* attempt to start the Application Processor */ 899 CHECK_INIT(99); /* setup checkpoints */ 900 if (!start_ap(apic_id)) { 901 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id); 902 CHECK_PRINT("trace"); /* show checkpoints */ 903 /* better panic as the AP may be running loose */ 904 printf("panic y/n? [y] "); 905 if (cngetc() != 'n') 906 panic("bye-bye"); 907 } 908 CHECK_PRINT("trace"); /* show checkpoints */ 909 910 all_cpus |= (1 << cpu); /* record AP in CPU map */ 911 } 912 913 /* build our map of 'other' CPUs */ 914 PCPU_SET(other_cpus, all_cpus & ~PCPU_GET(cpumask)); 915 916 /* restore the warmstart vector */ 917 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 918 919 #ifndef PC98 920 outb(CMOS_REG, BIOS_RESET); 921 outb(CMOS_DATA, mpbiosreason); 922 #endif 923 924 /* Undo V==P hack from above */ 925 for (i = TMPMAP_START; i < NKPT; i++) 926 PTD[i] = 0; 927 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 928 929 /* number of APs actually started */ 930 return mp_naps; 931 } 932 933 /* 934 * load the 1st level AP boot code into base memory. 935 */ 936 937 /* targets for relocation */ 938 extern void bigJump(void); 939 extern void bootCodeSeg(void); 940 extern void bootDataSeg(void); 941 extern void MPentry(void); 942 extern u_int MP_GDT; 943 extern u_int mp_gdtbase; 944 945 static void 946 install_ap_tramp(void) 947 { 948 int x; 949 int size = *(int *) ((u_long) & bootMP_size); 950 vm_offset_t va = boot_address + KERNBASE; 951 u_char *src = (u_char *) ((u_long) bootMP); 952 u_char *dst = (u_char *) va; 953 u_int boot_base = (u_int) bootMP; 954 u_int8_t *dst8; 955 u_int16_t *dst16; 956 u_int32_t *dst32; 957 958 KASSERT (size <= PAGE_SIZE, 959 ("'size' do not fit into PAGE_SIZE, as expected.")); 960 pmap_kenter(va, boot_address); 961 pmap_invalidate_page (kernel_pmap, va); 962 for (x = 0; x < size; ++x) 963 *dst++ = *src++; 964 965 /* 966 * modify addresses in code we just moved to basemem. unfortunately we 967 * need fairly detailed info about mpboot.s for this to work. changes 968 * to mpboot.s might require changes here. 969 */ 970 971 /* boot code is located in KERNEL space */ 972 dst = (u_char *) va; 973 974 /* modify the lgdt arg */ 975 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 976 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base); 977 978 /* modify the ljmp target for MPentry() */ 979 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 980 *dst32 = ((u_int) MPentry - KERNBASE); 981 982 /* modify the target for boot code segment */ 983 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 984 dst8 = (u_int8_t *) (dst16 + 1); 985 *dst16 = (u_int) boot_address & 0xffff; 986 *dst8 = ((u_int) boot_address >> 16) & 0xff; 987 988 /* modify the target for boot data segment */ 989 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 990 dst8 = (u_int8_t *) (dst16 + 1); 991 *dst16 = (u_int) boot_address & 0xffff; 992 *dst8 = ((u_int) boot_address >> 16) & 0xff; 993 } 994 995 /* 996 * This function starts the AP (application processor) identified 997 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 998 * to accomplish this. This is necessary because of the nuances 999 * of the different hardware we might encounter. It isn't pretty, 1000 * but it seems to work. 1001 */ 1002 static int 1003 start_ap(int apic_id) 1004 { 1005 int vector, ms; 1006 int cpus; 1007 1008 /* calculate the vector */ 1009 vector = (boot_address >> 12) & 0xff; 1010 1011 /* used as a watchpoint to signal AP startup */ 1012 cpus = mp_naps; 1013 1014 /* 1015 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting 1016 * and running the target CPU. OR this INIT IPI might be latched (P5 1017 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1018 * ignored. 1019 */ 1020 1021 /* do an INIT IPI: assert RESET */ 1022 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1023 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 1024 1025 /* wait for pending status end */ 1026 lapic_ipi_wait(-1); 1027 1028 /* do an INIT IPI: deassert RESET */ 1029 lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL | 1030 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0); 1031 1032 /* wait for pending status end */ 1033 DELAY(10000); /* wait ~10mS */ 1034 lapic_ipi_wait(-1); 1035 1036 /* 1037 * next we do a STARTUP IPI: the previous INIT IPI might still be 1038 * latched, (P5 bug) this 1st STARTUP would then terminate 1039 * immediately, and the previously started INIT IPI would continue. OR 1040 * the previous INIT IPI has already run. and this STARTUP IPI will 1041 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1042 * will run. 1043 */ 1044 1045 /* do a STARTUP IPI */ 1046 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1047 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1048 vector, apic_id); 1049 lapic_ipi_wait(-1); 1050 DELAY(200); /* wait ~200uS */ 1051 1052 /* 1053 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1054 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1055 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1056 * recognized after hardware RESET or INIT IPI. 1057 */ 1058 1059 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1060 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1061 vector, apic_id); 1062 lapic_ipi_wait(-1); 1063 DELAY(200); /* wait ~200uS */ 1064 1065 /* Wait up to 5 seconds for it to start. */ 1066 for (ms = 0; ms < 5000; ms++) { 1067 if (mp_naps > cpus) 1068 return 1; /* return SUCCESS */ 1069 DELAY(1000); 1070 } 1071 return 0; /* return FAILURE */ 1072 } 1073 1074 #ifdef COUNT_XINVLTLB_HITS 1075 u_int xhits_gbl[MAXCPU]; 1076 u_int xhits_pg[MAXCPU]; 1077 u_int xhits_rng[MAXCPU]; 1078 SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 1079 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 1080 sizeof(xhits_gbl), "IU", ""); 1081 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 1082 sizeof(xhits_pg), "IU", ""); 1083 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 1084 sizeof(xhits_rng), "IU", ""); 1085 1086 u_int ipi_global; 1087 u_int ipi_page; 1088 u_int ipi_range; 1089 u_int ipi_range_size; 1090 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 1091 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 1092 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 1093 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 1094 0, ""); 1095 1096 u_int ipi_masked_global; 1097 u_int ipi_masked_page; 1098 u_int ipi_masked_range; 1099 u_int ipi_masked_range_size; 1100 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 1101 &ipi_masked_global, 0, ""); 1102 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 1103 &ipi_masked_page, 0, ""); 1104 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 1105 &ipi_masked_range, 0, ""); 1106 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 1107 &ipi_masked_range_size, 0, ""); 1108 #endif /* COUNT_XINVLTLB_HITS */ 1109 1110 /* 1111 * Flush the TLB on all other CPU's 1112 */ 1113 static void 1114 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1115 { 1116 u_int ncpu; 1117 1118 ncpu = mp_ncpus - 1; /* does not shootdown self */ 1119 if (ncpu < 1) 1120 return; /* no other cpus */ 1121 if (!(read_eflags() & PSL_I)) 1122 panic("%s: interrupts disabled", __func__); 1123 mtx_lock_spin(&smp_ipi_mtx); 1124 smp_tlb_addr1 = addr1; 1125 smp_tlb_addr2 = addr2; 1126 atomic_store_rel_int(&smp_tlb_wait, 0); 1127 ipi_all_but_self(vector); 1128 while (smp_tlb_wait < ncpu) 1129 ia32_pause(); 1130 mtx_unlock_spin(&smp_ipi_mtx); 1131 } 1132 1133 static void 1134 smp_targeted_tlb_shootdown(cpumask_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1135 { 1136 int ncpu, othercpus; 1137 1138 othercpus = mp_ncpus - 1; 1139 if (mask == (u_int)-1) { 1140 ncpu = othercpus; 1141 if (ncpu < 1) 1142 return; 1143 } else { 1144 mask &= ~PCPU_GET(cpumask); 1145 if (mask == 0) 1146 return; 1147 ncpu = bitcount32(mask); 1148 if (ncpu > othercpus) { 1149 /* XXX this should be a panic offence */ 1150 printf("SMP: tlb shootdown to %d other cpus (only have %d)\n", 1151 ncpu, othercpus); 1152 ncpu = othercpus; 1153 } 1154 /* XXX should be a panic, implied by mask == 0 above */ 1155 if (ncpu < 1) 1156 return; 1157 } 1158 if (!(read_eflags() & PSL_I)) 1159 panic("%s: interrupts disabled", __func__); 1160 mtx_lock_spin(&smp_ipi_mtx); 1161 smp_tlb_addr1 = addr1; 1162 smp_tlb_addr2 = addr2; 1163 atomic_store_rel_int(&smp_tlb_wait, 0); 1164 if (mask == (u_int)-1) 1165 ipi_all_but_self(vector); 1166 else 1167 ipi_selected(mask, vector); 1168 while (smp_tlb_wait < ncpu) 1169 ia32_pause(); 1170 mtx_unlock_spin(&smp_ipi_mtx); 1171 } 1172 1173 void 1174 smp_cache_flush(void) 1175 { 1176 1177 if (smp_started) 1178 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0); 1179 } 1180 1181 void 1182 smp_invltlb(void) 1183 { 1184 1185 if (smp_started) { 1186 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 1187 #ifdef COUNT_XINVLTLB_HITS 1188 ipi_global++; 1189 #endif 1190 } 1191 } 1192 1193 void 1194 smp_invlpg(vm_offset_t addr) 1195 { 1196 1197 if (smp_started) { 1198 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 1199 #ifdef COUNT_XINVLTLB_HITS 1200 ipi_page++; 1201 #endif 1202 } 1203 } 1204 1205 void 1206 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 1207 { 1208 1209 if (smp_started) { 1210 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 1211 #ifdef COUNT_XINVLTLB_HITS 1212 ipi_range++; 1213 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1214 #endif 1215 } 1216 } 1217 1218 void 1219 smp_masked_invltlb(cpumask_t mask) 1220 { 1221 1222 if (smp_started) { 1223 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 1224 #ifdef COUNT_XINVLTLB_HITS 1225 ipi_masked_global++; 1226 #endif 1227 } 1228 } 1229 1230 void 1231 smp_masked_invlpg(cpumask_t mask, vm_offset_t addr) 1232 { 1233 1234 if (smp_started) { 1235 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 1236 #ifdef COUNT_XINVLTLB_HITS 1237 ipi_masked_page++; 1238 #endif 1239 } 1240 } 1241 1242 void 1243 smp_masked_invlpg_range(cpumask_t mask, vm_offset_t addr1, vm_offset_t addr2) 1244 { 1245 1246 if (smp_started) { 1247 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 1248 #ifdef COUNT_XINVLTLB_HITS 1249 ipi_masked_range++; 1250 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1251 #endif 1252 } 1253 } 1254 1255 void 1256 ipi_bitmap_handler(struct trapframe frame) 1257 { 1258 int cpu = PCPU_GET(cpuid); 1259 u_int ipi_bitmap; 1260 1261 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1262 1263 if (ipi_bitmap & (1 << IPI_PREEMPT)) { 1264 #ifdef COUNT_IPIS 1265 (*ipi_preempt_counts[cpu])++; 1266 #endif 1267 sched_preempt(curthread); 1268 } 1269 1270 if (ipi_bitmap & (1 << IPI_AST)) { 1271 #ifdef COUNT_IPIS 1272 (*ipi_ast_counts[cpu])++; 1273 #endif 1274 /* Nothing to do for AST */ 1275 } 1276 1277 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) 1278 hardclockintr(&frame); 1279 1280 if (ipi_bitmap & (1 << IPI_STATCLOCK)) 1281 statclockintr(&frame); 1282 1283 if (ipi_bitmap & (1 << IPI_PROFCLOCK)) 1284 profclockintr(&frame); 1285 } 1286 1287 /* 1288 * send an IPI to a set of cpus. 1289 */ 1290 void 1291 ipi_selected(cpumask_t cpus, u_int ipi) 1292 { 1293 int cpu; 1294 u_int bitmap = 0; 1295 u_int old_pending; 1296 u_int new_pending; 1297 1298 if (IPI_IS_BITMAPED(ipi)) { 1299 bitmap = 1 << ipi; 1300 ipi = IPI_BITMAP_VECTOR; 1301 } 1302 1303 /* 1304 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1305 * of help in order to understand what is the source. 1306 * Set the mask of receiving CPUs for this purpose. 1307 */ 1308 if (ipi == IPI_STOP_HARD) 1309 atomic_set_int(&ipi_nmi_pending, cpus); 1310 1311 CTR3(KTR_SMP, "%s: cpus: %x ipi: %x", __func__, cpus, ipi); 1312 while ((cpu = ffs(cpus)) != 0) { 1313 cpu--; 1314 cpus &= ~(1 << cpu); 1315 1316 KASSERT(cpu_apic_ids[cpu] != -1, 1317 ("IPI to non-existent CPU %d", cpu)); 1318 1319 if (bitmap) { 1320 do { 1321 old_pending = cpu_ipi_pending[cpu]; 1322 new_pending = old_pending | bitmap; 1323 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu],old_pending, new_pending)); 1324 1325 if (old_pending) 1326 continue; 1327 } 1328 1329 lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]); 1330 } 1331 1332 } 1333 1334 /* 1335 * send an IPI to all CPUs EXCEPT myself 1336 */ 1337 void 1338 ipi_all_but_self(u_int ipi) 1339 { 1340 1341 if (IPI_IS_BITMAPED(ipi)) { 1342 ipi_selected(PCPU_GET(other_cpus), ipi); 1343 return; 1344 } 1345 1346 /* 1347 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1348 * of help in order to understand what is the source. 1349 * Set the mask of receiving CPUs for this purpose. 1350 */ 1351 if (ipi == IPI_STOP_HARD) 1352 atomic_set_int(&ipi_nmi_pending, PCPU_GET(other_cpus)); 1353 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1354 lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1355 } 1356 1357 int 1358 ipi_nmi_handler() 1359 { 1360 cpumask_t cpumask; 1361 1362 /* 1363 * As long as there is not a simple way to know about a NMI's 1364 * source, if the bitmask for the current CPU is present in 1365 * the global pending bitword an IPI_STOP_HARD has been issued 1366 * and should be handled. 1367 */ 1368 cpumask = PCPU_GET(cpumask); 1369 if ((ipi_nmi_pending & cpumask) == 0) 1370 return (1); 1371 1372 atomic_clear_int(&ipi_nmi_pending, cpumask); 1373 cpustop_handler(); 1374 return (0); 1375 } 1376 1377 /* 1378 * Handle an IPI_STOP by saving our current context and spinning until we 1379 * are resumed. 1380 */ 1381 void 1382 cpustop_handler(void) 1383 { 1384 int cpu = PCPU_GET(cpuid); 1385 int cpumask = PCPU_GET(cpumask); 1386 1387 savectx(&stoppcbs[cpu]); 1388 1389 /* Indicate that we are stopped */ 1390 atomic_set_int(&stopped_cpus, cpumask); 1391 1392 /* Wait for restart */ 1393 while (!(started_cpus & cpumask)) 1394 ia32_pause(); 1395 1396 atomic_clear_int(&started_cpus, cpumask); 1397 atomic_clear_int(&stopped_cpus, cpumask); 1398 1399 if (cpu == 0 && cpustop_restartfunc != NULL) { 1400 cpustop_restartfunc(); 1401 cpustop_restartfunc = NULL; 1402 } 1403 } 1404 1405 /* 1406 * This is called once the rest of the system is up and running and we're 1407 * ready to let the AP's out of the pen. 1408 */ 1409 static void 1410 release_aps(void *dummy __unused) 1411 { 1412 1413 if (mp_ncpus == 1) 1414 return; 1415 atomic_store_rel_int(&aps_ready, 1); 1416 while (smp_started == 0) 1417 ia32_pause(); 1418 } 1419 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1420 1421 static int 1422 sysctl_hlt_cpus(SYSCTL_HANDLER_ARGS) 1423 { 1424 cpumask_t mask; 1425 int error; 1426 1427 mask = hlt_cpus_mask; 1428 error = sysctl_handle_int(oidp, &mask, 0, req); 1429 if (error || !req->newptr) 1430 return (error); 1431 1432 if (logical_cpus_mask != 0 && 1433 (mask & logical_cpus_mask) == logical_cpus_mask) 1434 hlt_logical_cpus = 1; 1435 else 1436 hlt_logical_cpus = 0; 1437 1438 if (! hyperthreading_allowed) 1439 mask |= hyperthreading_cpus_mask; 1440 1441 if ((mask & all_cpus) == all_cpus) 1442 mask &= ~(1<<0); 1443 hlt_cpus_mask = mask; 1444 return (error); 1445 } 1446 SYSCTL_PROC(_machdep, OID_AUTO, hlt_cpus, CTLTYPE_INT|CTLFLAG_RW, 1447 0, 0, sysctl_hlt_cpus, "IU", 1448 "Bitmap of CPUs to halt. 101 (binary) will halt CPUs 0 and 2."); 1449 1450 static int 1451 sysctl_hlt_logical_cpus(SYSCTL_HANDLER_ARGS) 1452 { 1453 int disable, error; 1454 1455 disable = hlt_logical_cpus; 1456 error = sysctl_handle_int(oidp, &disable, 0, req); 1457 if (error || !req->newptr) 1458 return (error); 1459 1460 if (disable) 1461 hlt_cpus_mask |= logical_cpus_mask; 1462 else 1463 hlt_cpus_mask &= ~logical_cpus_mask; 1464 1465 if (! hyperthreading_allowed) 1466 hlt_cpus_mask |= hyperthreading_cpus_mask; 1467 1468 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1469 hlt_cpus_mask &= ~(1<<0); 1470 1471 hlt_logical_cpus = disable; 1472 return (error); 1473 } 1474 1475 static int 1476 sysctl_hyperthreading_allowed(SYSCTL_HANDLER_ARGS) 1477 { 1478 int allowed, error; 1479 1480 allowed = hyperthreading_allowed; 1481 error = sysctl_handle_int(oidp, &allowed, 0, req); 1482 if (error || !req->newptr) 1483 return (error); 1484 1485 #ifdef SCHED_ULE 1486 /* 1487 * SCHED_ULE doesn't allow enabling/disabling HT cores at 1488 * run-time. 1489 */ 1490 if (allowed != hyperthreading_allowed) 1491 return (ENOTSUP); 1492 return (error); 1493 #endif 1494 1495 if (allowed) 1496 hlt_cpus_mask &= ~hyperthreading_cpus_mask; 1497 else 1498 hlt_cpus_mask |= hyperthreading_cpus_mask; 1499 1500 if (logical_cpus_mask != 0 && 1501 (hlt_cpus_mask & logical_cpus_mask) == logical_cpus_mask) 1502 hlt_logical_cpus = 1; 1503 else 1504 hlt_logical_cpus = 0; 1505 1506 if ((hlt_cpus_mask & all_cpus) == all_cpus) 1507 hlt_cpus_mask &= ~(1<<0); 1508 1509 hyperthreading_allowed = allowed; 1510 return (error); 1511 } 1512 1513 static void 1514 cpu_hlt_setup(void *dummy __unused) 1515 { 1516 1517 if (logical_cpus_mask != 0) { 1518 TUNABLE_INT_FETCH("machdep.hlt_logical_cpus", 1519 &hlt_logical_cpus); 1520 sysctl_ctx_init(&logical_cpu_clist); 1521 SYSCTL_ADD_PROC(&logical_cpu_clist, 1522 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1523 "hlt_logical_cpus", CTLTYPE_INT|CTLFLAG_RW, 0, 0, 1524 sysctl_hlt_logical_cpus, "IU", ""); 1525 SYSCTL_ADD_UINT(&logical_cpu_clist, 1526 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1527 "logical_cpus_mask", CTLTYPE_INT|CTLFLAG_RD, 1528 &logical_cpus_mask, 0, ""); 1529 1530 if (hlt_logical_cpus) 1531 hlt_cpus_mask |= logical_cpus_mask; 1532 1533 /* 1534 * If necessary for security purposes, force 1535 * hyperthreading off, regardless of the value 1536 * of hlt_logical_cpus. 1537 */ 1538 if (hyperthreading_cpus_mask) { 1539 SYSCTL_ADD_PROC(&logical_cpu_clist, 1540 SYSCTL_STATIC_CHILDREN(_machdep), OID_AUTO, 1541 "hyperthreading_allowed", CTLTYPE_INT|CTLFLAG_RW, 1542 0, 0, sysctl_hyperthreading_allowed, "IU", ""); 1543 if (! hyperthreading_allowed) 1544 hlt_cpus_mask |= hyperthreading_cpus_mask; 1545 } 1546 } 1547 } 1548 SYSINIT(cpu_hlt, SI_SUB_SMP, SI_ORDER_ANY, cpu_hlt_setup, NULL); 1549 1550 int 1551 mp_grab_cpu_hlt(void) 1552 { 1553 u_int mask = PCPU_GET(cpumask); 1554 #ifdef MP_WATCHDOG 1555 u_int cpuid = PCPU_GET(cpuid); 1556 #endif 1557 int retval; 1558 1559 #ifdef MP_WATCHDOG 1560 ap_watchdog(cpuid); 1561 #endif 1562 1563 retval = mask & hlt_cpus_mask; 1564 while (mask & hlt_cpus_mask) 1565 __asm __volatile("sti; hlt" : : : "memory"); 1566 return (retval); 1567 } 1568 1569 #ifdef COUNT_IPIS 1570 /* 1571 * Setup interrupt counters for IPI handlers. 1572 */ 1573 static void 1574 mp_ipi_intrcnt(void *dummy) 1575 { 1576 char buf[64]; 1577 int i; 1578 1579 for (i = 0; i < mp_maxid; i++) { 1580 if (CPU_ABSENT(i)) 1581 continue; 1582 snprintf(buf, sizeof(buf), "cpu%d: invltlb", i); 1583 intrcnt_add(buf, &ipi_invltlb_counts[i]); 1584 snprintf(buf, sizeof(buf), "cpu%d: invlrng", i); 1585 intrcnt_add(buf, &ipi_invlrng_counts[i]); 1586 snprintf(buf, sizeof(buf), "cpu%d: invlpg", i); 1587 intrcnt_add(buf, &ipi_invlpg_counts[i]); 1588 snprintf(buf, sizeof(buf), "cpu%d: preempt", i); 1589 intrcnt_add(buf, &ipi_preempt_counts[i]); 1590 snprintf(buf, sizeof(buf), "cpu%d: ast", i); 1591 intrcnt_add(buf, &ipi_ast_counts[i]); 1592 snprintf(buf, sizeof(buf), "cpu%d: rendezvous", i); 1593 intrcnt_add(buf, &ipi_rendezvous_counts[i]); 1594 snprintf(buf, sizeof(buf), "cpu%d: lazypmap", i); 1595 intrcnt_add(buf, &ipi_lazypmap_counts[i]); 1596 } 1597 } 1598 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL); 1599 #endif
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