The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/mp_machdep.c

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    1 /*-
    2  * Copyright (c) 1996, by Steve Passe
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. The name of the developer may NOT be used to endorse or promote products
   11  *    derived from this software without specific prior written permission.
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   23  * SUCH DAMAGE.
   24  */
   25 
   26 #include <sys/cdefs.h>
   27 __FBSDID("$FreeBSD: releng/9.1/sys/i386/i386/mp_machdep.c 235796 2012-05-22 17:44:01Z iwasaki $");
   28 
   29 #include "opt_apic.h"
   30 #include "opt_cpu.h"
   31 #include "opt_kstack_pages.h"
   32 #include "opt_pmap.h"
   33 #include "opt_sched.h"
   34 #include "opt_smp.h"
   35 
   36 #if !defined(lint)
   37 #if !defined(SMP)
   38 #error How did you get here?
   39 #endif
   40 
   41 #ifndef DEV_APIC
   42 #error The apic device is required for SMP, add "device apic" to your config file.
   43 #endif
   44 #if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT)
   45 #error SMP not supported with CPU_DISABLE_CMPXCHG
   46 #endif
   47 #endif /* not lint */
   48 
   49 #include <sys/param.h>
   50 #include <sys/systm.h>
   51 #include <sys/bus.h>
   52 #include <sys/cons.h>   /* cngetc() */
   53 #include <sys/cpuset.h>
   54 #ifdef GPROF 
   55 #include <sys/gmon.h>
   56 #endif
   57 #include <sys/kernel.h>
   58 #include <sys/ktr.h>
   59 #include <sys/lock.h>
   60 #include <sys/malloc.h>
   61 #include <sys/memrange.h>
   62 #include <sys/mutex.h>
   63 #include <sys/pcpu.h>
   64 #include <sys/proc.h>
   65 #include <sys/sched.h>
   66 #include <sys/smp.h>
   67 #include <sys/sysctl.h>
   68 
   69 #include <vm/vm.h>
   70 #include <vm/vm_param.h>
   71 #include <vm/pmap.h>
   72 #include <vm/vm_kern.h>
   73 #include <vm/vm_extern.h>
   74 
   75 #include <x86/apicreg.h>
   76 #include <machine/clock.h>
   77 #include <machine/cputypes.h>
   78 #include <x86/mca.h>
   79 #include <machine/md_var.h>
   80 #include <machine/pcb.h>
   81 #include <machine/psl.h>
   82 #include <machine/smp.h>
   83 #include <machine/specialreg.h>
   84 
   85 #define WARMBOOT_TARGET         0
   86 #define WARMBOOT_OFF            (KERNBASE + 0x0467)
   87 #define WARMBOOT_SEG            (KERNBASE + 0x0469)
   88 
   89 #define CMOS_REG                (0x70)
   90 #define CMOS_DATA               (0x71)
   91 #define BIOS_RESET              (0x0f)
   92 #define BIOS_WARM               (0x0a)
   93 
   94 /*
   95  * this code MUST be enabled here and in mpboot.s.
   96  * it follows the very early stages of AP boot by placing values in CMOS ram.
   97  * it NORMALLY will never be needed and thus the primitive method for enabling.
   98  *
   99 #define CHECK_POINTS
  100  */
  101 
  102 #if defined(CHECK_POINTS) && !defined(PC98)
  103 #define CHECK_READ(A)    (outb(CMOS_REG, (A)), inb(CMOS_DATA))
  104 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
  105 
  106 #define CHECK_INIT(D);                          \
  107         CHECK_WRITE(0x34, (D));                 \
  108         CHECK_WRITE(0x35, (D));                 \
  109         CHECK_WRITE(0x36, (D));                 \
  110         CHECK_WRITE(0x37, (D));                 \
  111         CHECK_WRITE(0x38, (D));                 \
  112         CHECK_WRITE(0x39, (D));
  113 
  114 #define CHECK_PRINT(S);                         \
  115         printf("%s: %d, %d, %d, %d, %d, %d\n",  \
  116            (S),                                 \
  117            CHECK_READ(0x34),                    \
  118            CHECK_READ(0x35),                    \
  119            CHECK_READ(0x36),                    \
  120            CHECK_READ(0x37),                    \
  121            CHECK_READ(0x38),                    \
  122            CHECK_READ(0x39));
  123 
  124 #else                           /* CHECK_POINTS */
  125 
  126 #define CHECK_INIT(D)
  127 #define CHECK_PRINT(S)
  128 #define CHECK_WRITE(A, D)
  129 
  130 #endif                          /* CHECK_POINTS */
  131 
  132 /* lock region used by kernel profiling */
  133 int     mcount_lock;
  134 
  135 int     mp_naps;                /* # of Applications processors */
  136 int     boot_cpu_id = -1;       /* designated BSP */
  137 
  138 extern  struct pcpu __pcpu[];
  139 
  140 /* AP uses this during bootstrap.  Do not staticize.  */
  141 char *bootSTK;
  142 static int bootAP;
  143 
  144 /* Free these after use */
  145 void *bootstacks[MAXCPU];
  146 static void *dpcpu;
  147 
  148 /* Hotwire a 0->4MB V==P mapping */
  149 extern pt_entry_t *KPTphys;
  150 
  151 struct pcb stoppcbs[MAXCPU];
  152 struct pcb **susppcbs = NULL;
  153 
  154 /* Variables needed for SMP tlb shootdown. */
  155 vm_offset_t smp_tlb_addr1;
  156 vm_offset_t smp_tlb_addr2;
  157 volatile int smp_tlb_wait;
  158 
  159 #ifdef COUNT_IPIS
  160 /* Interrupt counts. */
  161 static u_long *ipi_preempt_counts[MAXCPU];
  162 static u_long *ipi_ast_counts[MAXCPU];
  163 u_long *ipi_invltlb_counts[MAXCPU];
  164 u_long *ipi_invlrng_counts[MAXCPU];
  165 u_long *ipi_invlpg_counts[MAXCPU];
  166 u_long *ipi_invlcache_counts[MAXCPU];
  167 u_long *ipi_rendezvous_counts[MAXCPU];
  168 u_long *ipi_lazypmap_counts[MAXCPU];
  169 static u_long *ipi_hardclock_counts[MAXCPU];
  170 #endif
  171 
  172 /*
  173  * Local data and functions.
  174  */
  175 
  176 static volatile cpuset_t ipi_nmi_pending;
  177 
  178 /* used to hold the AP's until we are ready to release them */
  179 static struct mtx ap_boot_mtx;
  180 
  181 /* Set to 1 once we're ready to let the APs out of the pen. */
  182 static volatile int aps_ready = 0;
  183 
  184 /*
  185  * Store data from cpu_add() until later in the boot when we actually setup
  186  * the APs.
  187  */
  188 struct cpu_info {
  189         int     cpu_present:1;
  190         int     cpu_bsp:1;
  191         int     cpu_disabled:1;
  192         int     cpu_hyperthread:1;
  193 } static cpu_info[MAX_APIC_ID + 1];
  194 int cpu_apic_ids[MAXCPU];
  195 int apic_cpuids[MAX_APIC_ID + 1];
  196 
  197 /* Holds pending bitmap based IPIs per CPU */
  198 static volatile u_int cpu_ipi_pending[MAXCPU];
  199 
  200 static u_int boot_address;
  201 static int cpu_logical;                 /* logical cpus per core */
  202 static int cpu_cores;                   /* cores per package */
  203 
  204 static void     assign_cpu_ids(void);
  205 static void     install_ap_tramp(void);
  206 static void     set_interrupt_apic_ids(void);
  207 static int      start_all_aps(void);
  208 static int      start_ap(int apic_id);
  209 static void     release_aps(void *dummy);
  210 
  211 static u_int    hyperthreading_cpus;    /* logical cpus sharing L1 cache */
  212 static int      hyperthreading_allowed = 1;
  213 
  214 static void
  215 mem_range_AP_init(void)
  216 {
  217         if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
  218                 mem_range_softc.mr_op->initAP(&mem_range_softc);
  219 }
  220 
  221 static void
  222 topo_probe_amd(void)
  223 {
  224         int core_id_bits;
  225         int id;
  226 
  227         /* AMD processors do not support HTT. */
  228         cpu_logical = 1;
  229 
  230         if ((amd_feature2 & AMDID2_CMP) == 0) {
  231                 cpu_cores = 1;
  232                 return;
  233         }
  234 
  235         core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
  236             AMDID_COREID_SIZE_SHIFT;
  237         if (core_id_bits == 0) {
  238                 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
  239                 return;
  240         }
  241 
  242         /* Fam 10h and newer should get here. */
  243         for (id = 0; id <= MAX_APIC_ID; id++) {
  244                 /* Check logical CPU availability. */
  245                 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
  246                         continue;
  247                 /* Check if logical CPU has the same package ID. */
  248                 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits))
  249                         continue;
  250                 cpu_cores++;
  251         }
  252 }
  253 
  254 /*
  255  * Round up to the next power of two, if necessary, and then
  256  * take log2.
  257  * Returns -1 if argument is zero.
  258  */
  259 static __inline int
  260 mask_width(u_int x)
  261 {
  262 
  263         return (fls(x << (1 - powerof2(x))) - 1);
  264 }
  265 
  266 static void
  267 topo_probe_0x4(void)
  268 {
  269         u_int p[4];
  270         int pkg_id_bits;
  271         int core_id_bits;
  272         int max_cores;
  273         int max_logical;
  274         int id;
  275 
  276         /* Both zero and one here mean one logical processor per package. */
  277         max_logical = (cpu_feature & CPUID_HTT) != 0 ?
  278             (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
  279         if (max_logical <= 1)
  280                 return;
  281 
  282         /*
  283          * Because of uniformity assumption we examine only
  284          * those logical processors that belong to the same
  285          * package as BSP.  Further, we count number of
  286          * logical processors that belong to the same core
  287          * as BSP thus deducing number of threads per core.
  288          */
  289         if (cpu_high >= 0x4) {
  290                 cpuid_count(0x04, 0, p);
  291                 max_cores = ((p[0] >> 26) & 0x3f) + 1;
  292         } else
  293                 max_cores = 1;
  294         core_id_bits = mask_width(max_logical/max_cores);
  295         if (core_id_bits < 0)
  296                 return;
  297         pkg_id_bits = core_id_bits + mask_width(max_cores);
  298 
  299         for (id = 0; id <= MAX_APIC_ID; id++) {
  300                 /* Check logical CPU availability. */
  301                 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
  302                         continue;
  303                 /* Check if logical CPU has the same package ID. */
  304                 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits))
  305                         continue;
  306                 cpu_cores++;
  307                 /* Check if logical CPU has the same package and core IDs. */
  308                 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits))
  309                         cpu_logical++;
  310         }
  311 
  312         KASSERT(cpu_cores >= 1 && cpu_logical >= 1,
  313             ("topo_probe_0x4 couldn't find BSP"));
  314 
  315         cpu_cores /= cpu_logical;
  316         hyperthreading_cpus = cpu_logical;
  317 }
  318 
  319 static void
  320 topo_probe_0xb(void)
  321 {
  322         u_int p[4];
  323         int bits;
  324         int cnt;
  325         int i;
  326         int logical;
  327         int type;
  328         int x;
  329 
  330         /* We only support three levels for now. */
  331         for (i = 0; i < 3; i++) {
  332                 cpuid_count(0x0b, i, p);
  333 
  334                 /* Fall back if CPU leaf 11 doesn't really exist. */
  335                 if (i == 0 && p[1] == 0) {
  336                         topo_probe_0x4();
  337                         return;
  338                 }
  339 
  340                 bits = p[0] & 0x1f;
  341                 logical = p[1] &= 0xffff;
  342                 type = (p[2] >> 8) & 0xff;
  343                 if (type == 0 || logical == 0)
  344                         break;
  345                 /*
  346                  * Because of uniformity assumption we examine only
  347                  * those logical processors that belong to the same
  348                  * package as BSP.
  349                  */
  350                 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
  351                         if (!cpu_info[x].cpu_present ||
  352                             cpu_info[x].cpu_disabled)
  353                                 continue;
  354                         if (x >> bits == boot_cpu_id >> bits)
  355                                 cnt++;
  356                 }
  357                 if (type == CPUID_TYPE_SMT)
  358                         cpu_logical = cnt;
  359                 else if (type == CPUID_TYPE_CORE)
  360                         cpu_cores = cnt;
  361         }
  362         if (cpu_logical == 0)
  363                 cpu_logical = 1;
  364         cpu_cores /= cpu_logical;
  365 }
  366 
  367 /*
  368  * Both topology discovery code and code that consumes topology
  369  * information assume top-down uniformity of the topology.
  370  * That is, all physical packages must be identical and each
  371  * core in a package must have the same number of threads.
  372  * Topology information is queried only on BSP, on which this
  373  * code runs and for which it can query CPUID information.
  374  * Then topology is extrapolated on all packages using the
  375  * uniformity assumption.
  376  */
  377 static void
  378 topo_probe(void)
  379 {
  380         static int cpu_topo_probed = 0;
  381 
  382         if (cpu_topo_probed)
  383                 return;
  384 
  385         CPU_ZERO(&logical_cpus_mask);
  386         if (mp_ncpus <= 1)
  387                 cpu_cores = cpu_logical = 1;
  388         else if (cpu_vendor_id == CPU_VENDOR_AMD)
  389                 topo_probe_amd();
  390         else if (cpu_vendor_id == CPU_VENDOR_INTEL) {
  391                 /*
  392                  * See Intel(R) 64 Architecture Processor
  393                  * Topology Enumeration article for details.
  394                  *
  395                  * Note that 0x1 <= cpu_high < 4 case should be
  396                  * compatible with topo_probe_0x4() logic when
  397                  * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
  398                  * or it should trigger the fallback otherwise.
  399                  */
  400                 if (cpu_high >= 0xb)
  401                         topo_probe_0xb();
  402                 else if (cpu_high >= 0x1)
  403                         topo_probe_0x4();
  404         }
  405 
  406         /*
  407          * Fallback: assume each logical CPU is in separate
  408          * physical package.  That is, no multi-core, no SMT.
  409          */
  410         if (cpu_cores == 0 || cpu_logical == 0)
  411                 cpu_cores = cpu_logical = 1;
  412         cpu_topo_probed = 1;
  413 }
  414 
  415 struct cpu_group *
  416 cpu_topo(void)
  417 {
  418         int cg_flags;
  419 
  420         /*
  421          * Determine whether any threading flags are
  422          * necessry.
  423          */
  424         topo_probe();
  425         if (cpu_logical > 1 && hyperthreading_cpus)
  426                 cg_flags = CG_FLAG_HTT;
  427         else if (cpu_logical > 1)
  428                 cg_flags = CG_FLAG_SMT;
  429         else
  430                 cg_flags = 0;
  431         if (mp_ncpus % (cpu_cores * cpu_logical) != 0) {
  432                 printf("WARNING: Non-uniform processors.\n");
  433                 printf("WARNING: Using suboptimal topology.\n");
  434                 return (smp_topo_none());
  435         }
  436         /*
  437          * No multi-core or hyper-threaded.
  438          */
  439         if (cpu_logical * cpu_cores == 1)
  440                 return (smp_topo_none());
  441         /*
  442          * Only HTT no multi-core.
  443          */
  444         if (cpu_logical > 1 && cpu_cores == 1)
  445                 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags));
  446         /*
  447          * Only multi-core no HTT.
  448          */
  449         if (cpu_cores > 1 && cpu_logical == 1)
  450                 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags));
  451         /*
  452          * Both HTT and multi-core.
  453          */
  454         return (smp_topo_2level(CG_SHARE_L2, cpu_cores,
  455             CG_SHARE_L1, cpu_logical, cg_flags));
  456 }
  457 
  458 
  459 /*
  460  * Calculate usable address in base memory for AP trampoline code.
  461  */
  462 u_int
  463 mp_bootaddress(u_int basemem)
  464 {
  465 
  466         boot_address = trunc_page(basemem);     /* round down to 4k boundary */
  467         if ((basemem - boot_address) < bootMP_size)
  468                 boot_address -= PAGE_SIZE;      /* not enough, lower by 4k */
  469 
  470         return boot_address;
  471 }
  472 
  473 void
  474 cpu_add(u_int apic_id, char boot_cpu)
  475 {
  476 
  477         if (apic_id > MAX_APIC_ID) {
  478                 panic("SMP: APIC ID %d too high", apic_id);
  479                 return;
  480         }
  481         KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
  482             apic_id));
  483         cpu_info[apic_id].cpu_present = 1;
  484         if (boot_cpu) {
  485                 KASSERT(boot_cpu_id == -1,
  486                     ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
  487                     boot_cpu_id));
  488                 boot_cpu_id = apic_id;
  489                 cpu_info[apic_id].cpu_bsp = 1;
  490         }
  491         if (mp_ncpus < MAXCPU) {
  492                 mp_ncpus++;
  493                 mp_maxid = mp_ncpus - 1;
  494         }
  495         if (bootverbose)
  496                 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
  497                     "AP");
  498 }
  499 
  500 void
  501 cpu_mp_setmaxid(void)
  502 {
  503 
  504         /*
  505          * mp_maxid should be already set by calls to cpu_add().
  506          * Just sanity check its value here.
  507          */
  508         if (mp_ncpus == 0)
  509                 KASSERT(mp_maxid == 0,
  510                     ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
  511         else if (mp_ncpus == 1)
  512                 mp_maxid = 0;
  513         else
  514                 KASSERT(mp_maxid >= mp_ncpus - 1,
  515                     ("%s: counters out of sync: max %d, count %d", __func__,
  516                         mp_maxid, mp_ncpus));
  517 }
  518 
  519 int
  520 cpu_mp_probe(void)
  521 {
  522 
  523         /*
  524          * Always record BSP in CPU map so that the mbuf init code works
  525          * correctly.
  526          */
  527         CPU_SETOF(0, &all_cpus);
  528         if (mp_ncpus == 0) {
  529                 /*
  530                  * No CPUs were found, so this must be a UP system.  Setup
  531                  * the variables to represent a system with a single CPU
  532                  * with an id of 0.
  533                  */
  534                 mp_ncpus = 1;
  535                 return (0);
  536         }
  537 
  538         /* At least one CPU was found. */
  539         if (mp_ncpus == 1) {
  540                 /*
  541                  * One CPU was found, so this must be a UP system with
  542                  * an I/O APIC.
  543                  */
  544                 mp_maxid = 0;
  545                 return (0);
  546         }
  547 
  548         /* At least two CPUs were found. */
  549         return (1);
  550 }
  551 
  552 /*
  553  * Initialize the IPI handlers and start up the AP's.
  554  */
  555 void
  556 cpu_mp_start(void)
  557 {
  558         int i;
  559 
  560         /* Initialize the logical ID to APIC ID table. */
  561         for (i = 0; i < MAXCPU; i++) {
  562                 cpu_apic_ids[i] = -1;
  563                 cpu_ipi_pending[i] = 0;
  564         }
  565 
  566         /* Install an inter-CPU IPI for TLB invalidation */
  567         setidt(IPI_INVLTLB, IDTVEC(invltlb),
  568                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  569         setidt(IPI_INVLPG, IDTVEC(invlpg),
  570                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  571         setidt(IPI_INVLRNG, IDTVEC(invlrng),
  572                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  573 
  574         /* Install an inter-CPU IPI for cache invalidation. */
  575         setidt(IPI_INVLCACHE, IDTVEC(invlcache),
  576                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  577 
  578         /* Install an inter-CPU IPI for lazy pmap release */
  579         setidt(IPI_LAZYPMAP, IDTVEC(lazypmap),
  580                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  581 
  582         /* Install an inter-CPU IPI for all-CPU rendezvous */
  583         setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous),
  584                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  585 
  586         /* Install generic inter-CPU IPI handler */
  587         setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
  588                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  589 
  590         /* Install an inter-CPU IPI for CPU stop/restart */
  591         setidt(IPI_STOP, IDTVEC(cpustop),
  592                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  593 
  594         /* Install an inter-CPU IPI for CPU suspend/resume */
  595         setidt(IPI_SUSPEND, IDTVEC(cpususpend),
  596                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  597 
  598         /* Set boot_cpu_id if needed. */
  599         if (boot_cpu_id == -1) {
  600                 boot_cpu_id = PCPU_GET(apic_id);
  601                 cpu_info[boot_cpu_id].cpu_bsp = 1;
  602         } else
  603                 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
  604                     ("BSP's APIC ID doesn't match boot_cpu_id"));
  605 
  606         /* Probe logical/physical core configuration. */
  607         topo_probe();
  608 
  609         assign_cpu_ids();
  610 
  611         /* Start each Application Processor */
  612         start_all_aps();
  613 
  614         set_interrupt_apic_ids();
  615 }
  616 
  617 
  618 /*
  619  * Print various information about the SMP system hardware and setup.
  620  */
  621 void
  622 cpu_mp_announce(void)
  623 {
  624         const char *hyperthread;
  625         int i;
  626 
  627         printf("FreeBSD/SMP: %d package(s) x %d core(s)",
  628             mp_ncpus / (cpu_cores * cpu_logical), cpu_cores);
  629         if (hyperthreading_cpus > 1)
  630             printf(" x %d HTT threads", cpu_logical);
  631         else if (cpu_logical > 1)
  632             printf(" x %d SMT threads", cpu_logical);
  633         printf("\n");
  634 
  635         /* List active CPUs first. */
  636         printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
  637         for (i = 1; i < mp_ncpus; i++) {
  638                 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
  639                         hyperthread = "/HT";
  640                 else
  641                         hyperthread = "";
  642                 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
  643                     cpu_apic_ids[i]);
  644         }
  645 
  646         /* List disabled CPUs last. */
  647         for (i = 0; i <= MAX_APIC_ID; i++) {
  648                 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
  649                         continue;
  650                 if (cpu_info[i].cpu_hyperthread)
  651                         hyperthread = "/HT";
  652                 else
  653                         hyperthread = "";
  654                 printf("  cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
  655                     i);
  656         }
  657 }
  658 
  659 /*
  660  * AP CPU's call this to initialize themselves.
  661  */
  662 void
  663 init_secondary(void)
  664 {
  665         struct pcpu *pc;
  666         vm_offset_t addr;
  667         int     gsel_tss;
  668         int     x, myid;
  669         u_int   cpuid, cr0;
  670 
  671         /* bootAP is set in start_ap() to our ID. */
  672         myid = bootAP;
  673 
  674         /* Get per-cpu data */
  675         pc = &__pcpu[myid];
  676 
  677         /* prime data page for it to use */
  678         pcpu_init(pc, myid, sizeof(struct pcpu));
  679         dpcpu_init(dpcpu, myid);
  680         pc->pc_apic_id = cpu_apic_ids[myid];
  681         pc->pc_prvspace = pc;
  682         pc->pc_curthread = 0;
  683 
  684         gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
  685         gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
  686 
  687         for (x = 0; x < NGDT; x++) {
  688                 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
  689         }
  690 
  691         r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
  692         r_gdt.rd_base = (int) &gdt[myid * NGDT];
  693         lgdt(&r_gdt);                   /* does magic intra-segment return */
  694 
  695         lidt(&r_idt);
  696 
  697         lldt(_default_ldt);
  698         PCPU_SET(currentldt, _default_ldt);
  699 
  700         gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
  701         gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
  702         PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
  703         PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
  704         PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
  705         PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
  706         PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
  707         ltr(gsel_tss);
  708 
  709         PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd);
  710 
  711         /*
  712          * Set to a known state:
  713          * Set by mpboot.s: CR0_PG, CR0_PE
  714          * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
  715          */
  716         cr0 = rcr0();
  717         cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
  718         load_cr0(cr0);
  719         CHECK_WRITE(0x38, 5);
  720         
  721         /* Disable local APIC just to be sure. */
  722         lapic_disable();
  723 
  724         /* signal our startup to the BSP. */
  725         mp_naps++;
  726         CHECK_WRITE(0x39, 6);
  727 
  728         /* Spin until the BSP releases the AP's. */
  729         while (!aps_ready)
  730                 ia32_pause();
  731 
  732         /* BSP may have changed PTD while we were waiting */
  733         invltlb();
  734         for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE)
  735                 invlpg(addr);
  736 
  737 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
  738         lidt(&r_idt);
  739 #endif
  740 
  741         /* Initialize the PAT MSR if present. */
  742         pmap_init_pat();
  743 
  744         /* set up CPU registers and state */
  745         cpu_setregs();
  746 
  747         /* set up FPU state on the AP */
  748         npxinit();
  749 
  750         /* set up SSE registers */
  751         enable_sse();
  752 
  753 #ifdef PAE
  754         /* Enable the PTE no-execute bit. */
  755         if ((amd_feature & AMDID_NX) != 0) {
  756                 uint64_t msr;
  757 
  758                 msr = rdmsr(MSR_EFER) | EFER_NXE;
  759                 wrmsr(MSR_EFER, msr);
  760         }
  761 #endif
  762 
  763         /* A quick check from sanity claus */
  764         cpuid = PCPU_GET(cpuid);
  765         if (PCPU_GET(apic_id) != lapic_id()) {
  766                 printf("SMP: cpuid = %d\n", cpuid);
  767                 printf("SMP: actual apic_id = %d\n", lapic_id());
  768                 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
  769                 panic("cpuid mismatch! boom!!");
  770         }
  771 
  772         /* Initialize curthread. */
  773         KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
  774         PCPU_SET(curthread, PCPU_GET(idlethread));
  775 
  776         mca_init();
  777 
  778         mtx_lock_spin(&ap_boot_mtx);
  779 
  780         /* Init local apic for irq's */
  781         lapic_setup(1);
  782 
  783         /* Set memory range attributes for this CPU to match the BSP */
  784         mem_range_AP_init();
  785 
  786         smp_cpus++;
  787 
  788         CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
  789         printf("SMP: AP CPU #%d Launched!\n", cpuid);
  790 
  791         /* Determine if we are a logical CPU. */
  792         /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */
  793         if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0)
  794                 CPU_SET(cpuid, &logical_cpus_mask);
  795 
  796         if (bootverbose)
  797                 lapic_dump("AP");
  798 
  799         if (smp_cpus == mp_ncpus) {
  800                 /* enable IPI's, tlb shootdown, freezes etc */
  801                 atomic_store_rel_int(&smp_started, 1);
  802                 smp_active = 1;  /* historic */
  803         }
  804 
  805         mtx_unlock_spin(&ap_boot_mtx);
  806 
  807         /* Wait until all the AP's are up. */
  808         while (smp_started == 0)
  809                 ia32_pause();
  810 
  811         /* Start per-CPU event timers. */
  812         cpu_initclocks_ap();
  813 
  814         /* Enter the scheduler. */
  815         sched_throw(NULL);
  816 
  817         panic("scheduler returned us to %s", __func__);
  818         /* NOTREACHED */
  819 }
  820 
  821 /*******************************************************************
  822  * local functions and data
  823  */
  824 
  825 /*
  826  * We tell the I/O APIC code about all the CPUs we want to receive
  827  * interrupts.  If we don't want certain CPUs to receive IRQs we
  828  * can simply not tell the I/O APIC code about them in this function.
  829  */
  830 static void
  831 set_interrupt_apic_ids(void)
  832 {
  833         u_int i, apic_id;
  834 
  835         for (i = 0; i < MAXCPU; i++) {
  836                 apic_id = cpu_apic_ids[i];
  837                 if (apic_id == -1)
  838                         continue;
  839                 if (cpu_info[apic_id].cpu_disabled)
  840                         continue;
  841 
  842                 /* Don't let hyperthreads service interrupts. */
  843                 if (hyperthreading_cpus > 1 &&
  844                     apic_id % hyperthreading_cpus != 0)
  845                         continue;
  846 
  847                 intr_add_cpu(i);
  848         }
  849 }
  850 
  851 /*
  852  * Assign logical CPU IDs to local APICs.
  853  */
  854 static void
  855 assign_cpu_ids(void)
  856 {
  857         u_int i;
  858 
  859         TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
  860             &hyperthreading_allowed);
  861 
  862         /* Check for explicitly disabled CPUs. */
  863         for (i = 0; i <= MAX_APIC_ID; i++) {
  864                 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
  865                         continue;
  866 
  867                 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
  868                         cpu_info[i].cpu_hyperthread = 1;
  869 
  870                         /*
  871                          * Don't use HT CPU if it has been disabled by a
  872                          * tunable.
  873                          */
  874                         if (hyperthreading_allowed == 0) {
  875                                 cpu_info[i].cpu_disabled = 1;
  876                                 continue;
  877                         }
  878                 }
  879 
  880                 /* Don't use this CPU if it has been disabled by a tunable. */
  881                 if (resource_disabled("lapic", i)) {
  882                         cpu_info[i].cpu_disabled = 1;
  883                         continue;
  884                 }
  885         }
  886 
  887         if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) {
  888                 hyperthreading_cpus = 0;
  889                 cpu_logical = 1;
  890         }
  891 
  892         /*
  893          * Assign CPU IDs to local APIC IDs and disable any CPUs
  894          * beyond MAXCPU.  CPU 0 is always assigned to the BSP.
  895          *
  896          * To minimize confusion for userland, we attempt to number
  897          * CPUs such that all threads and cores in a package are
  898          * grouped together.  For now we assume that the BSP is always
  899          * the first thread in a package and just start adding APs
  900          * starting with the BSP's APIC ID.
  901          */
  902         mp_ncpus = 1;
  903         cpu_apic_ids[0] = boot_cpu_id;
  904         apic_cpuids[boot_cpu_id] = 0;
  905         for (i = boot_cpu_id + 1; i != boot_cpu_id;
  906              i == MAX_APIC_ID ? i = 0 : i++) {
  907                 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
  908                     cpu_info[i].cpu_disabled)
  909                         continue;
  910 
  911                 if (mp_ncpus < MAXCPU) {
  912                         cpu_apic_ids[mp_ncpus] = i;
  913                         apic_cpuids[i] = mp_ncpus;
  914                         mp_ncpus++;
  915                 } else
  916                         cpu_info[i].cpu_disabled = 1;
  917         }
  918         KASSERT(mp_maxid >= mp_ncpus - 1,
  919             ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
  920             mp_ncpus));         
  921 }
  922 
  923 /*
  924  * start each AP in our list
  925  */
  926 /* Lowest 1MB is already mapped: don't touch*/
  927 #define TMPMAP_START 1
  928 static int
  929 start_all_aps(void)
  930 {
  931 #ifndef PC98
  932         u_char mpbiosreason;
  933 #endif
  934         uintptr_t kptbase;
  935         u_int32_t mpbioswarmvec;
  936         int apic_id, cpu, i;
  937 
  938         mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
  939 
  940         /* install the AP 1st level boot code */
  941         install_ap_tramp();
  942 
  943         /* save the current value of the warm-start vector */
  944         mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
  945 #ifndef PC98
  946         outb(CMOS_REG, BIOS_RESET);
  947         mpbiosreason = inb(CMOS_DATA);
  948 #endif
  949 
  950         /* set up temporary P==V mapping for AP boot */
  951         /* XXX this is a hack, we should boot the AP on its own stack/PTD */
  952 
  953         kptbase = (uintptr_t)(void *)KPTphys;
  954         for (i = TMPMAP_START; i < NKPT; i++)
  955                 PTD[i] = (pd_entry_t)(PG_V | PG_RW |
  956                     ((kptbase + i * PAGE_SIZE) & PG_FRAME));
  957         invltlb();
  958 
  959         /* start each AP */
  960         for (cpu = 1; cpu < mp_ncpus; cpu++) {
  961                 apic_id = cpu_apic_ids[cpu];
  962 
  963                 /* allocate and set up a boot stack data page */
  964                 bootstacks[cpu] =
  965                     (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
  966                 dpcpu = (void *)kmem_alloc(kernel_map, DPCPU_SIZE);
  967                 /* setup a vector to our boot code */
  968                 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
  969                 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
  970 #ifndef PC98
  971                 outb(CMOS_REG, BIOS_RESET);
  972                 outb(CMOS_DATA, BIOS_WARM);     /* 'warm-start' */
  973 #endif
  974 
  975                 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4;
  976                 bootAP = cpu;
  977 
  978                 /* attempt to start the Application Processor */
  979                 CHECK_INIT(99); /* setup checkpoints */
  980                 if (!start_ap(apic_id)) {
  981                         printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id);
  982                         CHECK_PRINT("trace");   /* show checkpoints */
  983                         /* better panic as the AP may be running loose */
  984                         printf("panic y/n? [y] ");
  985                         if (cngetc() != 'n')
  986                                 panic("bye-bye");
  987                 }
  988                 CHECK_PRINT("trace");           /* show checkpoints */
  989 
  990                 CPU_SET(cpu, &all_cpus);        /* record AP in CPU map */
  991         }
  992 
  993         /* restore the warmstart vector */
  994         *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
  995 
  996 #ifndef PC98
  997         outb(CMOS_REG, BIOS_RESET);
  998         outb(CMOS_DATA, mpbiosreason);
  999 #endif
 1000 
 1001         /* Undo V==P hack from above */
 1002         for (i = TMPMAP_START; i < NKPT; i++)
 1003                 PTD[i] = 0;
 1004         pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1);
 1005 
 1006         /* number of APs actually started */
 1007         return mp_naps;
 1008 }
 1009 
 1010 /*
 1011  * load the 1st level AP boot code into base memory.
 1012  */
 1013 
 1014 /* targets for relocation */
 1015 extern void bigJump(void);
 1016 extern void bootCodeSeg(void);
 1017 extern void bootDataSeg(void);
 1018 extern void MPentry(void);
 1019 extern u_int MP_GDT;
 1020 extern u_int mp_gdtbase;
 1021 
 1022 static void
 1023 install_ap_tramp(void)
 1024 {
 1025         int     x;
 1026         int     size = *(int *) ((u_long) & bootMP_size);
 1027         vm_offset_t va = boot_address + KERNBASE;
 1028         u_char *src = (u_char *) ((u_long) bootMP);
 1029         u_char *dst = (u_char *) va;
 1030         u_int   boot_base = (u_int) bootMP;
 1031         u_int8_t *dst8;
 1032         u_int16_t *dst16;
 1033         u_int32_t *dst32;
 1034 
 1035         KASSERT (size <= PAGE_SIZE,
 1036             ("'size' do not fit into PAGE_SIZE, as expected."));
 1037         pmap_kenter(va, boot_address);
 1038         pmap_invalidate_page (kernel_pmap, va);
 1039         for (x = 0; x < size; ++x)
 1040                 *dst++ = *src++;
 1041 
 1042         /*
 1043          * modify addresses in code we just moved to basemem. unfortunately we
 1044          * need fairly detailed info about mpboot.s for this to work.  changes
 1045          * to mpboot.s might require changes here.
 1046          */
 1047 
 1048         /* boot code is located in KERNEL space */
 1049         dst = (u_char *) va;
 1050 
 1051         /* modify the lgdt arg */
 1052         dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
 1053         *dst32 = boot_address + ((u_int) & MP_GDT - boot_base);
 1054 
 1055         /* modify the ljmp target for MPentry() */
 1056         dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
 1057         *dst32 = ((u_int) MPentry - KERNBASE);
 1058 
 1059         /* modify the target for boot code segment */
 1060         dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
 1061         dst8 = (u_int8_t *) (dst16 + 1);
 1062         *dst16 = (u_int) boot_address & 0xffff;
 1063         *dst8 = ((u_int) boot_address >> 16) & 0xff;
 1064 
 1065         /* modify the target for boot data segment */
 1066         dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
 1067         dst8 = (u_int8_t *) (dst16 + 1);
 1068         *dst16 = (u_int) boot_address & 0xffff;
 1069         *dst8 = ((u_int) boot_address >> 16) & 0xff;
 1070 }
 1071 
 1072 /*
 1073  * This function starts the AP (application processor) identified
 1074  * by the APIC ID 'physicalCpu'.  It does quite a "song and dance"
 1075  * to accomplish this.  This is necessary because of the nuances
 1076  * of the different hardware we might encounter.  It isn't pretty,
 1077  * but it seems to work.
 1078  */
 1079 static int
 1080 start_ap(int apic_id)
 1081 {
 1082         int vector, ms;
 1083         int cpus;
 1084 
 1085         /* calculate the vector */
 1086         vector = (boot_address >> 12) & 0xff;
 1087 
 1088         /* used as a watchpoint to signal AP startup */
 1089         cpus = mp_naps;
 1090 
 1091         /*
 1092          * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
 1093          * and running the target CPU. OR this INIT IPI might be latched (P5
 1094          * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
 1095          * ignored.
 1096          */
 1097 
 1098         /* do an INIT IPI: assert RESET */
 1099         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
 1100             APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
 1101 
 1102         /* wait for pending status end */
 1103         lapic_ipi_wait(-1);
 1104 
 1105         /* do an INIT IPI: deassert RESET */
 1106         lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
 1107             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
 1108 
 1109         /* wait for pending status end */
 1110         DELAY(10000);           /* wait ~10mS */
 1111         lapic_ipi_wait(-1);
 1112 
 1113         /*
 1114          * next we do a STARTUP IPI: the previous INIT IPI might still be
 1115          * latched, (P5 bug) this 1st STARTUP would then terminate
 1116          * immediately, and the previously started INIT IPI would continue. OR
 1117          * the previous INIT IPI has already run. and this STARTUP IPI will
 1118          * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
 1119          * will run.
 1120          */
 1121 
 1122         /* do a STARTUP IPI */
 1123         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
 1124             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
 1125             vector, apic_id);
 1126         lapic_ipi_wait(-1);
 1127         DELAY(200);             /* wait ~200uS */
 1128 
 1129         /*
 1130          * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
 1131          * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
 1132          * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
 1133          * recognized after hardware RESET or INIT IPI.
 1134          */
 1135 
 1136         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
 1137             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
 1138             vector, apic_id);
 1139         lapic_ipi_wait(-1);
 1140         DELAY(200);             /* wait ~200uS */
 1141 
 1142         /* Wait up to 5 seconds for it to start. */
 1143         for (ms = 0; ms < 5000; ms++) {
 1144                 if (mp_naps > cpus)
 1145                         return 1;       /* return SUCCESS */
 1146                 DELAY(1000);
 1147         }
 1148         return 0;               /* return FAILURE */
 1149 }
 1150 
 1151 #ifdef COUNT_XINVLTLB_HITS
 1152 u_int xhits_gbl[MAXCPU];
 1153 u_int xhits_pg[MAXCPU];
 1154 u_int xhits_rng[MAXCPU];
 1155 SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
 1156 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
 1157     sizeof(xhits_gbl), "IU", "");
 1158 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
 1159     sizeof(xhits_pg), "IU", "");
 1160 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
 1161     sizeof(xhits_rng), "IU", "");
 1162 
 1163 u_int ipi_global;
 1164 u_int ipi_page;
 1165 u_int ipi_range;
 1166 u_int ipi_range_size;
 1167 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
 1168 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
 1169 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
 1170 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
 1171     0, "");
 1172 
 1173 u_int ipi_masked_global;
 1174 u_int ipi_masked_page;
 1175 u_int ipi_masked_range;
 1176 u_int ipi_masked_range_size;
 1177 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
 1178     &ipi_masked_global, 0, "");
 1179 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
 1180     &ipi_masked_page, 0, "");
 1181 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
 1182     &ipi_masked_range, 0, "");
 1183 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
 1184     &ipi_masked_range_size, 0, "");
 1185 #endif /* COUNT_XINVLTLB_HITS */
 1186 
 1187 /*
 1188  * Send an IPI to specified CPU handling the bitmap logic.
 1189  */
 1190 static void
 1191 ipi_send_cpu(int cpu, u_int ipi)
 1192 {
 1193         u_int bitmap, old_pending, new_pending;
 1194 
 1195         KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
 1196 
 1197         if (IPI_IS_BITMAPED(ipi)) {
 1198                 bitmap = 1 << ipi;
 1199                 ipi = IPI_BITMAP_VECTOR;
 1200                 do {
 1201                         old_pending = cpu_ipi_pending[cpu];
 1202                         new_pending = old_pending | bitmap;
 1203                 } while  (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
 1204                     old_pending, new_pending)); 
 1205                 if (old_pending)
 1206                         return;
 1207         }
 1208         lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
 1209 }
 1210 
 1211 /*
 1212  * Flush the TLB on all other CPU's
 1213  */
 1214 static void
 1215 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
 1216 {
 1217         u_int ncpu;
 1218 
 1219         ncpu = mp_ncpus - 1;    /* does not shootdown self */
 1220         if (ncpu < 1)
 1221                 return;         /* no other cpus */
 1222         if (!(read_eflags() & PSL_I))
 1223                 panic("%s: interrupts disabled", __func__);
 1224         mtx_lock_spin(&smp_ipi_mtx);
 1225         smp_tlb_addr1 = addr1;
 1226         smp_tlb_addr2 = addr2;
 1227         atomic_store_rel_int(&smp_tlb_wait, 0);
 1228         ipi_all_but_self(vector);
 1229         while (smp_tlb_wait < ncpu)
 1230                 ia32_pause();
 1231         mtx_unlock_spin(&smp_ipi_mtx);
 1232 }
 1233 
 1234 static void
 1235 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
 1236 {
 1237         int cpu, ncpu, othercpus;
 1238 
 1239         othercpus = mp_ncpus - 1;
 1240         if (CPU_ISFULLSET(&mask)) {
 1241                 if (othercpus < 1)
 1242                         return;
 1243         } else {
 1244                 CPU_CLR(PCPU_GET(cpuid), &mask);
 1245                 if (CPU_EMPTY(&mask))
 1246                         return;
 1247         }
 1248         if (!(read_eflags() & PSL_I))
 1249                 panic("%s: interrupts disabled", __func__);
 1250         mtx_lock_spin(&smp_ipi_mtx);
 1251         smp_tlb_addr1 = addr1;
 1252         smp_tlb_addr2 = addr2;
 1253         atomic_store_rel_int(&smp_tlb_wait, 0);
 1254         if (CPU_ISFULLSET(&mask)) {
 1255                 ncpu = othercpus;
 1256                 ipi_all_but_self(vector);
 1257         } else {
 1258                 ncpu = 0;
 1259                 while ((cpu = cpusetobj_ffs(&mask)) != 0) {
 1260                         cpu--;
 1261                         CPU_CLR(cpu, &mask);
 1262                         CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu,
 1263                             vector);
 1264                         ipi_send_cpu(cpu, vector);
 1265                         ncpu++;
 1266                 }
 1267         }
 1268         while (smp_tlb_wait < ncpu)
 1269                 ia32_pause();
 1270         mtx_unlock_spin(&smp_ipi_mtx);
 1271 }
 1272 
 1273 void
 1274 smp_cache_flush(void)
 1275 {
 1276 
 1277         if (smp_started)
 1278                 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
 1279 }
 1280 
 1281 void
 1282 smp_invltlb(void)
 1283 {
 1284 
 1285         if (smp_started) {
 1286                 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
 1287 #ifdef COUNT_XINVLTLB_HITS
 1288                 ipi_global++;
 1289 #endif
 1290         }
 1291 }
 1292 
 1293 void
 1294 smp_invlpg(vm_offset_t addr)
 1295 {
 1296 
 1297         if (smp_started) {
 1298                 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
 1299 #ifdef COUNT_XINVLTLB_HITS
 1300                 ipi_page++;
 1301 #endif
 1302         }
 1303 }
 1304 
 1305 void
 1306 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
 1307 {
 1308 
 1309         if (smp_started) {
 1310                 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
 1311 #ifdef COUNT_XINVLTLB_HITS
 1312                 ipi_range++;
 1313                 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
 1314 #endif
 1315         }
 1316 }
 1317 
 1318 void
 1319 smp_masked_invltlb(cpuset_t mask)
 1320 {
 1321 
 1322         if (smp_started) {
 1323                 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
 1324 #ifdef COUNT_XINVLTLB_HITS
 1325                 ipi_masked_global++;
 1326 #endif
 1327         }
 1328 }
 1329 
 1330 void
 1331 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr)
 1332 {
 1333 
 1334         if (smp_started) {
 1335                 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
 1336 #ifdef COUNT_XINVLTLB_HITS
 1337                 ipi_masked_page++;
 1338 #endif
 1339         }
 1340 }
 1341 
 1342 void
 1343 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2)
 1344 {
 1345 
 1346         if (smp_started) {
 1347                 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
 1348 #ifdef COUNT_XINVLTLB_HITS
 1349                 ipi_masked_range++;
 1350                 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
 1351 #endif
 1352         }
 1353 }
 1354 
 1355 void
 1356 ipi_bitmap_handler(struct trapframe frame)
 1357 {
 1358         struct trapframe *oldframe;
 1359         struct thread *td;
 1360         int cpu = PCPU_GET(cpuid);
 1361         u_int ipi_bitmap;
 1362 
 1363         critical_enter();
 1364         td = curthread;
 1365         td->td_intr_nesting_level++;
 1366         oldframe = td->td_intr_frame;
 1367         td->td_intr_frame = &frame;
 1368         ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
 1369         if (ipi_bitmap & (1 << IPI_PREEMPT)) {
 1370 #ifdef COUNT_IPIS
 1371                 (*ipi_preempt_counts[cpu])++;
 1372 #endif
 1373                 sched_preempt(td);
 1374         }
 1375         if (ipi_bitmap & (1 << IPI_AST)) {
 1376 #ifdef COUNT_IPIS
 1377                 (*ipi_ast_counts[cpu])++;
 1378 #endif
 1379                 /* Nothing to do for AST */
 1380         }
 1381         if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
 1382 #ifdef COUNT_IPIS
 1383                 (*ipi_hardclock_counts[cpu])++;
 1384 #endif
 1385                 hardclockintr();
 1386         }
 1387         td->td_intr_frame = oldframe;
 1388         td->td_intr_nesting_level--;
 1389         critical_exit();
 1390 }
 1391 
 1392 /*
 1393  * send an IPI to a set of cpus.
 1394  */
 1395 void
 1396 ipi_selected(cpuset_t cpus, u_int ipi)
 1397 {
 1398         int cpu;
 1399 
 1400         /*
 1401          * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
 1402          * of help in order to understand what is the source.
 1403          * Set the mask of receiving CPUs for this purpose.
 1404          */
 1405         if (ipi == IPI_STOP_HARD)
 1406                 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus);
 1407 
 1408         while ((cpu = cpusetobj_ffs(&cpus)) != 0) {
 1409                 cpu--;
 1410                 CPU_CLR(cpu, &cpus);
 1411                 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
 1412                 ipi_send_cpu(cpu, ipi);
 1413         }
 1414 }
 1415 
 1416 /*
 1417  * send an IPI to a specific CPU.
 1418  */
 1419 void
 1420 ipi_cpu(int cpu, u_int ipi)
 1421 {
 1422 
 1423         /*
 1424          * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
 1425          * of help in order to understand what is the source.
 1426          * Set the mask of receiving CPUs for this purpose.
 1427          */
 1428         if (ipi == IPI_STOP_HARD)
 1429                 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending);
 1430 
 1431         CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
 1432         ipi_send_cpu(cpu, ipi);
 1433 }
 1434 
 1435 /*
 1436  * send an IPI to all CPUs EXCEPT myself
 1437  */
 1438 void
 1439 ipi_all_but_self(u_int ipi)
 1440 {
 1441         cpuset_t other_cpus;
 1442 
 1443         other_cpus = all_cpus;
 1444         CPU_CLR(PCPU_GET(cpuid), &other_cpus);
 1445         if (IPI_IS_BITMAPED(ipi)) {
 1446                 ipi_selected(other_cpus, ipi);
 1447                 return;
 1448         }
 1449 
 1450         /*
 1451          * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
 1452          * of help in order to understand what is the source.
 1453          * Set the mask of receiving CPUs for this purpose.
 1454          */
 1455         if (ipi == IPI_STOP_HARD)
 1456                 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus);
 1457 
 1458         CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
 1459         lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
 1460 }
 1461 
 1462 int
 1463 ipi_nmi_handler()
 1464 {
 1465         u_int cpuid;
 1466 
 1467         /*
 1468          * As long as there is not a simple way to know about a NMI's
 1469          * source, if the bitmask for the current CPU is present in
 1470          * the global pending bitword an IPI_STOP_HARD has been issued
 1471          * and should be handled.
 1472          */
 1473         cpuid = PCPU_GET(cpuid);
 1474         if (!CPU_ISSET(cpuid, &ipi_nmi_pending))
 1475                 return (1);
 1476 
 1477         CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending);
 1478         cpustop_handler();
 1479         return (0);
 1480 }
 1481 
 1482 /*
 1483  * Handle an IPI_STOP by saving our current context and spinning until we
 1484  * are resumed.
 1485  */
 1486 void
 1487 cpustop_handler(void)
 1488 {
 1489         u_int cpu;
 1490 
 1491         cpu = PCPU_GET(cpuid);
 1492 
 1493         savectx(&stoppcbs[cpu]);
 1494 
 1495         /* Indicate that we are stopped */
 1496         CPU_SET_ATOMIC(cpu, &stopped_cpus);
 1497 
 1498         /* Wait for restart */
 1499         while (!CPU_ISSET(cpu, &started_cpus))
 1500             ia32_pause();
 1501 
 1502         CPU_CLR_ATOMIC(cpu, &started_cpus);
 1503         CPU_CLR_ATOMIC(cpu, &stopped_cpus);
 1504 
 1505         if (cpu == 0 && cpustop_restartfunc != NULL) {
 1506                 cpustop_restartfunc();
 1507                 cpustop_restartfunc = NULL;
 1508         }
 1509 }
 1510 
 1511 /*
 1512  * Handle an IPI_SUSPEND by saving our current context and spinning until we
 1513  * are resumed.
 1514  */
 1515 void
 1516 cpususpend_handler(void)
 1517 {
 1518         u_int cpu;
 1519 
 1520         cpu = PCPU_GET(cpuid);
 1521 
 1522         if (suspendctx(susppcbs[cpu])) {
 1523                 wbinvd();
 1524                 CPU_SET_ATOMIC(cpu, &stopped_cpus);
 1525         } else {
 1526                 pmap_init_pat();
 1527                 PCPU_SET(switchtime, 0);
 1528                 PCPU_SET(switchticks, ticks);
 1529                 susppcbs[cpu]->pcb_eip = 0;
 1530         }
 1531 
 1532         /* Wait for resume */
 1533         while (!CPU_ISSET(cpu, &started_cpus))
 1534                 ia32_pause();
 1535 
 1536         CPU_CLR_ATOMIC(cpu, &started_cpus);
 1537         CPU_CLR_ATOMIC(cpu, &stopped_cpus);
 1538 
 1539         /* Resume MCA and local APIC */
 1540         mca_resume();
 1541         lapic_setup(0);
 1542 }
 1543 /*
 1544  * This is called once the rest of the system is up and running and we're
 1545  * ready to let the AP's out of the pen.
 1546  */
 1547 static void
 1548 release_aps(void *dummy __unused)
 1549 {
 1550 
 1551         if (mp_ncpus == 1) 
 1552                 return;
 1553         atomic_store_rel_int(&aps_ready, 1);
 1554         while (smp_started == 0)
 1555                 ia32_pause();
 1556 }
 1557 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
 1558 
 1559 #ifdef COUNT_IPIS
 1560 /*
 1561  * Setup interrupt counters for IPI handlers.
 1562  */
 1563 static void
 1564 mp_ipi_intrcnt(void *dummy)
 1565 {
 1566         char buf[64];
 1567         int i;
 1568 
 1569         CPU_FOREACH(i) {
 1570                 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
 1571                 intrcnt_add(buf, &ipi_invltlb_counts[i]);
 1572                 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
 1573                 intrcnt_add(buf, &ipi_invlrng_counts[i]);
 1574                 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
 1575                 intrcnt_add(buf, &ipi_invlpg_counts[i]);
 1576                 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i);
 1577                 intrcnt_add(buf, &ipi_invlcache_counts[i]);
 1578                 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
 1579                 intrcnt_add(buf, &ipi_preempt_counts[i]);
 1580                 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
 1581                 intrcnt_add(buf, &ipi_ast_counts[i]);
 1582                 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
 1583                 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
 1584                 snprintf(buf, sizeof(buf), "cpu%d:lazypmap", i);
 1585                 intrcnt_add(buf, &ipi_lazypmap_counts[i]);
 1586                 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
 1587                 intrcnt_add(buf, &ipi_hardclock_counts[i]);
 1588         }               
 1589 }
 1590 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);
 1591 #endif

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