The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/mp_machdep.c

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    1 /*-
    2  * Copyright (c) 1996, by Steve Passe
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. The name of the developer may NOT be used to endorse or promote products
   11  *    derived from this software without specific prior written permission.
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   23  * SUCH DAMAGE.
   24  */
   25 
   26 #include <sys/cdefs.h>
   27 __FBSDID("$FreeBSD: releng/9.0/sys/i386/i386/mp_machdep.c 223758 2011-07-04 12:04:52Z attilio $");
   28 
   29 #include "opt_apic.h"
   30 #include "opt_cpu.h"
   31 #include "opt_kstack_pages.h"
   32 #include "opt_pmap.h"
   33 #include "opt_sched.h"
   34 #include "opt_smp.h"
   35 
   36 #if !defined(lint)
   37 #if !defined(SMP)
   38 #error How did you get here?
   39 #endif
   40 
   41 #ifndef DEV_APIC
   42 #error The apic device is required for SMP, add "device apic" to your config file.
   43 #endif
   44 #if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT)
   45 #error SMP not supported with CPU_DISABLE_CMPXCHG
   46 #endif
   47 #endif /* not lint */
   48 
   49 #include <sys/param.h>
   50 #include <sys/systm.h>
   51 #include <sys/bus.h>
   52 #include <sys/cons.h>   /* cngetc() */
   53 #include <sys/cpuset.h>
   54 #ifdef GPROF 
   55 #include <sys/gmon.h>
   56 #endif
   57 #include <sys/kernel.h>
   58 #include <sys/ktr.h>
   59 #include <sys/lock.h>
   60 #include <sys/malloc.h>
   61 #include <sys/memrange.h>
   62 #include <sys/mutex.h>
   63 #include <sys/pcpu.h>
   64 #include <sys/proc.h>
   65 #include <sys/sched.h>
   66 #include <sys/smp.h>
   67 #include <sys/sysctl.h>
   68 
   69 #include <vm/vm.h>
   70 #include <vm/vm_param.h>
   71 #include <vm/pmap.h>
   72 #include <vm/vm_kern.h>
   73 #include <vm/vm_extern.h>
   74 
   75 #include <x86/apicreg.h>
   76 #include <machine/clock.h>
   77 #include <machine/cputypes.h>
   78 #include <x86/mca.h>
   79 #include <machine/md_var.h>
   80 #include <machine/pcb.h>
   81 #include <machine/psl.h>
   82 #include <machine/smp.h>
   83 #include <machine/specialreg.h>
   84 
   85 #define WARMBOOT_TARGET         0
   86 #define WARMBOOT_OFF            (KERNBASE + 0x0467)
   87 #define WARMBOOT_SEG            (KERNBASE + 0x0469)
   88 
   89 #define CMOS_REG                (0x70)
   90 #define CMOS_DATA               (0x71)
   91 #define BIOS_RESET              (0x0f)
   92 #define BIOS_WARM               (0x0a)
   93 
   94 /*
   95  * this code MUST be enabled here and in mpboot.s.
   96  * it follows the very early stages of AP boot by placing values in CMOS ram.
   97  * it NORMALLY will never be needed and thus the primitive method for enabling.
   98  *
   99 #define CHECK_POINTS
  100  */
  101 
  102 #if defined(CHECK_POINTS) && !defined(PC98)
  103 #define CHECK_READ(A)    (outb(CMOS_REG, (A)), inb(CMOS_DATA))
  104 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
  105 
  106 #define CHECK_INIT(D);                          \
  107         CHECK_WRITE(0x34, (D));                 \
  108         CHECK_WRITE(0x35, (D));                 \
  109         CHECK_WRITE(0x36, (D));                 \
  110         CHECK_WRITE(0x37, (D));                 \
  111         CHECK_WRITE(0x38, (D));                 \
  112         CHECK_WRITE(0x39, (D));
  113 
  114 #define CHECK_PRINT(S);                         \
  115         printf("%s: %d, %d, %d, %d, %d, %d\n",  \
  116            (S),                                 \
  117            CHECK_READ(0x34),                    \
  118            CHECK_READ(0x35),                    \
  119            CHECK_READ(0x36),                    \
  120            CHECK_READ(0x37),                    \
  121            CHECK_READ(0x38),                    \
  122            CHECK_READ(0x39));
  123 
  124 #else                           /* CHECK_POINTS */
  125 
  126 #define CHECK_INIT(D)
  127 #define CHECK_PRINT(S)
  128 #define CHECK_WRITE(A, D)
  129 
  130 #endif                          /* CHECK_POINTS */
  131 
  132 /* lock region used by kernel profiling */
  133 int     mcount_lock;
  134 
  135 int     mp_naps;                /* # of Applications processors */
  136 int     boot_cpu_id = -1;       /* designated BSP */
  137 
  138 extern  struct pcpu __pcpu[];
  139 
  140 /* AP uses this during bootstrap.  Do not staticize.  */
  141 char *bootSTK;
  142 static int bootAP;
  143 
  144 /* Free these after use */
  145 void *bootstacks[MAXCPU];
  146 static void *dpcpu;
  147 
  148 /* Hotwire a 0->4MB V==P mapping */
  149 extern pt_entry_t *KPTphys;
  150 
  151 struct pcb stoppcbs[MAXCPU];
  152 
  153 /* Variables needed for SMP tlb shootdown. */
  154 vm_offset_t smp_tlb_addr1;
  155 vm_offset_t smp_tlb_addr2;
  156 volatile int smp_tlb_wait;
  157 
  158 #ifdef COUNT_IPIS
  159 /* Interrupt counts. */
  160 static u_long *ipi_preempt_counts[MAXCPU];
  161 static u_long *ipi_ast_counts[MAXCPU];
  162 u_long *ipi_invltlb_counts[MAXCPU];
  163 u_long *ipi_invlrng_counts[MAXCPU];
  164 u_long *ipi_invlpg_counts[MAXCPU];
  165 u_long *ipi_invlcache_counts[MAXCPU];
  166 u_long *ipi_rendezvous_counts[MAXCPU];
  167 u_long *ipi_lazypmap_counts[MAXCPU];
  168 static u_long *ipi_hardclock_counts[MAXCPU];
  169 #endif
  170 
  171 /*
  172  * Local data and functions.
  173  */
  174 
  175 static volatile cpuset_t ipi_nmi_pending;
  176 
  177 /* used to hold the AP's until we are ready to release them */
  178 static struct mtx ap_boot_mtx;
  179 
  180 /* Set to 1 once we're ready to let the APs out of the pen. */
  181 static volatile int aps_ready = 0;
  182 
  183 /*
  184  * Store data from cpu_add() until later in the boot when we actually setup
  185  * the APs.
  186  */
  187 struct cpu_info {
  188         int     cpu_present:1;
  189         int     cpu_bsp:1;
  190         int     cpu_disabled:1;
  191         int     cpu_hyperthread:1;
  192 } static cpu_info[MAX_APIC_ID + 1];
  193 int cpu_apic_ids[MAXCPU];
  194 int apic_cpuids[MAX_APIC_ID + 1];
  195 
  196 /* Holds pending bitmap based IPIs per CPU */
  197 static volatile u_int cpu_ipi_pending[MAXCPU];
  198 
  199 static u_int boot_address;
  200 static int cpu_logical;                 /* logical cpus per core */
  201 static int cpu_cores;                   /* cores per package */
  202 
  203 static void     assign_cpu_ids(void);
  204 static void     install_ap_tramp(void);
  205 static void     set_interrupt_apic_ids(void);
  206 static int      start_all_aps(void);
  207 static int      start_ap(int apic_id);
  208 static void     release_aps(void *dummy);
  209 
  210 static u_int    hyperthreading_cpus;    /* logical cpus sharing L1 cache */
  211 static int      hyperthreading_allowed = 1;
  212 
  213 static void
  214 mem_range_AP_init(void)
  215 {
  216         if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP)
  217                 mem_range_softc.mr_op->initAP(&mem_range_softc);
  218 }
  219 
  220 static void
  221 topo_probe_amd(void)
  222 {
  223         int core_id_bits;
  224         int id;
  225 
  226         /* AMD processors do not support HTT. */
  227         cpu_logical = 1;
  228 
  229         if ((amd_feature2 & AMDID2_CMP) == 0) {
  230                 cpu_cores = 1;
  231                 return;
  232         }
  233 
  234         core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >>
  235             AMDID_COREID_SIZE_SHIFT;
  236         if (core_id_bits == 0) {
  237                 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
  238                 return;
  239         }
  240 
  241         /* Fam 10h and newer should get here. */
  242         for (id = 0; id <= MAX_APIC_ID; id++) {
  243                 /* Check logical CPU availability. */
  244                 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
  245                         continue;
  246                 /* Check if logical CPU has the same package ID. */
  247                 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits))
  248                         continue;
  249                 cpu_cores++;
  250         }
  251 }
  252 
  253 /*
  254  * Round up to the next power of two, if necessary, and then
  255  * take log2.
  256  * Returns -1 if argument is zero.
  257  */
  258 static __inline int
  259 mask_width(u_int x)
  260 {
  261 
  262         return (fls(x << (1 - powerof2(x))) - 1);
  263 }
  264 
  265 static void
  266 topo_probe_0x4(void)
  267 {
  268         u_int p[4];
  269         int pkg_id_bits;
  270         int core_id_bits;
  271         int max_cores;
  272         int max_logical;
  273         int id;
  274 
  275         /* Both zero and one here mean one logical processor per package. */
  276         max_logical = (cpu_feature & CPUID_HTT) != 0 ?
  277             (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1;
  278         if (max_logical <= 1)
  279                 return;
  280 
  281         /*
  282          * Because of uniformity assumption we examine only
  283          * those logical processors that belong to the same
  284          * package as BSP.  Further, we count number of
  285          * logical processors that belong to the same core
  286          * as BSP thus deducing number of threads per core.
  287          */
  288         if (cpu_high >= 0x4) {
  289                 cpuid_count(0x04, 0, p);
  290                 max_cores = ((p[0] >> 26) & 0x3f) + 1;
  291         } else
  292                 max_cores = 1;
  293         core_id_bits = mask_width(max_logical/max_cores);
  294         if (core_id_bits < 0)
  295                 return;
  296         pkg_id_bits = core_id_bits + mask_width(max_cores);
  297 
  298         for (id = 0; id <= MAX_APIC_ID; id++) {
  299                 /* Check logical CPU availability. */
  300                 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled)
  301                         continue;
  302                 /* Check if logical CPU has the same package ID. */
  303                 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits))
  304                         continue;
  305                 cpu_cores++;
  306                 /* Check if logical CPU has the same package and core IDs. */
  307                 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits))
  308                         cpu_logical++;
  309         }
  310 
  311         KASSERT(cpu_cores >= 1 && cpu_logical >= 1,
  312             ("topo_probe_0x4 couldn't find BSP"));
  313 
  314         cpu_cores /= cpu_logical;
  315         hyperthreading_cpus = cpu_logical;
  316 }
  317 
  318 static void
  319 topo_probe_0xb(void)
  320 {
  321         u_int p[4];
  322         int bits;
  323         int cnt;
  324         int i;
  325         int logical;
  326         int type;
  327         int x;
  328 
  329         /* We only support three levels for now. */
  330         for (i = 0; i < 3; i++) {
  331                 cpuid_count(0x0b, i, p);
  332 
  333                 /* Fall back if CPU leaf 11 doesn't really exist. */
  334                 if (i == 0 && p[1] == 0) {
  335                         topo_probe_0x4();
  336                         return;
  337                 }
  338 
  339                 bits = p[0] & 0x1f;
  340                 logical = p[1] &= 0xffff;
  341                 type = (p[2] >> 8) & 0xff;
  342                 if (type == 0 || logical == 0)
  343                         break;
  344                 /*
  345                  * Because of uniformity assumption we examine only
  346                  * those logical processors that belong to the same
  347                  * package as BSP.
  348                  */
  349                 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) {
  350                         if (!cpu_info[x].cpu_present ||
  351                             cpu_info[x].cpu_disabled)
  352                                 continue;
  353                         if (x >> bits == boot_cpu_id >> bits)
  354                                 cnt++;
  355                 }
  356                 if (type == CPUID_TYPE_SMT)
  357                         cpu_logical = cnt;
  358                 else if (type == CPUID_TYPE_CORE)
  359                         cpu_cores = cnt;
  360         }
  361         if (cpu_logical == 0)
  362                 cpu_logical = 1;
  363         cpu_cores /= cpu_logical;
  364 }
  365 
  366 /*
  367  * Both topology discovery code and code that consumes topology
  368  * information assume top-down uniformity of the topology.
  369  * That is, all physical packages must be identical and each
  370  * core in a package must have the same number of threads.
  371  * Topology information is queried only on BSP, on which this
  372  * code runs and for which it can query CPUID information.
  373  * Then topology is extrapolated on all packages using the
  374  * uniformity assumption.
  375  */
  376 static void
  377 topo_probe(void)
  378 {
  379         static int cpu_topo_probed = 0;
  380 
  381         if (cpu_topo_probed)
  382                 return;
  383 
  384         CPU_ZERO(&logical_cpus_mask);
  385         if (mp_ncpus <= 1)
  386                 cpu_cores = cpu_logical = 1;
  387         else if (cpu_vendor_id == CPU_VENDOR_AMD)
  388                 topo_probe_amd();
  389         else if (cpu_vendor_id == CPU_VENDOR_INTEL) {
  390                 /*
  391                  * See Intel(R) 64 Architecture Processor
  392                  * Topology Enumeration article for details.
  393                  *
  394                  * Note that 0x1 <= cpu_high < 4 case should be
  395                  * compatible with topo_probe_0x4() logic when
  396                  * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1)
  397                  * or it should trigger the fallback otherwise.
  398                  */
  399                 if (cpu_high >= 0xb)
  400                         topo_probe_0xb();
  401                 else if (cpu_high >= 0x1)
  402                         topo_probe_0x4();
  403         }
  404 
  405         /*
  406          * Fallback: assume each logical CPU is in separate
  407          * physical package.  That is, no multi-core, no SMT.
  408          */
  409         if (cpu_cores == 0 || cpu_logical == 0)
  410                 cpu_cores = cpu_logical = 1;
  411         cpu_topo_probed = 1;
  412 }
  413 
  414 struct cpu_group *
  415 cpu_topo(void)
  416 {
  417         int cg_flags;
  418 
  419         /*
  420          * Determine whether any threading flags are
  421          * necessry.
  422          */
  423         topo_probe();
  424         if (cpu_logical > 1 && hyperthreading_cpus)
  425                 cg_flags = CG_FLAG_HTT;
  426         else if (cpu_logical > 1)
  427                 cg_flags = CG_FLAG_SMT;
  428         else
  429                 cg_flags = 0;
  430         if (mp_ncpus % (cpu_cores * cpu_logical) != 0) {
  431                 printf("WARNING: Non-uniform processors.\n");
  432                 printf("WARNING: Using suboptimal topology.\n");
  433                 return (smp_topo_none());
  434         }
  435         /*
  436          * No multi-core or hyper-threaded.
  437          */
  438         if (cpu_logical * cpu_cores == 1)
  439                 return (smp_topo_none());
  440         /*
  441          * Only HTT no multi-core.
  442          */
  443         if (cpu_logical > 1 && cpu_cores == 1)
  444                 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags));
  445         /*
  446          * Only multi-core no HTT.
  447          */
  448         if (cpu_cores > 1 && cpu_logical == 1)
  449                 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags));
  450         /*
  451          * Both HTT and multi-core.
  452          */
  453         return (smp_topo_2level(CG_SHARE_L2, cpu_cores,
  454             CG_SHARE_L1, cpu_logical, cg_flags));
  455 }
  456 
  457 
  458 /*
  459  * Calculate usable address in base memory for AP trampoline code.
  460  */
  461 u_int
  462 mp_bootaddress(u_int basemem)
  463 {
  464 
  465         boot_address = trunc_page(basemem);     /* round down to 4k boundary */
  466         if ((basemem - boot_address) < bootMP_size)
  467                 boot_address -= PAGE_SIZE;      /* not enough, lower by 4k */
  468 
  469         return boot_address;
  470 }
  471 
  472 void
  473 cpu_add(u_int apic_id, char boot_cpu)
  474 {
  475 
  476         if (apic_id > MAX_APIC_ID) {
  477                 panic("SMP: APIC ID %d too high", apic_id);
  478                 return;
  479         }
  480         KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice",
  481             apic_id));
  482         cpu_info[apic_id].cpu_present = 1;
  483         if (boot_cpu) {
  484                 KASSERT(boot_cpu_id == -1,
  485                     ("CPU %d claims to be BSP, but CPU %d already is", apic_id,
  486                     boot_cpu_id));
  487                 boot_cpu_id = apic_id;
  488                 cpu_info[apic_id].cpu_bsp = 1;
  489         }
  490         if (mp_ncpus < MAXCPU) {
  491                 mp_ncpus++;
  492                 mp_maxid = mp_ncpus - 1;
  493         }
  494         if (bootverbose)
  495                 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" :
  496                     "AP");
  497 }
  498 
  499 void
  500 cpu_mp_setmaxid(void)
  501 {
  502 
  503         /*
  504          * mp_maxid should be already set by calls to cpu_add().
  505          * Just sanity check its value here.
  506          */
  507         if (mp_ncpus == 0)
  508                 KASSERT(mp_maxid == 0,
  509                     ("%s: mp_ncpus is zero, but mp_maxid is not", __func__));
  510         else if (mp_ncpus == 1)
  511                 mp_maxid = 0;
  512         else
  513                 KASSERT(mp_maxid >= mp_ncpus - 1,
  514                     ("%s: counters out of sync: max %d, count %d", __func__,
  515                         mp_maxid, mp_ncpus));
  516 }
  517 
  518 int
  519 cpu_mp_probe(void)
  520 {
  521 
  522         /*
  523          * Always record BSP in CPU map so that the mbuf init code works
  524          * correctly.
  525          */
  526         CPU_SETOF(0, &all_cpus);
  527         if (mp_ncpus == 0) {
  528                 /*
  529                  * No CPUs were found, so this must be a UP system.  Setup
  530                  * the variables to represent a system with a single CPU
  531                  * with an id of 0.
  532                  */
  533                 mp_ncpus = 1;
  534                 return (0);
  535         }
  536 
  537         /* At least one CPU was found. */
  538         if (mp_ncpus == 1) {
  539                 /*
  540                  * One CPU was found, so this must be a UP system with
  541                  * an I/O APIC.
  542                  */
  543                 mp_maxid = 0;
  544                 return (0);
  545         }
  546 
  547         /* At least two CPUs were found. */
  548         return (1);
  549 }
  550 
  551 /*
  552  * Initialize the IPI handlers and start up the AP's.
  553  */
  554 void
  555 cpu_mp_start(void)
  556 {
  557         int i;
  558 
  559         /* Initialize the logical ID to APIC ID table. */
  560         for (i = 0; i < MAXCPU; i++) {
  561                 cpu_apic_ids[i] = -1;
  562                 cpu_ipi_pending[i] = 0;
  563         }
  564 
  565         /* Install an inter-CPU IPI for TLB invalidation */
  566         setidt(IPI_INVLTLB, IDTVEC(invltlb),
  567                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  568         setidt(IPI_INVLPG, IDTVEC(invlpg),
  569                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  570         setidt(IPI_INVLRNG, IDTVEC(invlrng),
  571                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  572 
  573         /* Install an inter-CPU IPI for cache invalidation. */
  574         setidt(IPI_INVLCACHE, IDTVEC(invlcache),
  575                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  576 
  577         /* Install an inter-CPU IPI for lazy pmap release */
  578         setidt(IPI_LAZYPMAP, IDTVEC(lazypmap),
  579                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  580 
  581         /* Install an inter-CPU IPI for all-CPU rendezvous */
  582         setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous),
  583                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  584 
  585         /* Install generic inter-CPU IPI handler */
  586         setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler),
  587                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  588 
  589         /* Install an inter-CPU IPI for CPU stop/restart */
  590         setidt(IPI_STOP, IDTVEC(cpustop),
  591                SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
  592 
  593 
  594         /* Set boot_cpu_id if needed. */
  595         if (boot_cpu_id == -1) {
  596                 boot_cpu_id = PCPU_GET(apic_id);
  597                 cpu_info[boot_cpu_id].cpu_bsp = 1;
  598         } else
  599                 KASSERT(boot_cpu_id == PCPU_GET(apic_id),
  600                     ("BSP's APIC ID doesn't match boot_cpu_id"));
  601 
  602         /* Probe logical/physical core configuration. */
  603         topo_probe();
  604 
  605         assign_cpu_ids();
  606 
  607         /* Start each Application Processor */
  608         start_all_aps();
  609 
  610         set_interrupt_apic_ids();
  611 }
  612 
  613 
  614 /*
  615  * Print various information about the SMP system hardware and setup.
  616  */
  617 void
  618 cpu_mp_announce(void)
  619 {
  620         const char *hyperthread;
  621         int i;
  622 
  623         printf("FreeBSD/SMP: %d package(s) x %d core(s)",
  624             mp_ncpus / (cpu_cores * cpu_logical), cpu_cores);
  625         if (hyperthreading_cpus > 1)
  626             printf(" x %d HTT threads", cpu_logical);
  627         else if (cpu_logical > 1)
  628             printf(" x %d SMT threads", cpu_logical);
  629         printf("\n");
  630 
  631         /* List active CPUs first. */
  632         printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id);
  633         for (i = 1; i < mp_ncpus; i++) {
  634                 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread)
  635                         hyperthread = "/HT";
  636                 else
  637                         hyperthread = "";
  638                 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread,
  639                     cpu_apic_ids[i]);
  640         }
  641 
  642         /* List disabled CPUs last. */
  643         for (i = 0; i <= MAX_APIC_ID; i++) {
  644                 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled)
  645                         continue;
  646                 if (cpu_info[i].cpu_hyperthread)
  647                         hyperthread = "/HT";
  648                 else
  649                         hyperthread = "";
  650                 printf("  cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread,
  651                     i);
  652         }
  653 }
  654 
  655 /*
  656  * AP CPU's call this to initialize themselves.
  657  */
  658 void
  659 init_secondary(void)
  660 {
  661         struct pcpu *pc;
  662         vm_offset_t addr;
  663         int     gsel_tss;
  664         int     x, myid;
  665         u_int   cpuid, cr0;
  666 
  667         /* bootAP is set in start_ap() to our ID. */
  668         myid = bootAP;
  669 
  670         /* Get per-cpu data */
  671         pc = &__pcpu[myid];
  672 
  673         /* prime data page for it to use */
  674         pcpu_init(pc, myid, sizeof(struct pcpu));
  675         dpcpu_init(dpcpu, myid);
  676         pc->pc_apic_id = cpu_apic_ids[myid];
  677         pc->pc_prvspace = pc;
  678         pc->pc_curthread = 0;
  679 
  680         gdt_segs[GPRIV_SEL].ssd_base = (int) pc;
  681         gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss;
  682 
  683         for (x = 0; x < NGDT; x++) {
  684                 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
  685         }
  686 
  687         r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
  688         r_gdt.rd_base = (int) &gdt[myid * NGDT];
  689         lgdt(&r_gdt);                   /* does magic intra-segment return */
  690 
  691         lidt(&r_idt);
  692 
  693         lldt(_default_ldt);
  694         PCPU_SET(currentldt, _default_ldt);
  695 
  696         gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
  697         gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
  698         PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */
  699         PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL));
  700         PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16);
  701         PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd);
  702         PCPU_SET(common_tssd, *PCPU_GET(tss_gdt));
  703         ltr(gsel_tss);
  704 
  705         PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd);
  706 
  707         /*
  708          * Set to a known state:
  709          * Set by mpboot.s: CR0_PG, CR0_PE
  710          * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
  711          */
  712         cr0 = rcr0();
  713         cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
  714         load_cr0(cr0);
  715         CHECK_WRITE(0x38, 5);
  716         
  717         /* Disable local APIC just to be sure. */
  718         lapic_disable();
  719 
  720         /* signal our startup to the BSP. */
  721         mp_naps++;
  722         CHECK_WRITE(0x39, 6);
  723 
  724         /* Spin until the BSP releases the AP's. */
  725         while (!aps_ready)
  726                 ia32_pause();
  727 
  728         /* BSP may have changed PTD while we were waiting */
  729         invltlb();
  730         for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE)
  731                 invlpg(addr);
  732 
  733 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
  734         lidt(&r_idt);
  735 #endif
  736 
  737         /* Initialize the PAT MSR if present. */
  738         pmap_init_pat();
  739 
  740         /* set up CPU registers and state */
  741         cpu_setregs();
  742 
  743         /* set up FPU state on the AP */
  744         npxinit();
  745 
  746         /* set up SSE registers */
  747         enable_sse();
  748 
  749 #ifdef PAE
  750         /* Enable the PTE no-execute bit. */
  751         if ((amd_feature & AMDID_NX) != 0) {
  752                 uint64_t msr;
  753 
  754                 msr = rdmsr(MSR_EFER) | EFER_NXE;
  755                 wrmsr(MSR_EFER, msr);
  756         }
  757 #endif
  758 
  759         /* A quick check from sanity claus */
  760         cpuid = PCPU_GET(cpuid);
  761         if (PCPU_GET(apic_id) != lapic_id()) {
  762                 printf("SMP: cpuid = %d\n", cpuid);
  763                 printf("SMP: actual apic_id = %d\n", lapic_id());
  764                 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id));
  765                 panic("cpuid mismatch! boom!!");
  766         }
  767 
  768         /* Initialize curthread. */
  769         KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread"));
  770         PCPU_SET(curthread, PCPU_GET(idlethread));
  771 
  772         mca_init();
  773 
  774         mtx_lock_spin(&ap_boot_mtx);
  775 
  776         /* Init local apic for irq's */
  777         lapic_setup(1);
  778 
  779         /* Set memory range attributes for this CPU to match the BSP */
  780         mem_range_AP_init();
  781 
  782         smp_cpus++;
  783 
  784         CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid);
  785         printf("SMP: AP CPU #%d Launched!\n", cpuid);
  786 
  787         /* Determine if we are a logical CPU. */
  788         /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */
  789         if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0)
  790                 CPU_SET(cpuid, &logical_cpus_mask);
  791 
  792         if (bootverbose)
  793                 lapic_dump("AP");
  794 
  795         if (smp_cpus == mp_ncpus) {
  796                 /* enable IPI's, tlb shootdown, freezes etc */
  797                 atomic_store_rel_int(&smp_started, 1);
  798                 smp_active = 1;  /* historic */
  799         }
  800 
  801         mtx_unlock_spin(&ap_boot_mtx);
  802 
  803         /* Wait until all the AP's are up. */
  804         while (smp_started == 0)
  805                 ia32_pause();
  806 
  807         /* Start per-CPU event timers. */
  808         cpu_initclocks_ap();
  809 
  810         /* Enter the scheduler. */
  811         sched_throw(NULL);
  812 
  813         panic("scheduler returned us to %s", __func__);
  814         /* NOTREACHED */
  815 }
  816 
  817 /*******************************************************************
  818  * local functions and data
  819  */
  820 
  821 /*
  822  * We tell the I/O APIC code about all the CPUs we want to receive
  823  * interrupts.  If we don't want certain CPUs to receive IRQs we
  824  * can simply not tell the I/O APIC code about them in this function.
  825  * We also do not tell it about the BSP since it tells itself about
  826  * the BSP internally to work with UP kernels and on UP machines.
  827  */
  828 static void
  829 set_interrupt_apic_ids(void)
  830 {
  831         u_int i, apic_id;
  832 
  833         for (i = 0; i < MAXCPU; i++) {
  834                 apic_id = cpu_apic_ids[i];
  835                 if (apic_id == -1)
  836                         continue;
  837                 if (cpu_info[apic_id].cpu_bsp)
  838                         continue;
  839                 if (cpu_info[apic_id].cpu_disabled)
  840                         continue;
  841 
  842                 /* Don't let hyperthreads service interrupts. */
  843                 if (hyperthreading_cpus > 1 &&
  844                     apic_id % hyperthreading_cpus != 0)
  845                         continue;
  846 
  847                 intr_add_cpu(i);
  848         }
  849 }
  850 
  851 /*
  852  * Assign logical CPU IDs to local APICs.
  853  */
  854 static void
  855 assign_cpu_ids(void)
  856 {
  857         u_int i;
  858 
  859         TUNABLE_INT_FETCH("machdep.hyperthreading_allowed",
  860             &hyperthreading_allowed);
  861 
  862         /* Check for explicitly disabled CPUs. */
  863         for (i = 0; i <= MAX_APIC_ID; i++) {
  864                 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp)
  865                         continue;
  866 
  867                 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) {
  868                         cpu_info[i].cpu_hyperthread = 1;
  869 
  870                         /*
  871                          * Don't use HT CPU if it has been disabled by a
  872                          * tunable.
  873                          */
  874                         if (hyperthreading_allowed == 0) {
  875                                 cpu_info[i].cpu_disabled = 1;
  876                                 continue;
  877                         }
  878                 }
  879 
  880                 /* Don't use this CPU if it has been disabled by a tunable. */
  881                 if (resource_disabled("lapic", i)) {
  882                         cpu_info[i].cpu_disabled = 1;
  883                         continue;
  884                 }
  885         }
  886 
  887         if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) {
  888                 hyperthreading_cpus = 0;
  889                 cpu_logical = 1;
  890         }
  891 
  892         /*
  893          * Assign CPU IDs to local APIC IDs and disable any CPUs
  894          * beyond MAXCPU.  CPU 0 is always assigned to the BSP.
  895          *
  896          * To minimize confusion for userland, we attempt to number
  897          * CPUs such that all threads and cores in a package are
  898          * grouped together.  For now we assume that the BSP is always
  899          * the first thread in a package and just start adding APs
  900          * starting with the BSP's APIC ID.
  901          */
  902         mp_ncpus = 1;
  903         cpu_apic_ids[0] = boot_cpu_id;
  904         apic_cpuids[boot_cpu_id] = 0;
  905         for (i = boot_cpu_id + 1; i != boot_cpu_id;
  906              i == MAX_APIC_ID ? i = 0 : i++) {
  907                 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp ||
  908                     cpu_info[i].cpu_disabled)
  909                         continue;
  910 
  911                 if (mp_ncpus < MAXCPU) {
  912                         cpu_apic_ids[mp_ncpus] = i;
  913                         apic_cpuids[i] = mp_ncpus;
  914                         mp_ncpus++;
  915                 } else
  916                         cpu_info[i].cpu_disabled = 1;
  917         }
  918         KASSERT(mp_maxid >= mp_ncpus - 1,
  919             ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid,
  920             mp_ncpus));         
  921 }
  922 
  923 /*
  924  * start each AP in our list
  925  */
  926 /* Lowest 1MB is already mapped: don't touch*/
  927 #define TMPMAP_START 1
  928 static int
  929 start_all_aps(void)
  930 {
  931 #ifndef PC98
  932         u_char mpbiosreason;
  933 #endif
  934         uintptr_t kptbase;
  935         u_int32_t mpbioswarmvec;
  936         int apic_id, cpu, i;
  937 
  938         mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN);
  939 
  940         /* install the AP 1st level boot code */
  941         install_ap_tramp();
  942 
  943         /* save the current value of the warm-start vector */
  944         mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF);
  945 #ifndef PC98
  946         outb(CMOS_REG, BIOS_RESET);
  947         mpbiosreason = inb(CMOS_DATA);
  948 #endif
  949 
  950         /* set up temporary P==V mapping for AP boot */
  951         /* XXX this is a hack, we should boot the AP on its own stack/PTD */
  952 
  953         kptbase = (uintptr_t)(void *)KPTphys;
  954         for (i = TMPMAP_START; i < NKPT; i++)
  955                 PTD[i] = (pd_entry_t)(PG_V | PG_RW |
  956                     ((kptbase + i * PAGE_SIZE) & PG_FRAME));
  957         invltlb();
  958 
  959         /* start each AP */
  960         for (cpu = 1; cpu < mp_ncpus; cpu++) {
  961                 apic_id = cpu_apic_ids[cpu];
  962 
  963                 /* allocate and set up a boot stack data page */
  964                 bootstacks[cpu] =
  965                     (char *)kmem_alloc(kernel_map, KSTACK_PAGES * PAGE_SIZE);
  966                 dpcpu = (void *)kmem_alloc(kernel_map, DPCPU_SIZE);
  967                 /* setup a vector to our boot code */
  968                 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
  969                 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4);
  970 #ifndef PC98
  971                 outb(CMOS_REG, BIOS_RESET);
  972                 outb(CMOS_DATA, BIOS_WARM);     /* 'warm-start' */
  973 #endif
  974 
  975                 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4;
  976                 bootAP = cpu;
  977 
  978                 /* attempt to start the Application Processor */
  979                 CHECK_INIT(99); /* setup checkpoints */
  980                 if (!start_ap(apic_id)) {
  981                         printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id);
  982                         CHECK_PRINT("trace");   /* show checkpoints */
  983                         /* better panic as the AP may be running loose */
  984                         printf("panic y/n? [y] ");
  985                         if (cngetc() != 'n')
  986                                 panic("bye-bye");
  987                 }
  988                 CHECK_PRINT("trace");           /* show checkpoints */
  989 
  990                 CPU_SET(cpu, &all_cpus);        /* record AP in CPU map */
  991         }
  992 
  993         /* restore the warmstart vector */
  994         *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec;
  995 
  996 #ifndef PC98
  997         outb(CMOS_REG, BIOS_RESET);
  998         outb(CMOS_DATA, mpbiosreason);
  999 #endif
 1000 
 1001         /* Undo V==P hack from above */
 1002         for (i = TMPMAP_START; i < NKPT; i++)
 1003                 PTD[i] = 0;
 1004         pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1);
 1005 
 1006         /* number of APs actually started */
 1007         return mp_naps;
 1008 }
 1009 
 1010 /*
 1011  * load the 1st level AP boot code into base memory.
 1012  */
 1013 
 1014 /* targets for relocation */
 1015 extern void bigJump(void);
 1016 extern void bootCodeSeg(void);
 1017 extern void bootDataSeg(void);
 1018 extern void MPentry(void);
 1019 extern u_int MP_GDT;
 1020 extern u_int mp_gdtbase;
 1021 
 1022 static void
 1023 install_ap_tramp(void)
 1024 {
 1025         int     x;
 1026         int     size = *(int *) ((u_long) & bootMP_size);
 1027         vm_offset_t va = boot_address + KERNBASE;
 1028         u_char *src = (u_char *) ((u_long) bootMP);
 1029         u_char *dst = (u_char *) va;
 1030         u_int   boot_base = (u_int) bootMP;
 1031         u_int8_t *dst8;
 1032         u_int16_t *dst16;
 1033         u_int32_t *dst32;
 1034 
 1035         KASSERT (size <= PAGE_SIZE,
 1036             ("'size' do not fit into PAGE_SIZE, as expected."));
 1037         pmap_kenter(va, boot_address);
 1038         pmap_invalidate_page (kernel_pmap, va);
 1039         for (x = 0; x < size; ++x)
 1040                 *dst++ = *src++;
 1041 
 1042         /*
 1043          * modify addresses in code we just moved to basemem. unfortunately we
 1044          * need fairly detailed info about mpboot.s for this to work.  changes
 1045          * to mpboot.s might require changes here.
 1046          */
 1047 
 1048         /* boot code is located in KERNEL space */
 1049         dst = (u_char *) va;
 1050 
 1051         /* modify the lgdt arg */
 1052         dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
 1053         *dst32 = boot_address + ((u_int) & MP_GDT - boot_base);
 1054 
 1055         /* modify the ljmp target for MPentry() */
 1056         dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
 1057         *dst32 = ((u_int) MPentry - KERNBASE);
 1058 
 1059         /* modify the target for boot code segment */
 1060         dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
 1061         dst8 = (u_int8_t *) (dst16 + 1);
 1062         *dst16 = (u_int) boot_address & 0xffff;
 1063         *dst8 = ((u_int) boot_address >> 16) & 0xff;
 1064 
 1065         /* modify the target for boot data segment */
 1066         dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
 1067         dst8 = (u_int8_t *) (dst16 + 1);
 1068         *dst16 = (u_int) boot_address & 0xffff;
 1069         *dst8 = ((u_int) boot_address >> 16) & 0xff;
 1070 }
 1071 
 1072 /*
 1073  * This function starts the AP (application processor) identified
 1074  * by the APIC ID 'physicalCpu'.  It does quite a "song and dance"
 1075  * to accomplish this.  This is necessary because of the nuances
 1076  * of the different hardware we might encounter.  It isn't pretty,
 1077  * but it seems to work.
 1078  */
 1079 static int
 1080 start_ap(int apic_id)
 1081 {
 1082         int vector, ms;
 1083         int cpus;
 1084 
 1085         /* calculate the vector */
 1086         vector = (boot_address >> 12) & 0xff;
 1087 
 1088         /* used as a watchpoint to signal AP startup */
 1089         cpus = mp_naps;
 1090 
 1091         /*
 1092          * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
 1093          * and running the target CPU. OR this INIT IPI might be latched (P5
 1094          * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
 1095          * ignored.
 1096          */
 1097 
 1098         /* do an INIT IPI: assert RESET */
 1099         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
 1100             APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id);
 1101 
 1102         /* wait for pending status end */
 1103         lapic_ipi_wait(-1);
 1104 
 1105         /* do an INIT IPI: deassert RESET */
 1106         lapic_ipi_raw(APIC_DEST_ALLESELF | APIC_TRIGMOD_LEVEL |
 1107             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 0);
 1108 
 1109         /* wait for pending status end */
 1110         DELAY(10000);           /* wait ~10mS */
 1111         lapic_ipi_wait(-1);
 1112 
 1113         /*
 1114          * next we do a STARTUP IPI: the previous INIT IPI might still be
 1115          * latched, (P5 bug) this 1st STARTUP would then terminate
 1116          * immediately, and the previously started INIT IPI would continue. OR
 1117          * the previous INIT IPI has already run. and this STARTUP IPI will
 1118          * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
 1119          * will run.
 1120          */
 1121 
 1122         /* do a STARTUP IPI */
 1123         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
 1124             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
 1125             vector, apic_id);
 1126         lapic_ipi_wait(-1);
 1127         DELAY(200);             /* wait ~200uS */
 1128 
 1129         /*
 1130          * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
 1131          * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
 1132          * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
 1133          * recognized after hardware RESET or INIT IPI.
 1134          */
 1135 
 1136         lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE |
 1137             APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP |
 1138             vector, apic_id);
 1139         lapic_ipi_wait(-1);
 1140         DELAY(200);             /* wait ~200uS */
 1141 
 1142         /* Wait up to 5 seconds for it to start. */
 1143         for (ms = 0; ms < 5000; ms++) {
 1144                 if (mp_naps > cpus)
 1145                         return 1;       /* return SUCCESS */
 1146                 DELAY(1000);
 1147         }
 1148         return 0;               /* return FAILURE */
 1149 }
 1150 
 1151 #ifdef COUNT_XINVLTLB_HITS
 1152 u_int xhits_gbl[MAXCPU];
 1153 u_int xhits_pg[MAXCPU];
 1154 u_int xhits_rng[MAXCPU];
 1155 SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, "");
 1156 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl,
 1157     sizeof(xhits_gbl), "IU", "");
 1158 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg,
 1159     sizeof(xhits_pg), "IU", "");
 1160 SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng,
 1161     sizeof(xhits_rng), "IU", "");
 1162 
 1163 u_int ipi_global;
 1164 u_int ipi_page;
 1165 u_int ipi_range;
 1166 u_int ipi_range_size;
 1167 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, "");
 1168 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, "");
 1169 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, "");
 1170 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size,
 1171     0, "");
 1172 
 1173 u_int ipi_masked_global;
 1174 u_int ipi_masked_page;
 1175 u_int ipi_masked_range;
 1176 u_int ipi_masked_range_size;
 1177 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW,
 1178     &ipi_masked_global, 0, "");
 1179 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW,
 1180     &ipi_masked_page, 0, "");
 1181 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW,
 1182     &ipi_masked_range, 0, "");
 1183 SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW,
 1184     &ipi_masked_range_size, 0, "");
 1185 #endif /* COUNT_XINVLTLB_HITS */
 1186 
 1187 /*
 1188  * Send an IPI to specified CPU handling the bitmap logic.
 1189  */
 1190 static void
 1191 ipi_send_cpu(int cpu, u_int ipi)
 1192 {
 1193         u_int bitmap, old_pending, new_pending;
 1194 
 1195         KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu));
 1196 
 1197         if (IPI_IS_BITMAPED(ipi)) {
 1198                 bitmap = 1 << ipi;
 1199                 ipi = IPI_BITMAP_VECTOR;
 1200                 do {
 1201                         old_pending = cpu_ipi_pending[cpu];
 1202                         new_pending = old_pending | bitmap;
 1203                 } while  (!atomic_cmpset_int(&cpu_ipi_pending[cpu],
 1204                     old_pending, new_pending)); 
 1205                 if (old_pending)
 1206                         return;
 1207         }
 1208         lapic_ipi_vectored(ipi, cpu_apic_ids[cpu]);
 1209 }
 1210 
 1211 /*
 1212  * Flush the TLB on all other CPU's
 1213  */
 1214 static void
 1215 smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
 1216 {
 1217         u_int ncpu;
 1218 
 1219         ncpu = mp_ncpus - 1;    /* does not shootdown self */
 1220         if (ncpu < 1)
 1221                 return;         /* no other cpus */
 1222         if (!(read_eflags() & PSL_I))
 1223                 panic("%s: interrupts disabled", __func__);
 1224         mtx_lock_spin(&smp_ipi_mtx);
 1225         smp_tlb_addr1 = addr1;
 1226         smp_tlb_addr2 = addr2;
 1227         atomic_store_rel_int(&smp_tlb_wait, 0);
 1228         ipi_all_but_self(vector);
 1229         while (smp_tlb_wait < ncpu)
 1230                 ia32_pause();
 1231         mtx_unlock_spin(&smp_ipi_mtx);
 1232 }
 1233 
 1234 static void
 1235 smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2)
 1236 {
 1237         int cpu, ncpu, othercpus;
 1238 
 1239         othercpus = mp_ncpus - 1;
 1240         if (CPU_ISFULLSET(&mask)) {
 1241                 if (othercpus < 1)
 1242                         return;
 1243         } else {
 1244                 CPU_CLR(PCPU_GET(cpuid), &mask);
 1245                 if (CPU_EMPTY(&mask))
 1246                         return;
 1247         }
 1248         if (!(read_eflags() & PSL_I))
 1249                 panic("%s: interrupts disabled", __func__);
 1250         mtx_lock_spin(&smp_ipi_mtx);
 1251         smp_tlb_addr1 = addr1;
 1252         smp_tlb_addr2 = addr2;
 1253         atomic_store_rel_int(&smp_tlb_wait, 0);
 1254         if (CPU_ISFULLSET(&mask)) {
 1255                 ncpu = othercpus;
 1256                 ipi_all_but_self(vector);
 1257         } else {
 1258                 ncpu = 0;
 1259                 while ((cpu = cpusetobj_ffs(&mask)) != 0) {
 1260                         cpu--;
 1261                         CPU_CLR(cpu, &mask);
 1262                         CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu,
 1263                             vector);
 1264                         ipi_send_cpu(cpu, vector);
 1265                         ncpu++;
 1266                 }
 1267         }
 1268         while (smp_tlb_wait < ncpu)
 1269                 ia32_pause();
 1270         mtx_unlock_spin(&smp_ipi_mtx);
 1271 }
 1272 
 1273 void
 1274 smp_cache_flush(void)
 1275 {
 1276 
 1277         if (smp_started)
 1278                 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0);
 1279 }
 1280 
 1281 void
 1282 smp_invltlb(void)
 1283 {
 1284 
 1285         if (smp_started) {
 1286                 smp_tlb_shootdown(IPI_INVLTLB, 0, 0);
 1287 #ifdef COUNT_XINVLTLB_HITS
 1288                 ipi_global++;
 1289 #endif
 1290         }
 1291 }
 1292 
 1293 void
 1294 smp_invlpg(vm_offset_t addr)
 1295 {
 1296 
 1297         if (smp_started) {
 1298                 smp_tlb_shootdown(IPI_INVLPG, addr, 0);
 1299 #ifdef COUNT_XINVLTLB_HITS
 1300                 ipi_page++;
 1301 #endif
 1302         }
 1303 }
 1304 
 1305 void
 1306 smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2)
 1307 {
 1308 
 1309         if (smp_started) {
 1310                 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2);
 1311 #ifdef COUNT_XINVLTLB_HITS
 1312                 ipi_range++;
 1313                 ipi_range_size += (addr2 - addr1) / PAGE_SIZE;
 1314 #endif
 1315         }
 1316 }
 1317 
 1318 void
 1319 smp_masked_invltlb(cpuset_t mask)
 1320 {
 1321 
 1322         if (smp_started) {
 1323                 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0);
 1324 #ifdef COUNT_XINVLTLB_HITS
 1325                 ipi_masked_global++;
 1326 #endif
 1327         }
 1328 }
 1329 
 1330 void
 1331 smp_masked_invlpg(cpuset_t mask, vm_offset_t addr)
 1332 {
 1333 
 1334         if (smp_started) {
 1335                 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0);
 1336 #ifdef COUNT_XINVLTLB_HITS
 1337                 ipi_masked_page++;
 1338 #endif
 1339         }
 1340 }
 1341 
 1342 void
 1343 smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2)
 1344 {
 1345 
 1346         if (smp_started) {
 1347                 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2);
 1348 #ifdef COUNT_XINVLTLB_HITS
 1349                 ipi_masked_range++;
 1350                 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE;
 1351 #endif
 1352         }
 1353 }
 1354 
 1355 void
 1356 ipi_bitmap_handler(struct trapframe frame)
 1357 {
 1358         struct trapframe *oldframe;
 1359         struct thread *td;
 1360         int cpu = PCPU_GET(cpuid);
 1361         u_int ipi_bitmap;
 1362 
 1363         critical_enter();
 1364         td = curthread;
 1365         td->td_intr_nesting_level++;
 1366         oldframe = td->td_intr_frame;
 1367         td->td_intr_frame = &frame;
 1368         ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]);
 1369         if (ipi_bitmap & (1 << IPI_PREEMPT)) {
 1370 #ifdef COUNT_IPIS
 1371                 (*ipi_preempt_counts[cpu])++;
 1372 #endif
 1373                 sched_preempt(td);
 1374         }
 1375         if (ipi_bitmap & (1 << IPI_AST)) {
 1376 #ifdef COUNT_IPIS
 1377                 (*ipi_ast_counts[cpu])++;
 1378 #endif
 1379                 /* Nothing to do for AST */
 1380         }
 1381         if (ipi_bitmap & (1 << IPI_HARDCLOCK)) {
 1382 #ifdef COUNT_IPIS
 1383                 (*ipi_hardclock_counts[cpu])++;
 1384 #endif
 1385                 hardclockintr();
 1386         }
 1387         td->td_intr_frame = oldframe;
 1388         td->td_intr_nesting_level--;
 1389         critical_exit();
 1390 }
 1391 
 1392 /*
 1393  * send an IPI to a set of cpus.
 1394  */
 1395 void
 1396 ipi_selected(cpuset_t cpus, u_int ipi)
 1397 {
 1398         int cpu;
 1399 
 1400         /*
 1401          * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
 1402          * of help in order to understand what is the source.
 1403          * Set the mask of receiving CPUs for this purpose.
 1404          */
 1405         if (ipi == IPI_STOP_HARD)
 1406                 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus);
 1407 
 1408         while ((cpu = cpusetobj_ffs(&cpus)) != 0) {
 1409                 cpu--;
 1410                 CPU_CLR(cpu, &cpus);
 1411                 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
 1412                 ipi_send_cpu(cpu, ipi);
 1413         }
 1414 }
 1415 
 1416 /*
 1417  * send an IPI to a specific CPU.
 1418  */
 1419 void
 1420 ipi_cpu(int cpu, u_int ipi)
 1421 {
 1422 
 1423         /*
 1424          * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
 1425          * of help in order to understand what is the source.
 1426          * Set the mask of receiving CPUs for this purpose.
 1427          */
 1428         if (ipi == IPI_STOP_HARD)
 1429                 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending);
 1430 
 1431         CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi);
 1432         ipi_send_cpu(cpu, ipi);
 1433 }
 1434 
 1435 /*
 1436  * send an IPI to all CPUs EXCEPT myself
 1437  */
 1438 void
 1439 ipi_all_but_self(u_int ipi)
 1440 {
 1441         cpuset_t other_cpus;
 1442 
 1443         other_cpus = all_cpus;
 1444         CPU_CLR(PCPU_GET(cpuid), &other_cpus);
 1445         if (IPI_IS_BITMAPED(ipi)) {
 1446                 ipi_selected(other_cpus, ipi);
 1447                 return;
 1448         }
 1449 
 1450         /*
 1451          * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit
 1452          * of help in order to understand what is the source.
 1453          * Set the mask of receiving CPUs for this purpose.
 1454          */
 1455         if (ipi == IPI_STOP_HARD)
 1456                 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus);
 1457 
 1458         CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi);
 1459         lapic_ipi_vectored(ipi, APIC_IPI_DEST_OTHERS);
 1460 }
 1461 
 1462 int
 1463 ipi_nmi_handler()
 1464 {
 1465         u_int cpuid;
 1466 
 1467         /*
 1468          * As long as there is not a simple way to know about a NMI's
 1469          * source, if the bitmask for the current CPU is present in
 1470          * the global pending bitword an IPI_STOP_HARD has been issued
 1471          * and should be handled.
 1472          */
 1473         cpuid = PCPU_GET(cpuid);
 1474         if (!CPU_ISSET(cpuid, &ipi_nmi_pending))
 1475                 return (1);
 1476 
 1477         CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending);
 1478         cpustop_handler();
 1479         return (0);
 1480 }
 1481 
 1482 /*
 1483  * Handle an IPI_STOP by saving our current context and spinning until we
 1484  * are resumed.
 1485  */
 1486 void
 1487 cpustop_handler(void)
 1488 {
 1489         u_int cpu;
 1490 
 1491         cpu = PCPU_GET(cpuid);
 1492 
 1493         savectx(&stoppcbs[cpu]);
 1494 
 1495         /* Indicate that we are stopped */
 1496         CPU_SET_ATOMIC(cpu, &stopped_cpus);
 1497 
 1498         /* Wait for restart */
 1499         while (!CPU_ISSET(cpu, &started_cpus))
 1500             ia32_pause();
 1501 
 1502         CPU_CLR_ATOMIC(cpu, &started_cpus);
 1503         CPU_CLR_ATOMIC(cpu, &stopped_cpus);
 1504 
 1505         if (cpu == 0 && cpustop_restartfunc != NULL) {
 1506                 cpustop_restartfunc();
 1507                 cpustop_restartfunc = NULL;
 1508         }
 1509 }
 1510 
 1511 /*
 1512  * This is called once the rest of the system is up and running and we're
 1513  * ready to let the AP's out of the pen.
 1514  */
 1515 static void
 1516 release_aps(void *dummy __unused)
 1517 {
 1518 
 1519         if (mp_ncpus == 1) 
 1520                 return;
 1521         atomic_store_rel_int(&aps_ready, 1);
 1522         while (smp_started == 0)
 1523                 ia32_pause();
 1524 }
 1525 SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL);
 1526 
 1527 #ifdef COUNT_IPIS
 1528 /*
 1529  * Setup interrupt counters for IPI handlers.
 1530  */
 1531 static void
 1532 mp_ipi_intrcnt(void *dummy)
 1533 {
 1534         char buf[64];
 1535         int i;
 1536 
 1537         CPU_FOREACH(i) {
 1538                 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i);
 1539                 intrcnt_add(buf, &ipi_invltlb_counts[i]);
 1540                 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i);
 1541                 intrcnt_add(buf, &ipi_invlrng_counts[i]);
 1542                 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i);
 1543                 intrcnt_add(buf, &ipi_invlpg_counts[i]);
 1544                 snprintf(buf, sizeof(buf), "cpu%d:preempt", i);
 1545                 intrcnt_add(buf, &ipi_preempt_counts[i]);
 1546                 snprintf(buf, sizeof(buf), "cpu%d:ast", i);
 1547                 intrcnt_add(buf, &ipi_ast_counts[i]);
 1548                 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i);
 1549                 intrcnt_add(buf, &ipi_rendezvous_counts[i]);
 1550                 snprintf(buf, sizeof(buf), "cpu%d:lazypmap", i);
 1551                 intrcnt_add(buf, &ipi_lazypmap_counts[i]);
 1552                 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i);
 1553                 intrcnt_add(buf, &ipi_hardclock_counts[i]);
 1554         }               
 1555 }
 1556 SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL);
 1557 #endif

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