1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/5.4/sys/i386/i386/mptable.c 145335 2005-04-20 19:11:07Z cvs2svn $");
29
30 #include "opt_mptable_force_htt.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36
37 #include <vm/vm.h>
38 #include <vm/vm_param.h>
39 #include <vm/pmap.h>
40
41 #include <machine/apicreg.h>
42 #include <machine/frame.h>
43 #include <machine/intr_machdep.h>
44 #include <machine/apicvar.h>
45 #include <machine/md_var.h>
46 #include <machine/mptable.h>
47 #include <machine/specialreg.h>
48
49 #include <dev/pci/pcivar.h>
50
51 /* string defined by the Intel MP Spec as identifying the MP table */
52 #define MP_SIG 0x5f504d5f /* _MP_ */
53
54 #define NAPICID 32 /* Max number of APIC's */
55
56 #ifdef PC98
57 #define BIOS_BASE (0xe8000)
58 #define BIOS_SIZE (0x18000)
59 #else
60 #define BIOS_BASE (0xf0000)
61 #define BIOS_SIZE (0x10000)
62 #endif
63 #define BIOS_COUNT (BIOS_SIZE/4)
64
65 typedef void mptable_entry_handler(u_char *entry, void *arg);
66
67 static basetable_entry basetable_entry_types[] =
68 {
69 {0, 20, "Processor"},
70 {1, 8, "Bus"},
71 {2, 8, "I/O APIC"},
72 {3, 8, "I/O INT"},
73 {4, 8, "Local INT"}
74 };
75
76 typedef struct BUSDATA {
77 u_char bus_id;
78 enum busTypes bus_type;
79 } bus_datum;
80
81 typedef struct INTDATA {
82 u_char int_type;
83 u_short int_flags;
84 u_char src_bus_id;
85 u_char src_bus_irq;
86 u_char dst_apic_id;
87 u_char dst_apic_int;
88 u_char int_vector;
89 } io_int, local_int;
90
91 typedef struct BUSTYPENAME {
92 u_char type;
93 char name[7];
94 } bus_type_name;
95
96 /* From MP spec v1.4, table 4-8. */
97 static bus_type_name bus_type_table[] =
98 {
99 {UNKNOWN_BUSTYPE, "CBUS "},
100 {UNKNOWN_BUSTYPE, "CBUSII"},
101 {EISA, "EISA "},
102 {UNKNOWN_BUSTYPE, "FUTURE"},
103 {UNKNOWN_BUSTYPE, "INTERN"},
104 {ISA, "ISA "},
105 {UNKNOWN_BUSTYPE, "MBI "},
106 {UNKNOWN_BUSTYPE, "MBII "},
107 {MCA, "MCA "},
108 {UNKNOWN_BUSTYPE, "MPI "},
109 {UNKNOWN_BUSTYPE, "MPSA "},
110 {UNKNOWN_BUSTYPE, "NUBUS "},
111 {PCI, "PCI "},
112 {UNKNOWN_BUSTYPE, "PCMCIA"},
113 {UNKNOWN_BUSTYPE, "TC "},
114 {UNKNOWN_BUSTYPE, "VL "},
115 {UNKNOWN_BUSTYPE, "VME "},
116 {UNKNOWN_BUSTYPE, "XPRESS"}
117 };
118
119 /* From MP spec v1.4, table 5-1. */
120 static int default_data[7][5] =
121 {
122 /* nbus, id0, type0, id1, type1 */
123 {1, 0, ISA, 255, NOBUS},
124 {1, 0, EISA, 255, NOBUS},
125 {1, 0, EISA, 255, NOBUS},
126 {1, 0, MCA, 255, NOBUS},
127 {2, 0, ISA, 1, PCI},
128 {2, 0, EISA, 1, PCI},
129 {2, 0, MCA, 1, PCI}
130 };
131
132 struct pci_probe_table_args {
133 u_char bus;
134 u_char found;
135 };
136
137 struct pci_route_interrupt_args {
138 u_char bus; /* Source bus. */
139 u_char irq; /* Source slot:pin. */
140 int vector; /* Return value. */
141 };
142
143 static mpfps_t mpfps;
144 static mpcth_t mpct;
145 static void *ioapics[NAPICID];
146 static bus_datum *busses;
147 static int mptable_nioapics, mptable_nbusses, mptable_maxbusid;
148 static int pci0 = -1;
149
150 MALLOC_DEFINE(M_MPTABLE, "MP Table", "MP Table Items");
151
152 static enum intr_polarity conforming_polarity(u_char src_bus,
153 u_char src_bus_irq);
154 static enum intr_trigger conforming_trigger(u_char src_bus, u_char src_bus_irq);
155 static enum intr_polarity intentry_polarity(int_entry_ptr intr);
156 static enum intr_trigger intentry_trigger(int_entry_ptr intr);
157 static int lookup_bus_type(char *name);
158 static void mptable_count_items(void);
159 static void mptable_count_items_handler(u_char *entry, void *arg);
160 #ifdef MPTABLE_FORCE_HTT
161 static void mptable_hyperthread_fixup(u_int id_mask);
162 #endif
163 static void mptable_parse_apics_and_busses(void);
164 static void mptable_parse_apics_and_busses_handler(u_char *entry,
165 void *arg);
166 static void mptable_parse_default_config_ints(void);
167 static void mptable_parse_ints(void);
168 static void mptable_parse_ints_handler(u_char *entry, void *arg);
169 static void mptable_parse_io_int(int_entry_ptr intr);
170 static void mptable_parse_local_int(int_entry_ptr intr);
171 static void mptable_pci_probe_table_handler(u_char *entry, void *arg);
172 static void mptable_pci_route_interrupt_handler(u_char *entry, void *arg);
173 static void mptable_pci_setup(void);
174 static int mptable_probe(void);
175 static int mptable_probe_cpus(void);
176 static void mptable_probe_cpus_handler(u_char *entry, void *arg __unused);
177 static void mptable_register(void *dummy);
178 static int mptable_setup_local(void);
179 static int mptable_setup_io(void);
180 static void mptable_walk_table(mptable_entry_handler *handler, void *arg);
181 static int search_for_sig(u_int32_t target, int count);
182
183 static struct apic_enumerator mptable_enumerator = {
184 "MPTable",
185 mptable_probe,
186 mptable_probe_cpus,
187 mptable_setup_local,
188 mptable_setup_io
189 };
190
191 /*
192 * look for the MP spec signature
193 */
194
195 static int
196 search_for_sig(u_int32_t target, int count)
197 {
198 int x;
199 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
200
201 for (x = 0; x < count; x += 4)
202 if (addr[x] == MP_SIG)
203 /* make array index a byte index */
204 return (target + (x * sizeof(u_int32_t)));
205 return (-1);
206 }
207
208 static int
209 lookup_bus_type(char *name)
210 {
211 int x;
212
213 for (x = 0; x < MAX_BUSTYPE; ++x)
214 if (strncmp(bus_type_table[x].name, name, 6) == 0)
215 return (bus_type_table[x].type);
216
217 return (UNKNOWN_BUSTYPE);
218 }
219
220 /*
221 * Look for an Intel MP spec table (ie, SMP capable hardware).
222 */
223 static int
224 mptable_probe(void)
225 {
226 int x;
227 u_long segment;
228 u_int32_t target;
229
230 /* see if EBDA exists */
231 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
232 /* search first 1K of EBDA */
233 target = (u_int32_t) (segment << 4);
234 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
235 goto found;
236 } else {
237 /* last 1K of base memory, effective 'top of base' passed in */
238 target = (u_int32_t) ((basemem * 1024) - 0x400);
239 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
240 goto found;
241 }
242
243 /* search the BIOS */
244 target = (u_int32_t) BIOS_BASE;
245 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
246 goto found;
247
248 /* nothing found */
249 return (ENXIO);
250
251 found:
252 mpfps = (mpfps_t)(KERNBASE + x);
253
254 /* Map in the configuration table if it exists. */
255 if (mpfps->config_type != 0) {
256 if (bootverbose)
257 printf(
258 "MP Table version 1.%d found using Default Configuration %d\n",
259 mpfps->spec_rev, mpfps->config_type);
260 if (mpfps->config_type != 5 && mpfps->config_type != 6) {
261 printf(
262 "MP Table Default Configuration %d is unsupported\n",
263 mpfps->config_type);
264 return (ENXIO);
265 }
266 mpct = NULL;
267 } else {
268 if ((uintptr_t)mpfps->pap >= 1024 * 1024) {
269 printf("%s: Unable to map MP Configuration Table\n",
270 __func__);
271 return (ENXIO);
272 }
273 mpct = (mpcth_t)(KERNBASE + (uintptr_t)mpfps->pap);
274 if (mpct->base_table_length + (uintptr_t)mpfps->pap >=
275 1024 * 1024) {
276 printf("%s: Unable to map end of MP Config Table\n",
277 __func__);
278 return (ENXIO);
279 }
280 if (mpct->signature[0] != 'P' || mpct->signature[1] != 'C' ||
281 mpct->signature[2] != 'M' || mpct->signature[3] != 'P') {
282 printf("%s: MP Config Table has bad signature: %c%c%c%c\n",
283 __func__, mpct->signature[0], mpct->signature[1],
284 mpct->signature[2], mpct->signature[3]);
285 return (ENXIO);
286 }
287 if (bootverbose)
288 printf(
289 "MP Configuration Table version 1.%d found at %p\n",
290 mpct->spec_rev, mpct);
291 }
292
293 return (-100);
294 }
295
296 /*
297 * Run through the MP table enumerating CPUs.
298 */
299 static int
300 mptable_probe_cpus(void)
301 {
302 u_int cpu_mask;
303
304 /* Is this a pre-defined config? */
305 if (mpfps->config_type != 0) {
306 lapic_create(0, 1);
307 lapic_create(1, 0);
308 } else {
309 cpu_mask = 0;
310 mptable_walk_table(mptable_probe_cpus_handler, &cpu_mask);
311 #ifdef MPTABLE_FORCE_HTT
312 mptable_hyperthread_fixup(cpu_mask);
313 #endif
314 }
315 return (0);
316 }
317
318 /*
319 * Initialize the local APIC on the BSP.
320 */
321 static int
322 mptable_setup_local(void)
323 {
324
325 /* Is this a pre-defined config? */
326 printf("MPTable: <");
327 if (mpfps->config_type != 0) {
328 lapic_init(DEFAULT_APIC_BASE);
329 printf("Default Configuration %d", mpfps->config_type);
330 } else {
331 lapic_init((uintptr_t)mpct->apic_address);
332 printf("%.*s %.*s", (int)sizeof(mpct->oem_id), mpct->oem_id,
333 (int)sizeof(mpct->product_id), mpct->product_id);
334 }
335 printf(">\n");
336 return (0);
337 }
338
339 /*
340 * Run through the MP table enumerating I/O APICs.
341 */
342 static int
343 mptable_setup_io(void)
344 {
345 int i;
346 u_char byte;
347
348 /* First, we count individual items and allocate arrays. */
349 mptable_count_items();
350 busses = malloc((mptable_maxbusid + 1) * sizeof(bus_datum), M_MPTABLE,
351 M_WAITOK);
352 for (i = 0; i <= mptable_maxbusid; i++)
353 busses[i].bus_type = NOBUS;
354
355 /* Second, we run through adding I/O APIC's and busses. */
356 ioapic_enable_mixed_mode();
357 mptable_parse_apics_and_busses();
358
359 /* Third, we run through the table tweaking interrupt sources. */
360 mptable_parse_ints();
361
362 /* Fourth, we register all the I/O APIC's. */
363 for (i = 0; i < NAPICID; i++)
364 if (ioapics[i] != NULL)
365 ioapic_register(ioapics[i]);
366
367 /* Fifth, we setup data structures to handle PCI interrupt routing. */
368 mptable_pci_setup();
369
370 /* Finally, we throw the switch to enable the I/O APIC's. */
371 if (mpfps->mpfb2 & MPFB2_IMCR_PRESENT) {
372 outb(0x22, 0x70); /* select IMCR */
373 byte = inb(0x23); /* current contents */
374 byte |= 0x01; /* mask external INTR */
375 outb(0x23, byte); /* disconnect 8259s/NMI */
376 }
377
378 return (0);
379 }
380
381 static void
382 mptable_register(void *dummy __unused)
383 {
384
385 apic_register_enumerator(&mptable_enumerator);
386 }
387 SYSINIT(mptable_register, SI_SUB_CPU - 1, SI_ORDER_FIRST, mptable_register,
388 NULL)
389
390 /*
391 * Call the handler routine for each entry in the MP config table.
392 */
393 static void
394 mptable_walk_table(mptable_entry_handler *handler, void *arg)
395 {
396 u_int i;
397 u_char *entry;
398
399 entry = (u_char *)(mpct + 1);
400 for (i = 0; i < mpct->entry_count; i++) {
401 switch (*entry) {
402 case MPCT_ENTRY_PROCESSOR:
403 case MPCT_ENTRY_IOAPIC:
404 case MPCT_ENTRY_BUS:
405 case MPCT_ENTRY_INT:
406 case MPCT_ENTRY_LOCAL_INT:
407 break;
408 default:
409 panic("%s: Unknown MP Config Entry %d\n", __func__,
410 (int)*entry);
411 }
412 handler(entry, arg);
413 entry += basetable_entry_types[*entry].length;
414 }
415 }
416
417 static void
418 mptable_probe_cpus_handler(u_char *entry, void *arg)
419 {
420 proc_entry_ptr proc;
421 u_int *cpu_mask;
422
423 switch (*entry) {
424 case MPCT_ENTRY_PROCESSOR:
425 proc = (proc_entry_ptr)entry;
426 if (proc->cpu_flags & PROCENTRY_FLAG_EN) {
427 lapic_create(proc->apic_id, proc->cpu_flags &
428 PROCENTRY_FLAG_BP);
429 cpu_mask = (u_int *)arg;
430 *cpu_mask |= (1 << proc->apic_id);
431 }
432 break;
433 }
434 }
435
436 static void
437 mptable_count_items_handler(u_char *entry, void *arg __unused)
438 {
439 io_apic_entry_ptr apic;
440 bus_entry_ptr bus;
441
442 switch (*entry) {
443 case MPCT_ENTRY_BUS:
444 bus = (bus_entry_ptr)entry;
445 mptable_nbusses++;
446 if (bus->bus_id > mptable_maxbusid)
447 mptable_maxbusid = bus->bus_id;
448 break;
449 case MPCT_ENTRY_IOAPIC:
450 apic = (io_apic_entry_ptr)entry;
451 if (apic->apic_flags & IOAPICENTRY_FLAG_EN)
452 mptable_nioapics++;
453 break;
454 }
455 }
456
457 /*
458 * Count items in the table.
459 */
460 static void
461 mptable_count_items(void)
462 {
463
464 /* Is this a pre-defined config? */
465 if (mpfps->config_type != 0) {
466 mptable_nioapics = 1;
467 switch (mpfps->config_type) {
468 case 1:
469 case 2:
470 case 3:
471 case 4:
472 mptable_nbusses = 1;
473 break;
474 case 5:
475 case 6:
476 case 7:
477 mptable_nbusses = 2;
478 break;
479 default:
480 panic("Unknown pre-defined MP Table config type %d",
481 mpfps->config_type);
482 }
483 mptable_maxbusid = mptable_nbusses - 1;
484 } else
485 mptable_walk_table(mptable_count_items_handler, NULL);
486 }
487
488 /*
489 * Add a bus or I/O APIC from an entry in the table.
490 */
491 static void
492 mptable_parse_apics_and_busses_handler(u_char *entry, void *arg __unused)
493 {
494 io_apic_entry_ptr apic;
495 bus_entry_ptr bus;
496 enum busTypes bus_type;
497 int i;
498
499
500 switch (*entry) {
501 case MPCT_ENTRY_BUS:
502 bus = (bus_entry_ptr)entry;
503 bus_type = lookup_bus_type(bus->bus_type);
504 if (bus_type == UNKNOWN_BUSTYPE) {
505 printf("MPTable: Unknown bus %d type \"", bus->bus_id);
506 for (i = 0; i < 6; i++)
507 printf("%c", bus->bus_type[i]);
508 printf("\"\n");
509 }
510 busses[bus->bus_id].bus_id = bus->bus_id;
511 busses[bus->bus_id].bus_type = bus_type;
512 break;
513 case MPCT_ENTRY_IOAPIC:
514 apic = (io_apic_entry_ptr)entry;
515 if (!(apic->apic_flags & IOAPICENTRY_FLAG_EN))
516 break;
517 if (apic->apic_id >= NAPICID)
518 panic("%s: I/O APIC ID %d too high", __func__,
519 apic->apic_id);
520 if (ioapics[apic->apic_id] != NULL)
521 panic("%s: Double APIC ID %d", __func__,
522 apic->apic_id);
523 ioapics[apic->apic_id] = ioapic_create(
524 (uintptr_t)apic->apic_address, apic->apic_id, -1);
525 break;
526 default:
527 break;
528 }
529 }
530
531 /*
532 * Enumerate I/O APIC's and busses.
533 */
534 static void
535 mptable_parse_apics_and_busses(void)
536 {
537
538 /* Is this a pre-defined config? */
539 if (mpfps->config_type != 0) {
540 ioapics[2] = ioapic_create(DEFAULT_IO_APIC_BASE, 2, 0);
541 busses[0].bus_id = 0;
542 busses[0].bus_type = default_data[mpfps->config_type - 1][2];
543 if (mptable_nbusses > 1) {
544 busses[1].bus_id = 1;
545 busses[1].bus_type =
546 default_data[mpfps->config_type - 1][4];
547 }
548 } else
549 mptable_walk_table(mptable_parse_apics_and_busses_handler,
550 NULL);
551 }
552
553 /*
554 * Determine conforming polarity for a given bus type.
555 */
556 static enum intr_polarity
557 conforming_polarity(u_char src_bus, u_char src_bus_irq)
558 {
559
560 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus));
561 switch (busses[src_bus].bus_type) {
562 case ISA:
563 case EISA:
564 return (INTR_POLARITY_HIGH);
565 case PCI:
566 return (INTR_POLARITY_LOW);
567 default:
568 panic("%s: unknown bus type %d", __func__,
569 busses[src_bus].bus_type);
570 }
571 }
572
573 /*
574 * Determine conforming trigger for a given bus type.
575 */
576 static enum intr_trigger
577 conforming_trigger(u_char src_bus, u_char src_bus_irq)
578 {
579
580 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus));
581 switch (busses[src_bus].bus_type) {
582 case ISA:
583 #ifndef PC98
584 if (elcr_found)
585 return (elcr_read_trigger(src_bus_irq));
586 else
587 #endif
588 return (INTR_TRIGGER_EDGE);
589 case PCI:
590 return (INTR_TRIGGER_LEVEL);
591 #ifndef PC98
592 case EISA:
593 KASSERT(src_bus_irq < 16, ("Invalid EISA IRQ %d", src_bus_irq));
594 KASSERT(elcr_found, ("Missing ELCR"));
595 return (elcr_read_trigger(src_bus_irq));
596 #endif
597 default:
598 panic("%s: unknown bus type %d", __func__,
599 busses[src_bus].bus_type);
600 }
601 }
602
603 static enum intr_polarity
604 intentry_polarity(int_entry_ptr intr)
605 {
606
607 switch (intr->int_flags & INTENTRY_FLAGS_POLARITY) {
608 case INTENTRY_FLAGS_POLARITY_CONFORM:
609 return (conforming_polarity(intr->src_bus_id,
610 intr->src_bus_irq));
611 case INTENTRY_FLAGS_POLARITY_ACTIVEHI:
612 return (INTR_POLARITY_HIGH);
613 case INTENTRY_FLAGS_POLARITY_ACTIVELO:
614 return (INTR_POLARITY_LOW);
615 default:
616 panic("Bogus interrupt flags");
617 }
618 }
619
620 static enum intr_trigger
621 intentry_trigger(int_entry_ptr intr)
622 {
623
624 switch (intr->int_flags & INTENTRY_FLAGS_TRIGGER) {
625 case INTENTRY_FLAGS_TRIGGER_CONFORM:
626 return (conforming_trigger(intr->src_bus_id,
627 intr->src_bus_irq));
628 case INTENTRY_FLAGS_TRIGGER_EDGE:
629 return (INTR_TRIGGER_EDGE);
630 case INTENTRY_FLAGS_TRIGGER_LEVEL:
631 return (INTR_TRIGGER_LEVEL);
632 default:
633 panic("Bogus interrupt flags");
634 }
635 }
636
637 /*
638 * Parse an interrupt entry for an I/O interrupt routed to a pin on an I/O APIC.
639 */
640 static void
641 mptable_parse_io_int(int_entry_ptr intr)
642 {
643 void *ioapic;
644 u_int pin, apic_id;
645
646 apic_id = intr->dst_apic_id;
647 if (intr->dst_apic_id == 0xff) {
648 /*
649 * An APIC ID of 0xff means that the interrupt is connected
650 * to the specified pin on all I/O APICs in the system. If
651 * there is only one I/O APIC, then use that APIC to route
652 * the interrupts. If there is more than one I/O APIC, then
653 * punt.
654 */
655 if (mptable_nioapics == 1) {
656 apic_id = 0;
657 while (ioapics[apic_id] == NULL)
658 apic_id++;
659 } else {
660 printf(
661 "MPTable: Ignoring global interrupt entry for pin %d\n",
662 intr->dst_apic_int);
663 return;
664 }
665 }
666 if (apic_id >= NAPICID) {
667 printf("MPTable: Ignoring interrupt entry for ioapic%d\n",
668 intr->dst_apic_id);
669 return;
670 }
671 ioapic = ioapics[apic_id];
672 if (ioapic == NULL) {
673 printf(
674 "MPTable: Ignoring interrupt entry for missing ioapic%d\n",
675 apic_id);
676 return;
677 }
678 pin = intr->dst_apic_int;
679 switch (intr->int_type) {
680 case INTENTRY_TYPE_INT:
681 switch (busses[intr->src_bus_id].bus_type) {
682 case NOBUS:
683 panic("interrupt from missing bus");
684 case ISA:
685 case EISA:
686 if (busses[intr->src_bus_id].bus_type == ISA)
687 ioapic_set_bus(ioapic, pin, APIC_BUS_ISA);
688 else
689 ioapic_set_bus(ioapic, pin, APIC_BUS_EISA);
690 if (intr->src_bus_irq == pin)
691 break;
692 ioapic_remap_vector(ioapic, pin, intr->src_bus_irq);
693 if (ioapic_get_vector(ioapic, intr->src_bus_irq) ==
694 intr->src_bus_irq)
695 ioapic_disable_pin(ioapic, intr->src_bus_irq);
696 break;
697 case PCI:
698 ioapic_set_bus(ioapic, pin, APIC_BUS_PCI);
699 break;
700 default:
701 ioapic_set_bus(ioapic, pin, APIC_BUS_UNKNOWN);
702 break;
703 }
704 break;
705 case INTENTRY_TYPE_NMI:
706 ioapic_set_nmi(ioapic, pin);
707 break;
708 case INTENTRY_TYPE_SMI:
709 ioapic_set_smi(ioapic, pin);
710 break;
711 case INTENTRY_TYPE_EXTINT:
712 ioapic_set_extint(ioapic, pin);
713 break;
714 default:
715 panic("%s: invalid interrupt entry type %d\n", __func__,
716 intr->int_type);
717 }
718 if (intr->int_type == INTENTRY_TYPE_INT ||
719 (intr->int_flags & INTENTRY_FLAGS_TRIGGER) !=
720 INTENTRY_FLAGS_TRIGGER_CONFORM)
721 ioapic_set_triggermode(ioapic, pin, intentry_trigger(intr));
722 if (intr->int_type == INTENTRY_TYPE_INT ||
723 (intr->int_flags & INTENTRY_FLAGS_POLARITY) !=
724 INTENTRY_FLAGS_POLARITY_CONFORM)
725 ioapic_set_polarity(ioapic, pin, intentry_polarity(intr));
726 }
727
728 /*
729 * Parse an interrupt entry for a local APIC LVT pin.
730 */
731 static void
732 mptable_parse_local_int(int_entry_ptr intr)
733 {
734 u_int apic_id, pin;
735
736 if (intr->dst_apic_id == 0xff)
737 apic_id = APIC_ID_ALL;
738 else
739 apic_id = intr->dst_apic_id;
740 if (intr->dst_apic_int == 0)
741 pin = LVT_LINT0;
742 else
743 pin = LVT_LINT1;
744 switch (intr->int_type) {
745 case INTENTRY_TYPE_INT:
746 #if 1
747 printf(
748 "MPTable: Ignoring vectored local interrupt for LINTIN%d vector %d\n",
749 intr->dst_apic_int, intr->src_bus_irq);
750 return;
751 #else
752 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_FIXED);
753 break;
754 #endif
755 case INTENTRY_TYPE_NMI:
756 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_NMI);
757 break;
758 case INTENTRY_TYPE_SMI:
759 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_SMI);
760 break;
761 case INTENTRY_TYPE_EXTINT:
762 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_EXTINT);
763 break;
764 default:
765 panic("%s: invalid interrupt entry type %d\n", __func__,
766 intr->int_type);
767 }
768 if ((intr->int_flags & INTENTRY_FLAGS_TRIGGER) !=
769 INTENTRY_FLAGS_TRIGGER_CONFORM)
770 lapic_set_lvt_triggermode(apic_id, pin,
771 intentry_trigger(intr));
772 if ((intr->int_flags & INTENTRY_FLAGS_POLARITY) !=
773 INTENTRY_FLAGS_POLARITY_CONFORM)
774 lapic_set_lvt_polarity(apic_id, pin, intentry_polarity(intr));
775 }
776
777 /*
778 * Parse interrupt entries.
779 */
780 static void
781 mptable_parse_ints_handler(u_char *entry, void *arg __unused)
782 {
783 int_entry_ptr intr;
784
785 intr = (int_entry_ptr)entry;
786 switch (*entry) {
787 case MPCT_ENTRY_INT:
788 mptable_parse_io_int(intr);
789 break;
790 case MPCT_ENTRY_LOCAL_INT:
791 mptable_parse_local_int(intr);
792 break;
793 }
794 }
795
796 /*
797 * Configure interrupt pins for a default configuration. For details see
798 * Table 5-2 in Section 5 of the MP Table specification.
799 */
800 static void
801 mptable_parse_default_config_ints(void)
802 {
803 struct INTENTRY entry;
804 int pin;
805
806 /*
807 * All default configs route IRQs from bus 0 to the first 16 pins
808 * of the first I/O APIC with an APIC ID of 2.
809 */
810 entry.type = MPCT_ENTRY_INT;
811 entry.int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
812 INTENTRY_FLAGS_TRIGGER_CONFORM;
813 entry.src_bus_id = 0;
814 entry.dst_apic_id = 2;
815
816 /* Run through all 16 pins. */
817 for (pin = 0; pin < 16; pin++) {
818 entry.dst_apic_int = pin;
819 switch (pin) {
820 case 0:
821 /* Pin 0 is an ExtINT pin. */
822 entry.int_type = INTENTRY_TYPE_EXTINT;
823 break;
824 case 2:
825 /* IRQ 0 is routed to pin 2. */
826 entry.int_type = INTENTRY_TYPE_INT;
827 entry.src_bus_irq = 0;
828 break;
829 default:
830 /* All other pins are identity mapped. */
831 entry.int_type = INTENTRY_TYPE_INT;
832 entry.src_bus_irq = pin;
833 break;
834 }
835 mptable_parse_io_int(&entry);
836 }
837
838 /* Certain configs disable certain pins. */
839 if (mpfps->config_type == 7)
840 ioapic_disable_pin(ioapics[2], 0);
841 if (mpfps->config_type == 2) {
842 ioapic_disable_pin(ioapics[2], 2);
843 ioapic_disable_pin(ioapics[2], 13);
844 }
845 }
846
847 /*
848 * Configure the interrupt pins
849 */
850 static void
851 mptable_parse_ints(void)
852 {
853
854 /* Is this a pre-defined config? */
855 if (mpfps->config_type != 0) {
856 /* Configure LINT pins. */
857 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT0, APIC_LVT_DM_EXTINT);
858 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT1, APIC_LVT_DM_NMI);
859
860 /* Configure I/O APIC pins. */
861 mptable_parse_default_config_ints();
862 } else
863 mptable_walk_table(mptable_parse_ints_handler, NULL);
864 }
865
866 #ifdef MPTABLE_FORCE_HTT
867 /*
868 * Perform a hyperthreading "fix-up" to enumerate any logical CPU's
869 * that aren't already listed in the table.
870 *
871 * XXX: We assume that all of the physical CPUs in the
872 * system have the same number of logical CPUs.
873 *
874 * XXX: We assume that APIC ID's are allocated such that
875 * the APIC ID's for a physical processor are aligned
876 * with the number of logical CPU's in the processor.
877 */
878 static void
879 mptable_hyperthread_fixup(u_int id_mask)
880 {
881 u_int i, id, logical_cpus;
882
883 /* Nothing to do if there is no HTT support. */
884 if ((cpu_feature & CPUID_HTT) == 0)
885 return;
886 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
887 if (logical_cpus <= 1)
888 return;
889
890 /*
891 * For each APIC ID of a CPU that is set in the mask,
892 * scan the other candidate APIC ID's for this
893 * physical processor. If any of those ID's are
894 * already in the table, then kill the fixup.
895 */
896 for (id = 0; id < NAPICID; id++) {
897 if ((id_mask & 1 << id) == 0)
898 continue;
899 /* First, make sure we are on a logical_cpus boundary. */
900 if (id % logical_cpus != 0)
901 return;
902 for (i = id + 1; i < id + logical_cpus; i++)
903 if ((id_mask & 1 << i) != 0)
904 return;
905 }
906
907 /*
908 * Ok, the ID's checked out, so perform the fixup by
909 * adding the logical CPUs.
910 */
911 while ((id = ffs(id_mask)) != 0) {
912 id--;
913 for (i = id + 1; i < id + logical_cpus; i++) {
914 if (bootverbose)
915 printf(
916 "MPTable: Adding logical CPU %d from main CPU %d\n",
917 i, id);
918 lapic_create(i, 0);
919 }
920 id_mask &= ~(1 << id);
921 }
922 }
923 #endif /* MPTABLE_FORCE_HTT */
924
925 /*
926 * Support code for routing PCI interrupts using the MP Table.
927 */
928 static void
929 mptable_pci_setup(void)
930 {
931 int i;
932
933 /*
934 * Find the first pci bus and call it 0. Panic if pci0 is not
935 * bus zero and there are multiple PCI busses.
936 */
937 for (i = 0; i <= mptable_maxbusid; i++)
938 if (busses[i].bus_type == PCI) {
939 if (pci0 == -1)
940 pci0 = i;
941 else if (pci0 != 0)
942 panic(
943 "MPTable contains multiple PCI busses but no PCI bus 0");
944 }
945 }
946
947 static void
948 mptable_pci_probe_table_handler(u_char *entry, void *arg)
949 {
950 struct pci_probe_table_args *args;
951 int_entry_ptr intr;
952
953 if (*entry != MPCT_ENTRY_INT)
954 return;
955 intr = (int_entry_ptr)entry;
956 args = (struct pci_probe_table_args *)arg;
957 KASSERT(args->bus <= mptable_maxbusid,
958 ("bus %d is too big", args->bus));
959 KASSERT(busses[args->bus].bus_type == PCI, ("probing for non-PCI bus"));
960 if (intr->src_bus_id == args->bus)
961 args->found = 1;
962 }
963
964 int
965 mptable_pci_probe_table(int bus)
966 {
967 struct pci_probe_table_args args;
968
969 if (bus < 0)
970 return (EINVAL);
971 if (mpct == NULL || pci0 == -1 || pci0 + bus > mptable_maxbusid)
972 return (ENXIO);
973 if (busses[pci0 + bus].bus_type != PCI)
974 return (ENXIO);
975 args.bus = pci0 + bus;
976 args.found = 0;
977 mptable_walk_table(mptable_pci_probe_table_handler, &args);
978 if (args.found == 0)
979 return (ENXIO);
980 return (0);
981 }
982
983 static void
984 mptable_pci_route_interrupt_handler(u_char *entry, void *arg)
985 {
986 struct pci_route_interrupt_args *args;
987 int_entry_ptr intr;
988 int vector;
989
990 if (*entry != MPCT_ENTRY_INT)
991 return;
992 intr = (int_entry_ptr)entry;
993 args = (struct pci_route_interrupt_args *)arg;
994 if (intr->src_bus_id != args->bus || intr->src_bus_irq != args->irq)
995 return;
996
997 /* Make sure the APIC maps to a known APIC. */
998 KASSERT(ioapics[intr->dst_apic_id] != NULL,
999 ("No I/O APIC %d to route interrupt to", intr->dst_apic_id));
1000
1001 /*
1002 * Look up the vector for this APIC / pin combination. If we
1003 * have previously matched an entry for this PCI IRQ but it
1004 * has the same vector as this entry, just return. Otherwise,
1005 * we use the vector for this APIC / pin combination.
1006 */
1007 vector = ioapic_get_vector(ioapics[intr->dst_apic_id],
1008 intr->dst_apic_int);
1009 if (args->vector == vector)
1010 return;
1011 KASSERT(args->vector == -1,
1012 ("Multiple IRQs for PCI interrupt %d.%d.INT%c: %d and %d\n",
1013 args->bus, args->irq >> 2, 'A' + (args->irq & 0x3), args->vector,
1014 vector));
1015 args->vector = vector;
1016 }
1017
1018 int
1019 mptable_pci_route_interrupt(device_t pcib, device_t dev, int pin)
1020 {
1021 struct pci_route_interrupt_args args;
1022 int slot;
1023
1024 /* Like ACPI, pin numbers are 0-3, not 1-4. */
1025 pin--;
1026 KASSERT(pci0 != -1, ("do not know how to route PCI interrupts"));
1027 args.bus = pci_get_bus(dev) + pci0;
1028 slot = pci_get_slot(dev);
1029
1030 /*
1031 * PCI interrupt entries in the MP Table encode both the slot and
1032 * pin into the IRQ with the pin being the two least significant
1033 * bits, the slot being the next five bits, and the most significant
1034 * bit being reserved.
1035 */
1036 args.irq = slot << 2 | pin;
1037 args.vector = -1;
1038 mptable_walk_table(mptable_pci_route_interrupt_handler, &args);
1039 if (args.vector < 0) {
1040 device_printf(pcib, "unable to route slot %d INT%c\n", slot,
1041 'A' + pin);
1042 return (PCI_INVALID_IRQ);
1043 }
1044 if (bootverbose)
1045 device_printf(pcib, "slot %d INT%c routed to irq %d\n", slot,
1046 'A' + pin, args.vector);
1047 return (args.vector);
1048 }
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