1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD: releng/6.2/sys/i386/i386/mptable.c 145080 2005-04-14 17:59:58Z jhb $");
29
30 #include "opt_mptable_force_htt.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36
37 #include <vm/vm.h>
38 #include <vm/vm_param.h>
39 #include <vm/pmap.h>
40
41 #include <machine/apicreg.h>
42 #include <machine/frame.h>
43 #include <machine/intr_machdep.h>
44 #include <machine/apicvar.h>
45 #include <machine/md_var.h>
46 #include <machine/mptable.h>
47 #include <machine/specialreg.h>
48
49 #include <dev/pci/pcivar.h>
50
51 /* string defined by the Intel MP Spec as identifying the MP table */
52 #define MP_SIG 0x5f504d5f /* _MP_ */
53
54 #define NAPICID 32 /* Max number of APIC's */
55
56 #ifdef PC98
57 #define BIOS_BASE (0xe8000)
58 #define BIOS_SIZE (0x18000)
59 #else
60 #define BIOS_BASE (0xf0000)
61 #define BIOS_SIZE (0x10000)
62 #endif
63 #define BIOS_COUNT (BIOS_SIZE/4)
64
65 typedef void mptable_entry_handler(u_char *entry, void *arg);
66
67 static basetable_entry basetable_entry_types[] =
68 {
69 {0, 20, "Processor"},
70 {1, 8, "Bus"},
71 {2, 8, "I/O APIC"},
72 {3, 8, "I/O INT"},
73 {4, 8, "Local INT"}
74 };
75
76 typedef struct BUSDATA {
77 u_char bus_id;
78 enum busTypes bus_type;
79 } bus_datum;
80
81 typedef struct INTDATA {
82 u_char int_type;
83 u_short int_flags;
84 u_char src_bus_id;
85 u_char src_bus_irq;
86 u_char dst_apic_id;
87 u_char dst_apic_int;
88 u_char int_vector;
89 } io_int, local_int;
90
91 typedef struct BUSTYPENAME {
92 u_char type;
93 char name[7];
94 } bus_type_name;
95
96 /* From MP spec v1.4, table 4-8. */
97 static bus_type_name bus_type_table[] =
98 {
99 {UNKNOWN_BUSTYPE, "CBUS "},
100 {UNKNOWN_BUSTYPE, "CBUSII"},
101 {EISA, "EISA "},
102 {UNKNOWN_BUSTYPE, "FUTURE"},
103 {UNKNOWN_BUSTYPE, "INTERN"},
104 {ISA, "ISA "},
105 {UNKNOWN_BUSTYPE, "MBI "},
106 {UNKNOWN_BUSTYPE, "MBII "},
107 {MCA, "MCA "},
108 {UNKNOWN_BUSTYPE, "MPI "},
109 {UNKNOWN_BUSTYPE, "MPSA "},
110 {UNKNOWN_BUSTYPE, "NUBUS "},
111 {PCI, "PCI "},
112 {UNKNOWN_BUSTYPE, "PCMCIA"},
113 {UNKNOWN_BUSTYPE, "TC "},
114 {UNKNOWN_BUSTYPE, "VL "},
115 {UNKNOWN_BUSTYPE, "VME "},
116 {UNKNOWN_BUSTYPE, "XPRESS"}
117 };
118
119 /* From MP spec v1.4, table 5-1. */
120 static int default_data[7][5] =
121 {
122 /* nbus, id0, type0, id1, type1 */
123 {1, 0, ISA, 255, NOBUS},
124 {1, 0, EISA, 255, NOBUS},
125 {1, 0, EISA, 255, NOBUS},
126 {1, 0, MCA, 255, NOBUS},
127 {2, 0, ISA, 1, PCI},
128 {2, 0, EISA, 1, PCI},
129 {2, 0, MCA, 1, PCI}
130 };
131
132 struct pci_probe_table_args {
133 u_char bus;
134 u_char found;
135 };
136
137 struct pci_route_interrupt_args {
138 u_char bus; /* Source bus. */
139 u_char irq; /* Source slot:pin. */
140 int vector; /* Return value. */
141 };
142
143 static mpfps_t mpfps;
144 static mpcth_t mpct;
145 static void *ioapics[NAPICID];
146 static bus_datum *busses;
147 static int mptable_nioapics, mptable_nbusses, mptable_maxbusid;
148 static int pci0 = -1;
149
150 static MALLOC_DEFINE(M_MPTABLE, "MP Table", "MP Table Items");
151
152 static enum intr_polarity conforming_polarity(u_char src_bus,
153 u_char src_bus_irq);
154 static enum intr_trigger conforming_trigger(u_char src_bus, u_char src_bus_irq);
155 static enum intr_polarity intentry_polarity(int_entry_ptr intr);
156 static enum intr_trigger intentry_trigger(int_entry_ptr intr);
157 static int lookup_bus_type(char *name);
158 static void mptable_count_items(void);
159 static void mptable_count_items_handler(u_char *entry, void *arg);
160 #ifdef MPTABLE_FORCE_HTT
161 static void mptable_hyperthread_fixup(u_int id_mask);
162 #endif
163 static void mptable_parse_apics_and_busses(void);
164 static void mptable_parse_apics_and_busses_handler(u_char *entry,
165 void *arg);
166 static void mptable_parse_default_config_ints(void);
167 static void mptable_parse_ints(void);
168 static void mptable_parse_ints_handler(u_char *entry, void *arg);
169 static void mptable_parse_io_int(int_entry_ptr intr);
170 static void mptable_parse_local_int(int_entry_ptr intr);
171 static void mptable_pci_probe_table_handler(u_char *entry, void *arg);
172 static void mptable_pci_route_interrupt_handler(u_char *entry, void *arg);
173 static void mptable_pci_setup(void);
174 static int mptable_probe(void);
175 static int mptable_probe_cpus(void);
176 static void mptable_probe_cpus_handler(u_char *entry, void *arg __unused);
177 static void mptable_register(void *dummy);
178 static int mptable_setup_local(void);
179 static int mptable_setup_io(void);
180 static void mptable_walk_table(mptable_entry_handler *handler, void *arg);
181 static int search_for_sig(u_int32_t target, int count);
182
183 static struct apic_enumerator mptable_enumerator = {
184 "MPTable",
185 mptable_probe,
186 mptable_probe_cpus,
187 mptable_setup_local,
188 mptable_setup_io
189 };
190
191 /*
192 * look for the MP spec signature
193 */
194
195 static int
196 search_for_sig(u_int32_t target, int count)
197 {
198 int x;
199 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
200
201 for (x = 0; x < count; x += 4)
202 if (addr[x] == MP_SIG)
203 /* make array index a byte index */
204 return (target + (x * sizeof(u_int32_t)));
205 return (-1);
206 }
207
208 static int
209 lookup_bus_type(char *name)
210 {
211 int x;
212
213 for (x = 0; x < MAX_BUSTYPE; ++x)
214 if (strncmp(bus_type_table[x].name, name, 6) == 0)
215 return (bus_type_table[x].type);
216
217 return (UNKNOWN_BUSTYPE);
218 }
219
220 /*
221 * Look for an Intel MP spec table (ie, SMP capable hardware).
222 */
223 static int
224 mptable_probe(void)
225 {
226 int x;
227 u_long segment;
228 u_int32_t target;
229
230 /* see if EBDA exists */
231 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
232 /* search first 1K of EBDA */
233 target = (u_int32_t) (segment << 4);
234 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
235 goto found;
236 } else {
237 /* last 1K of base memory, effective 'top of base' passed in */
238 target = (u_int32_t) ((basemem * 1024) - 0x400);
239 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
240 goto found;
241 }
242
243 /* search the BIOS */
244 target = (u_int32_t) BIOS_BASE;
245 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
246 goto found;
247
248 /* nothing found */
249 return (ENXIO);
250
251 found:
252 mpfps = (mpfps_t)(KERNBASE + x);
253
254 /* Map in the configuration table if it exists. */
255 if (mpfps->config_type != 0) {
256 if (bootverbose)
257 printf(
258 "MP Table version 1.%d found using Default Configuration %d\n",
259 mpfps->spec_rev, mpfps->config_type);
260 if (mpfps->config_type != 5 && mpfps->config_type != 6) {
261 printf(
262 "MP Table Default Configuration %d is unsupported\n",
263 mpfps->config_type);
264 return (ENXIO);
265 }
266 mpct = NULL;
267 } else {
268 if ((uintptr_t)mpfps->pap >= 1024 * 1024) {
269 printf("%s: Unable to map MP Configuration Table\n",
270 __func__);
271 return (ENXIO);
272 }
273 mpct = (mpcth_t)(KERNBASE + (uintptr_t)mpfps->pap);
274 if (mpct->base_table_length + (uintptr_t)mpfps->pap >=
275 1024 * 1024) {
276 printf("%s: Unable to map end of MP Config Table\n",
277 __func__);
278 return (ENXIO);
279 }
280 if (mpct->signature[0] != 'P' || mpct->signature[1] != 'C' ||
281 mpct->signature[2] != 'M' || mpct->signature[3] != 'P') {
282 printf("%s: MP Config Table has bad signature: %c%c%c%c\n",
283 __func__, mpct->signature[0], mpct->signature[1],
284 mpct->signature[2], mpct->signature[3]);
285 return (ENXIO);
286 }
287 if (bootverbose)
288 printf(
289 "MP Configuration Table version 1.%d found at %p\n",
290 mpct->spec_rev, mpct);
291 }
292
293 return (-100);
294 }
295
296 /*
297 * Run through the MP table enumerating CPUs.
298 */
299 static int
300 mptable_probe_cpus(void)
301 {
302 u_int cpu_mask;
303
304 /* Is this a pre-defined config? */
305 if (mpfps->config_type != 0) {
306 lapic_create(0, 1);
307 lapic_create(1, 0);
308 } else {
309 cpu_mask = 0;
310 mptable_walk_table(mptable_probe_cpus_handler, &cpu_mask);
311 #ifdef MPTABLE_FORCE_HTT
312 mptable_hyperthread_fixup(cpu_mask);
313 #endif
314 }
315 return (0);
316 }
317
318 /*
319 * Initialize the local APIC on the BSP.
320 */
321 static int
322 mptable_setup_local(void)
323 {
324
325 /* Is this a pre-defined config? */
326 printf("MPTable: <");
327 if (mpfps->config_type != 0) {
328 lapic_init(DEFAULT_APIC_BASE);
329 printf("Default Configuration %d", mpfps->config_type);
330 } else {
331 lapic_init((uintptr_t)mpct->apic_address);
332 printf("%.*s %.*s", (int)sizeof(mpct->oem_id), mpct->oem_id,
333 (int)sizeof(mpct->product_id), mpct->product_id);
334 }
335 printf(">\n");
336 return (0);
337 }
338
339 /*
340 * Run through the MP table enumerating I/O APICs.
341 */
342 static int
343 mptable_setup_io(void)
344 {
345 int i;
346 u_char byte;
347
348 /* First, we count individual items and allocate arrays. */
349 mptable_count_items();
350 busses = malloc((mptable_maxbusid + 1) * sizeof(bus_datum), M_MPTABLE,
351 M_WAITOK);
352 for (i = 0; i <= mptable_maxbusid; i++)
353 busses[i].bus_type = NOBUS;
354
355 /* Second, we run through adding I/O APIC's and busses. */
356 mptable_parse_apics_and_busses();
357
358 /* Third, we run through the table tweaking interrupt sources. */
359 mptable_parse_ints();
360
361 /* Fourth, we register all the I/O APIC's. */
362 for (i = 0; i < NAPICID; i++)
363 if (ioapics[i] != NULL)
364 ioapic_register(ioapics[i]);
365
366 /* Fifth, we setup data structures to handle PCI interrupt routing. */
367 mptable_pci_setup();
368
369 /* Finally, we throw the switch to enable the I/O APIC's. */
370 if (mpfps->mpfb2 & MPFB2_IMCR_PRESENT) {
371 outb(0x22, 0x70); /* select IMCR */
372 byte = inb(0x23); /* current contents */
373 byte |= 0x01; /* mask external INTR */
374 outb(0x23, byte); /* disconnect 8259s/NMI */
375 }
376
377 return (0);
378 }
379
380 static void
381 mptable_register(void *dummy __unused)
382 {
383
384 apic_register_enumerator(&mptable_enumerator);
385 }
386 SYSINIT(mptable_register, SI_SUB_CPU - 1, SI_ORDER_FIRST, mptable_register,
387 NULL)
388
389 /*
390 * Call the handler routine for each entry in the MP config table.
391 */
392 static void
393 mptable_walk_table(mptable_entry_handler *handler, void *arg)
394 {
395 u_int i;
396 u_char *entry;
397
398 entry = (u_char *)(mpct + 1);
399 for (i = 0; i < mpct->entry_count; i++) {
400 switch (*entry) {
401 case MPCT_ENTRY_PROCESSOR:
402 case MPCT_ENTRY_IOAPIC:
403 case MPCT_ENTRY_BUS:
404 case MPCT_ENTRY_INT:
405 case MPCT_ENTRY_LOCAL_INT:
406 break;
407 default:
408 panic("%s: Unknown MP Config Entry %d\n", __func__,
409 (int)*entry);
410 }
411 handler(entry, arg);
412 entry += basetable_entry_types[*entry].length;
413 }
414 }
415
416 static void
417 mptable_probe_cpus_handler(u_char *entry, void *arg)
418 {
419 proc_entry_ptr proc;
420 u_int *cpu_mask;
421
422 switch (*entry) {
423 case MPCT_ENTRY_PROCESSOR:
424 proc = (proc_entry_ptr)entry;
425 if (proc->cpu_flags & PROCENTRY_FLAG_EN) {
426 lapic_create(proc->apic_id, proc->cpu_flags &
427 PROCENTRY_FLAG_BP);
428 cpu_mask = (u_int *)arg;
429 *cpu_mask |= (1 << proc->apic_id);
430 }
431 break;
432 }
433 }
434
435 static void
436 mptable_count_items_handler(u_char *entry, void *arg __unused)
437 {
438 io_apic_entry_ptr apic;
439 bus_entry_ptr bus;
440
441 switch (*entry) {
442 case MPCT_ENTRY_BUS:
443 bus = (bus_entry_ptr)entry;
444 mptable_nbusses++;
445 if (bus->bus_id > mptable_maxbusid)
446 mptable_maxbusid = bus->bus_id;
447 break;
448 case MPCT_ENTRY_IOAPIC:
449 apic = (io_apic_entry_ptr)entry;
450 if (apic->apic_flags & IOAPICENTRY_FLAG_EN)
451 mptable_nioapics++;
452 break;
453 }
454 }
455
456 /*
457 * Count items in the table.
458 */
459 static void
460 mptable_count_items(void)
461 {
462
463 /* Is this a pre-defined config? */
464 if (mpfps->config_type != 0) {
465 mptable_nioapics = 1;
466 switch (mpfps->config_type) {
467 case 1:
468 case 2:
469 case 3:
470 case 4:
471 mptable_nbusses = 1;
472 break;
473 case 5:
474 case 6:
475 case 7:
476 mptable_nbusses = 2;
477 break;
478 default:
479 panic("Unknown pre-defined MP Table config type %d",
480 mpfps->config_type);
481 }
482 mptable_maxbusid = mptable_nbusses - 1;
483 } else
484 mptable_walk_table(mptable_count_items_handler, NULL);
485 }
486
487 /*
488 * Add a bus or I/O APIC from an entry in the table.
489 */
490 static void
491 mptable_parse_apics_and_busses_handler(u_char *entry, void *arg __unused)
492 {
493 io_apic_entry_ptr apic;
494 bus_entry_ptr bus;
495 enum busTypes bus_type;
496 int i;
497
498
499 switch (*entry) {
500 case MPCT_ENTRY_BUS:
501 bus = (bus_entry_ptr)entry;
502 bus_type = lookup_bus_type(bus->bus_type);
503 if (bus_type == UNKNOWN_BUSTYPE) {
504 printf("MPTable: Unknown bus %d type \"", bus->bus_id);
505 for (i = 0; i < 6; i++)
506 printf("%c", bus->bus_type[i]);
507 printf("\"\n");
508 }
509 busses[bus->bus_id].bus_id = bus->bus_id;
510 busses[bus->bus_id].bus_type = bus_type;
511 break;
512 case MPCT_ENTRY_IOAPIC:
513 apic = (io_apic_entry_ptr)entry;
514 if (!(apic->apic_flags & IOAPICENTRY_FLAG_EN))
515 break;
516 if (apic->apic_id >= NAPICID)
517 panic("%s: I/O APIC ID %d too high", __func__,
518 apic->apic_id);
519 if (ioapics[apic->apic_id] != NULL)
520 panic("%s: Double APIC ID %d", __func__,
521 apic->apic_id);
522 ioapics[apic->apic_id] = ioapic_create(
523 (uintptr_t)apic->apic_address, apic->apic_id, -1);
524 break;
525 default:
526 break;
527 }
528 }
529
530 /*
531 * Enumerate I/O APIC's and busses.
532 */
533 static void
534 mptable_parse_apics_and_busses(void)
535 {
536
537 /* Is this a pre-defined config? */
538 if (mpfps->config_type != 0) {
539 ioapics[2] = ioapic_create(DEFAULT_IO_APIC_BASE, 2, 0);
540 busses[0].bus_id = 0;
541 busses[0].bus_type = default_data[mpfps->config_type - 1][2];
542 if (mptable_nbusses > 1) {
543 busses[1].bus_id = 1;
544 busses[1].bus_type =
545 default_data[mpfps->config_type - 1][4];
546 }
547 } else
548 mptable_walk_table(mptable_parse_apics_and_busses_handler,
549 NULL);
550 }
551
552 /*
553 * Determine conforming polarity for a given bus type.
554 */
555 static enum intr_polarity
556 conforming_polarity(u_char src_bus, u_char src_bus_irq)
557 {
558
559 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus));
560 switch (busses[src_bus].bus_type) {
561 case ISA:
562 case EISA:
563 return (INTR_POLARITY_HIGH);
564 case PCI:
565 return (INTR_POLARITY_LOW);
566 default:
567 panic("%s: unknown bus type %d", __func__,
568 busses[src_bus].bus_type);
569 }
570 }
571
572 /*
573 * Determine conforming trigger for a given bus type.
574 */
575 static enum intr_trigger
576 conforming_trigger(u_char src_bus, u_char src_bus_irq)
577 {
578
579 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus));
580 switch (busses[src_bus].bus_type) {
581 case ISA:
582 #ifndef PC98
583 if (elcr_found)
584 return (elcr_read_trigger(src_bus_irq));
585 else
586 #endif
587 return (INTR_TRIGGER_EDGE);
588 case PCI:
589 return (INTR_TRIGGER_LEVEL);
590 #ifndef PC98
591 case EISA:
592 KASSERT(src_bus_irq < 16, ("Invalid EISA IRQ %d", src_bus_irq));
593 KASSERT(elcr_found, ("Missing ELCR"));
594 return (elcr_read_trigger(src_bus_irq));
595 #endif
596 default:
597 panic("%s: unknown bus type %d", __func__,
598 busses[src_bus].bus_type);
599 }
600 }
601
602 static enum intr_polarity
603 intentry_polarity(int_entry_ptr intr)
604 {
605
606 switch (intr->int_flags & INTENTRY_FLAGS_POLARITY) {
607 case INTENTRY_FLAGS_POLARITY_CONFORM:
608 return (conforming_polarity(intr->src_bus_id,
609 intr->src_bus_irq));
610 case INTENTRY_FLAGS_POLARITY_ACTIVEHI:
611 return (INTR_POLARITY_HIGH);
612 case INTENTRY_FLAGS_POLARITY_ACTIVELO:
613 return (INTR_POLARITY_LOW);
614 default:
615 panic("Bogus interrupt flags");
616 }
617 }
618
619 static enum intr_trigger
620 intentry_trigger(int_entry_ptr intr)
621 {
622
623 switch (intr->int_flags & INTENTRY_FLAGS_TRIGGER) {
624 case INTENTRY_FLAGS_TRIGGER_CONFORM:
625 return (conforming_trigger(intr->src_bus_id,
626 intr->src_bus_irq));
627 case INTENTRY_FLAGS_TRIGGER_EDGE:
628 return (INTR_TRIGGER_EDGE);
629 case INTENTRY_FLAGS_TRIGGER_LEVEL:
630 return (INTR_TRIGGER_LEVEL);
631 default:
632 panic("Bogus interrupt flags");
633 }
634 }
635
636 /*
637 * Parse an interrupt entry for an I/O interrupt routed to a pin on an I/O APIC.
638 */
639 static void
640 mptable_parse_io_int(int_entry_ptr intr)
641 {
642 void *ioapic;
643 u_int pin, apic_id;
644
645 apic_id = intr->dst_apic_id;
646 if (intr->dst_apic_id == 0xff) {
647 /*
648 * An APIC ID of 0xff means that the interrupt is connected
649 * to the specified pin on all I/O APICs in the system. If
650 * there is only one I/O APIC, then use that APIC to route
651 * the interrupts. If there is more than one I/O APIC, then
652 * punt.
653 */
654 if (mptable_nioapics == 1) {
655 apic_id = 0;
656 while (ioapics[apic_id] == NULL)
657 apic_id++;
658 } else {
659 printf(
660 "MPTable: Ignoring global interrupt entry for pin %d\n",
661 intr->dst_apic_int);
662 return;
663 }
664 }
665 if (apic_id >= NAPICID) {
666 printf("MPTable: Ignoring interrupt entry for ioapic%d\n",
667 intr->dst_apic_id);
668 return;
669 }
670 ioapic = ioapics[apic_id];
671 if (ioapic == NULL) {
672 printf(
673 "MPTable: Ignoring interrupt entry for missing ioapic%d\n",
674 apic_id);
675 return;
676 }
677 pin = intr->dst_apic_int;
678 switch (intr->int_type) {
679 case INTENTRY_TYPE_INT:
680 switch (busses[intr->src_bus_id].bus_type) {
681 case NOBUS:
682 panic("interrupt from missing bus");
683 case ISA:
684 case EISA:
685 if (busses[intr->src_bus_id].bus_type == ISA)
686 ioapic_set_bus(ioapic, pin, APIC_BUS_ISA);
687 else
688 ioapic_set_bus(ioapic, pin, APIC_BUS_EISA);
689 if (intr->src_bus_irq == pin)
690 break;
691 ioapic_remap_vector(ioapic, pin, intr->src_bus_irq);
692 if (ioapic_get_vector(ioapic, intr->src_bus_irq) ==
693 intr->src_bus_irq)
694 ioapic_disable_pin(ioapic, intr->src_bus_irq);
695 break;
696 case PCI:
697 ioapic_set_bus(ioapic, pin, APIC_BUS_PCI);
698 break;
699 default:
700 ioapic_set_bus(ioapic, pin, APIC_BUS_UNKNOWN);
701 break;
702 }
703 break;
704 case INTENTRY_TYPE_NMI:
705 ioapic_set_nmi(ioapic, pin);
706 break;
707 case INTENTRY_TYPE_SMI:
708 ioapic_set_smi(ioapic, pin);
709 break;
710 case INTENTRY_TYPE_EXTINT:
711 ioapic_set_extint(ioapic, pin);
712 break;
713 default:
714 panic("%s: invalid interrupt entry type %d\n", __func__,
715 intr->int_type);
716 }
717 if (intr->int_type == INTENTRY_TYPE_INT ||
718 (intr->int_flags & INTENTRY_FLAGS_TRIGGER) !=
719 INTENTRY_FLAGS_TRIGGER_CONFORM)
720 ioapic_set_triggermode(ioapic, pin, intentry_trigger(intr));
721 if (intr->int_type == INTENTRY_TYPE_INT ||
722 (intr->int_flags & INTENTRY_FLAGS_POLARITY) !=
723 INTENTRY_FLAGS_POLARITY_CONFORM)
724 ioapic_set_polarity(ioapic, pin, intentry_polarity(intr));
725 }
726
727 /*
728 * Parse an interrupt entry for a local APIC LVT pin.
729 */
730 static void
731 mptable_parse_local_int(int_entry_ptr intr)
732 {
733 u_int apic_id, pin;
734
735 if (intr->dst_apic_id == 0xff)
736 apic_id = APIC_ID_ALL;
737 else
738 apic_id = intr->dst_apic_id;
739 if (intr->dst_apic_int == 0)
740 pin = LVT_LINT0;
741 else
742 pin = LVT_LINT1;
743 switch (intr->int_type) {
744 case INTENTRY_TYPE_INT:
745 #if 1
746 printf(
747 "MPTable: Ignoring vectored local interrupt for LINTIN%d vector %d\n",
748 intr->dst_apic_int, intr->src_bus_irq);
749 return;
750 #else
751 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_FIXED);
752 break;
753 #endif
754 case INTENTRY_TYPE_NMI:
755 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_NMI);
756 break;
757 case INTENTRY_TYPE_SMI:
758 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_SMI);
759 break;
760 case INTENTRY_TYPE_EXTINT:
761 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_EXTINT);
762 break;
763 default:
764 panic("%s: invalid interrupt entry type %d\n", __func__,
765 intr->int_type);
766 }
767 if ((intr->int_flags & INTENTRY_FLAGS_TRIGGER) !=
768 INTENTRY_FLAGS_TRIGGER_CONFORM)
769 lapic_set_lvt_triggermode(apic_id, pin,
770 intentry_trigger(intr));
771 if ((intr->int_flags & INTENTRY_FLAGS_POLARITY) !=
772 INTENTRY_FLAGS_POLARITY_CONFORM)
773 lapic_set_lvt_polarity(apic_id, pin, intentry_polarity(intr));
774 }
775
776 /*
777 * Parse interrupt entries.
778 */
779 static void
780 mptable_parse_ints_handler(u_char *entry, void *arg __unused)
781 {
782 int_entry_ptr intr;
783
784 intr = (int_entry_ptr)entry;
785 switch (*entry) {
786 case MPCT_ENTRY_INT:
787 mptable_parse_io_int(intr);
788 break;
789 case MPCT_ENTRY_LOCAL_INT:
790 mptable_parse_local_int(intr);
791 break;
792 }
793 }
794
795 /*
796 * Configure interrupt pins for a default configuration. For details see
797 * Table 5-2 in Section 5 of the MP Table specification.
798 */
799 static void
800 mptable_parse_default_config_ints(void)
801 {
802 struct INTENTRY entry;
803 int pin;
804
805 /*
806 * All default configs route IRQs from bus 0 to the first 16 pins
807 * of the first I/O APIC with an APIC ID of 2.
808 */
809 entry.type = MPCT_ENTRY_INT;
810 entry.int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
811 INTENTRY_FLAGS_TRIGGER_CONFORM;
812 entry.src_bus_id = 0;
813 entry.dst_apic_id = 2;
814
815 /* Run through all 16 pins. */
816 for (pin = 0; pin < 16; pin++) {
817 entry.dst_apic_int = pin;
818 switch (pin) {
819 case 0:
820 /* Pin 0 is an ExtINT pin. */
821 entry.int_type = INTENTRY_TYPE_EXTINT;
822 break;
823 case 2:
824 /* IRQ 0 is routed to pin 2. */
825 entry.int_type = INTENTRY_TYPE_INT;
826 entry.src_bus_irq = 0;
827 break;
828 default:
829 /* All other pins are identity mapped. */
830 entry.int_type = INTENTRY_TYPE_INT;
831 entry.src_bus_irq = pin;
832 break;
833 }
834 mptable_parse_io_int(&entry);
835 }
836
837 /* Certain configs disable certain pins. */
838 if (mpfps->config_type == 7)
839 ioapic_disable_pin(ioapics[2], 0);
840 if (mpfps->config_type == 2) {
841 ioapic_disable_pin(ioapics[2], 2);
842 ioapic_disable_pin(ioapics[2], 13);
843 }
844 }
845
846 /*
847 * Configure the interrupt pins
848 */
849 static void
850 mptable_parse_ints(void)
851 {
852
853 /* Is this a pre-defined config? */
854 if (mpfps->config_type != 0) {
855 /* Configure LINT pins. */
856 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT0, APIC_LVT_DM_EXTINT);
857 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT1, APIC_LVT_DM_NMI);
858
859 /* Configure I/O APIC pins. */
860 mptable_parse_default_config_ints();
861 } else
862 mptable_walk_table(mptable_parse_ints_handler, NULL);
863 }
864
865 #ifdef MPTABLE_FORCE_HTT
866 /*
867 * Perform a hyperthreading "fix-up" to enumerate any logical CPU's
868 * that aren't already listed in the table.
869 *
870 * XXX: We assume that all of the physical CPUs in the
871 * system have the same number of logical CPUs.
872 *
873 * XXX: We assume that APIC ID's are allocated such that
874 * the APIC ID's for a physical processor are aligned
875 * with the number of logical CPU's in the processor.
876 */
877 static void
878 mptable_hyperthread_fixup(u_int id_mask)
879 {
880 u_int i, id, logical_cpus;
881
882 /* Nothing to do if there is no HTT support. */
883 if ((cpu_feature & CPUID_HTT) == 0)
884 return;
885 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
886 if (logical_cpus <= 1)
887 return;
888
889 /*
890 * For each APIC ID of a CPU that is set in the mask,
891 * scan the other candidate APIC ID's for this
892 * physical processor. If any of those ID's are
893 * already in the table, then kill the fixup.
894 */
895 for (id = 0; id < NAPICID; id++) {
896 if ((id_mask & 1 << id) == 0)
897 continue;
898 /* First, make sure we are on a logical_cpus boundary. */
899 if (id % logical_cpus != 0)
900 return;
901 for (i = id + 1; i < id + logical_cpus; i++)
902 if ((id_mask & 1 << i) != 0)
903 return;
904 }
905
906 /*
907 * Ok, the ID's checked out, so perform the fixup by
908 * adding the logical CPUs.
909 */
910 while ((id = ffs(id_mask)) != 0) {
911 id--;
912 for (i = id + 1; i < id + logical_cpus; i++) {
913 if (bootverbose)
914 printf(
915 "MPTable: Adding logical CPU %d from main CPU %d\n",
916 i, id);
917 lapic_create(i, 0);
918 }
919 id_mask &= ~(1 << id);
920 }
921 }
922 #endif /* MPTABLE_FORCE_HTT */
923
924 /*
925 * Support code for routing PCI interrupts using the MP Table.
926 */
927 static void
928 mptable_pci_setup(void)
929 {
930 int i;
931
932 /*
933 * Find the first pci bus and call it 0. Panic if pci0 is not
934 * bus zero and there are multiple PCI busses.
935 */
936 for (i = 0; i <= mptable_maxbusid; i++)
937 if (busses[i].bus_type == PCI) {
938 if (pci0 == -1)
939 pci0 = i;
940 else if (pci0 != 0)
941 panic(
942 "MPTable contains multiple PCI busses but no PCI bus 0");
943 }
944 }
945
946 static void
947 mptable_pci_probe_table_handler(u_char *entry, void *arg)
948 {
949 struct pci_probe_table_args *args;
950 int_entry_ptr intr;
951
952 if (*entry != MPCT_ENTRY_INT)
953 return;
954 intr = (int_entry_ptr)entry;
955 args = (struct pci_probe_table_args *)arg;
956 KASSERT(args->bus <= mptable_maxbusid,
957 ("bus %d is too big", args->bus));
958 KASSERT(busses[args->bus].bus_type == PCI, ("probing for non-PCI bus"));
959 if (intr->src_bus_id == args->bus)
960 args->found = 1;
961 }
962
963 int
964 mptable_pci_probe_table(int bus)
965 {
966 struct pci_probe_table_args args;
967
968 if (bus < 0)
969 return (EINVAL);
970 if (mpct == NULL || pci0 == -1 || pci0 + bus > mptable_maxbusid)
971 return (ENXIO);
972 if (busses[pci0 + bus].bus_type != PCI)
973 return (ENXIO);
974 args.bus = pci0 + bus;
975 args.found = 0;
976 mptable_walk_table(mptable_pci_probe_table_handler, &args);
977 if (args.found == 0)
978 return (ENXIO);
979 return (0);
980 }
981
982 static void
983 mptable_pci_route_interrupt_handler(u_char *entry, void *arg)
984 {
985 struct pci_route_interrupt_args *args;
986 int_entry_ptr intr;
987 int vector;
988
989 if (*entry != MPCT_ENTRY_INT)
990 return;
991 intr = (int_entry_ptr)entry;
992 args = (struct pci_route_interrupt_args *)arg;
993 if (intr->src_bus_id != args->bus || intr->src_bus_irq != args->irq)
994 return;
995
996 /* Make sure the APIC maps to a known APIC. */
997 KASSERT(ioapics[intr->dst_apic_id] != NULL,
998 ("No I/O APIC %d to route interrupt to", intr->dst_apic_id));
999
1000 /*
1001 * Look up the vector for this APIC / pin combination. If we
1002 * have previously matched an entry for this PCI IRQ but it
1003 * has the same vector as this entry, just return. Otherwise,
1004 * we use the vector for this APIC / pin combination.
1005 */
1006 vector = ioapic_get_vector(ioapics[intr->dst_apic_id],
1007 intr->dst_apic_int);
1008 if (args->vector == vector)
1009 return;
1010 KASSERT(args->vector == -1,
1011 ("Multiple IRQs for PCI interrupt %d.%d.INT%c: %d and %d\n",
1012 args->bus, args->irq >> 2, 'A' + (args->irq & 0x3), args->vector,
1013 vector));
1014 args->vector = vector;
1015 }
1016
1017 int
1018 mptable_pci_route_interrupt(device_t pcib, device_t dev, int pin)
1019 {
1020 struct pci_route_interrupt_args args;
1021 int slot;
1022
1023 /* Like ACPI, pin numbers are 0-3, not 1-4. */
1024 pin--;
1025 KASSERT(pci0 != -1, ("do not know how to route PCI interrupts"));
1026 args.bus = pci_get_bus(dev) + pci0;
1027 slot = pci_get_slot(dev);
1028
1029 /*
1030 * PCI interrupt entries in the MP Table encode both the slot and
1031 * pin into the IRQ with the pin being the two least significant
1032 * bits, the slot being the next five bits, and the most significant
1033 * bit being reserved.
1034 */
1035 args.irq = slot << 2 | pin;
1036 args.vector = -1;
1037 mptable_walk_table(mptable_pci_route_interrupt_handler, &args);
1038 if (args.vector < 0) {
1039 device_printf(pcib, "unable to route slot %d INT%c\n", slot,
1040 'A' + pin);
1041 return (PCI_INVALID_IRQ);
1042 }
1043 if (bootverbose)
1044 device_printf(pcib, "slot %d INT%c routed to irq %d\n", slot,
1045 'A' + pin, args.vector);
1046 return (args.vector);
1047 }
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