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sys/i386/i386/mptable.c
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1 /*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include "opt_mptable_force_htt.h" 31 #include <sys/param.h> 32 #include <sys/systm.h> 33 #include <sys/bus.h> 34 #include <sys/kernel.h> 35 #include <sys/malloc.h> 36 37 #include <vm/vm.h> 38 #include <vm/vm_param.h> 39 #include <vm/pmap.h> 40 41 #include <machine/apicreg.h> 42 #include <machine/frame.h> 43 #include <machine/intr_machdep.h> 44 #include <machine/apicvar.h> 45 #include <machine/md_var.h> 46 #include <machine/mptable.h> 47 #include <machine/specialreg.h> 48 49 #include <dev/pci/pcivar.h> 50 51 /* string defined by the Intel MP Spec as identifying the MP table */ 52 #define MP_SIG 0x5f504d5f /* _MP_ */ 53 54 #define MAX_LAPIC_ID 31 /* Max local APIC ID for HTT fixup */ 55 56 #ifdef PC98 57 #define BIOS_BASE (0xe8000) 58 #define BIOS_SIZE (0x18000) 59 #else 60 #define BIOS_BASE (0xf0000) 61 #define BIOS_SIZE (0x10000) 62 #endif 63 #define BIOS_COUNT (BIOS_SIZE/4) 64 65 typedef void mptable_entry_handler(u_char *entry, void *arg); 66 67 static basetable_entry basetable_entry_types[] = 68 { 69 {0, 20, "Processor"}, 70 {1, 8, "Bus"}, 71 {2, 8, "I/O APIC"}, 72 {3, 8, "I/O INT"}, 73 {4, 8, "Local INT"} 74 }; 75 76 typedef struct BUSDATA { 77 u_char bus_id; 78 enum busTypes bus_type; 79 } bus_datum; 80 81 typedef struct INTDATA { 82 u_char int_type; 83 u_short int_flags; 84 u_char src_bus_id; 85 u_char src_bus_irq; 86 u_char dst_apic_id; 87 u_char dst_apic_int; 88 u_char int_vector; 89 } io_int, local_int; 90 91 typedef struct BUSTYPENAME { 92 u_char type; 93 char name[7]; 94 } bus_type_name; 95 96 /* From MP spec v1.4, table 4-8. */ 97 static bus_type_name bus_type_table[] = 98 { 99 {UNKNOWN_BUSTYPE, "CBUS "}, 100 {UNKNOWN_BUSTYPE, "CBUSII"}, 101 {EISA, "EISA "}, 102 {UNKNOWN_BUSTYPE, "FUTURE"}, 103 {UNKNOWN_BUSTYPE, "INTERN"}, 104 {ISA, "ISA "}, 105 {UNKNOWN_BUSTYPE, "MBI "}, 106 {UNKNOWN_BUSTYPE, "MBII "}, 107 {MCA, "MCA "}, 108 {UNKNOWN_BUSTYPE, "MPI "}, 109 {UNKNOWN_BUSTYPE, "MPSA "}, 110 {UNKNOWN_BUSTYPE, "NUBUS "}, 111 {PCI, "PCI "}, 112 {UNKNOWN_BUSTYPE, "PCMCIA"}, 113 {UNKNOWN_BUSTYPE, "TC "}, 114 {UNKNOWN_BUSTYPE, "VL "}, 115 {UNKNOWN_BUSTYPE, "VME "}, 116 {UNKNOWN_BUSTYPE, "XPRESS"} 117 }; 118 119 /* From MP spec v1.4, table 5-1. */ 120 static int default_data[7][5] = 121 { 122 /* nbus, id0, type0, id1, type1 */ 123 {1, 0, ISA, 255, NOBUS}, 124 {1, 0, EISA, 255, NOBUS}, 125 {1, 0, EISA, 255, NOBUS}, 126 {1, 0, MCA, 255, NOBUS}, 127 {2, 0, ISA, 1, PCI}, 128 {2, 0, EISA, 1, PCI}, 129 {2, 0, MCA, 1, PCI} 130 }; 131 132 struct pci_probe_table_args { 133 u_char bus; 134 u_char found; 135 }; 136 137 struct pci_route_interrupt_args { 138 u_char bus; /* Source bus. */ 139 u_char irq; /* Source slot:pin. */ 140 int vector; /* Return value. */ 141 }; 142 143 static mpfps_t mpfps; 144 static mpcth_t mpct; 145 static void *ioapics[MAX_APIC_ID + 1]; 146 static bus_datum *busses; 147 static int mptable_nioapics, mptable_nbusses, mptable_maxbusid; 148 static int pci0 = -1; 149 150 static MALLOC_DEFINE(M_MPTABLE, "MP Table", "MP Table Items"); 151 152 static enum intr_polarity conforming_polarity(u_char src_bus, 153 u_char src_bus_irq); 154 static enum intr_trigger conforming_trigger(u_char src_bus, u_char src_bus_irq); 155 static enum intr_polarity intentry_polarity(int_entry_ptr intr); 156 static enum intr_trigger intentry_trigger(int_entry_ptr intr); 157 static int lookup_bus_type(char *name); 158 static void mptable_count_items(void); 159 static void mptable_count_items_handler(u_char *entry, void *arg); 160 #ifdef MPTABLE_FORCE_HTT 161 static void mptable_hyperthread_fixup(u_int id_mask); 162 #endif 163 static void mptable_parse_apics_and_busses(void); 164 static void mptable_parse_apics_and_busses_handler(u_char *entry, 165 void *arg); 166 static void mptable_parse_default_config_ints(void); 167 static void mptable_parse_ints(void); 168 static void mptable_parse_ints_handler(u_char *entry, void *arg); 169 static void mptable_parse_io_int(int_entry_ptr intr); 170 static void mptable_parse_local_int(int_entry_ptr intr); 171 static void mptable_pci_probe_table_handler(u_char *entry, void *arg); 172 static void mptable_pci_route_interrupt_handler(u_char *entry, void *arg); 173 static void mptable_pci_setup(void); 174 static int mptable_probe(void); 175 static int mptable_probe_cpus(void); 176 static void mptable_probe_cpus_handler(u_char *entry, void *arg __unused); 177 static void mptable_register(void *dummy); 178 static int mptable_setup_local(void); 179 static int mptable_setup_io(void); 180 static void mptable_walk_table(mptable_entry_handler *handler, void *arg); 181 static int search_for_sig(u_int32_t target, int count); 182 183 static struct apic_enumerator mptable_enumerator = { 184 "MPTable", 185 mptable_probe, 186 mptable_probe_cpus, 187 mptable_setup_local, 188 mptable_setup_io 189 }; 190 191 /* 192 * look for the MP spec signature 193 */ 194 195 static int 196 search_for_sig(u_int32_t target, int count) 197 { 198 int x; 199 u_int32_t *addr = (u_int32_t *) (KERNBASE + target); 200 201 for (x = 0; x < count; x += 4) 202 if (addr[x] == MP_SIG) 203 /* make array index a byte index */ 204 return (target + (x * sizeof(u_int32_t))); 205 return (-1); 206 } 207 208 static int 209 lookup_bus_type(char *name) 210 { 211 int x; 212 213 for (x = 0; x < MAX_BUSTYPE; ++x) 214 if (strncmp(bus_type_table[x].name, name, 6) == 0) 215 return (bus_type_table[x].type); 216 217 return (UNKNOWN_BUSTYPE); 218 } 219 220 /* 221 * Look for an Intel MP spec table (ie, SMP capable hardware). 222 */ 223 static int 224 mptable_probe(void) 225 { 226 int x; 227 u_long segment; 228 u_int32_t target; 229 230 /* see if EBDA exists */ 231 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) { 232 /* search first 1K of EBDA */ 233 target = (u_int32_t) (segment << 4); 234 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 235 goto found; 236 } else { 237 /* last 1K of base memory, effective 'top of base' passed in */ 238 target = (u_int32_t) ((basemem * 1024) - 0x400); 239 if ((x = search_for_sig(target, 1024 / 4)) >= 0) 240 goto found; 241 } 242 243 /* search the BIOS */ 244 target = (u_int32_t) BIOS_BASE; 245 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0) 246 goto found; 247 248 /* nothing found */ 249 return (ENXIO); 250 251 found: 252 mpfps = (mpfps_t)(KERNBASE + x); 253 254 /* Map in the configuration table if it exists. */ 255 if (mpfps->config_type != 0) { 256 if (bootverbose) 257 printf( 258 "MP Table version 1.%d found using Default Configuration %d\n", 259 mpfps->spec_rev, mpfps->config_type); 260 if (mpfps->config_type != 5 && mpfps->config_type != 6) { 261 printf( 262 "MP Table Default Configuration %d is unsupported\n", 263 mpfps->config_type); 264 return (ENXIO); 265 } 266 mpct = NULL; 267 } else { 268 if ((uintptr_t)mpfps->pap >= 1024 * 1024) { 269 printf("%s: Unable to map MP Configuration Table\n", 270 __func__); 271 return (ENXIO); 272 } 273 mpct = (mpcth_t)(KERNBASE + (uintptr_t)mpfps->pap); 274 if (mpct->base_table_length + (uintptr_t)mpfps->pap >= 275 1024 * 1024) { 276 printf("%s: Unable to map end of MP Config Table\n", 277 __func__); 278 return (ENXIO); 279 } 280 if (mpct->signature[0] != 'P' || mpct->signature[1] != 'C' || 281 mpct->signature[2] != 'M' || mpct->signature[3] != 'P') { 282 printf("%s: MP Config Table has bad signature: %c%c%c%c\n", 283 __func__, mpct->signature[0], mpct->signature[1], 284 mpct->signature[2], mpct->signature[3]); 285 return (ENXIO); 286 } 287 if (bootverbose) 288 printf( 289 "MP Configuration Table version 1.%d found at %p\n", 290 mpct->spec_rev, mpct); 291 } 292 293 return (-100); 294 } 295 296 /* 297 * Run through the MP table enumerating CPUs. 298 */ 299 static int 300 mptable_probe_cpus(void) 301 { 302 u_int cpu_mask; 303 304 /* Is this a pre-defined config? */ 305 if (mpfps->config_type != 0) { 306 lapic_create(0, 1); 307 lapic_create(1, 0); 308 } else { 309 cpu_mask = 0; 310 mptable_walk_table(mptable_probe_cpus_handler, &cpu_mask); 311 #ifdef MPTABLE_FORCE_HTT 312 mptable_hyperthread_fixup(cpu_mask); 313 #endif 314 } 315 return (0); 316 } 317 318 /* 319 * Initialize the local APIC on the BSP. 320 */ 321 static int 322 mptable_setup_local(void) 323 { 324 325 /* Is this a pre-defined config? */ 326 printf("MPTable: <"); 327 if (mpfps->config_type != 0) { 328 lapic_init(DEFAULT_APIC_BASE); 329 printf("Default Configuration %d", mpfps->config_type); 330 } else { 331 lapic_init((uintptr_t)mpct->apic_address); 332 printf("%.*s %.*s", (int)sizeof(mpct->oem_id), mpct->oem_id, 333 (int)sizeof(mpct->product_id), mpct->product_id); 334 } 335 printf(">\n"); 336 return (0); 337 } 338 339 /* 340 * Run through the MP table enumerating I/O APICs. 341 */ 342 static int 343 mptable_setup_io(void) 344 { 345 int i; 346 u_char byte; 347 348 /* First, we count individual items and allocate arrays. */ 349 mptable_count_items(); 350 busses = malloc((mptable_maxbusid + 1) * sizeof(bus_datum), M_MPTABLE, 351 M_WAITOK); 352 for (i = 0; i <= mptable_maxbusid; i++) 353 busses[i].bus_type = NOBUS; 354 355 /* Second, we run through adding I/O APIC's and busses. */ 356 mptable_parse_apics_and_busses(); 357 358 /* Third, we run through the table tweaking interrupt sources. */ 359 mptable_parse_ints(); 360 361 /* Fourth, we register all the I/O APIC's. */ 362 for (i = 0; i <= MAX_APIC_ID; i++) 363 if (ioapics[i] != NULL) 364 ioapic_register(ioapics[i]); 365 366 /* Fifth, we setup data structures to handle PCI interrupt routing. */ 367 mptable_pci_setup(); 368 369 /* Finally, we throw the switch to enable the I/O APIC's. */ 370 if (mpfps->mpfb2 & MPFB2_IMCR_PRESENT) { 371 outb(0x22, 0x70); /* select IMCR */ 372 byte = inb(0x23); /* current contents */ 373 byte |= 0x01; /* mask external INTR */ 374 outb(0x23, byte); /* disconnect 8259s/NMI */ 375 } 376 377 return (0); 378 } 379 380 static void 381 mptable_register(void *dummy __unused) 382 { 383 384 apic_register_enumerator(&mptable_enumerator); 385 } 386 SYSINIT(mptable_register, SI_SUB_CPU - 1, SI_ORDER_FIRST, mptable_register, 387 NULL) 388 389 /* 390 * Call the handler routine for each entry in the MP config table. 391 */ 392 static void 393 mptable_walk_table(mptable_entry_handler *handler, void *arg) 394 { 395 u_int i; 396 u_char *entry; 397 398 entry = (u_char *)(mpct + 1); 399 for (i = 0; i < mpct->entry_count; i++) { 400 switch (*entry) { 401 case MPCT_ENTRY_PROCESSOR: 402 case MPCT_ENTRY_IOAPIC: 403 case MPCT_ENTRY_BUS: 404 case MPCT_ENTRY_INT: 405 case MPCT_ENTRY_LOCAL_INT: 406 break; 407 default: 408 panic("%s: Unknown MP Config Entry %d\n", __func__, 409 (int)*entry); 410 } 411 handler(entry, arg); 412 entry += basetable_entry_types[*entry].length; 413 } 414 } 415 416 static void 417 mptable_probe_cpus_handler(u_char *entry, void *arg) 418 { 419 proc_entry_ptr proc; 420 u_int *cpu_mask; 421 422 switch (*entry) { 423 case MPCT_ENTRY_PROCESSOR: 424 proc = (proc_entry_ptr)entry; 425 if (proc->cpu_flags & PROCENTRY_FLAG_EN) { 426 lapic_create(proc->apic_id, proc->cpu_flags & 427 PROCENTRY_FLAG_BP); 428 if (proc->apic_id < MAX_LAPIC_ID) { 429 cpu_mask = (u_int *)arg; 430 *cpu_mask |= (1ul << proc->apic_id); 431 } 432 } 433 break; 434 } 435 } 436 437 static void 438 mptable_count_items_handler(u_char *entry, void *arg __unused) 439 { 440 io_apic_entry_ptr apic; 441 bus_entry_ptr bus; 442 443 switch (*entry) { 444 case MPCT_ENTRY_BUS: 445 bus = (bus_entry_ptr)entry; 446 mptable_nbusses++; 447 if (bus->bus_id > mptable_maxbusid) 448 mptable_maxbusid = bus->bus_id; 449 break; 450 case MPCT_ENTRY_IOAPIC: 451 apic = (io_apic_entry_ptr)entry; 452 if (apic->apic_flags & IOAPICENTRY_FLAG_EN) 453 mptable_nioapics++; 454 break; 455 } 456 } 457 458 /* 459 * Count items in the table. 460 */ 461 static void 462 mptable_count_items(void) 463 { 464 465 /* Is this a pre-defined config? */ 466 if (mpfps->config_type != 0) { 467 mptable_nioapics = 1; 468 switch (mpfps->config_type) { 469 case 1: 470 case 2: 471 case 3: 472 case 4: 473 mptable_nbusses = 1; 474 break; 475 case 5: 476 case 6: 477 case 7: 478 mptable_nbusses = 2; 479 break; 480 default: 481 panic("Unknown pre-defined MP Table config type %d", 482 mpfps->config_type); 483 } 484 mptable_maxbusid = mptable_nbusses - 1; 485 } else 486 mptable_walk_table(mptable_count_items_handler, NULL); 487 } 488 489 /* 490 * Add a bus or I/O APIC from an entry in the table. 491 */ 492 static void 493 mptable_parse_apics_and_busses_handler(u_char *entry, void *arg __unused) 494 { 495 io_apic_entry_ptr apic; 496 bus_entry_ptr bus; 497 enum busTypes bus_type; 498 int i; 499 500 501 switch (*entry) { 502 case MPCT_ENTRY_BUS: 503 bus = (bus_entry_ptr)entry; 504 bus_type = lookup_bus_type(bus->bus_type); 505 if (bus_type == UNKNOWN_BUSTYPE) { 506 printf("MPTable: Unknown bus %d type \"", bus->bus_id); 507 for (i = 0; i < 6; i++) 508 printf("%c", bus->bus_type[i]); 509 printf("\"\n"); 510 } 511 busses[bus->bus_id].bus_id = bus->bus_id; 512 busses[bus->bus_id].bus_type = bus_type; 513 break; 514 case MPCT_ENTRY_IOAPIC: 515 apic = (io_apic_entry_ptr)entry; 516 if (!(apic->apic_flags & IOAPICENTRY_FLAG_EN)) 517 break; 518 if (apic->apic_id > MAX_APIC_ID) 519 panic("%s: I/O APIC ID %d too high", __func__, 520 apic->apic_id); 521 if (ioapics[apic->apic_id] != NULL) 522 panic("%s: Double APIC ID %d", __func__, 523 apic->apic_id); 524 ioapics[apic->apic_id] = ioapic_create( 525 (uintptr_t)apic->apic_address, apic->apic_id, -1); 526 break; 527 default: 528 break; 529 } 530 } 531 532 /* 533 * Enumerate I/O APIC's and busses. 534 */ 535 static void 536 mptable_parse_apics_and_busses(void) 537 { 538 539 /* Is this a pre-defined config? */ 540 if (mpfps->config_type != 0) { 541 ioapics[2] = ioapic_create(DEFAULT_IO_APIC_BASE, 2, 0); 542 busses[0].bus_id = 0; 543 busses[0].bus_type = default_data[mpfps->config_type - 1][2]; 544 if (mptable_nbusses > 1) { 545 busses[1].bus_id = 1; 546 busses[1].bus_type = 547 default_data[mpfps->config_type - 1][4]; 548 } 549 } else 550 mptable_walk_table(mptable_parse_apics_and_busses_handler, 551 NULL); 552 } 553 554 /* 555 * Determine conforming polarity for a given bus type. 556 */ 557 static enum intr_polarity 558 conforming_polarity(u_char src_bus, u_char src_bus_irq) 559 { 560 561 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus)); 562 switch (busses[src_bus].bus_type) { 563 case ISA: 564 case EISA: 565 return (INTR_POLARITY_HIGH); 566 case PCI: 567 return (INTR_POLARITY_LOW); 568 default: 569 panic("%s: unknown bus type %d", __func__, 570 busses[src_bus].bus_type); 571 } 572 } 573 574 /* 575 * Determine conforming trigger for a given bus type. 576 */ 577 static enum intr_trigger 578 conforming_trigger(u_char src_bus, u_char src_bus_irq) 579 { 580 581 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus)); 582 switch (busses[src_bus].bus_type) { 583 case ISA: 584 #ifndef PC98 585 if (elcr_found) 586 return (elcr_read_trigger(src_bus_irq)); 587 else 588 #endif 589 return (INTR_TRIGGER_EDGE); 590 case PCI: 591 return (INTR_TRIGGER_LEVEL); 592 #ifndef PC98 593 case EISA: 594 KASSERT(src_bus_irq < 16, ("Invalid EISA IRQ %d", src_bus_irq)); 595 KASSERT(elcr_found, ("Missing ELCR")); 596 return (elcr_read_trigger(src_bus_irq)); 597 #endif 598 default: 599 panic("%s: unknown bus type %d", __func__, 600 busses[src_bus].bus_type); 601 } 602 } 603 604 static enum intr_polarity 605 intentry_polarity(int_entry_ptr intr) 606 { 607 608 switch (intr->int_flags & INTENTRY_FLAGS_POLARITY) { 609 case INTENTRY_FLAGS_POLARITY_CONFORM: 610 return (conforming_polarity(intr->src_bus_id, 611 intr->src_bus_irq)); 612 case INTENTRY_FLAGS_POLARITY_ACTIVEHI: 613 return (INTR_POLARITY_HIGH); 614 case INTENTRY_FLAGS_POLARITY_ACTIVELO: 615 return (INTR_POLARITY_LOW); 616 default: 617 panic("Bogus interrupt flags"); 618 } 619 } 620 621 static enum intr_trigger 622 intentry_trigger(int_entry_ptr intr) 623 { 624 625 switch (intr->int_flags & INTENTRY_FLAGS_TRIGGER) { 626 case INTENTRY_FLAGS_TRIGGER_CONFORM: 627 return (conforming_trigger(intr->src_bus_id, 628 intr->src_bus_irq)); 629 case INTENTRY_FLAGS_TRIGGER_EDGE: 630 return (INTR_TRIGGER_EDGE); 631 case INTENTRY_FLAGS_TRIGGER_LEVEL: 632 return (INTR_TRIGGER_LEVEL); 633 default: 634 panic("Bogus interrupt flags"); 635 } 636 } 637 638 /* 639 * Parse an interrupt entry for an I/O interrupt routed to a pin on an I/O APIC. 640 */ 641 static void 642 mptable_parse_io_int(int_entry_ptr intr) 643 { 644 void *ioapic; 645 u_int pin, apic_id; 646 647 apic_id = intr->dst_apic_id; 648 if (intr->dst_apic_id == 0xff) { 649 /* 650 * An APIC ID of 0xff means that the interrupt is connected 651 * to the specified pin on all I/O APICs in the system. If 652 * there is only one I/O APIC, then use that APIC to route 653 * the interrupts. If there is more than one I/O APIC, then 654 * punt. 655 */ 656 if (mptable_nioapics == 1) { 657 apic_id = 0; 658 while (ioapics[apic_id] == NULL) 659 apic_id++; 660 } else { 661 printf( 662 "MPTable: Ignoring global interrupt entry for pin %d\n", 663 intr->dst_apic_int); 664 return; 665 } 666 } 667 if (apic_id > MAX_APIC_ID) { 668 printf("MPTable: Ignoring interrupt entry for ioapic%d\n", 669 intr->dst_apic_id); 670 return; 671 } 672 ioapic = ioapics[apic_id]; 673 if (ioapic == NULL) { 674 printf( 675 "MPTable: Ignoring interrupt entry for missing ioapic%d\n", 676 apic_id); 677 return; 678 } 679 pin = intr->dst_apic_int; 680 switch (intr->int_type) { 681 case INTENTRY_TYPE_INT: 682 switch (busses[intr->src_bus_id].bus_type) { 683 case NOBUS: 684 panic("interrupt from missing bus"); 685 case ISA: 686 case EISA: 687 if (busses[intr->src_bus_id].bus_type == ISA) 688 ioapic_set_bus(ioapic, pin, APIC_BUS_ISA); 689 else 690 ioapic_set_bus(ioapic, pin, APIC_BUS_EISA); 691 if (intr->src_bus_irq == pin) 692 break; 693 ioapic_remap_vector(ioapic, pin, intr->src_bus_irq); 694 if (ioapic_get_vector(ioapic, intr->src_bus_irq) == 695 intr->src_bus_irq) 696 ioapic_disable_pin(ioapic, intr->src_bus_irq); 697 break; 698 case PCI: 699 ioapic_set_bus(ioapic, pin, APIC_BUS_PCI); 700 break; 701 default: 702 ioapic_set_bus(ioapic, pin, APIC_BUS_UNKNOWN); 703 break; 704 } 705 break; 706 case INTENTRY_TYPE_NMI: 707 ioapic_set_nmi(ioapic, pin); 708 break; 709 case INTENTRY_TYPE_SMI: 710 ioapic_set_smi(ioapic, pin); 711 break; 712 case INTENTRY_TYPE_EXTINT: 713 ioapic_set_extint(ioapic, pin); 714 break; 715 default: 716 panic("%s: invalid interrupt entry type %d\n", __func__, 717 intr->int_type); 718 } 719 if (intr->int_type == INTENTRY_TYPE_INT || 720 (intr->int_flags & INTENTRY_FLAGS_TRIGGER) != 721 INTENTRY_FLAGS_TRIGGER_CONFORM) 722 ioapic_set_triggermode(ioapic, pin, intentry_trigger(intr)); 723 if (intr->int_type == INTENTRY_TYPE_INT || 724 (intr->int_flags & INTENTRY_FLAGS_POLARITY) != 725 INTENTRY_FLAGS_POLARITY_CONFORM) 726 ioapic_set_polarity(ioapic, pin, intentry_polarity(intr)); 727 } 728 729 /* 730 * Parse an interrupt entry for a local APIC LVT pin. 731 */ 732 static void 733 mptable_parse_local_int(int_entry_ptr intr) 734 { 735 u_int apic_id, pin; 736 737 if (intr->dst_apic_id == 0xff) 738 apic_id = APIC_ID_ALL; 739 else 740 apic_id = intr->dst_apic_id; 741 if (intr->dst_apic_int == 0) 742 pin = LVT_LINT0; 743 else 744 pin = LVT_LINT1; 745 switch (intr->int_type) { 746 case INTENTRY_TYPE_INT: 747 #if 1 748 printf( 749 "MPTable: Ignoring vectored local interrupt for LINTIN%d vector %d\n", 750 intr->dst_apic_int, intr->src_bus_irq); 751 return; 752 #else 753 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_FIXED); 754 break; 755 #endif 756 case INTENTRY_TYPE_NMI: 757 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_NMI); 758 break; 759 case INTENTRY_TYPE_SMI: 760 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_SMI); 761 break; 762 case INTENTRY_TYPE_EXTINT: 763 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_EXTINT); 764 break; 765 default: 766 panic("%s: invalid interrupt entry type %d\n", __func__, 767 intr->int_type); 768 } 769 if ((intr->int_flags & INTENTRY_FLAGS_TRIGGER) != 770 INTENTRY_FLAGS_TRIGGER_CONFORM) 771 lapic_set_lvt_triggermode(apic_id, pin, 772 intentry_trigger(intr)); 773 if ((intr->int_flags & INTENTRY_FLAGS_POLARITY) != 774 INTENTRY_FLAGS_POLARITY_CONFORM) 775 lapic_set_lvt_polarity(apic_id, pin, intentry_polarity(intr)); 776 } 777 778 /* 779 * Parse interrupt entries. 780 */ 781 static void 782 mptable_parse_ints_handler(u_char *entry, void *arg __unused) 783 { 784 int_entry_ptr intr; 785 786 intr = (int_entry_ptr)entry; 787 switch (*entry) { 788 case MPCT_ENTRY_INT: 789 mptable_parse_io_int(intr); 790 break; 791 case MPCT_ENTRY_LOCAL_INT: 792 mptable_parse_local_int(intr); 793 break; 794 } 795 } 796 797 /* 798 * Configure interrupt pins for a default configuration. For details see 799 * Table 5-2 in Section 5 of the MP Table specification. 800 */ 801 static void 802 mptable_parse_default_config_ints(void) 803 { 804 struct INTENTRY entry; 805 int pin; 806 807 /* 808 * All default configs route IRQs from bus 0 to the first 16 pins 809 * of the first I/O APIC with an APIC ID of 2. 810 */ 811 entry.type = MPCT_ENTRY_INT; 812 entry.int_flags = INTENTRY_FLAGS_POLARITY_CONFORM | 813 INTENTRY_FLAGS_TRIGGER_CONFORM; 814 entry.src_bus_id = 0; 815 entry.dst_apic_id = 2; 816 817 /* Run through all 16 pins. */ 818 for (pin = 0; pin < 16; pin++) { 819 entry.dst_apic_int = pin; 820 switch (pin) { 821 case 0: 822 /* Pin 0 is an ExtINT pin. */ 823 entry.int_type = INTENTRY_TYPE_EXTINT; 824 break; 825 case 2: 826 /* IRQ 0 is routed to pin 2. */ 827 entry.int_type = INTENTRY_TYPE_INT; 828 entry.src_bus_irq = 0; 829 break; 830 default: 831 /* All other pins are identity mapped. */ 832 entry.int_type = INTENTRY_TYPE_INT; 833 entry.src_bus_irq = pin; 834 break; 835 } 836 mptable_parse_io_int(&entry); 837 } 838 839 /* Certain configs disable certain pins. */ 840 if (mpfps->config_type == 7) 841 ioapic_disable_pin(ioapics[2], 0); 842 if (mpfps->config_type == 2) { 843 ioapic_disable_pin(ioapics[2], 2); 844 ioapic_disable_pin(ioapics[2], 13); 845 } 846 } 847 848 /* 849 * Configure the interrupt pins 850 */ 851 static void 852 mptable_parse_ints(void) 853 { 854 855 /* Is this a pre-defined config? */ 856 if (mpfps->config_type != 0) { 857 /* Configure LINT pins. */ 858 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT0, APIC_LVT_DM_EXTINT); 859 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT1, APIC_LVT_DM_NMI); 860 861 /* Configure I/O APIC pins. */ 862 mptable_parse_default_config_ints(); 863 } else 864 mptable_walk_table(mptable_parse_ints_handler, NULL); 865 } 866 867 #ifdef MPTABLE_FORCE_HTT 868 /* 869 * Perform a hyperthreading "fix-up" to enumerate any logical CPU's 870 * that aren't already listed in the table. 871 * 872 * XXX: We assume that all of the physical CPUs in the 873 * system have the same number of logical CPUs. 874 * 875 * XXX: We assume that APIC ID's are allocated such that 876 * the APIC ID's for a physical processor are aligned 877 * with the number of logical CPU's in the processor. 878 */ 879 static void 880 mptable_hyperthread_fixup(u_int id_mask) 881 { 882 u_int i, id, logical_cpus; 883 884 /* Nothing to do if there is no HTT support. */ 885 if ((cpu_feature & CPUID_HTT) == 0) 886 return; 887 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16; 888 if (logical_cpus <= 1) 889 return; 890 891 /* 892 * For each APIC ID of a CPU that is set in the mask, 893 * scan the other candidate APIC ID's for this 894 * physical processor. If any of those ID's are 895 * already in the table, then kill the fixup. 896 */ 897 for (id = 0; id <= MAX_LAPIC_ID; id++) { 898 if ((id_mask & 1 << id) == 0) 899 continue; 900 /* First, make sure we are on a logical_cpus boundary. */ 901 if (id % logical_cpus != 0) 902 return; 903 for (i = id + 1; i < id + logical_cpus; i++) 904 if ((id_mask & 1 << i) != 0) 905 return; 906 } 907 908 /* 909 * Ok, the ID's checked out, so perform the fixup by 910 * adding the logical CPUs. 911 */ 912 while ((id = ffs(id_mask)) != 0) { 913 id--; 914 for (i = id + 1; i < id + logical_cpus; i++) { 915 if (bootverbose) 916 printf( 917 "MPTable: Adding logical CPU %d from main CPU %d\n", 918 i, id); 919 lapic_create(i, 0); 920 } 921 id_mask &= ~(1 << id); 922 } 923 } 924 #endif /* MPTABLE_FORCE_HTT */ 925 926 /* 927 * Support code for routing PCI interrupts using the MP Table. 928 */ 929 static void 930 mptable_pci_setup(void) 931 { 932 int i; 933 934 /* 935 * Find the first pci bus and call it 0. Panic if pci0 is not 936 * bus zero and there are multiple PCI busses. 937 */ 938 for (i = 0; i <= mptable_maxbusid; i++) 939 if (busses[i].bus_type == PCI) { 940 if (pci0 == -1) 941 pci0 = i; 942 else if (pci0 != 0) 943 panic( 944 "MPTable contains multiple PCI busses but no PCI bus 0"); 945 } 946 } 947 948 static void 949 mptable_pci_probe_table_handler(u_char *entry, void *arg) 950 { 951 struct pci_probe_table_args *args; 952 int_entry_ptr intr; 953 954 if (*entry != MPCT_ENTRY_INT) 955 return; 956 intr = (int_entry_ptr)entry; 957 args = (struct pci_probe_table_args *)arg; 958 KASSERT(args->bus <= mptable_maxbusid, 959 ("bus %d is too big", args->bus)); 960 KASSERT(busses[args->bus].bus_type == PCI, ("probing for non-PCI bus")); 961 if (intr->src_bus_id == args->bus) 962 args->found = 1; 963 } 964 965 int 966 mptable_pci_probe_table(int bus) 967 { 968 struct pci_probe_table_args args; 969 970 if (bus < 0) 971 return (EINVAL); 972 if (mpct == NULL || pci0 == -1 || pci0 + bus > mptable_maxbusid) 973 return (ENXIO); 974 if (busses[pci0 + bus].bus_type != PCI) 975 return (ENXIO); 976 args.bus = pci0 + bus; 977 args.found = 0; 978 mptable_walk_table(mptable_pci_probe_table_handler, &args); 979 if (args.found == 0) 980 return (ENXIO); 981 return (0); 982 } 983 984 static void 985 mptable_pci_route_interrupt_handler(u_char *entry, void *arg) 986 { 987 struct pci_route_interrupt_args *args; 988 int_entry_ptr intr; 989 int vector; 990 991 if (*entry != MPCT_ENTRY_INT) 992 return; 993 intr = (int_entry_ptr)entry; 994 args = (struct pci_route_interrupt_args *)arg; 995 if (intr->src_bus_id != args->bus || intr->src_bus_irq != args->irq) 996 return; 997 998 /* Make sure the APIC maps to a known APIC. */ 999 KASSERT(ioapics[intr->dst_apic_id] != NULL, 1000 ("No I/O APIC %d to route interrupt to", intr->dst_apic_id)); 1001 1002 /* 1003 * Look up the vector for this APIC / pin combination. If we 1004 * have previously matched an entry for this PCI IRQ but it 1005 * has the same vector as this entry, just return. Otherwise, 1006 * we use the vector for this APIC / pin combination. 1007 */ 1008 vector = ioapic_get_vector(ioapics[intr->dst_apic_id], 1009 intr->dst_apic_int); 1010 if (args->vector == vector) 1011 return; 1012 KASSERT(args->vector == -1, 1013 ("Multiple IRQs for PCI interrupt %d.%d.INT%c: %d and %d\n", 1014 args->bus, args->irq >> 2, 'A' + (args->irq & 0x3), args->vector, 1015 vector)); 1016 args->vector = vector; 1017 } 1018 1019 int 1020 mptable_pci_route_interrupt(device_t pcib, device_t dev, int pin) 1021 { 1022 struct pci_route_interrupt_args args; 1023 int slot; 1024 1025 /* Like ACPI, pin numbers are 0-3, not 1-4. */ 1026 pin--; 1027 KASSERT(pci0 != -1, ("do not know how to route PCI interrupts")); 1028 args.bus = pci_get_bus(dev) + pci0; 1029 slot = pci_get_slot(dev); 1030 1031 /* 1032 * PCI interrupt entries in the MP Table encode both the slot and 1033 * pin into the IRQ with the pin being the two least significant 1034 * bits, the slot being the next five bits, and the most significant 1035 * bit being reserved. 1036 */ 1037 args.irq = slot << 2 | pin; 1038 args.vector = -1; 1039 mptable_walk_table(mptable_pci_route_interrupt_handler, &args); 1040 if (args.vector < 0) { 1041 device_printf(pcib, "unable to route slot %d INT%c\n", slot, 1042 'A' + pin); 1043 return (PCI_INVALID_IRQ); 1044 } 1045 if (bootverbose) 1046 device_printf(pcib, "slot %d INT%c routed to irq %d\n", slot, 1047 'A' + pin, args.vector); 1048 return (args.vector); 1049 }
Cache object: abce862417b29458e9c94814f0c0e452
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