1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * Copyright (c) 1996, by Steve Passe
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. The name of the developer may NOT be used to endorse or promote products
12 * derived from this software without specific prior written permission.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29
30 #include "opt_mptable_force_htt.h"
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/bus.h>
34 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36
37 #include <vm/vm.h>
38 #include <vm/vm_param.h>
39 #include <vm/pmap.h>
40
41 #include <machine/apicreg.h>
42 #include <machine/frame.h>
43 #include <machine/intr_machdep.h>
44 #include <machine/apicvar.h>
45 #include <machine/md_var.h>
46 #include <machine/mptable.h>
47 #include <machine/specialreg.h>
48
49 #include <dev/pci/pcivar.h>
50
51 /* string defined by the Intel MP Spec as identifying the MP table */
52 #define MP_SIG 0x5f504d5f /* _MP_ */
53
54 #define MAX_LAPIC_ID 31 /* Max local APIC ID for HTT fixup */
55
56 #ifdef PC98
57 #define BIOS_BASE (0xe8000)
58 #define BIOS_SIZE (0x18000)
59 #else
60 #define BIOS_BASE (0xf0000)
61 #define BIOS_SIZE (0x10000)
62 #endif
63 #define BIOS_COUNT (BIOS_SIZE/4)
64
65 typedef void mptable_entry_handler(u_char *entry, void *arg);
66
67 static basetable_entry basetable_entry_types[] =
68 {
69 {0, 20, "Processor"},
70 {1, 8, "Bus"},
71 {2, 8, "I/O APIC"},
72 {3, 8, "I/O INT"},
73 {4, 8, "Local INT"}
74 };
75
76 typedef struct BUSDATA {
77 u_char bus_id;
78 enum busTypes bus_type;
79 } bus_datum;
80
81 typedef struct INTDATA {
82 u_char int_type;
83 u_short int_flags;
84 u_char src_bus_id;
85 u_char src_bus_irq;
86 u_char dst_apic_id;
87 u_char dst_apic_int;
88 u_char int_vector;
89 } io_int, local_int;
90
91 typedef struct BUSTYPENAME {
92 u_char type;
93 char name[7];
94 } bus_type_name;
95
96 /* From MP spec v1.4, table 4-8. */
97 static bus_type_name bus_type_table[] =
98 {
99 {UNKNOWN_BUSTYPE, "CBUS "},
100 {UNKNOWN_BUSTYPE, "CBUSII"},
101 {EISA, "EISA "},
102 {UNKNOWN_BUSTYPE, "FUTURE"},
103 {UNKNOWN_BUSTYPE, "INTERN"},
104 {ISA, "ISA "},
105 {UNKNOWN_BUSTYPE, "MBI "},
106 {UNKNOWN_BUSTYPE, "MBII "},
107 {MCA, "MCA "},
108 {UNKNOWN_BUSTYPE, "MPI "},
109 {UNKNOWN_BUSTYPE, "MPSA "},
110 {UNKNOWN_BUSTYPE, "NUBUS "},
111 {PCI, "PCI "},
112 {UNKNOWN_BUSTYPE, "PCMCIA"},
113 {UNKNOWN_BUSTYPE, "TC "},
114 {UNKNOWN_BUSTYPE, "VL "},
115 {UNKNOWN_BUSTYPE, "VME "},
116 {UNKNOWN_BUSTYPE, "XPRESS"}
117 };
118
119 /* From MP spec v1.4, table 5-1. */
120 static int default_data[7][5] =
121 {
122 /* nbus, id0, type0, id1, type1 */
123 {1, 0, ISA, 255, NOBUS},
124 {1, 0, EISA, 255, NOBUS},
125 {1, 0, EISA, 255, NOBUS},
126 {1, 0, MCA, 255, NOBUS},
127 {2, 0, ISA, 1, PCI},
128 {2, 0, EISA, 1, PCI},
129 {2, 0, MCA, 1, PCI}
130 };
131
132 struct pci_probe_table_args {
133 u_char bus;
134 u_char found;
135 };
136
137 struct pci_route_interrupt_args {
138 u_char bus; /* Source bus. */
139 u_char irq; /* Source slot:pin. */
140 int vector; /* Return value. */
141 };
142
143 static mpfps_t mpfps;
144 static mpcth_t mpct;
145 static void *ioapics[MAX_APIC_ID + 1];
146 static bus_datum *busses;
147 static int mptable_nioapics, mptable_nbusses, mptable_maxbusid;
148 static int pci0 = -1;
149
150 static MALLOC_DEFINE(M_MPTABLE, "mptable", "MP Table Items");
151
152 static enum intr_polarity conforming_polarity(u_char src_bus,
153 u_char src_bus_irq);
154 static enum intr_trigger conforming_trigger(u_char src_bus, u_char src_bus_irq);
155 static enum intr_polarity intentry_polarity(int_entry_ptr intr);
156 static enum intr_trigger intentry_trigger(int_entry_ptr intr);
157 static int lookup_bus_type(char *name);
158 static void mptable_count_items(void);
159 static void mptable_count_items_handler(u_char *entry, void *arg);
160 #ifdef MPTABLE_FORCE_HTT
161 static void mptable_hyperthread_fixup(u_int id_mask);
162 #endif
163 static void mptable_parse_apics_and_busses(void);
164 static void mptable_parse_apics_and_busses_handler(u_char *entry,
165 void *arg);
166 static void mptable_parse_default_config_ints(void);
167 static void mptable_parse_ints(void);
168 static void mptable_parse_ints_handler(u_char *entry, void *arg);
169 static void mptable_parse_io_int(int_entry_ptr intr);
170 static void mptable_parse_local_int(int_entry_ptr intr);
171 static void mptable_pci_probe_table_handler(u_char *entry, void *arg);
172 static void mptable_pci_route_interrupt_handler(u_char *entry, void *arg);
173 static void mptable_pci_setup(void);
174 static int mptable_probe(void);
175 static int mptable_probe_cpus(void);
176 static void mptable_probe_cpus_handler(u_char *entry, void *arg __unused);
177 static void mptable_register(void *dummy);
178 static int mptable_setup_local(void);
179 static int mptable_setup_io(void);
180 static void mptable_walk_table(mptable_entry_handler *handler, void *arg);
181 static int search_for_sig(u_int32_t target, int count);
182
183 static struct apic_enumerator mptable_enumerator = {
184 "MPTable",
185 mptable_probe,
186 mptable_probe_cpus,
187 mptable_setup_local,
188 mptable_setup_io
189 };
190
191 /*
192 * look for the MP spec signature
193 */
194
195 static int
196 search_for_sig(u_int32_t target, int count)
197 {
198 int x;
199 u_int32_t *addr = (u_int32_t *) (KERNBASE + target);
200
201 for (x = 0; x < count; x += 4)
202 if (addr[x] == MP_SIG)
203 /* make array index a byte index */
204 return (target + (x * sizeof(u_int32_t)));
205 return (-1);
206 }
207
208 static int
209 lookup_bus_type(char *name)
210 {
211 int x;
212
213 for (x = 0; x < MAX_BUSTYPE; ++x)
214 if (strncmp(bus_type_table[x].name, name, 6) == 0)
215 return (bus_type_table[x].type);
216
217 return (UNKNOWN_BUSTYPE);
218 }
219
220 /*
221 * Look for an Intel MP spec table (ie, SMP capable hardware).
222 */
223 static int
224 mptable_probe(void)
225 {
226 int x;
227 u_long segment;
228 u_int32_t target;
229
230 /* see if EBDA exists */
231 if ((segment = (u_long) * (u_short *) (KERNBASE + 0x40e)) != 0) {
232 /* search first 1K of EBDA */
233 target = (u_int32_t) (segment << 4);
234 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
235 goto found;
236 } else {
237 /* last 1K of base memory, effective 'top of base' passed in */
238 target = (u_int32_t) ((basemem * 1024) - 0x400);
239 if ((x = search_for_sig(target, 1024 / 4)) >= 0)
240 goto found;
241 }
242
243 /* search the BIOS */
244 target = (u_int32_t) BIOS_BASE;
245 if ((x = search_for_sig(target, BIOS_COUNT)) >= 0)
246 goto found;
247
248 /* nothing found */
249 return (ENXIO);
250
251 found:
252 mpfps = (mpfps_t)(KERNBASE + x);
253
254 /* Map in the configuration table if it exists. */
255 if (mpfps->config_type != 0) {
256 if (bootverbose)
257 printf(
258 "MP Table version 1.%d found using Default Configuration %d\n",
259 mpfps->spec_rev, mpfps->config_type);
260 if (mpfps->config_type != 5 && mpfps->config_type != 6) {
261 printf(
262 "MP Table Default Configuration %d is unsupported\n",
263 mpfps->config_type);
264 return (ENXIO);
265 }
266 mpct = NULL;
267 } else {
268 if ((uintptr_t)mpfps->pap >= 1024 * 1024) {
269 printf("%s: Unable to map MP Configuration Table\n",
270 __func__);
271 return (ENXIO);
272 }
273 mpct = (mpcth_t)(KERNBASE + (uintptr_t)mpfps->pap);
274 if (mpct->base_table_length + (uintptr_t)mpfps->pap >=
275 1024 * 1024) {
276 printf("%s: Unable to map end of MP Config Table\n",
277 __func__);
278 return (ENXIO);
279 }
280 if (mpct->signature[0] != 'P' || mpct->signature[1] != 'C' ||
281 mpct->signature[2] != 'M' || mpct->signature[3] != 'P') {
282 printf("%s: MP Config Table has bad signature: %c%c%c%c\n",
283 __func__, mpct->signature[0], mpct->signature[1],
284 mpct->signature[2], mpct->signature[3]);
285 return (ENXIO);
286 }
287 if (bootverbose)
288 printf(
289 "MP Configuration Table version 1.%d found at %p\n",
290 mpct->spec_rev, mpct);
291 }
292
293 return (-100);
294 }
295
296 /*
297 * Run through the MP table enumerating CPUs.
298 */
299 static int
300 mptable_probe_cpus(void)
301 {
302 u_int cpu_mask;
303
304 /* Is this a pre-defined config? */
305 if (mpfps->config_type != 0) {
306 lapic_create(0, 1);
307 lapic_create(1, 0);
308 } else {
309 cpu_mask = 0;
310 mptable_walk_table(mptable_probe_cpus_handler, &cpu_mask);
311 #ifdef MPTABLE_FORCE_HTT
312 mptable_hyperthread_fixup(cpu_mask);
313 #endif
314 }
315 return (0);
316 }
317
318 /*
319 * Initialize the local APIC on the BSP.
320 */
321 static int
322 mptable_setup_local(void)
323 {
324 vm_paddr_t addr;
325
326 /* Is this a pre-defined config? */
327 printf("MPTable: <");
328 if (mpfps->config_type != 0) {
329 addr = DEFAULT_APIC_BASE;
330 printf("Default Configuration %d", mpfps->config_type);
331 } else {
332 addr = mpct->apic_address;
333 printf("%.*s %.*s", (int)sizeof(mpct->oem_id), mpct->oem_id,
334 (int)sizeof(mpct->product_id), mpct->product_id);
335 }
336 printf(">\n");
337 lapic_init(addr);
338 return (0);
339 }
340
341 /*
342 * Run through the MP table enumerating I/O APICs.
343 */
344 static int
345 mptable_setup_io(void)
346 {
347 int i;
348 u_char byte;
349
350 /* First, we count individual items and allocate arrays. */
351 mptable_count_items();
352 busses = malloc((mptable_maxbusid + 1) * sizeof(bus_datum), M_MPTABLE,
353 M_WAITOK);
354 for (i = 0; i <= mptable_maxbusid; i++)
355 busses[i].bus_type = NOBUS;
356
357 /* Second, we run through adding I/O APIC's and busses. */
358 mptable_parse_apics_and_busses();
359
360 /* Third, we run through the table tweaking interrupt sources. */
361 mptable_parse_ints();
362
363 /* Fourth, we register all the I/O APIC's. */
364 for (i = 0; i <= MAX_APIC_ID; i++)
365 if (ioapics[i] != NULL)
366 ioapic_register(ioapics[i]);
367
368 /* Fifth, we setup data structures to handle PCI interrupt routing. */
369 mptable_pci_setup();
370
371 /* Finally, we throw the switch to enable the I/O APIC's. */
372 if (mpfps->mpfb2 & MPFB2_IMCR_PRESENT) {
373 outb(0x22, 0x70); /* select IMCR */
374 byte = inb(0x23); /* current contents */
375 byte |= 0x01; /* mask external INTR */
376 outb(0x23, byte); /* disconnect 8259s/NMI */
377 }
378
379 return (0);
380 }
381
382 static void
383 mptable_register(void *dummy __unused)
384 {
385
386 apic_register_enumerator(&mptable_enumerator);
387 }
388 SYSINIT(mptable_register, SI_SUB_CPU - 1, SI_ORDER_FIRST, mptable_register,
389 NULL);
390
391 /*
392 * Call the handler routine for each entry in the MP config table.
393 */
394 static void
395 mptable_walk_table(mptable_entry_handler *handler, void *arg)
396 {
397 u_int i;
398 u_char *entry;
399
400 entry = (u_char *)(mpct + 1);
401 for (i = 0; i < mpct->entry_count; i++) {
402 switch (*entry) {
403 case MPCT_ENTRY_PROCESSOR:
404 case MPCT_ENTRY_IOAPIC:
405 case MPCT_ENTRY_BUS:
406 case MPCT_ENTRY_INT:
407 case MPCT_ENTRY_LOCAL_INT:
408 break;
409 default:
410 panic("%s: Unknown MP Config Entry %d\n", __func__,
411 (int)*entry);
412 }
413 handler(entry, arg);
414 entry += basetable_entry_types[*entry].length;
415 }
416 }
417
418 static void
419 mptable_probe_cpus_handler(u_char *entry, void *arg)
420 {
421 proc_entry_ptr proc;
422 u_int *cpu_mask;
423
424 switch (*entry) {
425 case MPCT_ENTRY_PROCESSOR:
426 proc = (proc_entry_ptr)entry;
427 if (proc->cpu_flags & PROCENTRY_FLAG_EN) {
428 lapic_create(proc->apic_id, proc->cpu_flags &
429 PROCENTRY_FLAG_BP);
430 if (proc->apic_id < MAX_LAPIC_ID) {
431 cpu_mask = (u_int *)arg;
432 *cpu_mask |= (1ul << proc->apic_id);
433 }
434 }
435 break;
436 }
437 }
438
439 static void
440 mptable_count_items_handler(u_char *entry, void *arg __unused)
441 {
442 io_apic_entry_ptr apic;
443 bus_entry_ptr bus;
444
445 switch (*entry) {
446 case MPCT_ENTRY_BUS:
447 bus = (bus_entry_ptr)entry;
448 mptable_nbusses++;
449 if (bus->bus_id > mptable_maxbusid)
450 mptable_maxbusid = bus->bus_id;
451 break;
452 case MPCT_ENTRY_IOAPIC:
453 apic = (io_apic_entry_ptr)entry;
454 if (apic->apic_flags & IOAPICENTRY_FLAG_EN)
455 mptable_nioapics++;
456 break;
457 }
458 }
459
460 /*
461 * Count items in the table.
462 */
463 static void
464 mptable_count_items(void)
465 {
466
467 /* Is this a pre-defined config? */
468 if (mpfps->config_type != 0) {
469 mptable_nioapics = 1;
470 switch (mpfps->config_type) {
471 case 1:
472 case 2:
473 case 3:
474 case 4:
475 mptable_nbusses = 1;
476 break;
477 case 5:
478 case 6:
479 case 7:
480 mptable_nbusses = 2;
481 break;
482 default:
483 panic("Unknown pre-defined MP Table config type %d",
484 mpfps->config_type);
485 }
486 mptable_maxbusid = mptable_nbusses - 1;
487 } else
488 mptable_walk_table(mptable_count_items_handler, NULL);
489 }
490
491 /*
492 * Add a bus or I/O APIC from an entry in the table.
493 */
494 static void
495 mptable_parse_apics_and_busses_handler(u_char *entry, void *arg __unused)
496 {
497 io_apic_entry_ptr apic;
498 bus_entry_ptr bus;
499 enum busTypes bus_type;
500 int i;
501
502
503 switch (*entry) {
504 case MPCT_ENTRY_BUS:
505 bus = (bus_entry_ptr)entry;
506 bus_type = lookup_bus_type(bus->bus_type);
507 if (bus_type == UNKNOWN_BUSTYPE) {
508 printf("MPTable: Unknown bus %d type \"", bus->bus_id);
509 for (i = 0; i < 6; i++)
510 printf("%c", bus->bus_type[i]);
511 printf("\"\n");
512 }
513 busses[bus->bus_id].bus_id = bus->bus_id;
514 busses[bus->bus_id].bus_type = bus_type;
515 break;
516 case MPCT_ENTRY_IOAPIC:
517 apic = (io_apic_entry_ptr)entry;
518 if (!(apic->apic_flags & IOAPICENTRY_FLAG_EN))
519 break;
520 if (apic->apic_id > MAX_APIC_ID)
521 panic("%s: I/O APIC ID %d too high", __func__,
522 apic->apic_id);
523 if (ioapics[apic->apic_id] != NULL)
524 panic("%s: Double APIC ID %d", __func__,
525 apic->apic_id);
526 ioapics[apic->apic_id] = ioapic_create(apic->apic_address,
527 apic->apic_id, -1);
528 break;
529 default:
530 break;
531 }
532 }
533
534 /*
535 * Enumerate I/O APIC's and busses.
536 */
537 static void
538 mptable_parse_apics_and_busses(void)
539 {
540
541 /* Is this a pre-defined config? */
542 if (mpfps->config_type != 0) {
543 ioapics[2] = ioapic_create(DEFAULT_IO_APIC_BASE, 2, 0);
544 busses[0].bus_id = 0;
545 busses[0].bus_type = default_data[mpfps->config_type - 1][2];
546 if (mptable_nbusses > 1) {
547 busses[1].bus_id = 1;
548 busses[1].bus_type =
549 default_data[mpfps->config_type - 1][4];
550 }
551 } else
552 mptable_walk_table(mptable_parse_apics_and_busses_handler,
553 NULL);
554 }
555
556 /*
557 * Determine conforming polarity for a given bus type.
558 */
559 static enum intr_polarity
560 conforming_polarity(u_char src_bus, u_char src_bus_irq)
561 {
562
563 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus));
564 switch (busses[src_bus].bus_type) {
565 case ISA:
566 case EISA:
567 return (INTR_POLARITY_HIGH);
568 case PCI:
569 return (INTR_POLARITY_LOW);
570 default:
571 panic("%s: unknown bus type %d", __func__,
572 busses[src_bus].bus_type);
573 }
574 }
575
576 /*
577 * Determine conforming trigger for a given bus type.
578 */
579 static enum intr_trigger
580 conforming_trigger(u_char src_bus, u_char src_bus_irq)
581 {
582
583 KASSERT(src_bus <= mptable_maxbusid, ("bus id %d too large", src_bus));
584 switch (busses[src_bus].bus_type) {
585 case ISA:
586 #ifndef PC98
587 if (elcr_found)
588 return (elcr_read_trigger(src_bus_irq));
589 else
590 #endif
591 return (INTR_TRIGGER_EDGE);
592 case PCI:
593 return (INTR_TRIGGER_LEVEL);
594 #ifndef PC98
595 case EISA:
596 KASSERT(src_bus_irq < 16, ("Invalid EISA IRQ %d", src_bus_irq));
597 KASSERT(elcr_found, ("Missing ELCR"));
598 return (elcr_read_trigger(src_bus_irq));
599 #endif
600 default:
601 panic("%s: unknown bus type %d", __func__,
602 busses[src_bus].bus_type);
603 }
604 }
605
606 static enum intr_polarity
607 intentry_polarity(int_entry_ptr intr)
608 {
609
610 switch (intr->int_flags & INTENTRY_FLAGS_POLARITY) {
611 case INTENTRY_FLAGS_POLARITY_CONFORM:
612 return (conforming_polarity(intr->src_bus_id,
613 intr->src_bus_irq));
614 case INTENTRY_FLAGS_POLARITY_ACTIVEHI:
615 return (INTR_POLARITY_HIGH);
616 case INTENTRY_FLAGS_POLARITY_ACTIVELO:
617 return (INTR_POLARITY_LOW);
618 default:
619 panic("Bogus interrupt flags");
620 }
621 }
622
623 static enum intr_trigger
624 intentry_trigger(int_entry_ptr intr)
625 {
626
627 switch (intr->int_flags & INTENTRY_FLAGS_TRIGGER) {
628 case INTENTRY_FLAGS_TRIGGER_CONFORM:
629 return (conforming_trigger(intr->src_bus_id,
630 intr->src_bus_irq));
631 case INTENTRY_FLAGS_TRIGGER_EDGE:
632 return (INTR_TRIGGER_EDGE);
633 case INTENTRY_FLAGS_TRIGGER_LEVEL:
634 return (INTR_TRIGGER_LEVEL);
635 default:
636 panic("Bogus interrupt flags");
637 }
638 }
639
640 /*
641 * Parse an interrupt entry for an I/O interrupt routed to a pin on an I/O APIC.
642 */
643 static void
644 mptable_parse_io_int(int_entry_ptr intr)
645 {
646 void *ioapic;
647 u_int pin, apic_id;
648
649 apic_id = intr->dst_apic_id;
650 if (intr->dst_apic_id == 0xff) {
651 /*
652 * An APIC ID of 0xff means that the interrupt is connected
653 * to the specified pin on all I/O APICs in the system. If
654 * there is only one I/O APIC, then use that APIC to route
655 * the interrupts. If there is more than one I/O APIC, then
656 * punt.
657 */
658 if (mptable_nioapics == 1) {
659 apic_id = 0;
660 while (ioapics[apic_id] == NULL)
661 apic_id++;
662 } else {
663 printf(
664 "MPTable: Ignoring global interrupt entry for pin %d\n",
665 intr->dst_apic_int);
666 return;
667 }
668 }
669 if (apic_id > MAX_APIC_ID) {
670 printf("MPTable: Ignoring interrupt entry for ioapic%d\n",
671 intr->dst_apic_id);
672 return;
673 }
674 ioapic = ioapics[apic_id];
675 if (ioapic == NULL) {
676 printf(
677 "MPTable: Ignoring interrupt entry for missing ioapic%d\n",
678 apic_id);
679 return;
680 }
681 pin = intr->dst_apic_int;
682 switch (intr->int_type) {
683 case INTENTRY_TYPE_INT:
684 switch (busses[intr->src_bus_id].bus_type) {
685 case NOBUS:
686 panic("interrupt from missing bus");
687 case ISA:
688 case EISA:
689 if (busses[intr->src_bus_id].bus_type == ISA)
690 ioapic_set_bus(ioapic, pin, APIC_BUS_ISA);
691 else
692 ioapic_set_bus(ioapic, pin, APIC_BUS_EISA);
693 if (intr->src_bus_irq == pin)
694 break;
695 ioapic_remap_vector(ioapic, pin, intr->src_bus_irq);
696 if (ioapic_get_vector(ioapic, intr->src_bus_irq) ==
697 intr->src_bus_irq)
698 ioapic_disable_pin(ioapic, intr->src_bus_irq);
699 break;
700 case PCI:
701 ioapic_set_bus(ioapic, pin, APIC_BUS_PCI);
702 break;
703 default:
704 ioapic_set_bus(ioapic, pin, APIC_BUS_UNKNOWN);
705 break;
706 }
707 break;
708 case INTENTRY_TYPE_NMI:
709 ioapic_set_nmi(ioapic, pin);
710 break;
711 case INTENTRY_TYPE_SMI:
712 ioapic_set_smi(ioapic, pin);
713 break;
714 case INTENTRY_TYPE_EXTINT:
715 ioapic_set_extint(ioapic, pin);
716 break;
717 default:
718 panic("%s: invalid interrupt entry type %d\n", __func__,
719 intr->int_type);
720 }
721 if (intr->int_type == INTENTRY_TYPE_INT ||
722 (intr->int_flags & INTENTRY_FLAGS_TRIGGER) !=
723 INTENTRY_FLAGS_TRIGGER_CONFORM)
724 ioapic_set_triggermode(ioapic, pin, intentry_trigger(intr));
725 if (intr->int_type == INTENTRY_TYPE_INT ||
726 (intr->int_flags & INTENTRY_FLAGS_POLARITY) !=
727 INTENTRY_FLAGS_POLARITY_CONFORM)
728 ioapic_set_polarity(ioapic, pin, intentry_polarity(intr));
729 }
730
731 /*
732 * Parse an interrupt entry for a local APIC LVT pin.
733 */
734 static void
735 mptable_parse_local_int(int_entry_ptr intr)
736 {
737 u_int apic_id, pin;
738
739 if (intr->dst_apic_id == 0xff)
740 apic_id = APIC_ID_ALL;
741 else
742 apic_id = intr->dst_apic_id;
743 if (intr->dst_apic_int == 0)
744 pin = LVT_LINT0;
745 else
746 pin = LVT_LINT1;
747 switch (intr->int_type) {
748 case INTENTRY_TYPE_INT:
749 #if 1
750 printf(
751 "MPTable: Ignoring vectored local interrupt for LINTIN%d vector %d\n",
752 intr->dst_apic_int, intr->src_bus_irq);
753 return;
754 #else
755 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_FIXED);
756 break;
757 #endif
758 case INTENTRY_TYPE_NMI:
759 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_NMI);
760 break;
761 case INTENTRY_TYPE_SMI:
762 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_SMI);
763 break;
764 case INTENTRY_TYPE_EXTINT:
765 lapic_set_lvt_mode(apic_id, pin, APIC_LVT_DM_EXTINT);
766 break;
767 default:
768 panic("%s: invalid interrupt entry type %d\n", __func__,
769 intr->int_type);
770 }
771 if ((intr->int_flags & INTENTRY_FLAGS_TRIGGER) !=
772 INTENTRY_FLAGS_TRIGGER_CONFORM)
773 lapic_set_lvt_triggermode(apic_id, pin,
774 intentry_trigger(intr));
775 if ((intr->int_flags & INTENTRY_FLAGS_POLARITY) !=
776 INTENTRY_FLAGS_POLARITY_CONFORM)
777 lapic_set_lvt_polarity(apic_id, pin, intentry_polarity(intr));
778 }
779
780 /*
781 * Parse interrupt entries.
782 */
783 static void
784 mptable_parse_ints_handler(u_char *entry, void *arg __unused)
785 {
786 int_entry_ptr intr;
787
788 intr = (int_entry_ptr)entry;
789 switch (*entry) {
790 case MPCT_ENTRY_INT:
791 mptable_parse_io_int(intr);
792 break;
793 case MPCT_ENTRY_LOCAL_INT:
794 mptable_parse_local_int(intr);
795 break;
796 }
797 }
798
799 /*
800 * Configure interrupt pins for a default configuration. For details see
801 * Table 5-2 in Section 5 of the MP Table specification.
802 */
803 static void
804 mptable_parse_default_config_ints(void)
805 {
806 struct INTENTRY entry;
807 int pin;
808
809 /*
810 * All default configs route IRQs from bus 0 to the first 16 pins
811 * of the first I/O APIC with an APIC ID of 2.
812 */
813 entry.type = MPCT_ENTRY_INT;
814 entry.int_flags = INTENTRY_FLAGS_POLARITY_CONFORM |
815 INTENTRY_FLAGS_TRIGGER_CONFORM;
816 entry.src_bus_id = 0;
817 entry.dst_apic_id = 2;
818
819 /* Run through all 16 pins. */
820 for (pin = 0; pin < 16; pin++) {
821 entry.dst_apic_int = pin;
822 switch (pin) {
823 case 0:
824 /* Pin 0 is an ExtINT pin. */
825 entry.int_type = INTENTRY_TYPE_EXTINT;
826 break;
827 case 2:
828 /* IRQ 0 is routed to pin 2. */
829 entry.int_type = INTENTRY_TYPE_INT;
830 entry.src_bus_irq = 0;
831 break;
832 default:
833 /* All other pins are identity mapped. */
834 entry.int_type = INTENTRY_TYPE_INT;
835 entry.src_bus_irq = pin;
836 break;
837 }
838 mptable_parse_io_int(&entry);
839 }
840
841 /* Certain configs disable certain pins. */
842 if (mpfps->config_type == 7)
843 ioapic_disable_pin(ioapics[2], 0);
844 if (mpfps->config_type == 2) {
845 ioapic_disable_pin(ioapics[2], 2);
846 ioapic_disable_pin(ioapics[2], 13);
847 }
848 }
849
850 /*
851 * Configure the interrupt pins
852 */
853 static void
854 mptable_parse_ints(void)
855 {
856
857 /* Is this a pre-defined config? */
858 if (mpfps->config_type != 0) {
859 /* Configure LINT pins. */
860 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT0, APIC_LVT_DM_EXTINT);
861 lapic_set_lvt_mode(APIC_ID_ALL, LVT_LINT1, APIC_LVT_DM_NMI);
862
863 /* Configure I/O APIC pins. */
864 mptable_parse_default_config_ints();
865 } else
866 mptable_walk_table(mptable_parse_ints_handler, NULL);
867 }
868
869 #ifdef MPTABLE_FORCE_HTT
870 /*
871 * Perform a hyperthreading "fix-up" to enumerate any logical CPU's
872 * that aren't already listed in the table.
873 *
874 * XXX: We assume that all of the physical CPUs in the
875 * system have the same number of logical CPUs.
876 *
877 * XXX: We assume that APIC ID's are allocated such that
878 * the APIC ID's for a physical processor are aligned
879 * with the number of logical CPU's in the processor.
880 */
881 static void
882 mptable_hyperthread_fixup(u_int id_mask)
883 {
884 u_int i, id, logical_cpus;
885
886 /* Nothing to do if there is no HTT support. */
887 if ((cpu_feature & CPUID_HTT) == 0)
888 return;
889 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
890 if (logical_cpus <= 1)
891 return;
892
893 /*
894 * For each APIC ID of a CPU that is set in the mask,
895 * scan the other candidate APIC ID's for this
896 * physical processor. If any of those ID's are
897 * already in the table, then kill the fixup.
898 */
899 for (id = 0; id <= MAX_LAPIC_ID; id++) {
900 if ((id_mask & 1 << id) == 0)
901 continue;
902 /* First, make sure we are on a logical_cpus boundary. */
903 if (id % logical_cpus != 0)
904 return;
905 for (i = id + 1; i < id + logical_cpus; i++)
906 if ((id_mask & 1 << i) != 0)
907 return;
908 }
909
910 /*
911 * Ok, the ID's checked out, so perform the fixup by
912 * adding the logical CPUs.
913 */
914 while ((id = ffs(id_mask)) != 0) {
915 id--;
916 for (i = id + 1; i < id + logical_cpus; i++) {
917 if (bootverbose)
918 printf(
919 "MPTable: Adding logical CPU %d from main CPU %d\n",
920 i, id);
921 lapic_create(i, 0);
922 }
923 id_mask &= ~(1 << id);
924 }
925 }
926 #endif /* MPTABLE_FORCE_HTT */
927
928 /*
929 * Support code for routing PCI interrupts using the MP Table.
930 */
931 static void
932 mptable_pci_setup(void)
933 {
934 int i;
935
936 /*
937 * Find the first pci bus and call it 0. Panic if pci0 is not
938 * bus zero and there are multiple PCI busses.
939 */
940 for (i = 0; i <= mptable_maxbusid; i++)
941 if (busses[i].bus_type == PCI) {
942 if (pci0 == -1)
943 pci0 = i;
944 else if (pci0 != 0)
945 panic(
946 "MPTable contains multiple PCI busses but no PCI bus 0");
947 }
948 }
949
950 static void
951 mptable_pci_probe_table_handler(u_char *entry, void *arg)
952 {
953 struct pci_probe_table_args *args;
954 int_entry_ptr intr;
955
956 if (*entry != MPCT_ENTRY_INT)
957 return;
958 intr = (int_entry_ptr)entry;
959 args = (struct pci_probe_table_args *)arg;
960 KASSERT(args->bus <= mptable_maxbusid,
961 ("bus %d is too big", args->bus));
962 KASSERT(busses[args->bus].bus_type == PCI, ("probing for non-PCI bus"));
963 if (intr->src_bus_id == args->bus)
964 args->found = 1;
965 }
966
967 int
968 mptable_pci_probe_table(int bus)
969 {
970 struct pci_probe_table_args args;
971
972 if (bus < 0)
973 return (EINVAL);
974 if (mpct == NULL || pci0 == -1 || pci0 + bus > mptable_maxbusid)
975 return (ENXIO);
976 if (busses[pci0 + bus].bus_type != PCI)
977 return (ENXIO);
978 args.bus = pci0 + bus;
979 args.found = 0;
980 mptable_walk_table(mptable_pci_probe_table_handler, &args);
981 if (args.found == 0)
982 return (ENXIO);
983 return (0);
984 }
985
986 static void
987 mptable_pci_route_interrupt_handler(u_char *entry, void *arg)
988 {
989 struct pci_route_interrupt_args *args;
990 int_entry_ptr intr;
991 int vector;
992
993 if (*entry != MPCT_ENTRY_INT)
994 return;
995 intr = (int_entry_ptr)entry;
996 args = (struct pci_route_interrupt_args *)arg;
997 if (intr->src_bus_id != args->bus || intr->src_bus_irq != args->irq)
998 return;
999
1000 /* Make sure the APIC maps to a known APIC. */
1001 KASSERT(ioapics[intr->dst_apic_id] != NULL,
1002 ("No I/O APIC %d to route interrupt to", intr->dst_apic_id));
1003
1004 /*
1005 * Look up the vector for this APIC / pin combination. If we
1006 * have previously matched an entry for this PCI IRQ but it
1007 * has the same vector as this entry, just return. Otherwise,
1008 * we use the vector for this APIC / pin combination.
1009 */
1010 vector = ioapic_get_vector(ioapics[intr->dst_apic_id],
1011 intr->dst_apic_int);
1012 if (args->vector == vector)
1013 return;
1014 KASSERT(args->vector == -1,
1015 ("Multiple IRQs for PCI interrupt %d.%d.INT%c: %d and %d\n",
1016 args->bus, args->irq >> 2, 'A' + (args->irq & 0x3), args->vector,
1017 vector));
1018 args->vector = vector;
1019 }
1020
1021 int
1022 mptable_pci_route_interrupt(device_t pcib, device_t dev, int pin)
1023 {
1024 struct pci_route_interrupt_args args;
1025 int slot;
1026
1027 /* Like ACPI, pin numbers are 0-3, not 1-4. */
1028 pin--;
1029 KASSERT(pci0 != -1, ("do not know how to route PCI interrupts"));
1030 args.bus = pci_get_bus(dev) + pci0;
1031 slot = pci_get_slot(dev);
1032
1033 /*
1034 * PCI interrupt entries in the MP Table encode both the slot and
1035 * pin into the IRQ with the pin being the two least significant
1036 * bits, the slot being the next five bits, and the most significant
1037 * bit being reserved.
1038 */
1039 args.irq = slot << 2 | pin;
1040 args.vector = -1;
1041 mptable_walk_table(mptable_pci_route_interrupt_handler, &args);
1042 if (args.vector < 0) {
1043 device_printf(pcib, "unable to route slot %d INT%c\n", slot,
1044 'A' + pin);
1045 return (PCI_INVALID_IRQ);
1046 }
1047 if (bootverbose)
1048 device_printf(pcib, "slot %d INT%c routed to irq %d\n", slot,
1049 'A' + pin, args.vector);
1050 return (args.vector);
1051 }
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