FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/pmap.c
1 /*-
2 * Copyright (c) 1991 Regents of the University of California.
3 * All rights reserved.
4 * Copyright (c) 1994 John S. Dyson
5 * All rights reserved.
6 * Copyright (c) 1994 David Greenman
7 * All rights reserved.
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
9 * All rights reserved.
10 *
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * SUCH DAMAGE.
42 *
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
44 */
45 /*-
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
48 *
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
54 *
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
57 * are met:
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
63 *
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 * SUCH DAMAGE.
75 */
76
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD: releng/10.0/sys/i386/i386/pmap.c 255724 2013-09-20 04:30:18Z alc $");
79
80 /*
81 * Manages physical address maps.
82 *
83 * Since the information managed by this module is
84 * also stored by the logical address mapping module,
85 * this module may throw away valid virtual-to-physical
86 * mappings at almost any time. However, invalidations
87 * of virtual-to-physical mappings must be done as
88 * requested.
89 *
90 * In order to cope with hardware architectures which
91 * make virtual-to-physical map invalidates expensive,
92 * this module may delay invalidate or reduced protection
93 * operations until such time as they are actually
94 * necessary. This module is given full information as
95 * to which processors are currently using which maps,
96 * and to when physical maps must be made correct.
97 */
98
99 #include "opt_apic.h"
100 #include "opt_cpu.h"
101 #include "opt_pmap.h"
102 #include "opt_smp.h"
103 #include "opt_xbox.h"
104
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/kernel.h>
108 #include <sys/ktr.h>
109 #include <sys/lock.h>
110 #include <sys/malloc.h>
111 #include <sys/mman.h>
112 #include <sys/msgbuf.h>
113 #include <sys/mutex.h>
114 #include <sys/proc.h>
115 #include <sys/rwlock.h>
116 #include <sys/sf_buf.h>
117 #include <sys/sx.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
121 #ifdef SMP
122 #include <sys/smp.h>
123 #else
124 #include <sys/cpuset.h>
125 #endif
126
127 #include <vm/vm.h>
128 #include <vm/vm_param.h>
129 #include <vm/vm_kern.h>
130 #include <vm/vm_page.h>
131 #include <vm/vm_map.h>
132 #include <vm/vm_object.h>
133 #include <vm/vm_extern.h>
134 #include <vm/vm_pageout.h>
135 #include <vm/vm_pager.h>
136 #include <vm/vm_radix.h>
137 #include <vm/vm_reserv.h>
138 #include <vm/uma.h>
139
140 #ifdef DEV_APIC
141 #include <sys/bus.h>
142 #include <machine/intr_machdep.h>
143 #include <machine/apicvar.h>
144 #endif
145 #include <machine/cpu.h>
146 #include <machine/cputypes.h>
147 #include <machine/md_var.h>
148 #include <machine/pcb.h>
149 #include <machine/specialreg.h>
150 #ifdef SMP
151 #include <machine/smp.h>
152 #endif
153
154 #ifdef XBOX
155 #include <machine/xbox.h>
156 #endif
157
158 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
159 #define CPU_ENABLE_SSE
160 #endif
161
162 #ifndef PMAP_SHPGPERPROC
163 #define PMAP_SHPGPERPROC 200
164 #endif
165
166 #if !defined(DIAGNOSTIC)
167 #ifdef __GNUC_GNU_INLINE__
168 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
169 #else
170 #define PMAP_INLINE extern inline
171 #endif
172 #else
173 #define PMAP_INLINE
174 #endif
175
176 #ifdef PV_STATS
177 #define PV_STAT(x) do { x ; } while (0)
178 #else
179 #define PV_STAT(x) do { } while (0)
180 #endif
181
182 #define pa_index(pa) ((pa) >> PDRSHIFT)
183 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
184
185 /*
186 * Get PDEs and PTEs for user/kernel address space
187 */
188 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
189 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
190
191 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
192 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
193 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
194 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
195 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
196
197 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
198 atomic_clear_int((u_int *)(pte), PG_W))
199 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
200
201 struct pmap kernel_pmap_store;
202 LIST_HEAD(pmaplist, pmap);
203 static struct pmaplist allpmaps;
204 static struct mtx allpmaps_lock;
205
206 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
207 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
208 int pgeflag = 0; /* PG_G or-in */
209 int pseflag = 0; /* PG_PS or-in */
210
211 static int nkpt = NKPT;
212 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
213 extern u_int32_t KERNend;
214 extern u_int32_t KPTphys;
215
216 #ifdef PAE
217 pt_entry_t pg_nx;
218 static uma_zone_t pdptzone;
219 #endif
220
221 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
222
223 static int pat_works = 1;
224 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
225 "Is page attribute table fully functional?");
226
227 static int pg_ps_enabled = 1;
228 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
229 "Are large page mappings enabled?");
230
231 #define PAT_INDEX_SIZE 8
232 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
233
234 static struct rwlock_padalign pvh_global_lock;
235
236 /*
237 * Data for the pv entry allocation mechanism
238 */
239 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
240 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
241 static struct md_page *pv_table;
242 static int shpgperproc = PMAP_SHPGPERPROC;
243
244 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
245 int pv_maxchunks; /* How many chunks we have KVA for */
246 vm_offset_t pv_vafree; /* freelist stored in the PTE */
247
248 /*
249 * All those kernel PT submaps that BSD is so fond of
250 */
251 struct sysmaps {
252 struct mtx lock;
253 pt_entry_t *CMAP1;
254 pt_entry_t *CMAP2;
255 caddr_t CADDR1;
256 caddr_t CADDR2;
257 };
258 static struct sysmaps sysmaps_pcpu[MAXCPU];
259 pt_entry_t *CMAP1 = 0;
260 static pt_entry_t *CMAP3;
261 static pd_entry_t *KPTD;
262 caddr_t CADDR1 = 0, ptvmmap = 0;
263 static caddr_t CADDR3;
264 struct msgbuf *msgbufp = 0;
265
266 /*
267 * Crashdump maps.
268 */
269 static caddr_t crashdumpmap;
270
271 static pt_entry_t *PMAP1 = 0, *PMAP2;
272 static pt_entry_t *PADDR1 = 0, *PADDR2;
273 #ifdef SMP
274 static int PMAP1cpu;
275 static int PMAP1changedcpu;
276 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
277 &PMAP1changedcpu, 0,
278 "Number of times pmap_pte_quick changed CPU with same PMAP1");
279 #endif
280 static int PMAP1changed;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
282 &PMAP1changed, 0,
283 "Number of times pmap_pte_quick changed PMAP1");
284 static int PMAP1unchanged;
285 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
286 &PMAP1unchanged, 0,
287 "Number of times pmap_pte_quick didn't change PMAP1");
288 static struct mtx PMAP2mutex;
289
290 static void free_pv_chunk(struct pv_chunk *pc);
291 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
292 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
293 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
294 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
295 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
296 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
297 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
298 vm_offset_t va);
299 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
300
301 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
302 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
303 vm_prot_t prot);
304 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
305 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
306 static void pmap_flush_page(vm_page_t m);
307 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
308 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
309 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
310 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
311 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
312 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
313 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
314 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
315 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
316 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
317 vm_prot_t prot);
318 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
319 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
320 struct spglist *free);
321 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
322 struct spglist *free);
323 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
324 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
325 struct spglist *free);
326 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
327 vm_offset_t va);
328 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
329 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
330 vm_page_t m);
331 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
332 pd_entry_t newpde);
333 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
334
335 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags);
336
337 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags);
338 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
339 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
340 static void pmap_pte_release(pt_entry_t *pte);
341 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
342 #ifdef PAE
343 static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait);
344 #endif
345 static void pmap_set_pg(void);
346
347 static __inline void pagezero(void *page);
348
349 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
350 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
351
352 /*
353 * If you get an error here, then you set KVA_PAGES wrong! See the
354 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
355 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
356 */
357 CTASSERT(KERNBASE % (1 << 24) == 0);
358
359 /*
360 * Bootstrap the system enough to run with virtual memory.
361 *
362 * On the i386 this is called after mapping has already been enabled
363 * and just syncs the pmap module with what has already been done.
364 * [We can't call it easily with mapping off since the kernel is not
365 * mapped with PA == VA, hence we would have to relocate every address
366 * from the linked base (virtual) address "KERNBASE" to the actual
367 * (physical) address starting relative to 0]
368 */
369 void
370 pmap_bootstrap(vm_paddr_t firstaddr)
371 {
372 vm_offset_t va;
373 pt_entry_t *pte, *unused;
374 struct sysmaps *sysmaps;
375 int i;
376
377 /*
378 * Initialize the first available kernel virtual address. However,
379 * using "firstaddr" may waste a few pages of the kernel virtual
380 * address space, because locore may not have mapped every physical
381 * page that it allocated. Preferably, locore would provide a first
382 * unused virtual address in addition to "firstaddr".
383 */
384 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
385
386 virtual_end = VM_MAX_KERNEL_ADDRESS;
387
388 /*
389 * Initialize the kernel pmap (which is statically allocated).
390 */
391 PMAP_LOCK_INIT(kernel_pmap);
392 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
393 #ifdef PAE
394 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
395 #endif
396 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
397 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
398
399 /*
400 * Initialize the global pv list lock.
401 */
402 rw_init(&pvh_global_lock, "pmap pv global");
403
404 LIST_INIT(&allpmaps);
405
406 /*
407 * Request a spin mutex so that changes to allpmaps cannot be
408 * preempted by smp_rendezvous_cpus(). Otherwise,
409 * pmap_update_pde_kernel() could access allpmaps while it is
410 * being changed.
411 */
412 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
413 mtx_lock_spin(&allpmaps_lock);
414 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
415 mtx_unlock_spin(&allpmaps_lock);
416
417 /*
418 * Reserve some special page table entries/VA space for temporary
419 * mapping of pages.
420 */
421 #define SYSMAP(c, p, v, n) \
422 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
423
424 va = virtual_avail;
425 pte = vtopte(va);
426
427 /*
428 * CMAP1/CMAP2 are used for zeroing and copying pages.
429 * CMAP3 is used for the idle process page zeroing.
430 */
431 for (i = 0; i < MAXCPU; i++) {
432 sysmaps = &sysmaps_pcpu[i];
433 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
434 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
435 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
436 }
437 SYSMAP(caddr_t, CMAP1, CADDR1, 1)
438 SYSMAP(caddr_t, CMAP3, CADDR3, 1)
439
440 /*
441 * Crashdump maps.
442 */
443 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
444
445 /*
446 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
447 */
448 SYSMAP(caddr_t, unused, ptvmmap, 1)
449
450 /*
451 * msgbufp is used to map the system message buffer.
452 */
453 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
454
455 /*
456 * KPTmap is used by pmap_kextract().
457 *
458 * KPTmap is first initialized by locore. However, that initial
459 * KPTmap can only support NKPT page table pages. Here, a larger
460 * KPTmap is created that can support KVA_PAGES page table pages.
461 */
462 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
463
464 for (i = 0; i < NKPT; i++)
465 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
466
467 /*
468 * Adjust the start of the KPTD and KPTmap so that the implementation
469 * of pmap_kextract() and pmap_growkernel() can be made simpler.
470 */
471 KPTD -= KPTDI;
472 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
473
474 /*
475 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
476 * respectively.
477 */
478 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
479 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
480
481 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
482
483 virtual_avail = va;
484
485 /*
486 * Leave in place an identity mapping (virt == phys) for the low 1 MB
487 * physical memory region that is used by the ACPI wakeup code. This
488 * mapping must not have PG_G set.
489 */
490 #ifdef XBOX
491 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
492 * an early stadium, we cannot yet neatly map video memory ... :-(
493 * Better fixes are very welcome! */
494 if (!arch_i386_is_xbox)
495 #endif
496 for (i = 1; i < NKPT; i++)
497 PTD[i] = 0;
498
499 /* Initialize the PAT MSR if present. */
500 pmap_init_pat();
501
502 /* Turn on PG_G on kernel page(s) */
503 pmap_set_pg();
504 }
505
506 /*
507 * Setup the PAT MSR.
508 */
509 void
510 pmap_init_pat(void)
511 {
512 int pat_table[PAT_INDEX_SIZE];
513 uint64_t pat_msr;
514 u_long cr0, cr4;
515 int i;
516
517 /* Set default PAT index table. */
518 for (i = 0; i < PAT_INDEX_SIZE; i++)
519 pat_table[i] = -1;
520 pat_table[PAT_WRITE_BACK] = 0;
521 pat_table[PAT_WRITE_THROUGH] = 1;
522 pat_table[PAT_UNCACHEABLE] = 3;
523 pat_table[PAT_WRITE_COMBINING] = 3;
524 pat_table[PAT_WRITE_PROTECTED] = 3;
525 pat_table[PAT_UNCACHED] = 3;
526
527 /* Bail if this CPU doesn't implement PAT. */
528 if ((cpu_feature & CPUID_PAT) == 0) {
529 for (i = 0; i < PAT_INDEX_SIZE; i++)
530 pat_index[i] = pat_table[i];
531 pat_works = 0;
532 return;
533 }
534
535 /*
536 * Due to some Intel errata, we can only safely use the lower 4
537 * PAT entries.
538 *
539 * Intel Pentium III Processor Specification Update
540 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
541 * or Mode C Paging)
542 *
543 * Intel Pentium IV Processor Specification Update
544 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
545 */
546 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
547 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
548 pat_works = 0;
549
550 /* Initialize default PAT entries. */
551 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
552 PAT_VALUE(1, PAT_WRITE_THROUGH) |
553 PAT_VALUE(2, PAT_UNCACHED) |
554 PAT_VALUE(3, PAT_UNCACHEABLE) |
555 PAT_VALUE(4, PAT_WRITE_BACK) |
556 PAT_VALUE(5, PAT_WRITE_THROUGH) |
557 PAT_VALUE(6, PAT_UNCACHED) |
558 PAT_VALUE(7, PAT_UNCACHEABLE);
559
560 if (pat_works) {
561 /*
562 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
563 * Program 5 and 6 as WP and WC.
564 * Leave 4 and 7 as WB and UC.
565 */
566 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
567 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
568 PAT_VALUE(6, PAT_WRITE_COMBINING);
569 pat_table[PAT_UNCACHED] = 2;
570 pat_table[PAT_WRITE_PROTECTED] = 5;
571 pat_table[PAT_WRITE_COMBINING] = 6;
572 } else {
573 /*
574 * Just replace PAT Index 2 with WC instead of UC-.
575 */
576 pat_msr &= ~PAT_MASK(2);
577 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
578 pat_table[PAT_WRITE_COMBINING] = 2;
579 }
580
581 /* Disable PGE. */
582 cr4 = rcr4();
583 load_cr4(cr4 & ~CR4_PGE);
584
585 /* Disable caches (CD = 1, NW = 0). */
586 cr0 = rcr0();
587 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
588
589 /* Flushes caches and TLBs. */
590 wbinvd();
591 invltlb();
592
593 /* Update PAT and index table. */
594 wrmsr(MSR_PAT, pat_msr);
595 for (i = 0; i < PAT_INDEX_SIZE; i++)
596 pat_index[i] = pat_table[i];
597
598 /* Flush caches and TLBs again. */
599 wbinvd();
600 invltlb();
601
602 /* Restore caches and PGE. */
603 load_cr0(cr0);
604 load_cr4(cr4);
605 }
606
607 /*
608 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
609 */
610 static void
611 pmap_set_pg(void)
612 {
613 pt_entry_t *pte;
614 vm_offset_t va, endva;
615
616 if (pgeflag == 0)
617 return;
618
619 endva = KERNBASE + KERNend;
620
621 if (pseflag) {
622 va = KERNBASE + KERNLOAD;
623 while (va < endva) {
624 pdir_pde(PTD, va) |= pgeflag;
625 invltlb(); /* Play it safe, invltlb() every time */
626 va += NBPDR;
627 }
628 } else {
629 va = (vm_offset_t)btext;
630 while (va < endva) {
631 pte = vtopte(va);
632 if (*pte)
633 *pte |= pgeflag;
634 invltlb(); /* Play it safe, invltlb() every time */
635 va += PAGE_SIZE;
636 }
637 }
638 }
639
640 /*
641 * Initialize a vm_page's machine-dependent fields.
642 */
643 void
644 pmap_page_init(vm_page_t m)
645 {
646
647 TAILQ_INIT(&m->md.pv_list);
648 m->md.pat_mode = PAT_WRITE_BACK;
649 }
650
651 #ifdef PAE
652 static void *
653 pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
654 {
655
656 /* Inform UMA that this allocator uses kernel_map/object. */
657 *flags = UMA_SLAB_KERNEL;
658 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL,
659 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
660 }
661 #endif
662
663 /*
664 * ABuse the pte nodes for unmapped kva to thread a kva freelist through.
665 * Requirements:
666 * - Must deal with pages in order to ensure that none of the PG_* bits
667 * are ever set, PG_V in particular.
668 * - Assumes we can write to ptes without pte_store() atomic ops, even
669 * on PAE systems. This should be ok.
670 * - Assumes nothing will ever test these addresses for 0 to indicate
671 * no mapping instead of correctly checking PG_V.
672 * - Assumes a vm_offset_t will fit in a pte (true for i386).
673 * Because PG_V is never set, there can be no mappings to invalidate.
674 */
675 static vm_offset_t
676 pmap_ptelist_alloc(vm_offset_t *head)
677 {
678 pt_entry_t *pte;
679 vm_offset_t va;
680
681 va = *head;
682 if (va == 0)
683 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
684 pte = vtopte(va);
685 *head = *pte;
686 if (*head & PG_V)
687 panic("pmap_ptelist_alloc: va with PG_V set!");
688 *pte = 0;
689 return (va);
690 }
691
692 static void
693 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
694 {
695 pt_entry_t *pte;
696
697 if (va & PG_V)
698 panic("pmap_ptelist_free: freeing va with PG_V set!");
699 pte = vtopte(va);
700 *pte = *head; /* virtual! PG_V is 0 though */
701 *head = va;
702 }
703
704 static void
705 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
706 {
707 int i;
708 vm_offset_t va;
709
710 *head = 0;
711 for (i = npages - 1; i >= 0; i--) {
712 va = (vm_offset_t)base + i * PAGE_SIZE;
713 pmap_ptelist_free(head, va);
714 }
715 }
716
717
718 /*
719 * Initialize the pmap module.
720 * Called by vm_init, to initialize any structures that the pmap
721 * system needs to map virtual memory.
722 */
723 void
724 pmap_init(void)
725 {
726 vm_page_t mpte;
727 vm_size_t s;
728 int i, pv_npg;
729
730 /*
731 * Initialize the vm page array entries for the kernel pmap's
732 * page table pages.
733 */
734 for (i = 0; i < NKPT; i++) {
735 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
736 KASSERT(mpte >= vm_page_array &&
737 mpte < &vm_page_array[vm_page_array_size],
738 ("pmap_init: page table page is out of range"));
739 mpte->pindex = i + KPTDI;
740 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
741 }
742
743 /*
744 * Initialize the address space (zone) for the pv entries. Set a
745 * high water mark so that the system can recover from excessive
746 * numbers of pv entries.
747 */
748 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
749 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
750 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
751 pv_entry_max = roundup(pv_entry_max, _NPCPV);
752 pv_entry_high_water = 9 * (pv_entry_max / 10);
753
754 /*
755 * If the kernel is running in a virtual machine on an AMD Family 10h
756 * processor, then it must assume that MCA is enabled by the virtual
757 * machine monitor.
758 */
759 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD &&
760 CPUID_TO_FAMILY(cpu_id) == 0x10)
761 workaround_erratum383 = 1;
762
763 /*
764 * Are large page mappings supported and enabled?
765 */
766 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
767 if (pseflag == 0)
768 pg_ps_enabled = 0;
769 else if (pg_ps_enabled) {
770 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
771 ("pmap_init: can't assign to pagesizes[1]"));
772 pagesizes[1] = NBPDR;
773 }
774
775 /*
776 * Calculate the size of the pv head table for superpages.
777 */
778 for (i = 0; phys_avail[i + 1]; i += 2);
779 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR;
780
781 /*
782 * Allocate memory for the pv head table for superpages.
783 */
784 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
785 s = round_page(s);
786 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
787 M_WAITOK | M_ZERO);
788 for (i = 0; i < pv_npg; i++)
789 TAILQ_INIT(&pv_table[i].pv_list);
790
791 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
792 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
793 if (pv_chunkbase == NULL)
794 panic("pmap_init: not enough kvm for pv chunks");
795 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
796 #ifdef PAE
797 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
798 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
799 UMA_ZONE_VM | UMA_ZONE_NOFREE);
800 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
801 #endif
802 }
803
804
805 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
806 "Max number of PV entries");
807 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
808 "Page share factor per proc");
809
810 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
811 "2/4MB page mapping counters");
812
813 static u_long pmap_pde_demotions;
814 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
815 &pmap_pde_demotions, 0, "2/4MB page demotions");
816
817 static u_long pmap_pde_mappings;
818 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
819 &pmap_pde_mappings, 0, "2/4MB page mappings");
820
821 static u_long pmap_pde_p_failures;
822 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
823 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
824
825 static u_long pmap_pde_promotions;
826 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
827 &pmap_pde_promotions, 0, "2/4MB page promotions");
828
829 /***************************************************
830 * Low level helper routines.....
831 ***************************************************/
832
833 /*
834 * Determine the appropriate bits to set in a PTE or PDE for a specified
835 * caching mode.
836 */
837 int
838 pmap_cache_bits(int mode, boolean_t is_pde)
839 {
840 int cache_bits, pat_flag, pat_idx;
841
842 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
843 panic("Unknown caching mode %d\n", mode);
844
845 /* The PAT bit is different for PTE's and PDE's. */
846 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
847
848 /* Map the caching mode to a PAT index. */
849 pat_idx = pat_index[mode];
850
851 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
852 cache_bits = 0;
853 if (pat_idx & 0x4)
854 cache_bits |= pat_flag;
855 if (pat_idx & 0x2)
856 cache_bits |= PG_NC_PCD;
857 if (pat_idx & 0x1)
858 cache_bits |= PG_NC_PWT;
859 return (cache_bits);
860 }
861
862 /*
863 * The caller is responsible for maintaining TLB consistency.
864 */
865 static void
866 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
867 {
868 pd_entry_t *pde;
869 pmap_t pmap;
870 boolean_t PTD_updated;
871
872 PTD_updated = FALSE;
873 mtx_lock_spin(&allpmaps_lock);
874 LIST_FOREACH(pmap, &allpmaps, pm_list) {
875 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
876 PG_FRAME))
877 PTD_updated = TRUE;
878 pde = pmap_pde(pmap, va);
879 pde_store(pde, newpde);
880 }
881 mtx_unlock_spin(&allpmaps_lock);
882 KASSERT(PTD_updated,
883 ("pmap_kenter_pde: current page table is not in allpmaps"));
884 }
885
886 /*
887 * After changing the page size for the specified virtual address in the page
888 * table, flush the corresponding entries from the processor's TLB. Only the
889 * calling processor's TLB is affected.
890 *
891 * The calling thread must be pinned to a processor.
892 */
893 static void
894 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
895 {
896 u_long cr4;
897
898 if ((newpde & PG_PS) == 0)
899 /* Demotion: flush a specific 2MB page mapping. */
900 invlpg(va);
901 else if ((newpde & PG_G) == 0)
902 /*
903 * Promotion: flush every 4KB page mapping from the TLB
904 * because there are too many to flush individually.
905 */
906 invltlb();
907 else {
908 /*
909 * Promotion: flush every 4KB page mapping from the TLB,
910 * including any global (PG_G) mappings.
911 */
912 cr4 = rcr4();
913 load_cr4(cr4 & ~CR4_PGE);
914 /*
915 * Although preemption at this point could be detrimental to
916 * performance, it would not lead to an error. PG_G is simply
917 * ignored if CR4.PGE is clear. Moreover, in case this block
918 * is re-entered, the load_cr4() either above or below will
919 * modify CR4.PGE flushing the TLB.
920 */
921 load_cr4(cr4 | CR4_PGE);
922 }
923 }
924 #ifdef SMP
925 /*
926 * For SMP, these functions have to use the IPI mechanism for coherence.
927 *
928 * N.B.: Before calling any of the following TLB invalidation functions,
929 * the calling processor must ensure that all stores updating a non-
930 * kernel page table are globally performed. Otherwise, another
931 * processor could cache an old, pre-update entry without being
932 * invalidated. This can happen one of two ways: (1) The pmap becomes
933 * active on another processor after its pm_active field is checked by
934 * one of the following functions but before a store updating the page
935 * table is globally performed. (2) The pmap becomes active on another
936 * processor before its pm_active field is checked but due to
937 * speculative loads one of the following functions stills reads the
938 * pmap as inactive on the other processor.
939 *
940 * The kernel page table is exempt because its pm_active field is
941 * immutable. The kernel page table is always active on every
942 * processor.
943 */
944 void
945 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
946 {
947 cpuset_t other_cpus;
948 u_int cpuid;
949
950 sched_pin();
951 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
952 invlpg(va);
953 smp_invlpg(va);
954 } else {
955 cpuid = PCPU_GET(cpuid);
956 other_cpus = all_cpus;
957 CPU_CLR(cpuid, &other_cpus);
958 if (CPU_ISSET(cpuid, &pmap->pm_active))
959 invlpg(va);
960 CPU_AND(&other_cpus, &pmap->pm_active);
961 if (!CPU_EMPTY(&other_cpus))
962 smp_masked_invlpg(other_cpus, va);
963 }
964 sched_unpin();
965 }
966
967 void
968 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
969 {
970 cpuset_t other_cpus;
971 vm_offset_t addr;
972 u_int cpuid;
973
974 sched_pin();
975 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
976 for (addr = sva; addr < eva; addr += PAGE_SIZE)
977 invlpg(addr);
978 smp_invlpg_range(sva, eva);
979 } else {
980 cpuid = PCPU_GET(cpuid);
981 other_cpus = all_cpus;
982 CPU_CLR(cpuid, &other_cpus);
983 if (CPU_ISSET(cpuid, &pmap->pm_active))
984 for (addr = sva; addr < eva; addr += PAGE_SIZE)
985 invlpg(addr);
986 CPU_AND(&other_cpus, &pmap->pm_active);
987 if (!CPU_EMPTY(&other_cpus))
988 smp_masked_invlpg_range(other_cpus, sva, eva);
989 }
990 sched_unpin();
991 }
992
993 void
994 pmap_invalidate_all(pmap_t pmap)
995 {
996 cpuset_t other_cpus;
997 u_int cpuid;
998
999 sched_pin();
1000 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1001 invltlb();
1002 smp_invltlb();
1003 } else {
1004 cpuid = PCPU_GET(cpuid);
1005 other_cpus = all_cpus;
1006 CPU_CLR(cpuid, &other_cpus);
1007 if (CPU_ISSET(cpuid, &pmap->pm_active))
1008 invltlb();
1009 CPU_AND(&other_cpus, &pmap->pm_active);
1010 if (!CPU_EMPTY(&other_cpus))
1011 smp_masked_invltlb(other_cpus);
1012 }
1013 sched_unpin();
1014 }
1015
1016 void
1017 pmap_invalidate_cache(void)
1018 {
1019
1020 sched_pin();
1021 wbinvd();
1022 smp_cache_flush();
1023 sched_unpin();
1024 }
1025
1026 struct pde_action {
1027 cpuset_t invalidate; /* processors that invalidate their TLB */
1028 vm_offset_t va;
1029 pd_entry_t *pde;
1030 pd_entry_t newpde;
1031 u_int store; /* processor that updates the PDE */
1032 };
1033
1034 static void
1035 pmap_update_pde_kernel(void *arg)
1036 {
1037 struct pde_action *act = arg;
1038 pd_entry_t *pde;
1039 pmap_t pmap;
1040
1041 if (act->store == PCPU_GET(cpuid)) {
1042
1043 /*
1044 * Elsewhere, this operation requires allpmaps_lock for
1045 * synchronization. Here, it does not because it is being
1046 * performed in the context of an all_cpus rendezvous.
1047 */
1048 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1049 pde = pmap_pde(pmap, act->va);
1050 pde_store(pde, act->newpde);
1051 }
1052 }
1053 }
1054
1055 static void
1056 pmap_update_pde_user(void *arg)
1057 {
1058 struct pde_action *act = arg;
1059
1060 if (act->store == PCPU_GET(cpuid))
1061 pde_store(act->pde, act->newpde);
1062 }
1063
1064 static void
1065 pmap_update_pde_teardown(void *arg)
1066 {
1067 struct pde_action *act = arg;
1068
1069 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1070 pmap_update_pde_invalidate(act->va, act->newpde);
1071 }
1072
1073 /*
1074 * Change the page size for the specified virtual address in a way that
1075 * prevents any possibility of the TLB ever having two entries that map the
1076 * same virtual address using different page sizes. This is the recommended
1077 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1078 * machine check exception for a TLB state that is improperly diagnosed as a
1079 * hardware error.
1080 */
1081 static void
1082 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1083 {
1084 struct pde_action act;
1085 cpuset_t active, other_cpus;
1086 u_int cpuid;
1087
1088 sched_pin();
1089 cpuid = PCPU_GET(cpuid);
1090 other_cpus = all_cpus;
1091 CPU_CLR(cpuid, &other_cpus);
1092 if (pmap == kernel_pmap)
1093 active = all_cpus;
1094 else
1095 active = pmap->pm_active;
1096 if (CPU_OVERLAP(&active, &other_cpus)) {
1097 act.store = cpuid;
1098 act.invalidate = active;
1099 act.va = va;
1100 act.pde = pde;
1101 act.newpde = newpde;
1102 CPU_SET(cpuid, &active);
1103 smp_rendezvous_cpus(active,
1104 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1105 pmap_update_pde_kernel : pmap_update_pde_user,
1106 pmap_update_pde_teardown, &act);
1107 } else {
1108 if (pmap == kernel_pmap)
1109 pmap_kenter_pde(va, newpde);
1110 else
1111 pde_store(pde, newpde);
1112 if (CPU_ISSET(cpuid, &active))
1113 pmap_update_pde_invalidate(va, newpde);
1114 }
1115 sched_unpin();
1116 }
1117 #else /* !SMP */
1118 /*
1119 * Normal, non-SMP, 486+ invalidation functions.
1120 * We inline these within pmap.c for speed.
1121 */
1122 PMAP_INLINE void
1123 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1124 {
1125
1126 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1127 invlpg(va);
1128 }
1129
1130 PMAP_INLINE void
1131 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1132 {
1133 vm_offset_t addr;
1134
1135 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1136 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1137 invlpg(addr);
1138 }
1139
1140 PMAP_INLINE void
1141 pmap_invalidate_all(pmap_t pmap)
1142 {
1143
1144 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1145 invltlb();
1146 }
1147
1148 PMAP_INLINE void
1149 pmap_invalidate_cache(void)
1150 {
1151
1152 wbinvd();
1153 }
1154
1155 static void
1156 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1157 {
1158
1159 if (pmap == kernel_pmap)
1160 pmap_kenter_pde(va, newpde);
1161 else
1162 pde_store(pde, newpde);
1163 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1164 pmap_update_pde_invalidate(va, newpde);
1165 }
1166 #endif /* !SMP */
1167
1168 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1169
1170 void
1171 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1172 {
1173
1174 KASSERT((sva & PAGE_MASK) == 0,
1175 ("pmap_invalidate_cache_range: sva not page-aligned"));
1176 KASSERT((eva & PAGE_MASK) == 0,
1177 ("pmap_invalidate_cache_range: eva not page-aligned"));
1178
1179 if (cpu_feature & CPUID_SS)
1180 ; /* If "Self Snoop" is supported, do nothing. */
1181 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1182 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1183
1184 #ifdef DEV_APIC
1185 /*
1186 * XXX: Some CPUs fault, hang, or trash the local APIC
1187 * registers if we use CLFLUSH on the local APIC
1188 * range. The local APIC is always uncached, so we
1189 * don't need to flush for that range anyway.
1190 */
1191 if (pmap_kextract(sva) == lapic_paddr)
1192 return;
1193 #endif
1194 /*
1195 * Otherwise, do per-cache line flush. Use the mfence
1196 * instruction to insure that previous stores are
1197 * included in the write-back. The processor
1198 * propagates flush to other processors in the cache
1199 * coherence domain.
1200 */
1201 mfence();
1202 for (; sva < eva; sva += cpu_clflush_line_size)
1203 clflush(sva);
1204 mfence();
1205 } else {
1206
1207 /*
1208 * No targeted cache flush methods are supported by CPU,
1209 * or the supplied range is bigger than 2MB.
1210 * Globally invalidate cache.
1211 */
1212 pmap_invalidate_cache();
1213 }
1214 }
1215
1216 void
1217 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1218 {
1219 int i;
1220
1221 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1222 (cpu_feature & CPUID_CLFSH) == 0) {
1223 pmap_invalidate_cache();
1224 } else {
1225 for (i = 0; i < count; i++)
1226 pmap_flush_page(pages[i]);
1227 }
1228 }
1229
1230 /*
1231 * Are we current address space or kernel? N.B. We return FALSE when
1232 * a pmap's page table is in use because a kernel thread is borrowing
1233 * it. The borrowed page table can change spontaneously, making any
1234 * dependence on its continued use subject to a race condition.
1235 */
1236 static __inline int
1237 pmap_is_current(pmap_t pmap)
1238 {
1239
1240 return (pmap == kernel_pmap ||
1241 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) &&
1242 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME)));
1243 }
1244
1245 /*
1246 * If the given pmap is not the current or kernel pmap, the returned pte must
1247 * be released by passing it to pmap_pte_release().
1248 */
1249 pt_entry_t *
1250 pmap_pte(pmap_t pmap, vm_offset_t va)
1251 {
1252 pd_entry_t newpf;
1253 pd_entry_t *pde;
1254
1255 pde = pmap_pde(pmap, va);
1256 if (*pde & PG_PS)
1257 return (pde);
1258 if (*pde != 0) {
1259 /* are we current address space or kernel? */
1260 if (pmap_is_current(pmap))
1261 return (vtopte(va));
1262 mtx_lock(&PMAP2mutex);
1263 newpf = *pde & PG_FRAME;
1264 if ((*PMAP2 & PG_FRAME) != newpf) {
1265 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1266 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1267 }
1268 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1269 }
1270 return (NULL);
1271 }
1272
1273 /*
1274 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1275 * being NULL.
1276 */
1277 static __inline void
1278 pmap_pte_release(pt_entry_t *pte)
1279 {
1280
1281 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1282 mtx_unlock(&PMAP2mutex);
1283 }
1284
1285 static __inline void
1286 invlcaddr(void *caddr)
1287 {
1288
1289 invlpg((u_int)caddr);
1290 }
1291
1292 /*
1293 * Super fast pmap_pte routine best used when scanning
1294 * the pv lists. This eliminates many coarse-grained
1295 * invltlb calls. Note that many of the pv list
1296 * scans are across different pmaps. It is very wasteful
1297 * to do an entire invltlb for checking a single mapping.
1298 *
1299 * If the given pmap is not the current pmap, pvh_global_lock
1300 * must be held and curthread pinned to a CPU.
1301 */
1302 static pt_entry_t *
1303 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1304 {
1305 pd_entry_t newpf;
1306 pd_entry_t *pde;
1307
1308 pde = pmap_pde(pmap, va);
1309 if (*pde & PG_PS)
1310 return (pde);
1311 if (*pde != 0) {
1312 /* are we current address space or kernel? */
1313 if (pmap_is_current(pmap))
1314 return (vtopte(va));
1315 rw_assert(&pvh_global_lock, RA_WLOCKED);
1316 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1317 newpf = *pde & PG_FRAME;
1318 if ((*PMAP1 & PG_FRAME) != newpf) {
1319 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1320 #ifdef SMP
1321 PMAP1cpu = PCPU_GET(cpuid);
1322 #endif
1323 invlcaddr(PADDR1);
1324 PMAP1changed++;
1325 } else
1326 #ifdef SMP
1327 if (PMAP1cpu != PCPU_GET(cpuid)) {
1328 PMAP1cpu = PCPU_GET(cpuid);
1329 invlcaddr(PADDR1);
1330 PMAP1changedcpu++;
1331 } else
1332 #endif
1333 PMAP1unchanged++;
1334 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1335 }
1336 return (0);
1337 }
1338
1339 /*
1340 * Routine: pmap_extract
1341 * Function:
1342 * Extract the physical page address associated
1343 * with the given map/virtual_address pair.
1344 */
1345 vm_paddr_t
1346 pmap_extract(pmap_t pmap, vm_offset_t va)
1347 {
1348 vm_paddr_t rtval;
1349 pt_entry_t *pte;
1350 pd_entry_t pde;
1351
1352 rtval = 0;
1353 PMAP_LOCK(pmap);
1354 pde = pmap->pm_pdir[va >> PDRSHIFT];
1355 if (pde != 0) {
1356 if ((pde & PG_PS) != 0)
1357 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1358 else {
1359 pte = pmap_pte(pmap, va);
1360 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1361 pmap_pte_release(pte);
1362 }
1363 }
1364 PMAP_UNLOCK(pmap);
1365 return (rtval);
1366 }
1367
1368 /*
1369 * Routine: pmap_extract_and_hold
1370 * Function:
1371 * Atomically extract and hold the physical page
1372 * with the given pmap and virtual address pair
1373 * if that mapping permits the given protection.
1374 */
1375 vm_page_t
1376 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1377 {
1378 pd_entry_t pde;
1379 pt_entry_t pte, *ptep;
1380 vm_page_t m;
1381 vm_paddr_t pa;
1382
1383 pa = 0;
1384 m = NULL;
1385 PMAP_LOCK(pmap);
1386 retry:
1387 pde = *pmap_pde(pmap, va);
1388 if (pde != 0) {
1389 if (pde & PG_PS) {
1390 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1391 if (vm_page_pa_tryrelock(pmap, (pde &
1392 PG_PS_FRAME) | (va & PDRMASK), &pa))
1393 goto retry;
1394 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1395 (va & PDRMASK));
1396 vm_page_hold(m);
1397 }
1398 } else {
1399 ptep = pmap_pte(pmap, va);
1400 pte = *ptep;
1401 pmap_pte_release(ptep);
1402 if (pte != 0 &&
1403 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1404 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1405 &pa))
1406 goto retry;
1407 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1408 vm_page_hold(m);
1409 }
1410 }
1411 }
1412 PA_UNLOCK_COND(pa);
1413 PMAP_UNLOCK(pmap);
1414 return (m);
1415 }
1416
1417 /***************************************************
1418 * Low level mapping routines.....
1419 ***************************************************/
1420
1421 /*
1422 * Add a wired page to the kva.
1423 * Note: not SMP coherent.
1424 *
1425 * This function may be used before pmap_bootstrap() is called.
1426 */
1427 PMAP_INLINE void
1428 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1429 {
1430 pt_entry_t *pte;
1431
1432 pte = vtopte(va);
1433 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1434 }
1435
1436 static __inline void
1437 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1438 {
1439 pt_entry_t *pte;
1440
1441 pte = vtopte(va);
1442 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1443 }
1444
1445 /*
1446 * Remove a page from the kernel pagetables.
1447 * Note: not SMP coherent.
1448 *
1449 * This function may be used before pmap_bootstrap() is called.
1450 */
1451 PMAP_INLINE void
1452 pmap_kremove(vm_offset_t va)
1453 {
1454 pt_entry_t *pte;
1455
1456 pte = vtopte(va);
1457 pte_clear(pte);
1458 }
1459
1460 /*
1461 * Used to map a range of physical addresses into kernel
1462 * virtual address space.
1463 *
1464 * The value passed in '*virt' is a suggested virtual address for
1465 * the mapping. Architectures which can support a direct-mapped
1466 * physical to virtual region can return the appropriate address
1467 * within that region, leaving '*virt' unchanged. Other
1468 * architectures should map the pages starting at '*virt' and
1469 * update '*virt' with the first usable address after the mapped
1470 * region.
1471 */
1472 vm_offset_t
1473 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1474 {
1475 vm_offset_t va, sva;
1476 vm_paddr_t superpage_offset;
1477 pd_entry_t newpde;
1478
1479 va = *virt;
1480 /*
1481 * Does the physical address range's size and alignment permit at
1482 * least one superpage mapping to be created?
1483 */
1484 superpage_offset = start & PDRMASK;
1485 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1486 /*
1487 * Increase the starting virtual address so that its alignment
1488 * does not preclude the use of superpage mappings.
1489 */
1490 if ((va & PDRMASK) < superpage_offset)
1491 va = (va & ~PDRMASK) + superpage_offset;
1492 else if ((va & PDRMASK) > superpage_offset)
1493 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1494 }
1495 sva = va;
1496 while (start < end) {
1497 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1498 pseflag) {
1499 KASSERT((va & PDRMASK) == 0,
1500 ("pmap_map: misaligned va %#x", va));
1501 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1502 pmap_kenter_pde(va, newpde);
1503 va += NBPDR;
1504 start += NBPDR;
1505 } else {
1506 pmap_kenter(va, start);
1507 va += PAGE_SIZE;
1508 start += PAGE_SIZE;
1509 }
1510 }
1511 pmap_invalidate_range(kernel_pmap, sva, va);
1512 *virt = va;
1513 return (sva);
1514 }
1515
1516
1517 /*
1518 * Add a list of wired pages to the kva
1519 * this routine is only used for temporary
1520 * kernel mappings that do not need to have
1521 * page modification or references recorded.
1522 * Note that old mappings are simply written
1523 * over. The page *must* be wired.
1524 * Note: SMP coherent. Uses a ranged shootdown IPI.
1525 */
1526 void
1527 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1528 {
1529 pt_entry_t *endpte, oldpte, pa, *pte;
1530 vm_page_t m;
1531
1532 oldpte = 0;
1533 pte = vtopte(sva);
1534 endpte = pte + count;
1535 while (pte < endpte) {
1536 m = *ma++;
1537 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1538 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1539 oldpte |= *pte;
1540 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1541 }
1542 pte++;
1543 }
1544 if (__predict_false((oldpte & PG_V) != 0))
1545 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1546 PAGE_SIZE);
1547 }
1548
1549 /*
1550 * This routine tears out page mappings from the
1551 * kernel -- it is meant only for temporary mappings.
1552 * Note: SMP coherent. Uses a ranged shootdown IPI.
1553 */
1554 void
1555 pmap_qremove(vm_offset_t sva, int count)
1556 {
1557 vm_offset_t va;
1558
1559 va = sva;
1560 while (count-- > 0) {
1561 pmap_kremove(va);
1562 va += PAGE_SIZE;
1563 }
1564 pmap_invalidate_range(kernel_pmap, sva, va);
1565 }
1566
1567 /***************************************************
1568 * Page table page management routines.....
1569 ***************************************************/
1570 static __inline void
1571 pmap_free_zero_pages(struct spglist *free)
1572 {
1573 vm_page_t m;
1574
1575 while ((m = SLIST_FIRST(free)) != NULL) {
1576 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1577 /* Preserve the page's PG_ZERO setting. */
1578 vm_page_free_toq(m);
1579 }
1580 }
1581
1582 /*
1583 * Schedule the specified unused page table page to be freed. Specifically,
1584 * add the page to the specified list of pages that will be released to the
1585 * physical memory manager after the TLB has been updated.
1586 */
1587 static __inline void
1588 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1589 boolean_t set_PG_ZERO)
1590 {
1591
1592 if (set_PG_ZERO)
1593 m->flags |= PG_ZERO;
1594 else
1595 m->flags &= ~PG_ZERO;
1596 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1597 }
1598
1599 /*
1600 * Inserts the specified page table page into the specified pmap's collection
1601 * of idle page table pages. Each of a pmap's page table pages is responsible
1602 * for mapping a distinct range of virtual addresses. The pmap's collection is
1603 * ordered by this virtual address range.
1604 */
1605 static __inline int
1606 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1607 {
1608
1609 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1610 return (vm_radix_insert(&pmap->pm_root, mpte));
1611 }
1612
1613 /*
1614 * Looks for a page table page mapping the specified virtual address in the
1615 * specified pmap's collection of idle page table pages. Returns NULL if there
1616 * is no page table page corresponding to the specified virtual address.
1617 */
1618 static __inline vm_page_t
1619 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1620 {
1621
1622 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1623 return (vm_radix_lookup(&pmap->pm_root, va >> PDRSHIFT));
1624 }
1625
1626 /*
1627 * Removes the specified page table page from the specified pmap's collection
1628 * of idle page table pages. The specified page table page must be a member of
1629 * the pmap's collection.
1630 */
1631 static __inline void
1632 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1633 {
1634
1635 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1636 vm_radix_remove(&pmap->pm_root, mpte->pindex);
1637 }
1638
1639 /*
1640 * Decrements a page table page's wire count, which is used to record the
1641 * number of valid page table entries within the page. If the wire count
1642 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1643 * page table page was unmapped and FALSE otherwise.
1644 */
1645 static inline boolean_t
1646 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1647 {
1648
1649 --m->wire_count;
1650 if (m->wire_count == 0) {
1651 _pmap_unwire_ptp(pmap, m, free);
1652 return (TRUE);
1653 } else
1654 return (FALSE);
1655 }
1656
1657 static void
1658 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1659 {
1660 vm_offset_t pteva;
1661
1662 /*
1663 * unmap the page table page
1664 */
1665 pmap->pm_pdir[m->pindex] = 0;
1666 --pmap->pm_stats.resident_count;
1667
1668 /*
1669 * This is a release store so that the ordinary store unmapping
1670 * the page table page is globally performed before TLB shoot-
1671 * down is begun.
1672 */
1673 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1674
1675 /*
1676 * Do an invltlb to make the invalidated mapping
1677 * take effect immediately.
1678 */
1679 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1680 pmap_invalidate_page(pmap, pteva);
1681
1682 /*
1683 * Put page on a list so that it is released after
1684 * *ALL* TLB shootdown is done
1685 */
1686 pmap_add_delayed_free_list(m, free, TRUE);
1687 }
1688
1689 /*
1690 * After removing a page table entry, this routine is used to
1691 * conditionally free the page, and manage the hold/wire counts.
1692 */
1693 static int
1694 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1695 {
1696 pd_entry_t ptepde;
1697 vm_page_t mpte;
1698
1699 if (va >= VM_MAXUSER_ADDRESS)
1700 return (0);
1701 ptepde = *pmap_pde(pmap, va);
1702 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1703 return (pmap_unwire_ptp(pmap, mpte, free));
1704 }
1705
1706 /*
1707 * Initialize the pmap for the swapper process.
1708 */
1709 void
1710 pmap_pinit0(pmap_t pmap)
1711 {
1712
1713 PMAP_LOCK_INIT(pmap);
1714 /*
1715 * Since the page table directory is shared with the kernel pmap,
1716 * which is already included in the list "allpmaps", this pmap does
1717 * not need to be inserted into that list.
1718 */
1719 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1720 #ifdef PAE
1721 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1722 #endif
1723 pmap->pm_root.rt_root = 0;
1724 CPU_ZERO(&pmap->pm_active);
1725 PCPU_SET(curpmap, pmap);
1726 TAILQ_INIT(&pmap->pm_pvchunk);
1727 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1728 }
1729
1730 /*
1731 * Initialize a preallocated and zeroed pmap structure,
1732 * such as one in a vmspace structure.
1733 */
1734 int
1735 pmap_pinit(pmap_t pmap)
1736 {
1737 vm_page_t m, ptdpg[NPGPTD];
1738 vm_paddr_t pa;
1739 int i;
1740
1741 /*
1742 * No need to allocate page table space yet but we do need a valid
1743 * page directory table.
1744 */
1745 if (pmap->pm_pdir == NULL) {
1746 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1747 if (pmap->pm_pdir == NULL) {
1748 PMAP_LOCK_DESTROY(pmap);
1749 return (0);
1750 }
1751 #ifdef PAE
1752 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1753 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1754 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1755 ("pmap_pinit: pdpt misaligned"));
1756 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1757 ("pmap_pinit: pdpt above 4g"));
1758 #endif
1759 pmap->pm_root.rt_root = 0;
1760 }
1761 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1762 ("pmap_pinit: pmap has reserved page table page(s)"));
1763
1764 /*
1765 * allocate the page directory page(s)
1766 */
1767 for (i = 0; i < NPGPTD;) {
1768 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1769 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1770 if (m == NULL)
1771 VM_WAIT;
1772 else {
1773 ptdpg[i++] = m;
1774 }
1775 }
1776
1777 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1778
1779 for (i = 0; i < NPGPTD; i++)
1780 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1781 pagezero(pmap->pm_pdir + (i * NPDEPG));
1782
1783 mtx_lock_spin(&allpmaps_lock);
1784 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1785 /* Copy the kernel page table directory entries. */
1786 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1787 mtx_unlock_spin(&allpmaps_lock);
1788
1789 /* install self-referential address mapping entry(s) */
1790 for (i = 0; i < NPGPTD; i++) {
1791 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1792 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1793 #ifdef PAE
1794 pmap->pm_pdpt[i] = pa | PG_V;
1795 #endif
1796 }
1797
1798 CPU_ZERO(&pmap->pm_active);
1799 TAILQ_INIT(&pmap->pm_pvchunk);
1800 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1801
1802 return (1);
1803 }
1804
1805 /*
1806 * this routine is called if the page table page is not
1807 * mapped correctly.
1808 */
1809 static vm_page_t
1810 _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags)
1811 {
1812 vm_paddr_t ptepa;
1813 vm_page_t m;
1814
1815 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1816 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1817 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1818
1819 /*
1820 * Allocate a page table page.
1821 */
1822 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1823 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1824 if (flags & M_WAITOK) {
1825 PMAP_UNLOCK(pmap);
1826 rw_wunlock(&pvh_global_lock);
1827 VM_WAIT;
1828 rw_wlock(&pvh_global_lock);
1829 PMAP_LOCK(pmap);
1830 }
1831
1832 /*
1833 * Indicate the need to retry. While waiting, the page table
1834 * page may have been allocated.
1835 */
1836 return (NULL);
1837 }
1838 if ((m->flags & PG_ZERO) == 0)
1839 pmap_zero_page(m);
1840
1841 /*
1842 * Map the pagetable page into the process address space, if
1843 * it isn't already there.
1844 */
1845
1846 pmap->pm_stats.resident_count++;
1847
1848 ptepa = VM_PAGE_TO_PHYS(m);
1849 pmap->pm_pdir[ptepindex] =
1850 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1851
1852 return (m);
1853 }
1854
1855 static vm_page_t
1856 pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags)
1857 {
1858 u_int ptepindex;
1859 pd_entry_t ptepa;
1860 vm_page_t m;
1861
1862 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1863 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1864 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1865
1866 /*
1867 * Calculate pagetable page index
1868 */
1869 ptepindex = va >> PDRSHIFT;
1870 retry:
1871 /*
1872 * Get the page directory entry
1873 */
1874 ptepa = pmap->pm_pdir[ptepindex];
1875
1876 /*
1877 * This supports switching from a 4MB page to a
1878 * normal 4K page.
1879 */
1880 if (ptepa & PG_PS) {
1881 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1882 ptepa = pmap->pm_pdir[ptepindex];
1883 }
1884
1885 /*
1886 * If the page table page is mapped, we just increment the
1887 * hold count, and activate it.
1888 */
1889 if (ptepa) {
1890 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1891 m->wire_count++;
1892 } else {
1893 /*
1894 * Here if the pte page isn't mapped, or if it has
1895 * been deallocated.
1896 */
1897 m = _pmap_allocpte(pmap, ptepindex, flags);
1898 if (m == NULL && (flags & M_WAITOK))
1899 goto retry;
1900 }
1901 return (m);
1902 }
1903
1904
1905 /***************************************************
1906 * Pmap allocation/deallocation routines.
1907 ***************************************************/
1908
1909 #ifdef SMP
1910 /*
1911 * Deal with a SMP shootdown of other users of the pmap that we are
1912 * trying to dispose of. This can be a bit hairy.
1913 */
1914 static cpuset_t *lazymask;
1915 static u_int lazyptd;
1916 static volatile u_int lazywait;
1917
1918 void pmap_lazyfix_action(void);
1919
1920 void
1921 pmap_lazyfix_action(void)
1922 {
1923
1924 #ifdef COUNT_IPIS
1925 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++;
1926 #endif
1927 if (rcr3() == lazyptd)
1928 load_cr3(curpcb->pcb_cr3);
1929 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask);
1930 atomic_store_rel_int(&lazywait, 1);
1931 }
1932
1933 static void
1934 pmap_lazyfix_self(u_int cpuid)
1935 {
1936
1937 if (rcr3() == lazyptd)
1938 load_cr3(curpcb->pcb_cr3);
1939 CPU_CLR_ATOMIC(cpuid, lazymask);
1940 }
1941
1942
1943 static void
1944 pmap_lazyfix(pmap_t pmap)
1945 {
1946 cpuset_t mymask, mask;
1947 u_int cpuid, spins;
1948 int lsb;
1949
1950 mask = pmap->pm_active;
1951 while (!CPU_EMPTY(&mask)) {
1952 spins = 50000000;
1953
1954 /* Find least significant set bit. */
1955 lsb = CPU_FFS(&mask);
1956 MPASS(lsb != 0);
1957 lsb--;
1958 CPU_SETOF(lsb, &mask);
1959 mtx_lock_spin(&smp_ipi_mtx);
1960 #ifdef PAE
1961 lazyptd = vtophys(pmap->pm_pdpt);
1962 #else
1963 lazyptd = vtophys(pmap->pm_pdir);
1964 #endif
1965 cpuid = PCPU_GET(cpuid);
1966
1967 /* Use a cpuset just for having an easy check. */
1968 CPU_SETOF(cpuid, &mymask);
1969 if (!CPU_CMP(&mask, &mymask)) {
1970 lazymask = &pmap->pm_active;
1971 pmap_lazyfix_self(cpuid);
1972 } else {
1973 atomic_store_rel_int((u_int *)&lazymask,
1974 (u_int)&pmap->pm_active);
1975 atomic_store_rel_int(&lazywait, 0);
1976 ipi_selected(mask, IPI_LAZYPMAP);
1977 while (lazywait == 0) {
1978 ia32_pause();
1979 if (--spins == 0)
1980 break;
1981 }
1982 }
1983 mtx_unlock_spin(&smp_ipi_mtx);
1984 if (spins == 0)
1985 printf("pmap_lazyfix: spun for 50000000\n");
1986 mask = pmap->pm_active;
1987 }
1988 }
1989
1990 #else /* SMP */
1991
1992 /*
1993 * Cleaning up on uniprocessor is easy. For various reasons, we're
1994 * unlikely to have to even execute this code, including the fact
1995 * that the cleanup is deferred until the parent does a wait(2), which
1996 * means that another userland process has run.
1997 */
1998 static void
1999 pmap_lazyfix(pmap_t pmap)
2000 {
2001 u_int cr3;
2002
2003 cr3 = vtophys(pmap->pm_pdir);
2004 if (cr3 == rcr3()) {
2005 load_cr3(curpcb->pcb_cr3);
2006 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active);
2007 }
2008 }
2009 #endif /* SMP */
2010
2011 /*
2012 * Release any resources held by the given physical map.
2013 * Called when a pmap initialized by pmap_pinit is being released.
2014 * Should only be called if the map contains no valid mappings.
2015 */
2016 void
2017 pmap_release(pmap_t pmap)
2018 {
2019 vm_page_t m, ptdpg[NPGPTD];
2020 int i;
2021
2022 KASSERT(pmap->pm_stats.resident_count == 0,
2023 ("pmap_release: pmap resident count %ld != 0",
2024 pmap->pm_stats.resident_count));
2025 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2026 ("pmap_release: pmap has reserved page table page(s)"));
2027
2028 pmap_lazyfix(pmap);
2029 mtx_lock_spin(&allpmaps_lock);
2030 LIST_REMOVE(pmap, pm_list);
2031 mtx_unlock_spin(&allpmaps_lock);
2032
2033 for (i = 0; i < NPGPTD; i++)
2034 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2035 PG_FRAME);
2036
2037 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2038 sizeof(*pmap->pm_pdir));
2039
2040 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2041
2042 for (i = 0; i < NPGPTD; i++) {
2043 m = ptdpg[i];
2044 #ifdef PAE
2045 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2046 ("pmap_release: got wrong ptd page"));
2047 #endif
2048 m->wire_count--;
2049 atomic_subtract_int(&cnt.v_wire_count, 1);
2050 vm_page_free_zero(m);
2051 }
2052 }
2053
2054 static int
2055 kvm_size(SYSCTL_HANDLER_ARGS)
2056 {
2057 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2058
2059 return (sysctl_handle_long(oidp, &ksize, 0, req));
2060 }
2061 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2062 0, 0, kvm_size, "IU", "Size of KVM");
2063
2064 static int
2065 kvm_free(SYSCTL_HANDLER_ARGS)
2066 {
2067 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2068
2069 return (sysctl_handle_long(oidp, &kfree, 0, req));
2070 }
2071 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2072 0, 0, kvm_free, "IU", "Amount of KVM free");
2073
2074 /*
2075 * grow the number of kernel page table entries, if needed
2076 */
2077 void
2078 pmap_growkernel(vm_offset_t addr)
2079 {
2080 vm_paddr_t ptppaddr;
2081 vm_page_t nkpg;
2082 pd_entry_t newpdir;
2083
2084 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2085 addr = roundup2(addr, NBPDR);
2086 if (addr - 1 >= kernel_map->max_offset)
2087 addr = kernel_map->max_offset;
2088 while (kernel_vm_end < addr) {
2089 if (pdir_pde(PTD, kernel_vm_end)) {
2090 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2091 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2092 kernel_vm_end = kernel_map->max_offset;
2093 break;
2094 }
2095 continue;
2096 }
2097
2098 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2099 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2100 VM_ALLOC_ZERO);
2101 if (nkpg == NULL)
2102 panic("pmap_growkernel: no memory to grow kernel");
2103
2104 nkpt++;
2105
2106 if ((nkpg->flags & PG_ZERO) == 0)
2107 pmap_zero_page(nkpg);
2108 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2109 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2110 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2111
2112 pmap_kenter_pde(kernel_vm_end, newpdir);
2113 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2114 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2115 kernel_vm_end = kernel_map->max_offset;
2116 break;
2117 }
2118 }
2119 }
2120
2121
2122 /***************************************************
2123 * page management routines.
2124 ***************************************************/
2125
2126 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2127 CTASSERT(_NPCM == 11);
2128 CTASSERT(_NPCPV == 336);
2129
2130 static __inline struct pv_chunk *
2131 pv_to_chunk(pv_entry_t pv)
2132 {
2133
2134 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2135 }
2136
2137 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2138
2139 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2140 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2141
2142 static const uint32_t pc_freemask[_NPCM] = {
2143 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2144 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2145 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2146 PC_FREE0_9, PC_FREE10
2147 };
2148
2149 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2150 "Current number of pv entries");
2151
2152 #ifdef PV_STATS
2153 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2154
2155 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2156 "Current number of pv entry chunks");
2157 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2158 "Current number of pv entry chunks allocated");
2159 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2160 "Current number of pv entry chunks frees");
2161 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2162 "Number of times tried to get a chunk page but failed.");
2163
2164 static long pv_entry_frees, pv_entry_allocs;
2165 static int pv_entry_spare;
2166
2167 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2168 "Current number of pv entry frees");
2169 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2170 "Current number of pv entry allocs");
2171 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2172 "Current number of spare pv entries");
2173 #endif
2174
2175 /*
2176 * We are in a serious low memory condition. Resort to
2177 * drastic measures to free some pages so we can allocate
2178 * another pv entry chunk.
2179 */
2180 static vm_page_t
2181 pmap_pv_reclaim(pmap_t locked_pmap)
2182 {
2183 struct pch newtail;
2184 struct pv_chunk *pc;
2185 struct md_page *pvh;
2186 pd_entry_t *pde;
2187 pmap_t pmap;
2188 pt_entry_t *pte, tpte;
2189 pv_entry_t pv;
2190 vm_offset_t va;
2191 vm_page_t m, m_pc;
2192 struct spglist free;
2193 uint32_t inuse;
2194 int bit, field, freed;
2195
2196 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2197 pmap = NULL;
2198 m_pc = NULL;
2199 SLIST_INIT(&free);
2200 TAILQ_INIT(&newtail);
2201 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2202 SLIST_EMPTY(&free))) {
2203 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2204 if (pmap != pc->pc_pmap) {
2205 if (pmap != NULL) {
2206 pmap_invalidate_all(pmap);
2207 if (pmap != locked_pmap)
2208 PMAP_UNLOCK(pmap);
2209 }
2210 pmap = pc->pc_pmap;
2211 /* Avoid deadlock and lock recursion. */
2212 if (pmap > locked_pmap)
2213 PMAP_LOCK(pmap);
2214 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2215 pmap = NULL;
2216 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2217 continue;
2218 }
2219 }
2220
2221 /*
2222 * Destroy every non-wired, 4 KB page mapping in the chunk.
2223 */
2224 freed = 0;
2225 for (field = 0; field < _NPCM; field++) {
2226 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2227 inuse != 0; inuse &= ~(1UL << bit)) {
2228 bit = bsfl(inuse);
2229 pv = &pc->pc_pventry[field * 32 + bit];
2230 va = pv->pv_va;
2231 pde = pmap_pde(pmap, va);
2232 if ((*pde & PG_PS) != 0)
2233 continue;
2234 pte = pmap_pte(pmap, va);
2235 tpte = *pte;
2236 if ((tpte & PG_W) == 0)
2237 tpte = pte_load_clear(pte);
2238 pmap_pte_release(pte);
2239 if ((tpte & PG_W) != 0)
2240 continue;
2241 KASSERT(tpte != 0,
2242 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2243 pmap, va));
2244 if ((tpte & PG_G) != 0)
2245 pmap_invalidate_page(pmap, va);
2246 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2247 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2248 vm_page_dirty(m);
2249 if ((tpte & PG_A) != 0)
2250 vm_page_aflag_set(m, PGA_REFERENCED);
2251 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2252 if (TAILQ_EMPTY(&m->md.pv_list) &&
2253 (m->flags & PG_FICTITIOUS) == 0) {
2254 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2255 if (TAILQ_EMPTY(&pvh->pv_list)) {
2256 vm_page_aflag_clear(m,
2257 PGA_WRITEABLE);
2258 }
2259 }
2260 pc->pc_map[field] |= 1UL << bit;
2261 pmap_unuse_pt(pmap, va, &free);
2262 freed++;
2263 }
2264 }
2265 if (freed == 0) {
2266 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2267 continue;
2268 }
2269 /* Every freed mapping is for a 4 KB page. */
2270 pmap->pm_stats.resident_count -= freed;
2271 PV_STAT(pv_entry_frees += freed);
2272 PV_STAT(pv_entry_spare += freed);
2273 pv_entry_count -= freed;
2274 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2275 for (field = 0; field < _NPCM; field++)
2276 if (pc->pc_map[field] != pc_freemask[field]) {
2277 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2278 pc_list);
2279 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2280
2281 /*
2282 * One freed pv entry in locked_pmap is
2283 * sufficient.
2284 */
2285 if (pmap == locked_pmap)
2286 goto out;
2287 break;
2288 }
2289 if (field == _NPCM) {
2290 PV_STAT(pv_entry_spare -= _NPCPV);
2291 PV_STAT(pc_chunk_count--);
2292 PV_STAT(pc_chunk_frees++);
2293 /* Entire chunk is free; return it. */
2294 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2295 pmap_qremove((vm_offset_t)pc, 1);
2296 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2297 break;
2298 }
2299 }
2300 out:
2301 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2302 if (pmap != NULL) {
2303 pmap_invalidate_all(pmap);
2304 if (pmap != locked_pmap)
2305 PMAP_UNLOCK(pmap);
2306 }
2307 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2308 m_pc = SLIST_FIRST(&free);
2309 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2310 /* Recycle a freed page table page. */
2311 m_pc->wire_count = 1;
2312 atomic_add_int(&cnt.v_wire_count, 1);
2313 }
2314 pmap_free_zero_pages(&free);
2315 return (m_pc);
2316 }
2317
2318 /*
2319 * free the pv_entry back to the free list
2320 */
2321 static void
2322 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2323 {
2324 struct pv_chunk *pc;
2325 int idx, field, bit;
2326
2327 rw_assert(&pvh_global_lock, RA_WLOCKED);
2328 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2329 PV_STAT(pv_entry_frees++);
2330 PV_STAT(pv_entry_spare++);
2331 pv_entry_count--;
2332 pc = pv_to_chunk(pv);
2333 idx = pv - &pc->pc_pventry[0];
2334 field = idx / 32;
2335 bit = idx % 32;
2336 pc->pc_map[field] |= 1ul << bit;
2337 for (idx = 0; idx < _NPCM; idx++)
2338 if (pc->pc_map[idx] != pc_freemask[idx]) {
2339 /*
2340 * 98% of the time, pc is already at the head of the
2341 * list. If it isn't already, move it to the head.
2342 */
2343 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2344 pc)) {
2345 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2346 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2347 pc_list);
2348 }
2349 return;
2350 }
2351 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2352 free_pv_chunk(pc);
2353 }
2354
2355 static void
2356 free_pv_chunk(struct pv_chunk *pc)
2357 {
2358 vm_page_t m;
2359
2360 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2361 PV_STAT(pv_entry_spare -= _NPCPV);
2362 PV_STAT(pc_chunk_count--);
2363 PV_STAT(pc_chunk_frees++);
2364 /* entire chunk is free, return it */
2365 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2366 pmap_qremove((vm_offset_t)pc, 1);
2367 vm_page_unwire(m, 0);
2368 vm_page_free(m);
2369 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2370 }
2371
2372 /*
2373 * get a new pv_entry, allocating a block from the system
2374 * when needed.
2375 */
2376 static pv_entry_t
2377 get_pv_entry(pmap_t pmap, boolean_t try)
2378 {
2379 static const struct timeval printinterval = { 60, 0 };
2380 static struct timeval lastprint;
2381 int bit, field;
2382 pv_entry_t pv;
2383 struct pv_chunk *pc;
2384 vm_page_t m;
2385
2386 rw_assert(&pvh_global_lock, RA_WLOCKED);
2387 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2388 PV_STAT(pv_entry_allocs++);
2389 pv_entry_count++;
2390 if (pv_entry_count > pv_entry_high_water)
2391 if (ratecheck(&lastprint, &printinterval))
2392 printf("Approaching the limit on PV entries, consider "
2393 "increasing either the vm.pmap.shpgperproc or the "
2394 "vm.pmap.pv_entry_max tunable.\n");
2395 retry:
2396 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2397 if (pc != NULL) {
2398 for (field = 0; field < _NPCM; field++) {
2399 if (pc->pc_map[field]) {
2400 bit = bsfl(pc->pc_map[field]);
2401 break;
2402 }
2403 }
2404 if (field < _NPCM) {
2405 pv = &pc->pc_pventry[field * 32 + bit];
2406 pc->pc_map[field] &= ~(1ul << bit);
2407 /* If this was the last item, move it to tail */
2408 for (field = 0; field < _NPCM; field++)
2409 if (pc->pc_map[field] != 0) {
2410 PV_STAT(pv_entry_spare--);
2411 return (pv); /* not full, return */
2412 }
2413 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2414 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2415 PV_STAT(pv_entry_spare--);
2416 return (pv);
2417 }
2418 }
2419 /*
2420 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2421 * global lock. If "pv_vafree" is currently non-empty, it will
2422 * remain non-empty until pmap_ptelist_alloc() completes.
2423 */
2424 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2425 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2426 if (try) {
2427 pv_entry_count--;
2428 PV_STAT(pc_chunk_tryfail++);
2429 return (NULL);
2430 }
2431 m = pmap_pv_reclaim(pmap);
2432 if (m == NULL)
2433 goto retry;
2434 }
2435 PV_STAT(pc_chunk_count++);
2436 PV_STAT(pc_chunk_allocs++);
2437 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2438 pmap_qenter((vm_offset_t)pc, &m, 1);
2439 pc->pc_pmap = pmap;
2440 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2441 for (field = 1; field < _NPCM; field++)
2442 pc->pc_map[field] = pc_freemask[field];
2443 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2444 pv = &pc->pc_pventry[0];
2445 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2446 PV_STAT(pv_entry_spare += _NPCPV - 1);
2447 return (pv);
2448 }
2449
2450 static __inline pv_entry_t
2451 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2452 {
2453 pv_entry_t pv;
2454
2455 rw_assert(&pvh_global_lock, RA_WLOCKED);
2456 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2457 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2458 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2459 break;
2460 }
2461 }
2462 return (pv);
2463 }
2464
2465 static void
2466 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2467 {
2468 struct md_page *pvh;
2469 pv_entry_t pv;
2470 vm_offset_t va_last;
2471 vm_page_t m;
2472
2473 rw_assert(&pvh_global_lock, RA_WLOCKED);
2474 KASSERT((pa & PDRMASK) == 0,
2475 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2476
2477 /*
2478 * Transfer the 4mpage's pv entry for this mapping to the first
2479 * page's pv list.
2480 */
2481 pvh = pa_to_pvh(pa);
2482 va = trunc_4mpage(va);
2483 pv = pmap_pvh_remove(pvh, pmap, va);
2484 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2485 m = PHYS_TO_VM_PAGE(pa);
2486 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2487 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2488 va_last = va + NBPDR - PAGE_SIZE;
2489 do {
2490 m++;
2491 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2492 ("pmap_pv_demote_pde: page %p is not managed", m));
2493 va += PAGE_SIZE;
2494 pmap_insert_entry(pmap, va, m);
2495 } while (va < va_last);
2496 }
2497
2498 static void
2499 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2500 {
2501 struct md_page *pvh;
2502 pv_entry_t pv;
2503 vm_offset_t va_last;
2504 vm_page_t m;
2505
2506 rw_assert(&pvh_global_lock, RA_WLOCKED);
2507 KASSERT((pa & PDRMASK) == 0,
2508 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2509
2510 /*
2511 * Transfer the first page's pv entry for this mapping to the
2512 * 4mpage's pv list. Aside from avoiding the cost of a call
2513 * to get_pv_entry(), a transfer avoids the possibility that
2514 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2515 * removes one of the mappings that is being promoted.
2516 */
2517 m = PHYS_TO_VM_PAGE(pa);
2518 va = trunc_4mpage(va);
2519 pv = pmap_pvh_remove(&m->md, pmap, va);
2520 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2521 pvh = pa_to_pvh(pa);
2522 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2523 /* Free the remaining NPTEPG - 1 pv entries. */
2524 va_last = va + NBPDR - PAGE_SIZE;
2525 do {
2526 m++;
2527 va += PAGE_SIZE;
2528 pmap_pvh_free(&m->md, pmap, va);
2529 } while (va < va_last);
2530 }
2531
2532 static void
2533 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2534 {
2535 pv_entry_t pv;
2536
2537 pv = pmap_pvh_remove(pvh, pmap, va);
2538 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2539 free_pv_entry(pmap, pv);
2540 }
2541
2542 static void
2543 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2544 {
2545 struct md_page *pvh;
2546
2547 rw_assert(&pvh_global_lock, RA_WLOCKED);
2548 pmap_pvh_free(&m->md, pmap, va);
2549 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2550 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2551 if (TAILQ_EMPTY(&pvh->pv_list))
2552 vm_page_aflag_clear(m, PGA_WRITEABLE);
2553 }
2554 }
2555
2556 /*
2557 * Create a pv entry for page at pa for
2558 * (pmap, va).
2559 */
2560 static void
2561 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2562 {
2563 pv_entry_t pv;
2564
2565 rw_assert(&pvh_global_lock, RA_WLOCKED);
2566 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2567 pv = get_pv_entry(pmap, FALSE);
2568 pv->pv_va = va;
2569 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2570 }
2571
2572 /*
2573 * Conditionally create a pv entry.
2574 */
2575 static boolean_t
2576 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2577 {
2578 pv_entry_t pv;
2579
2580 rw_assert(&pvh_global_lock, RA_WLOCKED);
2581 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2582 if (pv_entry_count < pv_entry_high_water &&
2583 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2584 pv->pv_va = va;
2585 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2586 return (TRUE);
2587 } else
2588 return (FALSE);
2589 }
2590
2591 /*
2592 * Create the pv entries for each of the pages within a superpage.
2593 */
2594 static boolean_t
2595 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2596 {
2597 struct md_page *pvh;
2598 pv_entry_t pv;
2599
2600 rw_assert(&pvh_global_lock, RA_WLOCKED);
2601 if (pv_entry_count < pv_entry_high_water &&
2602 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2603 pv->pv_va = va;
2604 pvh = pa_to_pvh(pa);
2605 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2606 return (TRUE);
2607 } else
2608 return (FALSE);
2609 }
2610
2611 /*
2612 * Fills a page table page with mappings to consecutive physical pages.
2613 */
2614 static void
2615 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2616 {
2617 pt_entry_t *pte;
2618
2619 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2620 *pte = newpte;
2621 newpte += PAGE_SIZE;
2622 }
2623 }
2624
2625 /*
2626 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2627 * 2- or 4MB page mapping is invalidated.
2628 */
2629 static boolean_t
2630 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2631 {
2632 pd_entry_t newpde, oldpde;
2633 pt_entry_t *firstpte, newpte;
2634 vm_paddr_t mptepa;
2635 vm_page_t mpte;
2636 struct spglist free;
2637
2638 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2639 oldpde = *pde;
2640 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2641 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2642 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
2643 NULL)
2644 pmap_remove_pt_page(pmap, mpte);
2645 else {
2646 KASSERT((oldpde & PG_W) == 0,
2647 ("pmap_demote_pde: page table page for a wired mapping"
2648 " is missing"));
2649
2650 /*
2651 * Invalidate the 2- or 4MB page mapping and return
2652 * "failure" if the mapping was never accessed or the
2653 * allocation of the new page table page fails.
2654 */
2655 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2656 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2657 VM_ALLOC_WIRED)) == NULL) {
2658 SLIST_INIT(&free);
2659 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free);
2660 pmap_invalidate_page(pmap, trunc_4mpage(va));
2661 pmap_free_zero_pages(&free);
2662 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2663 " in pmap %p", va, pmap);
2664 return (FALSE);
2665 }
2666 if (va < VM_MAXUSER_ADDRESS)
2667 pmap->pm_stats.resident_count++;
2668 }
2669 mptepa = VM_PAGE_TO_PHYS(mpte);
2670
2671 /*
2672 * If the page mapping is in the kernel's address space, then the
2673 * KPTmap can provide access to the page table page. Otherwise,
2674 * temporarily map the page table page (mpte) into the kernel's
2675 * address space at either PADDR1 or PADDR2.
2676 */
2677 if (va >= KERNBASE)
2678 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2679 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2680 if ((*PMAP1 & PG_FRAME) != mptepa) {
2681 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2682 #ifdef SMP
2683 PMAP1cpu = PCPU_GET(cpuid);
2684 #endif
2685 invlcaddr(PADDR1);
2686 PMAP1changed++;
2687 } else
2688 #ifdef SMP
2689 if (PMAP1cpu != PCPU_GET(cpuid)) {
2690 PMAP1cpu = PCPU_GET(cpuid);
2691 invlcaddr(PADDR1);
2692 PMAP1changedcpu++;
2693 } else
2694 #endif
2695 PMAP1unchanged++;
2696 firstpte = PADDR1;
2697 } else {
2698 mtx_lock(&PMAP2mutex);
2699 if ((*PMAP2 & PG_FRAME) != mptepa) {
2700 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2701 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2702 }
2703 firstpte = PADDR2;
2704 }
2705 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2706 KASSERT((oldpde & PG_A) != 0,
2707 ("pmap_demote_pde: oldpde is missing PG_A"));
2708 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2709 ("pmap_demote_pde: oldpde is missing PG_M"));
2710 newpte = oldpde & ~PG_PS;
2711 if ((newpte & PG_PDE_PAT) != 0)
2712 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2713
2714 /*
2715 * If the page table page is new, initialize it.
2716 */
2717 if (mpte->wire_count == 1) {
2718 mpte->wire_count = NPTEPG;
2719 pmap_fill_ptp(firstpte, newpte);
2720 }
2721 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2722 ("pmap_demote_pde: firstpte and newpte map different physical"
2723 " addresses"));
2724
2725 /*
2726 * If the mapping has changed attributes, update the page table
2727 * entries.
2728 */
2729 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2730 pmap_fill_ptp(firstpte, newpte);
2731
2732 /*
2733 * Demote the mapping. This pmap is locked. The old PDE has
2734 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2735 * set. Thus, there is no danger of a race with another
2736 * processor changing the setting of PG_A and/or PG_M between
2737 * the read above and the store below.
2738 */
2739 if (workaround_erratum383)
2740 pmap_update_pde(pmap, va, pde, newpde);
2741 else if (pmap == kernel_pmap)
2742 pmap_kenter_pde(va, newpde);
2743 else
2744 pde_store(pde, newpde);
2745 if (firstpte == PADDR2)
2746 mtx_unlock(&PMAP2mutex);
2747
2748 /*
2749 * Invalidate the recursive mapping of the page table page.
2750 */
2751 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2752
2753 /*
2754 * Demote the pv entry. This depends on the earlier demotion
2755 * of the mapping. Specifically, the (re)creation of a per-
2756 * page pv entry might trigger the execution of pmap_collect(),
2757 * which might reclaim a newly (re)created per-page pv entry
2758 * and destroy the associated mapping. In order to destroy
2759 * the mapping, the PDE must have already changed from mapping
2760 * the 2mpage to referencing the page table page.
2761 */
2762 if ((oldpde & PG_MANAGED) != 0)
2763 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2764
2765 pmap_pde_demotions++;
2766 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2767 " in pmap %p", va, pmap);
2768 return (TRUE);
2769 }
2770
2771 /*
2772 * Removes a 2- or 4MB page mapping from the kernel pmap.
2773 */
2774 static void
2775 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2776 {
2777 pd_entry_t newpde;
2778 vm_paddr_t mptepa;
2779 vm_page_t mpte;
2780
2781 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2782 mpte = pmap_lookup_pt_page(pmap, va);
2783 if (mpte == NULL)
2784 panic("pmap_remove_kernel_pde: Missing pt page.");
2785
2786 pmap_remove_pt_page(pmap, mpte);
2787 mptepa = VM_PAGE_TO_PHYS(mpte);
2788 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2789
2790 /*
2791 * Initialize the page table page.
2792 */
2793 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2794
2795 /*
2796 * Remove the mapping.
2797 */
2798 if (workaround_erratum383)
2799 pmap_update_pde(pmap, va, pde, newpde);
2800 else
2801 pmap_kenter_pde(va, newpde);
2802
2803 /*
2804 * Invalidate the recursive mapping of the page table page.
2805 */
2806 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2807 }
2808
2809 /*
2810 * pmap_remove_pde: do the things to unmap a superpage in a process
2811 */
2812 static void
2813 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2814 struct spglist *free)
2815 {
2816 struct md_page *pvh;
2817 pd_entry_t oldpde;
2818 vm_offset_t eva, va;
2819 vm_page_t m, mpte;
2820
2821 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2822 KASSERT((sva & PDRMASK) == 0,
2823 ("pmap_remove_pde: sva is not 4mpage aligned"));
2824 oldpde = pte_load_clear(pdq);
2825 if (oldpde & PG_W)
2826 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2827
2828 /*
2829 * Machines that don't support invlpg, also don't support
2830 * PG_G.
2831 */
2832 if (oldpde & PG_G)
2833 pmap_invalidate_page(kernel_pmap, sva);
2834 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2835 if (oldpde & PG_MANAGED) {
2836 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2837 pmap_pvh_free(pvh, pmap, sva);
2838 eva = sva + NBPDR;
2839 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2840 va < eva; va += PAGE_SIZE, m++) {
2841 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2842 vm_page_dirty(m);
2843 if (oldpde & PG_A)
2844 vm_page_aflag_set(m, PGA_REFERENCED);
2845 if (TAILQ_EMPTY(&m->md.pv_list) &&
2846 TAILQ_EMPTY(&pvh->pv_list))
2847 vm_page_aflag_clear(m, PGA_WRITEABLE);
2848 }
2849 }
2850 if (pmap == kernel_pmap) {
2851 pmap_remove_kernel_pde(pmap, pdq, sva);
2852 } else {
2853 mpte = pmap_lookup_pt_page(pmap, sva);
2854 if (mpte != NULL) {
2855 pmap_remove_pt_page(pmap, mpte);
2856 pmap->pm_stats.resident_count--;
2857 KASSERT(mpte->wire_count == NPTEPG,
2858 ("pmap_remove_pde: pte page wire count error"));
2859 mpte->wire_count = 0;
2860 pmap_add_delayed_free_list(mpte, free, FALSE);
2861 atomic_subtract_int(&cnt.v_wire_count, 1);
2862 }
2863 }
2864 }
2865
2866 /*
2867 * pmap_remove_pte: do the things to unmap a page in a process
2868 */
2869 static int
2870 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2871 struct spglist *free)
2872 {
2873 pt_entry_t oldpte;
2874 vm_page_t m;
2875
2876 rw_assert(&pvh_global_lock, RA_WLOCKED);
2877 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2878 oldpte = pte_load_clear(ptq);
2879 KASSERT(oldpte != 0,
2880 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2881 if (oldpte & PG_W)
2882 pmap->pm_stats.wired_count -= 1;
2883 /*
2884 * Machines that don't support invlpg, also don't support
2885 * PG_G.
2886 */
2887 if (oldpte & PG_G)
2888 pmap_invalidate_page(kernel_pmap, va);
2889 pmap->pm_stats.resident_count -= 1;
2890 if (oldpte & PG_MANAGED) {
2891 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2892 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2893 vm_page_dirty(m);
2894 if (oldpte & PG_A)
2895 vm_page_aflag_set(m, PGA_REFERENCED);
2896 pmap_remove_entry(pmap, m, va);
2897 }
2898 return (pmap_unuse_pt(pmap, va, free));
2899 }
2900
2901 /*
2902 * Remove a single page from a process address space
2903 */
2904 static void
2905 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2906 {
2907 pt_entry_t *pte;
2908
2909 rw_assert(&pvh_global_lock, RA_WLOCKED);
2910 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2911 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2912 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2913 return;
2914 pmap_remove_pte(pmap, pte, va, free);
2915 pmap_invalidate_page(pmap, va);
2916 }
2917
2918 /*
2919 * Remove the given range of addresses from the specified map.
2920 *
2921 * It is assumed that the start and end are properly
2922 * rounded to the page size.
2923 */
2924 void
2925 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2926 {
2927 vm_offset_t pdnxt;
2928 pd_entry_t ptpaddr;
2929 pt_entry_t *pte;
2930 struct spglist free;
2931 int anyvalid;
2932
2933 /*
2934 * Perform an unsynchronized read. This is, however, safe.
2935 */
2936 if (pmap->pm_stats.resident_count == 0)
2937 return;
2938
2939 anyvalid = 0;
2940 SLIST_INIT(&free);
2941
2942 rw_wlock(&pvh_global_lock);
2943 sched_pin();
2944 PMAP_LOCK(pmap);
2945
2946 /*
2947 * special handling of removing one page. a very
2948 * common operation and easy to short circuit some
2949 * code.
2950 */
2951 if ((sva + PAGE_SIZE == eva) &&
2952 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2953 pmap_remove_page(pmap, sva, &free);
2954 goto out;
2955 }
2956
2957 for (; sva < eva; sva = pdnxt) {
2958 u_int pdirindex;
2959
2960 /*
2961 * Calculate index for next page table.
2962 */
2963 pdnxt = (sva + NBPDR) & ~PDRMASK;
2964 if (pdnxt < sva)
2965 pdnxt = eva;
2966 if (pmap->pm_stats.resident_count == 0)
2967 break;
2968
2969 pdirindex = sva >> PDRSHIFT;
2970 ptpaddr = pmap->pm_pdir[pdirindex];
2971
2972 /*
2973 * Weed out invalid mappings. Note: we assume that the page
2974 * directory table is always allocated, and in kernel virtual.
2975 */
2976 if (ptpaddr == 0)
2977 continue;
2978
2979 /*
2980 * Check for large page.
2981 */
2982 if ((ptpaddr & PG_PS) != 0) {
2983 /*
2984 * Are we removing the entire large page? If not,
2985 * demote the mapping and fall through.
2986 */
2987 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2988 /*
2989 * The TLB entry for a PG_G mapping is
2990 * invalidated by pmap_remove_pde().
2991 */
2992 if ((ptpaddr & PG_G) == 0)
2993 anyvalid = 1;
2994 pmap_remove_pde(pmap,
2995 &pmap->pm_pdir[pdirindex], sva, &free);
2996 continue;
2997 } else if (!pmap_demote_pde(pmap,
2998 &pmap->pm_pdir[pdirindex], sva)) {
2999 /* The large page mapping was destroyed. */
3000 continue;
3001 }
3002 }
3003
3004 /*
3005 * Limit our scan to either the end of the va represented
3006 * by the current page table page, or to the end of the
3007 * range being removed.
3008 */
3009 if (pdnxt > eva)
3010 pdnxt = eva;
3011
3012 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3013 sva += PAGE_SIZE) {
3014 if (*pte == 0)
3015 continue;
3016
3017 /*
3018 * The TLB entry for a PG_G mapping is invalidated
3019 * by pmap_remove_pte().
3020 */
3021 if ((*pte & PG_G) == 0)
3022 anyvalid = 1;
3023 if (pmap_remove_pte(pmap, pte, sva, &free))
3024 break;
3025 }
3026 }
3027 out:
3028 sched_unpin();
3029 if (anyvalid)
3030 pmap_invalidate_all(pmap);
3031 rw_wunlock(&pvh_global_lock);
3032 PMAP_UNLOCK(pmap);
3033 pmap_free_zero_pages(&free);
3034 }
3035
3036 /*
3037 * Routine: pmap_remove_all
3038 * Function:
3039 * Removes this physical page from
3040 * all physical maps in which it resides.
3041 * Reflects back modify bits to the pager.
3042 *
3043 * Notes:
3044 * Original versions of this routine were very
3045 * inefficient because they iteratively called
3046 * pmap_remove (slow...)
3047 */
3048
3049 void
3050 pmap_remove_all(vm_page_t m)
3051 {
3052 struct md_page *pvh;
3053 pv_entry_t pv;
3054 pmap_t pmap;
3055 pt_entry_t *pte, tpte;
3056 pd_entry_t *pde;
3057 vm_offset_t va;
3058 struct spglist free;
3059
3060 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3061 ("pmap_remove_all: page %p is not managed", m));
3062 SLIST_INIT(&free);
3063 rw_wlock(&pvh_global_lock);
3064 sched_pin();
3065 if ((m->flags & PG_FICTITIOUS) != 0)
3066 goto small_mappings;
3067 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3068 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3069 va = pv->pv_va;
3070 pmap = PV_PMAP(pv);
3071 PMAP_LOCK(pmap);
3072 pde = pmap_pde(pmap, va);
3073 (void)pmap_demote_pde(pmap, pde, va);
3074 PMAP_UNLOCK(pmap);
3075 }
3076 small_mappings:
3077 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3078 pmap = PV_PMAP(pv);
3079 PMAP_LOCK(pmap);
3080 pmap->pm_stats.resident_count--;
3081 pde = pmap_pde(pmap, pv->pv_va);
3082 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3083 " a 4mpage in page %p's pv list", m));
3084 pte = pmap_pte_quick(pmap, pv->pv_va);
3085 tpte = pte_load_clear(pte);
3086 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3087 pmap, pv->pv_va));
3088 if (tpte & PG_W)
3089 pmap->pm_stats.wired_count--;
3090 if (tpte & PG_A)
3091 vm_page_aflag_set(m, PGA_REFERENCED);
3092
3093 /*
3094 * Update the vm_page_t clean and reference bits.
3095 */
3096 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3097 vm_page_dirty(m);
3098 pmap_unuse_pt(pmap, pv->pv_va, &free);
3099 pmap_invalidate_page(pmap, pv->pv_va);
3100 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3101 free_pv_entry(pmap, pv);
3102 PMAP_UNLOCK(pmap);
3103 }
3104 vm_page_aflag_clear(m, PGA_WRITEABLE);
3105 sched_unpin();
3106 rw_wunlock(&pvh_global_lock);
3107 pmap_free_zero_pages(&free);
3108 }
3109
3110 /*
3111 * pmap_protect_pde: do the things to protect a 4mpage in a process
3112 */
3113 static boolean_t
3114 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3115 {
3116 pd_entry_t newpde, oldpde;
3117 vm_offset_t eva, va;
3118 vm_page_t m;
3119 boolean_t anychanged;
3120
3121 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3122 KASSERT((sva & PDRMASK) == 0,
3123 ("pmap_protect_pde: sva is not 4mpage aligned"));
3124 anychanged = FALSE;
3125 retry:
3126 oldpde = newpde = *pde;
3127 if (oldpde & PG_MANAGED) {
3128 eva = sva + NBPDR;
3129 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3130 va < eva; va += PAGE_SIZE, m++)
3131 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3132 vm_page_dirty(m);
3133 }
3134 if ((prot & VM_PROT_WRITE) == 0)
3135 newpde &= ~(PG_RW | PG_M);
3136 #ifdef PAE
3137 if ((prot & VM_PROT_EXECUTE) == 0)
3138 newpde |= pg_nx;
3139 #endif
3140 if (newpde != oldpde) {
3141 if (!pde_cmpset(pde, oldpde, newpde))
3142 goto retry;
3143 if (oldpde & PG_G)
3144 pmap_invalidate_page(pmap, sva);
3145 else
3146 anychanged = TRUE;
3147 }
3148 return (anychanged);
3149 }
3150
3151 /*
3152 * Set the physical protection on the
3153 * specified range of this map as requested.
3154 */
3155 void
3156 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3157 {
3158 vm_offset_t pdnxt;
3159 pd_entry_t ptpaddr;
3160 pt_entry_t *pte;
3161 boolean_t anychanged, pv_lists_locked;
3162
3163 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
3164 pmap_remove(pmap, sva, eva);
3165 return;
3166 }
3167
3168 #ifdef PAE
3169 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3170 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3171 return;
3172 #else
3173 if (prot & VM_PROT_WRITE)
3174 return;
3175 #endif
3176
3177 if (pmap_is_current(pmap))
3178 pv_lists_locked = FALSE;
3179 else {
3180 pv_lists_locked = TRUE;
3181 resume:
3182 rw_wlock(&pvh_global_lock);
3183 sched_pin();
3184 }
3185 anychanged = FALSE;
3186
3187 PMAP_LOCK(pmap);
3188 for (; sva < eva; sva = pdnxt) {
3189 pt_entry_t obits, pbits;
3190 u_int pdirindex;
3191
3192 pdnxt = (sva + NBPDR) & ~PDRMASK;
3193 if (pdnxt < sva)
3194 pdnxt = eva;
3195
3196 pdirindex = sva >> PDRSHIFT;
3197 ptpaddr = pmap->pm_pdir[pdirindex];
3198
3199 /*
3200 * Weed out invalid mappings. Note: we assume that the page
3201 * directory table is always allocated, and in kernel virtual.
3202 */
3203 if (ptpaddr == 0)
3204 continue;
3205
3206 /*
3207 * Check for large page.
3208 */
3209 if ((ptpaddr & PG_PS) != 0) {
3210 /*
3211 * Are we protecting the entire large page? If not,
3212 * demote the mapping and fall through.
3213 */
3214 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3215 /*
3216 * The TLB entry for a PG_G mapping is
3217 * invalidated by pmap_protect_pde().
3218 */
3219 if (pmap_protect_pde(pmap,
3220 &pmap->pm_pdir[pdirindex], sva, prot))
3221 anychanged = TRUE;
3222 continue;
3223 } else {
3224 if (!pv_lists_locked) {
3225 pv_lists_locked = TRUE;
3226 if (!rw_try_wlock(&pvh_global_lock)) {
3227 if (anychanged)
3228 pmap_invalidate_all(
3229 pmap);
3230 PMAP_UNLOCK(pmap);
3231 goto resume;
3232 }
3233 sched_pin();
3234 }
3235 if (!pmap_demote_pde(pmap,
3236 &pmap->pm_pdir[pdirindex], sva)) {
3237 /*
3238 * The large page mapping was
3239 * destroyed.
3240 */
3241 continue;
3242 }
3243 }
3244 }
3245
3246 if (pdnxt > eva)
3247 pdnxt = eva;
3248
3249 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3250 sva += PAGE_SIZE) {
3251 vm_page_t m;
3252
3253 retry:
3254 /*
3255 * Regardless of whether a pte is 32 or 64 bits in
3256 * size, PG_RW, PG_A, and PG_M are among the least
3257 * significant 32 bits.
3258 */
3259 obits = pbits = *pte;
3260 if ((pbits & PG_V) == 0)
3261 continue;
3262
3263 if ((prot & VM_PROT_WRITE) == 0) {
3264 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3265 (PG_MANAGED | PG_M | PG_RW)) {
3266 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3267 vm_page_dirty(m);
3268 }
3269 pbits &= ~(PG_RW | PG_M);
3270 }
3271 #ifdef PAE
3272 if ((prot & VM_PROT_EXECUTE) == 0)
3273 pbits |= pg_nx;
3274 #endif
3275
3276 if (pbits != obits) {
3277 #ifdef PAE
3278 if (!atomic_cmpset_64(pte, obits, pbits))
3279 goto retry;
3280 #else
3281 if (!atomic_cmpset_int((u_int *)pte, obits,
3282 pbits))
3283 goto retry;
3284 #endif
3285 if (obits & PG_G)
3286 pmap_invalidate_page(pmap, sva);
3287 else
3288 anychanged = TRUE;
3289 }
3290 }
3291 }
3292 if (anychanged)
3293 pmap_invalidate_all(pmap);
3294 if (pv_lists_locked) {
3295 sched_unpin();
3296 rw_wunlock(&pvh_global_lock);
3297 }
3298 PMAP_UNLOCK(pmap);
3299 }
3300
3301 /*
3302 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3303 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3304 * For promotion to occur, two conditions must be met: (1) the 4KB page
3305 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3306 * mappings must have identical characteristics.
3307 *
3308 * Managed (PG_MANAGED) mappings within the kernel address space are not
3309 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3310 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3311 * pmap.
3312 */
3313 static void
3314 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3315 {
3316 pd_entry_t newpde;
3317 pt_entry_t *firstpte, oldpte, pa, *pte;
3318 vm_offset_t oldpteva;
3319 vm_page_t mpte;
3320
3321 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3322
3323 /*
3324 * Examine the first PTE in the specified PTP. Abort if this PTE is
3325 * either invalid, unused, or does not map the first 4KB physical page
3326 * within a 2- or 4MB page.
3327 */
3328 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3329 setpde:
3330 newpde = *firstpte;
3331 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3332 pmap_pde_p_failures++;
3333 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3334 " in pmap %p", va, pmap);
3335 return;
3336 }
3337 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3338 pmap_pde_p_failures++;
3339 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3340 " in pmap %p", va, pmap);
3341 return;
3342 }
3343 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3344 /*
3345 * When PG_M is already clear, PG_RW can be cleared without
3346 * a TLB invalidation.
3347 */
3348 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3349 ~PG_RW))
3350 goto setpde;
3351 newpde &= ~PG_RW;
3352 }
3353
3354 /*
3355 * Examine each of the other PTEs in the specified PTP. Abort if this
3356 * PTE maps an unexpected 4KB physical page or does not have identical
3357 * characteristics to the first PTE.
3358 */
3359 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3360 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3361 setpte:
3362 oldpte = *pte;
3363 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3364 pmap_pde_p_failures++;
3365 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3366 " in pmap %p", va, pmap);
3367 return;
3368 }
3369 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3370 /*
3371 * When PG_M is already clear, PG_RW can be cleared
3372 * without a TLB invalidation.
3373 */
3374 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3375 oldpte & ~PG_RW))
3376 goto setpte;
3377 oldpte &= ~PG_RW;
3378 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3379 (va & ~PDRMASK);
3380 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3381 " in pmap %p", oldpteva, pmap);
3382 }
3383 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3384 pmap_pde_p_failures++;
3385 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3386 " in pmap %p", va, pmap);
3387 return;
3388 }
3389 pa -= PAGE_SIZE;
3390 }
3391
3392 /*
3393 * Save the page table page in its current state until the PDE
3394 * mapping the superpage is demoted by pmap_demote_pde() or
3395 * destroyed by pmap_remove_pde().
3396 */
3397 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3398 KASSERT(mpte >= vm_page_array &&
3399 mpte < &vm_page_array[vm_page_array_size],
3400 ("pmap_promote_pde: page table page is out of range"));
3401 KASSERT(mpte->pindex == va >> PDRSHIFT,
3402 ("pmap_promote_pde: page table page's pindex is wrong"));
3403 if (pmap_insert_pt_page(pmap, mpte)) {
3404 pmap_pde_p_failures++;
3405 CTR2(KTR_PMAP,
3406 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3407 pmap);
3408 return;
3409 }
3410
3411 /*
3412 * Promote the pv entries.
3413 */
3414 if ((newpde & PG_MANAGED) != 0)
3415 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3416
3417 /*
3418 * Propagate the PAT index to its proper position.
3419 */
3420 if ((newpde & PG_PTE_PAT) != 0)
3421 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3422
3423 /*
3424 * Map the superpage.
3425 */
3426 if (workaround_erratum383)
3427 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3428 else if (pmap == kernel_pmap)
3429 pmap_kenter_pde(va, PG_PS | newpde);
3430 else
3431 pde_store(pde, PG_PS | newpde);
3432
3433 pmap_pde_promotions++;
3434 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3435 " in pmap %p", va, pmap);
3436 }
3437
3438 /*
3439 * Insert the given physical page (p) at
3440 * the specified virtual address (v) in the
3441 * target physical map with the protection requested.
3442 *
3443 * If specified, the page will be wired down, meaning
3444 * that the related pte can not be reclaimed.
3445 *
3446 * NB: This is the only routine which MAY NOT lazy-evaluate
3447 * or lose information. That is, this routine must actually
3448 * insert this page into the given map NOW.
3449 */
3450 void
3451 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3452 vm_prot_t prot, boolean_t wired)
3453 {
3454 pd_entry_t *pde;
3455 pt_entry_t *pte;
3456 pt_entry_t newpte, origpte;
3457 pv_entry_t pv;
3458 vm_paddr_t opa, pa;
3459 vm_page_t mpte, om;
3460 boolean_t invlva;
3461
3462 va = trunc_page(va);
3463 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3464 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3465 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3466 va));
3467 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3468 VM_OBJECT_ASSERT_WLOCKED(m->object);
3469
3470 mpte = NULL;
3471
3472 rw_wlock(&pvh_global_lock);
3473 PMAP_LOCK(pmap);
3474 sched_pin();
3475
3476 /*
3477 * In the case that a page table page is not
3478 * resident, we are creating it here.
3479 */
3480 if (va < VM_MAXUSER_ADDRESS) {
3481 mpte = pmap_allocpte(pmap, va, M_WAITOK);
3482 }
3483
3484 pde = pmap_pde(pmap, va);
3485 if ((*pde & PG_PS) != 0)
3486 panic("pmap_enter: attempted pmap_enter on 4MB page");
3487 pte = pmap_pte_quick(pmap, va);
3488
3489 /*
3490 * Page Directory table entry not valid, we need a new PT page
3491 */
3492 if (pte == NULL) {
3493 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3494 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3495 }
3496
3497 pa = VM_PAGE_TO_PHYS(m);
3498 om = NULL;
3499 origpte = *pte;
3500 opa = origpte & PG_FRAME;
3501
3502 /*
3503 * Mapping has not changed, must be protection or wiring change.
3504 */
3505 if (origpte && (opa == pa)) {
3506 /*
3507 * Wiring change, just update stats. We don't worry about
3508 * wiring PT pages as they remain resident as long as there
3509 * are valid mappings in them. Hence, if a user page is wired,
3510 * the PT page will be also.
3511 */
3512 if (wired && ((origpte & PG_W) == 0))
3513 pmap->pm_stats.wired_count++;
3514 else if (!wired && (origpte & PG_W))
3515 pmap->pm_stats.wired_count--;
3516
3517 /*
3518 * Remove extra pte reference
3519 */
3520 if (mpte)
3521 mpte->wire_count--;
3522
3523 if (origpte & PG_MANAGED) {
3524 om = m;
3525 pa |= PG_MANAGED;
3526 }
3527 goto validate;
3528 }
3529
3530 pv = NULL;
3531
3532 /*
3533 * Mapping has changed, invalidate old range and fall through to
3534 * handle validating new mapping.
3535 */
3536 if (opa) {
3537 if (origpte & PG_W)
3538 pmap->pm_stats.wired_count--;
3539 if (origpte & PG_MANAGED) {
3540 om = PHYS_TO_VM_PAGE(opa);
3541 pv = pmap_pvh_remove(&om->md, pmap, va);
3542 }
3543 if (mpte != NULL) {
3544 mpte->wire_count--;
3545 KASSERT(mpte->wire_count > 0,
3546 ("pmap_enter: missing reference to page table page,"
3547 " va: 0x%x", va));
3548 }
3549 } else
3550 pmap->pm_stats.resident_count++;
3551
3552 /*
3553 * Enter on the PV list if part of our managed memory.
3554 */
3555 if ((m->oflags & VPO_UNMANAGED) == 0) {
3556 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3557 ("pmap_enter: managed mapping within the clean submap"));
3558 if (pv == NULL)
3559 pv = get_pv_entry(pmap, FALSE);
3560 pv->pv_va = va;
3561 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3562 pa |= PG_MANAGED;
3563 } else if (pv != NULL)
3564 free_pv_entry(pmap, pv);
3565
3566 /*
3567 * Increment counters
3568 */
3569 if (wired)
3570 pmap->pm_stats.wired_count++;
3571
3572 validate:
3573 /*
3574 * Now validate mapping with desired protection/wiring.
3575 */
3576 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3577 if ((prot & VM_PROT_WRITE) != 0) {
3578 newpte |= PG_RW;
3579 if ((newpte & PG_MANAGED) != 0)
3580 vm_page_aflag_set(m, PGA_WRITEABLE);
3581 }
3582 #ifdef PAE
3583 if ((prot & VM_PROT_EXECUTE) == 0)
3584 newpte |= pg_nx;
3585 #endif
3586 if (wired)
3587 newpte |= PG_W;
3588 if (va < VM_MAXUSER_ADDRESS)
3589 newpte |= PG_U;
3590 if (pmap == kernel_pmap)
3591 newpte |= pgeflag;
3592
3593 /*
3594 * if the mapping or permission bits are different, we need
3595 * to update the pte.
3596 */
3597 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3598 newpte |= PG_A;
3599 if ((access & VM_PROT_WRITE) != 0)
3600 newpte |= PG_M;
3601 if (origpte & PG_V) {
3602 invlva = FALSE;
3603 origpte = pte_load_store(pte, newpte);
3604 if (origpte & PG_A) {
3605 if (origpte & PG_MANAGED)
3606 vm_page_aflag_set(om, PGA_REFERENCED);
3607 if (opa != VM_PAGE_TO_PHYS(m))
3608 invlva = TRUE;
3609 #ifdef PAE
3610 if ((origpte & PG_NX) == 0 &&
3611 (newpte & PG_NX) != 0)
3612 invlva = TRUE;
3613 #endif
3614 }
3615 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3616 if ((origpte & PG_MANAGED) != 0)
3617 vm_page_dirty(om);
3618 if ((prot & VM_PROT_WRITE) == 0)
3619 invlva = TRUE;
3620 }
3621 if ((origpte & PG_MANAGED) != 0 &&
3622 TAILQ_EMPTY(&om->md.pv_list) &&
3623 ((om->flags & PG_FICTITIOUS) != 0 ||
3624 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3625 vm_page_aflag_clear(om, PGA_WRITEABLE);
3626 if (invlva)
3627 pmap_invalidate_page(pmap, va);
3628 } else
3629 pte_store(pte, newpte);
3630 }
3631
3632 /*
3633 * If both the page table page and the reservation are fully
3634 * populated, then attempt promotion.
3635 */
3636 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3637 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3638 vm_reserv_level_iffullpop(m) == 0)
3639 pmap_promote_pde(pmap, pde, va);
3640
3641 sched_unpin();
3642 rw_wunlock(&pvh_global_lock);
3643 PMAP_UNLOCK(pmap);
3644 }
3645
3646 /*
3647 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3648 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3649 * blocking, (2) a mapping already exists at the specified virtual address, or
3650 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3651 */
3652 static boolean_t
3653 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3654 {
3655 pd_entry_t *pde, newpde;
3656
3657 rw_assert(&pvh_global_lock, RA_WLOCKED);
3658 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3659 pde = pmap_pde(pmap, va);
3660 if (*pde != 0) {
3661 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3662 " in pmap %p", va, pmap);
3663 return (FALSE);
3664 }
3665 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3666 PG_PS | PG_V;
3667 if ((m->oflags & VPO_UNMANAGED) == 0) {
3668 newpde |= PG_MANAGED;
3669
3670 /*
3671 * Abort this mapping if its PV entry could not be created.
3672 */
3673 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3674 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3675 " in pmap %p", va, pmap);
3676 return (FALSE);
3677 }
3678 }
3679 #ifdef PAE
3680 if ((prot & VM_PROT_EXECUTE) == 0)
3681 newpde |= pg_nx;
3682 #endif
3683 if (va < VM_MAXUSER_ADDRESS)
3684 newpde |= PG_U;
3685
3686 /*
3687 * Increment counters.
3688 */
3689 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3690
3691 /*
3692 * Map the superpage.
3693 */
3694 pde_store(pde, newpde);
3695
3696 pmap_pde_mappings++;
3697 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3698 " in pmap %p", va, pmap);
3699 return (TRUE);
3700 }
3701
3702 /*
3703 * Maps a sequence of resident pages belonging to the same object.
3704 * The sequence begins with the given page m_start. This page is
3705 * mapped at the given virtual address start. Each subsequent page is
3706 * mapped at a virtual address that is offset from start by the same
3707 * amount as the page is offset from m_start within the object. The
3708 * last page in the sequence is the page with the largest offset from
3709 * m_start that can be mapped at a virtual address less than the given
3710 * virtual address end. Not every virtual page between start and end
3711 * is mapped; only those for which a resident page exists with the
3712 * corresponding offset from m_start are mapped.
3713 */
3714 void
3715 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3716 vm_page_t m_start, vm_prot_t prot)
3717 {
3718 vm_offset_t va;
3719 vm_page_t m, mpte;
3720 vm_pindex_t diff, psize;
3721
3722 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3723
3724 psize = atop(end - start);
3725 mpte = NULL;
3726 m = m_start;
3727 rw_wlock(&pvh_global_lock);
3728 PMAP_LOCK(pmap);
3729 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3730 va = start + ptoa(diff);
3731 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3732 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 &&
3733 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 &&
3734 pmap_enter_pde(pmap, va, m, prot))
3735 m = &m[NBPDR / PAGE_SIZE - 1];
3736 else
3737 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3738 mpte);
3739 m = TAILQ_NEXT(m, listq);
3740 }
3741 rw_wunlock(&pvh_global_lock);
3742 PMAP_UNLOCK(pmap);
3743 }
3744
3745 /*
3746 * this code makes some *MAJOR* assumptions:
3747 * 1. Current pmap & pmap exists.
3748 * 2. Not wired.
3749 * 3. Read access.
3750 * 4. No page table pages.
3751 * but is *MUCH* faster than pmap_enter...
3752 */
3753
3754 void
3755 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3756 {
3757
3758 rw_wlock(&pvh_global_lock);
3759 PMAP_LOCK(pmap);
3760 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3761 rw_wunlock(&pvh_global_lock);
3762 PMAP_UNLOCK(pmap);
3763 }
3764
3765 static vm_page_t
3766 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3767 vm_prot_t prot, vm_page_t mpte)
3768 {
3769 pt_entry_t *pte;
3770 vm_paddr_t pa;
3771 struct spglist free;
3772
3773 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3774 (m->oflags & VPO_UNMANAGED) != 0,
3775 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3776 rw_assert(&pvh_global_lock, RA_WLOCKED);
3777 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3778
3779 /*
3780 * In the case that a page table page is not
3781 * resident, we are creating it here.
3782 */
3783 if (va < VM_MAXUSER_ADDRESS) {
3784 u_int ptepindex;
3785 pd_entry_t ptepa;
3786
3787 /*
3788 * Calculate pagetable page index
3789 */
3790 ptepindex = va >> PDRSHIFT;
3791 if (mpte && (mpte->pindex == ptepindex)) {
3792 mpte->wire_count++;
3793 } else {
3794 /*
3795 * Get the page directory entry
3796 */
3797 ptepa = pmap->pm_pdir[ptepindex];
3798
3799 /*
3800 * If the page table page is mapped, we just increment
3801 * the hold count, and activate it.
3802 */
3803 if (ptepa) {
3804 if (ptepa & PG_PS)
3805 return (NULL);
3806 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3807 mpte->wire_count++;
3808 } else {
3809 mpte = _pmap_allocpte(pmap, ptepindex,
3810 M_NOWAIT);
3811 if (mpte == NULL)
3812 return (mpte);
3813 }
3814 }
3815 } else {
3816 mpte = NULL;
3817 }
3818
3819 /*
3820 * This call to vtopte makes the assumption that we are
3821 * entering the page into the current pmap. In order to support
3822 * quick entry into any pmap, one would likely use pmap_pte_quick.
3823 * But that isn't as quick as vtopte.
3824 */
3825 pte = vtopte(va);
3826 if (*pte) {
3827 if (mpte != NULL) {
3828 mpte->wire_count--;
3829 mpte = NULL;
3830 }
3831 return (mpte);
3832 }
3833
3834 /*
3835 * Enter on the PV list if part of our managed memory.
3836 */
3837 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3838 !pmap_try_insert_pv_entry(pmap, va, m)) {
3839 if (mpte != NULL) {
3840 SLIST_INIT(&free);
3841 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3842 pmap_invalidate_page(pmap, va);
3843 pmap_free_zero_pages(&free);
3844 }
3845
3846 mpte = NULL;
3847 }
3848 return (mpte);
3849 }
3850
3851 /*
3852 * Increment counters
3853 */
3854 pmap->pm_stats.resident_count++;
3855
3856 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3857 #ifdef PAE
3858 if ((prot & VM_PROT_EXECUTE) == 0)
3859 pa |= pg_nx;
3860 #endif
3861
3862 /*
3863 * Now validate mapping with RO protection
3864 */
3865 if ((m->oflags & VPO_UNMANAGED) != 0)
3866 pte_store(pte, pa | PG_V | PG_U);
3867 else
3868 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3869 return (mpte);
3870 }
3871
3872 /*
3873 * Make a temporary mapping for a physical address. This is only intended
3874 * to be used for panic dumps.
3875 */
3876 void *
3877 pmap_kenter_temporary(vm_paddr_t pa, int i)
3878 {
3879 vm_offset_t va;
3880
3881 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3882 pmap_kenter(va, pa);
3883 invlpg(va);
3884 return ((void *)crashdumpmap);
3885 }
3886
3887 /*
3888 * This code maps large physical mmap regions into the
3889 * processor address space. Note that some shortcuts
3890 * are taken, but the code works.
3891 */
3892 void
3893 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3894 vm_pindex_t pindex, vm_size_t size)
3895 {
3896 pd_entry_t *pde;
3897 vm_paddr_t pa, ptepa;
3898 vm_page_t p;
3899 int pat_mode;
3900
3901 VM_OBJECT_ASSERT_WLOCKED(object);
3902 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3903 ("pmap_object_init_pt: non-device object"));
3904 if (pseflag &&
3905 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3906 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3907 return;
3908 p = vm_page_lookup(object, pindex);
3909 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3910 ("pmap_object_init_pt: invalid page %p", p));
3911 pat_mode = p->md.pat_mode;
3912
3913 /*
3914 * Abort the mapping if the first page is not physically
3915 * aligned to a 2/4MB page boundary.
3916 */
3917 ptepa = VM_PAGE_TO_PHYS(p);
3918 if (ptepa & (NBPDR - 1))
3919 return;
3920
3921 /*
3922 * Skip the first page. Abort the mapping if the rest of
3923 * the pages are not physically contiguous or have differing
3924 * memory attributes.
3925 */
3926 p = TAILQ_NEXT(p, listq);
3927 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3928 pa += PAGE_SIZE) {
3929 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3930 ("pmap_object_init_pt: invalid page %p", p));
3931 if (pa != VM_PAGE_TO_PHYS(p) ||
3932 pat_mode != p->md.pat_mode)
3933 return;
3934 p = TAILQ_NEXT(p, listq);
3935 }
3936
3937 /*
3938 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3939 * "size" is a multiple of 2/4M, adding the PAT setting to
3940 * "pa" will not affect the termination of this loop.
3941 */
3942 PMAP_LOCK(pmap);
3943 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3944 size; pa += NBPDR) {
3945 pde = pmap_pde(pmap, addr);
3946 if (*pde == 0) {
3947 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3948 PG_U | PG_RW | PG_V);
3949 pmap->pm_stats.resident_count += NBPDR /
3950 PAGE_SIZE;
3951 pmap_pde_mappings++;
3952 }
3953 /* Else continue on if the PDE is already valid. */
3954 addr += NBPDR;
3955 }
3956 PMAP_UNLOCK(pmap);
3957 }
3958 }
3959
3960 /*
3961 * Routine: pmap_change_wiring
3962 * Function: Change the wiring attribute for a map/virtual-address
3963 * pair.
3964 * In/out conditions:
3965 * The mapping must already exist in the pmap.
3966 */
3967 void
3968 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3969 {
3970 pd_entry_t *pde;
3971 pt_entry_t *pte;
3972 boolean_t are_queues_locked;
3973
3974 are_queues_locked = FALSE;
3975 retry:
3976 PMAP_LOCK(pmap);
3977 pde = pmap_pde(pmap, va);
3978 if ((*pde & PG_PS) != 0) {
3979 if (!wired != ((*pde & PG_W) == 0)) {
3980 if (!are_queues_locked) {
3981 are_queues_locked = TRUE;
3982 if (!rw_try_wlock(&pvh_global_lock)) {
3983 PMAP_UNLOCK(pmap);
3984 rw_wlock(&pvh_global_lock);
3985 goto retry;
3986 }
3987 }
3988 if (!pmap_demote_pde(pmap, pde, va))
3989 panic("pmap_change_wiring: demotion failed");
3990 } else
3991 goto out;
3992 }
3993 pte = pmap_pte(pmap, va);
3994
3995 if (wired && !pmap_pte_w(pte))
3996 pmap->pm_stats.wired_count++;
3997 else if (!wired && pmap_pte_w(pte))
3998 pmap->pm_stats.wired_count--;
3999
4000 /*
4001 * Wiring is not a hardware characteristic so there is no need to
4002 * invalidate TLB.
4003 */
4004 pmap_pte_set_w(pte, wired);
4005 pmap_pte_release(pte);
4006 out:
4007 if (are_queues_locked)
4008 rw_wunlock(&pvh_global_lock);
4009 PMAP_UNLOCK(pmap);
4010 }
4011
4012
4013
4014 /*
4015 * Copy the range specified by src_addr/len
4016 * from the source map to the range dst_addr/len
4017 * in the destination map.
4018 *
4019 * This routine is only advisory and need not do anything.
4020 */
4021
4022 void
4023 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4024 vm_offset_t src_addr)
4025 {
4026 struct spglist free;
4027 vm_offset_t addr;
4028 vm_offset_t end_addr = src_addr + len;
4029 vm_offset_t pdnxt;
4030
4031 if (dst_addr != src_addr)
4032 return;
4033
4034 if (!pmap_is_current(src_pmap))
4035 return;
4036
4037 rw_wlock(&pvh_global_lock);
4038 if (dst_pmap < src_pmap) {
4039 PMAP_LOCK(dst_pmap);
4040 PMAP_LOCK(src_pmap);
4041 } else {
4042 PMAP_LOCK(src_pmap);
4043 PMAP_LOCK(dst_pmap);
4044 }
4045 sched_pin();
4046 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4047 pt_entry_t *src_pte, *dst_pte;
4048 vm_page_t dstmpte, srcmpte;
4049 pd_entry_t srcptepaddr;
4050 u_int ptepindex;
4051
4052 KASSERT(addr < UPT_MIN_ADDRESS,
4053 ("pmap_copy: invalid to pmap_copy page tables"));
4054
4055 pdnxt = (addr + NBPDR) & ~PDRMASK;
4056 if (pdnxt < addr)
4057 pdnxt = end_addr;
4058 ptepindex = addr >> PDRSHIFT;
4059
4060 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4061 if (srcptepaddr == 0)
4062 continue;
4063
4064 if (srcptepaddr & PG_PS) {
4065 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4066 continue;
4067 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4068 ((srcptepaddr & PG_MANAGED) == 0 ||
4069 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4070 PG_PS_FRAME))) {
4071 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4072 ~PG_W;
4073 dst_pmap->pm_stats.resident_count +=
4074 NBPDR / PAGE_SIZE;
4075 }
4076 continue;
4077 }
4078
4079 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4080 KASSERT(srcmpte->wire_count > 0,
4081 ("pmap_copy: source page table page is unused"));
4082
4083 if (pdnxt > end_addr)
4084 pdnxt = end_addr;
4085
4086 src_pte = vtopte(addr);
4087 while (addr < pdnxt) {
4088 pt_entry_t ptetemp;
4089 ptetemp = *src_pte;
4090 /*
4091 * we only virtual copy managed pages
4092 */
4093 if ((ptetemp & PG_MANAGED) != 0) {
4094 dstmpte = pmap_allocpte(dst_pmap, addr,
4095 M_NOWAIT);
4096 if (dstmpte == NULL)
4097 goto out;
4098 dst_pte = pmap_pte_quick(dst_pmap, addr);
4099 if (*dst_pte == 0 &&
4100 pmap_try_insert_pv_entry(dst_pmap, addr,
4101 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4102 /*
4103 * Clear the wired, modified, and
4104 * accessed (referenced) bits
4105 * during the copy.
4106 */
4107 *dst_pte = ptetemp & ~(PG_W | PG_M |
4108 PG_A);
4109 dst_pmap->pm_stats.resident_count++;
4110 } else {
4111 SLIST_INIT(&free);
4112 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4113 &free)) {
4114 pmap_invalidate_page(dst_pmap,
4115 addr);
4116 pmap_free_zero_pages(&free);
4117 }
4118 goto out;
4119 }
4120 if (dstmpte->wire_count >= srcmpte->wire_count)
4121 break;
4122 }
4123 addr += PAGE_SIZE;
4124 src_pte++;
4125 }
4126 }
4127 out:
4128 sched_unpin();
4129 rw_wunlock(&pvh_global_lock);
4130 PMAP_UNLOCK(src_pmap);
4131 PMAP_UNLOCK(dst_pmap);
4132 }
4133
4134 static __inline void
4135 pagezero(void *page)
4136 {
4137 #if defined(I686_CPU)
4138 if (cpu_class == CPUCLASS_686) {
4139 #if defined(CPU_ENABLE_SSE)
4140 if (cpu_feature & CPUID_SSE2)
4141 sse2_pagezero(page);
4142 else
4143 #endif
4144 i686_pagezero(page);
4145 } else
4146 #endif
4147 bzero(page, PAGE_SIZE);
4148 }
4149
4150 /*
4151 * pmap_zero_page zeros the specified hardware page by mapping
4152 * the page into KVM and using bzero to clear its contents.
4153 */
4154 void
4155 pmap_zero_page(vm_page_t m)
4156 {
4157 struct sysmaps *sysmaps;
4158
4159 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4160 mtx_lock(&sysmaps->lock);
4161 if (*sysmaps->CMAP2)
4162 panic("pmap_zero_page: CMAP2 busy");
4163 sched_pin();
4164 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4165 pmap_cache_bits(m->md.pat_mode, 0);
4166 invlcaddr(sysmaps->CADDR2);
4167 pagezero(sysmaps->CADDR2);
4168 *sysmaps->CMAP2 = 0;
4169 sched_unpin();
4170 mtx_unlock(&sysmaps->lock);
4171 }
4172
4173 /*
4174 * pmap_zero_page_area zeros the specified hardware page by mapping
4175 * the page into KVM and using bzero to clear its contents.
4176 *
4177 * off and size may not cover an area beyond a single hardware page.
4178 */
4179 void
4180 pmap_zero_page_area(vm_page_t m, int off, int size)
4181 {
4182 struct sysmaps *sysmaps;
4183
4184 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4185 mtx_lock(&sysmaps->lock);
4186 if (*sysmaps->CMAP2)
4187 panic("pmap_zero_page_area: CMAP2 busy");
4188 sched_pin();
4189 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4190 pmap_cache_bits(m->md.pat_mode, 0);
4191 invlcaddr(sysmaps->CADDR2);
4192 if (off == 0 && size == PAGE_SIZE)
4193 pagezero(sysmaps->CADDR2);
4194 else
4195 bzero((char *)sysmaps->CADDR2 + off, size);
4196 *sysmaps->CMAP2 = 0;
4197 sched_unpin();
4198 mtx_unlock(&sysmaps->lock);
4199 }
4200
4201 /*
4202 * pmap_zero_page_idle zeros the specified hardware page by mapping
4203 * the page into KVM and using bzero to clear its contents. This
4204 * is intended to be called from the vm_pagezero process only and
4205 * outside of Giant.
4206 */
4207 void
4208 pmap_zero_page_idle(vm_page_t m)
4209 {
4210
4211 if (*CMAP3)
4212 panic("pmap_zero_page_idle: CMAP3 busy");
4213 sched_pin();
4214 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4215 pmap_cache_bits(m->md.pat_mode, 0);
4216 invlcaddr(CADDR3);
4217 pagezero(CADDR3);
4218 *CMAP3 = 0;
4219 sched_unpin();
4220 }
4221
4222 /*
4223 * pmap_copy_page copies the specified (machine independent)
4224 * page by mapping the page into virtual memory and using
4225 * bcopy to copy the page, one machine dependent page at a
4226 * time.
4227 */
4228 void
4229 pmap_copy_page(vm_page_t src, vm_page_t dst)
4230 {
4231 struct sysmaps *sysmaps;
4232
4233 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4234 mtx_lock(&sysmaps->lock);
4235 if (*sysmaps->CMAP1)
4236 panic("pmap_copy_page: CMAP1 busy");
4237 if (*sysmaps->CMAP2)
4238 panic("pmap_copy_page: CMAP2 busy");
4239 sched_pin();
4240 invlpg((u_int)sysmaps->CADDR1);
4241 invlpg((u_int)sysmaps->CADDR2);
4242 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4243 pmap_cache_bits(src->md.pat_mode, 0);
4244 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4245 pmap_cache_bits(dst->md.pat_mode, 0);
4246 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
4247 *sysmaps->CMAP1 = 0;
4248 *sysmaps->CMAP2 = 0;
4249 sched_unpin();
4250 mtx_unlock(&sysmaps->lock);
4251 }
4252
4253 int unmapped_buf_allowed = 1;
4254
4255 void
4256 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4257 vm_offset_t b_offset, int xfersize)
4258 {
4259 struct sysmaps *sysmaps;
4260 vm_page_t a_pg, b_pg;
4261 char *a_cp, *b_cp;
4262 vm_offset_t a_pg_offset, b_pg_offset;
4263 int cnt;
4264
4265 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4266 mtx_lock(&sysmaps->lock);
4267 if (*sysmaps->CMAP1 != 0)
4268 panic("pmap_copy_pages: CMAP1 busy");
4269 if (*sysmaps->CMAP2 != 0)
4270 panic("pmap_copy_pages: CMAP2 busy");
4271 sched_pin();
4272 while (xfersize > 0) {
4273 invlpg((u_int)sysmaps->CADDR1);
4274 invlpg((u_int)sysmaps->CADDR2);
4275 a_pg = ma[a_offset >> PAGE_SHIFT];
4276 a_pg_offset = a_offset & PAGE_MASK;
4277 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4278 b_pg = mb[b_offset >> PAGE_SHIFT];
4279 b_pg_offset = b_offset & PAGE_MASK;
4280 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4281 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4282 pmap_cache_bits(b_pg->md.pat_mode, 0);
4283 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4284 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4285 a_cp = sysmaps->CADDR1 + a_pg_offset;
4286 b_cp = sysmaps->CADDR2 + b_pg_offset;
4287 bcopy(a_cp, b_cp, cnt);
4288 a_offset += cnt;
4289 b_offset += cnt;
4290 xfersize -= cnt;
4291 }
4292 *sysmaps->CMAP1 = 0;
4293 *sysmaps->CMAP2 = 0;
4294 sched_unpin();
4295 mtx_unlock(&sysmaps->lock);
4296 }
4297
4298 /*
4299 * Returns true if the pmap's pv is one of the first
4300 * 16 pvs linked to from this page. This count may
4301 * be changed upwards or downwards in the future; it
4302 * is only necessary that true be returned for a small
4303 * subset of pmaps for proper page aging.
4304 */
4305 boolean_t
4306 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4307 {
4308 struct md_page *pvh;
4309 pv_entry_t pv;
4310 int loops = 0;
4311 boolean_t rv;
4312
4313 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4314 ("pmap_page_exists_quick: page %p is not managed", m));
4315 rv = FALSE;
4316 rw_wlock(&pvh_global_lock);
4317 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4318 if (PV_PMAP(pv) == pmap) {
4319 rv = TRUE;
4320 break;
4321 }
4322 loops++;
4323 if (loops >= 16)
4324 break;
4325 }
4326 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4327 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4328 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4329 if (PV_PMAP(pv) == pmap) {
4330 rv = TRUE;
4331 break;
4332 }
4333 loops++;
4334 if (loops >= 16)
4335 break;
4336 }
4337 }
4338 rw_wunlock(&pvh_global_lock);
4339 return (rv);
4340 }
4341
4342 /*
4343 * pmap_page_wired_mappings:
4344 *
4345 * Return the number of managed mappings to the given physical page
4346 * that are wired.
4347 */
4348 int
4349 pmap_page_wired_mappings(vm_page_t m)
4350 {
4351 int count;
4352
4353 count = 0;
4354 if ((m->oflags & VPO_UNMANAGED) != 0)
4355 return (count);
4356 rw_wlock(&pvh_global_lock);
4357 count = pmap_pvh_wired_mappings(&m->md, count);
4358 if ((m->flags & PG_FICTITIOUS) == 0) {
4359 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4360 count);
4361 }
4362 rw_wunlock(&pvh_global_lock);
4363 return (count);
4364 }
4365
4366 /*
4367 * pmap_pvh_wired_mappings:
4368 *
4369 * Return the updated number "count" of managed mappings that are wired.
4370 */
4371 static int
4372 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4373 {
4374 pmap_t pmap;
4375 pt_entry_t *pte;
4376 pv_entry_t pv;
4377
4378 rw_assert(&pvh_global_lock, RA_WLOCKED);
4379 sched_pin();
4380 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4381 pmap = PV_PMAP(pv);
4382 PMAP_LOCK(pmap);
4383 pte = pmap_pte_quick(pmap, pv->pv_va);
4384 if ((*pte & PG_W) != 0)
4385 count++;
4386 PMAP_UNLOCK(pmap);
4387 }
4388 sched_unpin();
4389 return (count);
4390 }
4391
4392 /*
4393 * Returns TRUE if the given page is mapped individually or as part of
4394 * a 4mpage. Otherwise, returns FALSE.
4395 */
4396 boolean_t
4397 pmap_page_is_mapped(vm_page_t m)
4398 {
4399 boolean_t rv;
4400
4401 if ((m->oflags & VPO_UNMANAGED) != 0)
4402 return (FALSE);
4403 rw_wlock(&pvh_global_lock);
4404 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4405 ((m->flags & PG_FICTITIOUS) == 0 &&
4406 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4407 rw_wunlock(&pvh_global_lock);
4408 return (rv);
4409 }
4410
4411 /*
4412 * Remove all pages from specified address space
4413 * this aids process exit speeds. Also, this code
4414 * is special cased for current process only, but
4415 * can have the more generic (and slightly slower)
4416 * mode enabled. This is much faster than pmap_remove
4417 * in the case of running down an entire address space.
4418 */
4419 void
4420 pmap_remove_pages(pmap_t pmap)
4421 {
4422 pt_entry_t *pte, tpte;
4423 vm_page_t m, mpte, mt;
4424 pv_entry_t pv;
4425 struct md_page *pvh;
4426 struct pv_chunk *pc, *npc;
4427 struct spglist free;
4428 int field, idx;
4429 int32_t bit;
4430 uint32_t inuse, bitmask;
4431 int allfree;
4432
4433 if (pmap != PCPU_GET(curpmap)) {
4434 printf("warning: pmap_remove_pages called with non-current pmap\n");
4435 return;
4436 }
4437 SLIST_INIT(&free);
4438 rw_wlock(&pvh_global_lock);
4439 PMAP_LOCK(pmap);
4440 sched_pin();
4441 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4442 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4443 pc->pc_pmap));
4444 allfree = 1;
4445 for (field = 0; field < _NPCM; field++) {
4446 inuse = ~pc->pc_map[field] & pc_freemask[field];
4447 while (inuse != 0) {
4448 bit = bsfl(inuse);
4449 bitmask = 1UL << bit;
4450 idx = field * 32 + bit;
4451 pv = &pc->pc_pventry[idx];
4452 inuse &= ~bitmask;
4453
4454 pte = pmap_pde(pmap, pv->pv_va);
4455 tpte = *pte;
4456 if ((tpte & PG_PS) == 0) {
4457 pte = vtopte(pv->pv_va);
4458 tpte = *pte & ~PG_PTE_PAT;
4459 }
4460
4461 if (tpte == 0) {
4462 printf(
4463 "TPTE at %p IS ZERO @ VA %08x\n",
4464 pte, pv->pv_va);
4465 panic("bad pte");
4466 }
4467
4468 /*
4469 * We cannot remove wired pages from a process' mapping at this time
4470 */
4471 if (tpte & PG_W) {
4472 allfree = 0;
4473 continue;
4474 }
4475
4476 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4477 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4478 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4479 m, (uintmax_t)m->phys_addr,
4480 (uintmax_t)tpte));
4481
4482 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4483 m < &vm_page_array[vm_page_array_size],
4484 ("pmap_remove_pages: bad tpte %#jx",
4485 (uintmax_t)tpte));
4486
4487 pte_clear(pte);
4488
4489 /*
4490 * Update the vm_page_t clean/reference bits.
4491 */
4492 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4493 if ((tpte & PG_PS) != 0) {
4494 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4495 vm_page_dirty(mt);
4496 } else
4497 vm_page_dirty(m);
4498 }
4499
4500 /* Mark free */
4501 PV_STAT(pv_entry_frees++);
4502 PV_STAT(pv_entry_spare++);
4503 pv_entry_count--;
4504 pc->pc_map[field] |= bitmask;
4505 if ((tpte & PG_PS) != 0) {
4506 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4507 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4508 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4509 if (TAILQ_EMPTY(&pvh->pv_list)) {
4510 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4511 if (TAILQ_EMPTY(&mt->md.pv_list))
4512 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4513 }
4514 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4515 if (mpte != NULL) {
4516 pmap_remove_pt_page(pmap, mpte);
4517 pmap->pm_stats.resident_count--;
4518 KASSERT(mpte->wire_count == NPTEPG,
4519 ("pmap_remove_pages: pte page wire count error"));
4520 mpte->wire_count = 0;
4521 pmap_add_delayed_free_list(mpte, &free, FALSE);
4522 atomic_subtract_int(&cnt.v_wire_count, 1);
4523 }
4524 } else {
4525 pmap->pm_stats.resident_count--;
4526 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4527 if (TAILQ_EMPTY(&m->md.pv_list) &&
4528 (m->flags & PG_FICTITIOUS) == 0) {
4529 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4530 if (TAILQ_EMPTY(&pvh->pv_list))
4531 vm_page_aflag_clear(m, PGA_WRITEABLE);
4532 }
4533 pmap_unuse_pt(pmap, pv->pv_va, &free);
4534 }
4535 }
4536 }
4537 if (allfree) {
4538 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4539 free_pv_chunk(pc);
4540 }
4541 }
4542 sched_unpin();
4543 pmap_invalidate_all(pmap);
4544 rw_wunlock(&pvh_global_lock);
4545 PMAP_UNLOCK(pmap);
4546 pmap_free_zero_pages(&free);
4547 }
4548
4549 /*
4550 * pmap_is_modified:
4551 *
4552 * Return whether or not the specified physical page was modified
4553 * in any physical maps.
4554 */
4555 boolean_t
4556 pmap_is_modified(vm_page_t m)
4557 {
4558 boolean_t rv;
4559
4560 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4561 ("pmap_is_modified: page %p is not managed", m));
4562
4563 /*
4564 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4565 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4566 * is clear, no PTEs can have PG_M set.
4567 */
4568 VM_OBJECT_ASSERT_WLOCKED(m->object);
4569 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4570 return (FALSE);
4571 rw_wlock(&pvh_global_lock);
4572 rv = pmap_is_modified_pvh(&m->md) ||
4573 ((m->flags & PG_FICTITIOUS) == 0 &&
4574 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4575 rw_wunlock(&pvh_global_lock);
4576 return (rv);
4577 }
4578
4579 /*
4580 * Returns TRUE if any of the given mappings were used to modify
4581 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4582 * mappings are supported.
4583 */
4584 static boolean_t
4585 pmap_is_modified_pvh(struct md_page *pvh)
4586 {
4587 pv_entry_t pv;
4588 pt_entry_t *pte;
4589 pmap_t pmap;
4590 boolean_t rv;
4591
4592 rw_assert(&pvh_global_lock, RA_WLOCKED);
4593 rv = FALSE;
4594 sched_pin();
4595 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4596 pmap = PV_PMAP(pv);
4597 PMAP_LOCK(pmap);
4598 pte = pmap_pte_quick(pmap, pv->pv_va);
4599 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4600 PMAP_UNLOCK(pmap);
4601 if (rv)
4602 break;
4603 }
4604 sched_unpin();
4605 return (rv);
4606 }
4607
4608 /*
4609 * pmap_is_prefaultable:
4610 *
4611 * Return whether or not the specified virtual address is elgible
4612 * for prefault.
4613 */
4614 boolean_t
4615 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4616 {
4617 pd_entry_t *pde;
4618 pt_entry_t *pte;
4619 boolean_t rv;
4620
4621 rv = FALSE;
4622 PMAP_LOCK(pmap);
4623 pde = pmap_pde(pmap, addr);
4624 if (*pde != 0 && (*pde & PG_PS) == 0) {
4625 pte = vtopte(addr);
4626 rv = *pte == 0;
4627 }
4628 PMAP_UNLOCK(pmap);
4629 return (rv);
4630 }
4631
4632 /*
4633 * pmap_is_referenced:
4634 *
4635 * Return whether or not the specified physical page was referenced
4636 * in any physical maps.
4637 */
4638 boolean_t
4639 pmap_is_referenced(vm_page_t m)
4640 {
4641 boolean_t rv;
4642
4643 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4644 ("pmap_is_referenced: page %p is not managed", m));
4645 rw_wlock(&pvh_global_lock);
4646 rv = pmap_is_referenced_pvh(&m->md) ||
4647 ((m->flags & PG_FICTITIOUS) == 0 &&
4648 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4649 rw_wunlock(&pvh_global_lock);
4650 return (rv);
4651 }
4652
4653 /*
4654 * Returns TRUE if any of the given mappings were referenced and FALSE
4655 * otherwise. Both page and 4mpage mappings are supported.
4656 */
4657 static boolean_t
4658 pmap_is_referenced_pvh(struct md_page *pvh)
4659 {
4660 pv_entry_t pv;
4661 pt_entry_t *pte;
4662 pmap_t pmap;
4663 boolean_t rv;
4664
4665 rw_assert(&pvh_global_lock, RA_WLOCKED);
4666 rv = FALSE;
4667 sched_pin();
4668 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4669 pmap = PV_PMAP(pv);
4670 PMAP_LOCK(pmap);
4671 pte = pmap_pte_quick(pmap, pv->pv_va);
4672 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4673 PMAP_UNLOCK(pmap);
4674 if (rv)
4675 break;
4676 }
4677 sched_unpin();
4678 return (rv);
4679 }
4680
4681 /*
4682 * Clear the write and modified bits in each of the given page's mappings.
4683 */
4684 void
4685 pmap_remove_write(vm_page_t m)
4686 {
4687 struct md_page *pvh;
4688 pv_entry_t next_pv, pv;
4689 pmap_t pmap;
4690 pd_entry_t *pde;
4691 pt_entry_t oldpte, *pte;
4692 vm_offset_t va;
4693
4694 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4695 ("pmap_remove_write: page %p is not managed", m));
4696
4697 /*
4698 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4699 * set by another thread while the object is locked. Thus,
4700 * if PGA_WRITEABLE is clear, no page table entries need updating.
4701 */
4702 VM_OBJECT_ASSERT_WLOCKED(m->object);
4703 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4704 return;
4705 rw_wlock(&pvh_global_lock);
4706 sched_pin();
4707 if ((m->flags & PG_FICTITIOUS) != 0)
4708 goto small_mappings;
4709 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4710 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4711 va = pv->pv_va;
4712 pmap = PV_PMAP(pv);
4713 PMAP_LOCK(pmap);
4714 pde = pmap_pde(pmap, va);
4715 if ((*pde & PG_RW) != 0)
4716 (void)pmap_demote_pde(pmap, pde, va);
4717 PMAP_UNLOCK(pmap);
4718 }
4719 small_mappings:
4720 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4721 pmap = PV_PMAP(pv);
4722 PMAP_LOCK(pmap);
4723 pde = pmap_pde(pmap, pv->pv_va);
4724 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4725 " a 4mpage in page %p's pv list", m));
4726 pte = pmap_pte_quick(pmap, pv->pv_va);
4727 retry:
4728 oldpte = *pte;
4729 if ((oldpte & PG_RW) != 0) {
4730 /*
4731 * Regardless of whether a pte is 32 or 64 bits
4732 * in size, PG_RW and PG_M are among the least
4733 * significant 32 bits.
4734 */
4735 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4736 oldpte & ~(PG_RW | PG_M)))
4737 goto retry;
4738 if ((oldpte & PG_M) != 0)
4739 vm_page_dirty(m);
4740 pmap_invalidate_page(pmap, pv->pv_va);
4741 }
4742 PMAP_UNLOCK(pmap);
4743 }
4744 vm_page_aflag_clear(m, PGA_WRITEABLE);
4745 sched_unpin();
4746 rw_wunlock(&pvh_global_lock);
4747 }
4748
4749 #define PMAP_TS_REFERENCED_MAX 5
4750
4751 /*
4752 * pmap_ts_referenced:
4753 *
4754 * Return a count of reference bits for a page, clearing those bits.
4755 * It is not necessary for every reference bit to be cleared, but it
4756 * is necessary that 0 only be returned when there are truly no
4757 * reference bits set.
4758 *
4759 * XXX: The exact number of bits to check and clear is a matter that
4760 * should be tested and standardized at some point in the future for
4761 * optimal aging of shared pages.
4762 */
4763 int
4764 pmap_ts_referenced(vm_page_t m)
4765 {
4766 struct md_page *pvh;
4767 pv_entry_t pv, pvf;
4768 pmap_t pmap;
4769 pd_entry_t *pde;
4770 pt_entry_t *pte;
4771 vm_paddr_t pa;
4772 int rtval = 0;
4773
4774 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4775 ("pmap_ts_referenced: page %p is not managed", m));
4776 pa = VM_PAGE_TO_PHYS(m);
4777 pvh = pa_to_pvh(pa);
4778 rw_wlock(&pvh_global_lock);
4779 sched_pin();
4780 if ((m->flags & PG_FICTITIOUS) != 0 ||
4781 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4782 goto small_mappings;
4783 pv = pvf;
4784 do {
4785 pmap = PV_PMAP(pv);
4786 PMAP_LOCK(pmap);
4787 pde = pmap_pde(pmap, pv->pv_va);
4788 if ((*pde & PG_A) != 0) {
4789 /*
4790 * Since this reference bit is shared by either 1024
4791 * or 512 4KB pages, it should not be cleared every
4792 * time it is tested. Apply a simple "hash" function
4793 * on the physical page number, the virtual superpage
4794 * number, and the pmap address to select one 4KB page
4795 * out of the 1024 or 512 on which testing the
4796 * reference bit will result in clearing that bit.
4797 * This function is designed to avoid the selection of
4798 * the same 4KB page for every 2- or 4MB page mapping.
4799 *
4800 * On demotion, a mapping that hasn't been referenced
4801 * is simply destroyed. To avoid the possibility of a
4802 * subsequent page fault on a demoted wired mapping,
4803 * always leave its reference bit set. Moreover,
4804 * since the superpage is wired, the current state of
4805 * its reference bit won't affect page replacement.
4806 */
4807 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4808 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4809 (*pde & PG_W) == 0) {
4810 atomic_clear_int((u_int *)pde, PG_A);
4811 pmap_invalidate_page(pmap, pv->pv_va);
4812 }
4813 rtval++;
4814 }
4815 PMAP_UNLOCK(pmap);
4816 /* Rotate the PV list if it has more than one entry. */
4817 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4818 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4819 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4820 }
4821 if (rtval >= PMAP_TS_REFERENCED_MAX)
4822 goto out;
4823 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4824 small_mappings:
4825 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4826 goto out;
4827 pv = pvf;
4828 do {
4829 pmap = PV_PMAP(pv);
4830 PMAP_LOCK(pmap);
4831 pde = pmap_pde(pmap, pv->pv_va);
4832 KASSERT((*pde & PG_PS) == 0,
4833 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4834 m));
4835 pte = pmap_pte_quick(pmap, pv->pv_va);
4836 if ((*pte & PG_A) != 0) {
4837 atomic_clear_int((u_int *)pte, PG_A);
4838 pmap_invalidate_page(pmap, pv->pv_va);
4839 rtval++;
4840 }
4841 PMAP_UNLOCK(pmap);
4842 /* Rotate the PV list if it has more than one entry. */
4843 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4844 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4845 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4846 }
4847 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4848 PMAP_TS_REFERENCED_MAX);
4849 out:
4850 sched_unpin();
4851 rw_wunlock(&pvh_global_lock);
4852 return (rtval);
4853 }
4854
4855 /*
4856 * Apply the given advice to the specified range of addresses within the
4857 * given pmap. Depending on the advice, clear the referenced and/or
4858 * modified flags in each mapping and set the mapped page's dirty field.
4859 */
4860 void
4861 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4862 {
4863 pd_entry_t oldpde, *pde;
4864 pt_entry_t *pte;
4865 vm_offset_t pdnxt;
4866 vm_page_t m;
4867 boolean_t anychanged, pv_lists_locked;
4868
4869 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4870 return;
4871 if (pmap_is_current(pmap))
4872 pv_lists_locked = FALSE;
4873 else {
4874 pv_lists_locked = TRUE;
4875 resume:
4876 rw_wlock(&pvh_global_lock);
4877 sched_pin();
4878 }
4879 anychanged = FALSE;
4880 PMAP_LOCK(pmap);
4881 for (; sva < eva; sva = pdnxt) {
4882 pdnxt = (sva + NBPDR) & ~PDRMASK;
4883 if (pdnxt < sva)
4884 pdnxt = eva;
4885 pde = pmap_pde(pmap, sva);
4886 oldpde = *pde;
4887 if ((oldpde & PG_V) == 0)
4888 continue;
4889 else if ((oldpde & PG_PS) != 0) {
4890 if ((oldpde & PG_MANAGED) == 0)
4891 continue;
4892 if (!pv_lists_locked) {
4893 pv_lists_locked = TRUE;
4894 if (!rw_try_wlock(&pvh_global_lock)) {
4895 if (anychanged)
4896 pmap_invalidate_all(pmap);
4897 PMAP_UNLOCK(pmap);
4898 goto resume;
4899 }
4900 sched_pin();
4901 }
4902 if (!pmap_demote_pde(pmap, pde, sva)) {
4903 /*
4904 * The large page mapping was destroyed.
4905 */
4906 continue;
4907 }
4908
4909 /*
4910 * Unless the page mappings are wired, remove the
4911 * mapping to a single page so that a subsequent
4912 * access may repromote. Since the underlying page
4913 * table page is fully populated, this removal never
4914 * frees a page table page.
4915 */
4916 if ((oldpde & PG_W) == 0) {
4917 pte = pmap_pte_quick(pmap, sva);
4918 KASSERT((*pte & PG_V) != 0,
4919 ("pmap_advise: invalid PTE"));
4920 pmap_remove_pte(pmap, pte, sva, NULL);
4921 anychanged = TRUE;
4922 }
4923 }
4924 if (pdnxt > eva)
4925 pdnxt = eva;
4926 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4927 sva += PAGE_SIZE) {
4928 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
4929 PG_V))
4930 continue;
4931 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4932 if (advice == MADV_DONTNEED) {
4933 /*
4934 * Future calls to pmap_is_modified()
4935 * can be avoided by making the page
4936 * dirty now.
4937 */
4938 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4939 vm_page_dirty(m);
4940 }
4941 atomic_clear_int((u_int *)pte, PG_M | PG_A);
4942 } else if ((*pte & PG_A) != 0)
4943 atomic_clear_int((u_int *)pte, PG_A);
4944 else
4945 continue;
4946 if ((*pte & PG_G) != 0)
4947 pmap_invalidate_page(pmap, sva);
4948 else
4949 anychanged = TRUE;
4950 }
4951 }
4952 if (anychanged)
4953 pmap_invalidate_all(pmap);
4954 if (pv_lists_locked) {
4955 sched_unpin();
4956 rw_wunlock(&pvh_global_lock);
4957 }
4958 PMAP_UNLOCK(pmap);
4959 }
4960
4961 /*
4962 * Clear the modify bits on the specified physical page.
4963 */
4964 void
4965 pmap_clear_modify(vm_page_t m)
4966 {
4967 struct md_page *pvh;
4968 pv_entry_t next_pv, pv;
4969 pmap_t pmap;
4970 pd_entry_t oldpde, *pde;
4971 pt_entry_t oldpte, *pte;
4972 vm_offset_t va;
4973
4974 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4975 ("pmap_clear_modify: page %p is not managed", m));
4976 VM_OBJECT_ASSERT_WLOCKED(m->object);
4977 KASSERT(!vm_page_xbusied(m),
4978 ("pmap_clear_modify: page %p is exclusive busied", m));
4979
4980 /*
4981 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
4982 * If the object containing the page is locked and the page is not
4983 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
4984 */
4985 if ((m->aflags & PGA_WRITEABLE) == 0)
4986 return;
4987 rw_wlock(&pvh_global_lock);
4988 sched_pin();
4989 if ((m->flags & PG_FICTITIOUS) != 0)
4990 goto small_mappings;
4991 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4992 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4993 va = pv->pv_va;
4994 pmap = PV_PMAP(pv);
4995 PMAP_LOCK(pmap);
4996 pde = pmap_pde(pmap, va);
4997 oldpde = *pde;
4998 if ((oldpde & PG_RW) != 0) {
4999 if (pmap_demote_pde(pmap, pde, va)) {
5000 if ((oldpde & PG_W) == 0) {
5001 /*
5002 * Write protect the mapping to a
5003 * single page so that a subsequent
5004 * write access may repromote.
5005 */
5006 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5007 PG_PS_FRAME);
5008 pte = pmap_pte_quick(pmap, va);
5009 oldpte = *pte;
5010 if ((oldpte & PG_V) != 0) {
5011 /*
5012 * Regardless of whether a pte is 32 or 64 bits
5013 * in size, PG_RW and PG_M are among the least
5014 * significant 32 bits.
5015 */
5016 while (!atomic_cmpset_int((u_int *)pte,
5017 oldpte,
5018 oldpte & ~(PG_M | PG_RW)))
5019 oldpte = *pte;
5020 vm_page_dirty(m);
5021 pmap_invalidate_page(pmap, va);
5022 }
5023 }
5024 }
5025 }
5026 PMAP_UNLOCK(pmap);
5027 }
5028 small_mappings:
5029 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5030 pmap = PV_PMAP(pv);
5031 PMAP_LOCK(pmap);
5032 pde = pmap_pde(pmap, pv->pv_va);
5033 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5034 " a 4mpage in page %p's pv list", m));
5035 pte = pmap_pte_quick(pmap, pv->pv_va);
5036 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5037 /*
5038 * Regardless of whether a pte is 32 or 64 bits
5039 * in size, PG_M is among the least significant
5040 * 32 bits.
5041 */
5042 atomic_clear_int((u_int *)pte, PG_M);
5043 pmap_invalidate_page(pmap, pv->pv_va);
5044 }
5045 PMAP_UNLOCK(pmap);
5046 }
5047 sched_unpin();
5048 rw_wunlock(&pvh_global_lock);
5049 }
5050
5051 /*
5052 * Miscellaneous support routines follow
5053 */
5054
5055 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5056 static __inline void
5057 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5058 {
5059 u_int opte, npte;
5060
5061 /*
5062 * The cache mode bits are all in the low 32-bits of the
5063 * PTE, so we can just spin on updating the low 32-bits.
5064 */
5065 do {
5066 opte = *(u_int *)pte;
5067 npte = opte & ~PG_PTE_CACHE;
5068 npte |= cache_bits;
5069 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5070 }
5071
5072 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5073 static __inline void
5074 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5075 {
5076 u_int opde, npde;
5077
5078 /*
5079 * The cache mode bits are all in the low 32-bits of the
5080 * PDE, so we can just spin on updating the low 32-bits.
5081 */
5082 do {
5083 opde = *(u_int *)pde;
5084 npde = opde & ~PG_PDE_CACHE;
5085 npde |= cache_bits;
5086 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5087 }
5088
5089 /*
5090 * Map a set of physical memory pages into the kernel virtual
5091 * address space. Return a pointer to where it is mapped. This
5092 * routine is intended to be used for mapping device memory,
5093 * NOT real memory.
5094 */
5095 void *
5096 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5097 {
5098 vm_offset_t va, offset;
5099 vm_size_t tmpsize;
5100
5101 offset = pa & PAGE_MASK;
5102 size = round_page(offset + size);
5103 pa = pa & PG_FRAME;
5104
5105 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5106 va = KERNBASE + pa;
5107 else
5108 va = kva_alloc(size);
5109 if (!va)
5110 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
5111
5112 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5113 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5114 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5115 pmap_invalidate_cache_range(va, va + size);
5116 return ((void *)(va + offset));
5117 }
5118
5119 void *
5120 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5121 {
5122
5123 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5124 }
5125
5126 void *
5127 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5128 {
5129
5130 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5131 }
5132
5133 void
5134 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5135 {
5136 vm_offset_t base, offset;
5137
5138 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5139 return;
5140 base = trunc_page(va);
5141 offset = va & PAGE_MASK;
5142 size = round_page(offset + size);
5143 kva_free(base, size);
5144 }
5145
5146 /*
5147 * Sets the memory attribute for the specified page.
5148 */
5149 void
5150 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5151 {
5152
5153 m->md.pat_mode = ma;
5154 if ((m->flags & PG_FICTITIOUS) != 0)
5155 return;
5156
5157 /*
5158 * If "m" is a normal page, flush it from the cache.
5159 * See pmap_invalidate_cache_range().
5160 *
5161 * First, try to find an existing mapping of the page by sf
5162 * buffer. sf_buf_invalidate_cache() modifies mapping and
5163 * flushes the cache.
5164 */
5165 if (sf_buf_invalidate_cache(m))
5166 return;
5167
5168 /*
5169 * If page is not mapped by sf buffer, but CPU does not
5170 * support self snoop, map the page transient and do
5171 * invalidation. In the worst case, whole cache is flushed by
5172 * pmap_invalidate_cache_range().
5173 */
5174 if ((cpu_feature & CPUID_SS) == 0)
5175 pmap_flush_page(m);
5176 }
5177
5178 static void
5179 pmap_flush_page(vm_page_t m)
5180 {
5181 struct sysmaps *sysmaps;
5182 vm_offset_t sva, eva;
5183
5184 if ((cpu_feature & CPUID_CLFSH) != 0) {
5185 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5186 mtx_lock(&sysmaps->lock);
5187 if (*sysmaps->CMAP2)
5188 panic("pmap_flush_page: CMAP2 busy");
5189 sched_pin();
5190 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5191 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5192 invlcaddr(sysmaps->CADDR2);
5193 sva = (vm_offset_t)sysmaps->CADDR2;
5194 eva = sva + PAGE_SIZE;
5195
5196 /*
5197 * Use mfence despite the ordering implied by
5198 * mtx_{un,}lock() because clflush is not guaranteed
5199 * to be ordered by any other instruction.
5200 */
5201 mfence();
5202 for (; sva < eva; sva += cpu_clflush_line_size)
5203 clflush(sva);
5204 mfence();
5205 *sysmaps->CMAP2 = 0;
5206 sched_unpin();
5207 mtx_unlock(&sysmaps->lock);
5208 } else
5209 pmap_invalidate_cache();
5210 }
5211
5212 /*
5213 * Changes the specified virtual address range's memory type to that given by
5214 * the parameter "mode". The specified virtual address range must be
5215 * completely contained within either the kernel map.
5216 *
5217 * Returns zero if the change completed successfully, and either EINVAL or
5218 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5219 * of the virtual address range was not mapped, and ENOMEM is returned if
5220 * there was insufficient memory available to complete the change.
5221 */
5222 int
5223 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5224 {
5225 vm_offset_t base, offset, tmpva;
5226 pd_entry_t *pde;
5227 pt_entry_t *pte;
5228 int cache_bits_pte, cache_bits_pde;
5229 boolean_t changed;
5230
5231 base = trunc_page(va);
5232 offset = va & PAGE_MASK;
5233 size = round_page(offset + size);
5234
5235 /*
5236 * Only supported on kernel virtual addresses above the recursive map.
5237 */
5238 if (base < VM_MIN_KERNEL_ADDRESS)
5239 return (EINVAL);
5240
5241 cache_bits_pde = pmap_cache_bits(mode, 1);
5242 cache_bits_pte = pmap_cache_bits(mode, 0);
5243 changed = FALSE;
5244
5245 /*
5246 * Pages that aren't mapped aren't supported. Also break down
5247 * 2/4MB pages into 4KB pages if required.
5248 */
5249 PMAP_LOCK(kernel_pmap);
5250 for (tmpva = base; tmpva < base + size; ) {
5251 pde = pmap_pde(kernel_pmap, tmpva);
5252 if (*pde == 0) {
5253 PMAP_UNLOCK(kernel_pmap);
5254 return (EINVAL);
5255 }
5256 if (*pde & PG_PS) {
5257 /*
5258 * If the current 2/4MB page already has
5259 * the required memory type, then we need not
5260 * demote this page. Just increment tmpva to
5261 * the next 2/4MB page frame.
5262 */
5263 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5264 tmpva = trunc_4mpage(tmpva) + NBPDR;
5265 continue;
5266 }
5267
5268 /*
5269 * If the current offset aligns with a 2/4MB
5270 * page frame and there is at least 2/4MB left
5271 * within the range, then we need not break
5272 * down this page into 4KB pages.
5273 */
5274 if ((tmpva & PDRMASK) == 0 &&
5275 tmpva + PDRMASK < base + size) {
5276 tmpva += NBPDR;
5277 continue;
5278 }
5279 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5280 PMAP_UNLOCK(kernel_pmap);
5281 return (ENOMEM);
5282 }
5283 }
5284 pte = vtopte(tmpva);
5285 if (*pte == 0) {
5286 PMAP_UNLOCK(kernel_pmap);
5287 return (EINVAL);
5288 }
5289 tmpva += PAGE_SIZE;
5290 }
5291 PMAP_UNLOCK(kernel_pmap);
5292
5293 /*
5294 * Ok, all the pages exist, so run through them updating their
5295 * cache mode if required.
5296 */
5297 for (tmpva = base; tmpva < base + size; ) {
5298 pde = pmap_pde(kernel_pmap, tmpva);
5299 if (*pde & PG_PS) {
5300 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5301 pmap_pde_attr(pde, cache_bits_pde);
5302 changed = TRUE;
5303 }
5304 tmpva = trunc_4mpage(tmpva) + NBPDR;
5305 } else {
5306 pte = vtopte(tmpva);
5307 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5308 pmap_pte_attr(pte, cache_bits_pte);
5309 changed = TRUE;
5310 }
5311 tmpva += PAGE_SIZE;
5312 }
5313 }
5314
5315 /*
5316 * Flush CPU caches to make sure any data isn't cached that
5317 * shouldn't be, etc.
5318 */
5319 if (changed) {
5320 pmap_invalidate_range(kernel_pmap, base, tmpva);
5321 pmap_invalidate_cache_range(base, tmpva);
5322 }
5323 return (0);
5324 }
5325
5326 /*
5327 * perform the pmap work for mincore
5328 */
5329 int
5330 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5331 {
5332 pd_entry_t *pdep;
5333 pt_entry_t *ptep, pte;
5334 vm_paddr_t pa;
5335 int val;
5336
5337 PMAP_LOCK(pmap);
5338 retry:
5339 pdep = pmap_pde(pmap, addr);
5340 if (*pdep != 0) {
5341 if (*pdep & PG_PS) {
5342 pte = *pdep;
5343 /* Compute the physical address of the 4KB page. */
5344 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5345 PG_FRAME;
5346 val = MINCORE_SUPER;
5347 } else {
5348 ptep = pmap_pte(pmap, addr);
5349 pte = *ptep;
5350 pmap_pte_release(ptep);
5351 pa = pte & PG_FRAME;
5352 val = 0;
5353 }
5354 } else {
5355 pte = 0;
5356 pa = 0;
5357 val = 0;
5358 }
5359 if ((pte & PG_V) != 0) {
5360 val |= MINCORE_INCORE;
5361 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5362 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5363 if ((pte & PG_A) != 0)
5364 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5365 }
5366 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5367 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5368 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5369 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5370 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5371 goto retry;
5372 } else
5373 PA_UNLOCK_COND(*locked_pa);
5374 PMAP_UNLOCK(pmap);
5375 return (val);
5376 }
5377
5378 void
5379 pmap_activate(struct thread *td)
5380 {
5381 pmap_t pmap, oldpmap;
5382 u_int cpuid;
5383 u_int32_t cr3;
5384
5385 critical_enter();
5386 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5387 oldpmap = PCPU_GET(curpmap);
5388 cpuid = PCPU_GET(cpuid);
5389 #if defined(SMP)
5390 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5391 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5392 #else
5393 CPU_CLR(cpuid, &oldpmap->pm_active);
5394 CPU_SET(cpuid, &pmap->pm_active);
5395 #endif
5396 #ifdef PAE
5397 cr3 = vtophys(pmap->pm_pdpt);
5398 #else
5399 cr3 = vtophys(pmap->pm_pdir);
5400 #endif
5401 /*
5402 * pmap_activate is for the current thread on the current cpu
5403 */
5404 td->td_pcb->pcb_cr3 = cr3;
5405 load_cr3(cr3);
5406 PCPU_SET(curpmap, pmap);
5407 critical_exit();
5408 }
5409
5410 void
5411 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5412 {
5413 }
5414
5415 /*
5416 * Increase the starting virtual address of the given mapping if a
5417 * different alignment might result in more superpage mappings.
5418 */
5419 void
5420 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5421 vm_offset_t *addr, vm_size_t size)
5422 {
5423 vm_offset_t superpage_offset;
5424
5425 if (size < NBPDR)
5426 return;
5427 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5428 offset += ptoa(object->pg_color);
5429 superpage_offset = offset & PDRMASK;
5430 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5431 (*addr & PDRMASK) == superpage_offset)
5432 return;
5433 if ((*addr & PDRMASK) < superpage_offset)
5434 *addr = (*addr & ~PDRMASK) + superpage_offset;
5435 else
5436 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5437 }
5438
5439
5440 #if defined(PMAP_DEBUG)
5441 pmap_pid_dump(int pid)
5442 {
5443 pmap_t pmap;
5444 struct proc *p;
5445 int npte = 0;
5446 int index;
5447
5448 sx_slock(&allproc_lock);
5449 FOREACH_PROC_IN_SYSTEM(p) {
5450 if (p->p_pid != pid)
5451 continue;
5452
5453 if (p->p_vmspace) {
5454 int i,j;
5455 index = 0;
5456 pmap = vmspace_pmap(p->p_vmspace);
5457 for (i = 0; i < NPDEPTD; i++) {
5458 pd_entry_t *pde;
5459 pt_entry_t *pte;
5460 vm_offset_t base = i << PDRSHIFT;
5461
5462 pde = &pmap->pm_pdir[i];
5463 if (pde && pmap_pde_v(pde)) {
5464 for (j = 0; j < NPTEPG; j++) {
5465 vm_offset_t va = base + (j << PAGE_SHIFT);
5466 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5467 if (index) {
5468 index = 0;
5469 printf("\n");
5470 }
5471 sx_sunlock(&allproc_lock);
5472 return (npte);
5473 }
5474 pte = pmap_pte(pmap, va);
5475 if (pte && pmap_pte_v(pte)) {
5476 pt_entry_t pa;
5477 vm_page_t m;
5478 pa = *pte;
5479 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5480 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5481 va, pa, m->hold_count, m->wire_count, m->flags);
5482 npte++;
5483 index++;
5484 if (index >= 2) {
5485 index = 0;
5486 printf("\n");
5487 } else {
5488 printf(" ");
5489 }
5490 }
5491 }
5492 }
5493 }
5494 }
5495 }
5496 sx_sunlock(&allproc_lock);
5497 return (npte);
5498 }
5499 #endif
5500
5501 #if defined(DEBUG)
5502
5503 static void pads(pmap_t pm);
5504 void pmap_pvdump(vm_paddr_t pa);
5505
5506 /* print address space of pmap*/
5507 static void
5508 pads(pmap_t pm)
5509 {
5510 int i, j;
5511 vm_paddr_t va;
5512 pt_entry_t *ptep;
5513
5514 if (pm == kernel_pmap)
5515 return;
5516 for (i = 0; i < NPDEPTD; i++)
5517 if (pm->pm_pdir[i])
5518 for (j = 0; j < NPTEPG; j++) {
5519 va = (i << PDRSHIFT) + (j << PAGE_SHIFT);
5520 if (pm == kernel_pmap && va < KERNBASE)
5521 continue;
5522 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS)
5523 continue;
5524 ptep = pmap_pte(pm, va);
5525 if (pmap_pte_v(ptep))
5526 printf("%x:%x ", va, *ptep);
5527 };
5528
5529 }
5530
5531 void
5532 pmap_pvdump(vm_paddr_t pa)
5533 {
5534 pv_entry_t pv;
5535 pmap_t pmap;
5536 vm_page_t m;
5537
5538 printf("pa %x", pa);
5539 m = PHYS_TO_VM_PAGE(pa);
5540 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5541 pmap = PV_PMAP(pv);
5542 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va);
5543 pads(pmap);
5544 }
5545 printf(" ");
5546 }
5547 #endif
Cache object: 84e03259e8402ffb2f9d07b7a695ba48
|