FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/pmap.c
1 /*-
2 * Copyright (c) 1991 Regents of the University of California.
3 * All rights reserved.
4 * Copyright (c) 1994 John S. Dyson
5 * All rights reserved.
6 * Copyright (c) 1994 David Greenman
7 * All rights reserved.
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
9 * All rights reserved.
10 *
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * SUCH DAMAGE.
42 *
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
44 */
45 /*-
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
48 *
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
54 *
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
57 * are met:
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
63 *
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 * SUCH DAMAGE.
75 */
76
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD: releng/11.0/sys/i386/i386/pmap.c 297974 2016-04-14 17:04:06Z pfg $");
79
80 /*
81 * Manages physical address maps.
82 *
83 * Since the information managed by this module is
84 * also stored by the logical address mapping module,
85 * this module may throw away valid virtual-to-physical
86 * mappings at almost any time. However, invalidations
87 * of virtual-to-physical mappings must be done as
88 * requested.
89 *
90 * In order to cope with hardware architectures which
91 * make virtual-to-physical map invalidates expensive,
92 * this module may delay invalidate or reduced protection
93 * operations until such time as they are actually
94 * necessary. This module is given full information as
95 * to which processors are currently using which maps,
96 * and to when physical maps must be made correct.
97 */
98
99 #include "opt_apic.h"
100 #include "opt_cpu.h"
101 #include "opt_pmap.h"
102 #include "opt_smp.h"
103 #include "opt_xbox.h"
104
105 #include <sys/param.h>
106 #include <sys/systm.h>
107 #include <sys/kernel.h>
108 #include <sys/ktr.h>
109 #include <sys/lock.h>
110 #include <sys/malloc.h>
111 #include <sys/mman.h>
112 #include <sys/msgbuf.h>
113 #include <sys/mutex.h>
114 #include <sys/proc.h>
115 #include <sys/rwlock.h>
116 #include <sys/sf_buf.h>
117 #include <sys/sx.h>
118 #include <sys/vmmeter.h>
119 #include <sys/sched.h>
120 #include <sys/sysctl.h>
121 #include <sys/smp.h>
122
123 #include <vm/vm.h>
124 #include <vm/vm_param.h>
125 #include <vm/vm_kern.h>
126 #include <vm/vm_page.h>
127 #include <vm/vm_map.h>
128 #include <vm/vm_object.h>
129 #include <vm/vm_extern.h>
130 #include <vm/vm_pageout.h>
131 #include <vm/vm_pager.h>
132 #include <vm/vm_phys.h>
133 #include <vm/vm_radix.h>
134 #include <vm/vm_reserv.h>
135 #include <vm/uma.h>
136
137 #ifdef DEV_APIC
138 #include <sys/bus.h>
139 #include <machine/intr_machdep.h>
140 #include <x86/apicvar.h>
141 #endif
142 #include <machine/cpu.h>
143 #include <machine/cputypes.h>
144 #include <machine/md_var.h>
145 #include <machine/pcb.h>
146 #include <machine/specialreg.h>
147 #ifdef SMP
148 #include <machine/smp.h>
149 #endif
150
151 #ifdef XBOX
152 #include <machine/xbox.h>
153 #endif
154
155 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
156 #define CPU_ENABLE_SSE
157 #endif
158
159 #ifndef PMAP_SHPGPERPROC
160 #define PMAP_SHPGPERPROC 200
161 #endif
162
163 #if !defined(DIAGNOSTIC)
164 #ifdef __GNUC_GNU_INLINE__
165 #define PMAP_INLINE __attribute__((__gnu_inline__)) inline
166 #else
167 #define PMAP_INLINE extern inline
168 #endif
169 #else
170 #define PMAP_INLINE
171 #endif
172
173 #ifdef PV_STATS
174 #define PV_STAT(x) do { x ; } while (0)
175 #else
176 #define PV_STAT(x) do { } while (0)
177 #endif
178
179 #define pa_index(pa) ((pa) >> PDRSHIFT)
180 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
181
182 /*
183 * Get PDEs and PTEs for user/kernel address space
184 */
185 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
186 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
187
188 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
189 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
190 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
191 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
192 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
193
194 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
195 atomic_clear_int((u_int *)(pte), PG_W))
196 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
197
198 struct pmap kernel_pmap_store;
199 LIST_HEAD(pmaplist, pmap);
200 static struct pmaplist allpmaps;
201 static struct mtx allpmaps_lock;
202
203 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
204 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
205 int pgeflag = 0; /* PG_G or-in */
206 int pseflag = 0; /* PG_PS or-in */
207
208 static int nkpt = NKPT;
209 vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR;
210 extern u_int32_t KERNend;
211 extern u_int32_t KPTphys;
212
213 #if defined(PAE) || defined(PAE_TABLES)
214 pt_entry_t pg_nx;
215 static uma_zone_t pdptzone;
216 #endif
217
218 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
219
220 static int pat_works = 1;
221 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
222 "Is page attribute table fully functional?");
223
224 static int pg_ps_enabled = 1;
225 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN | CTLFLAG_NOFETCH,
226 &pg_ps_enabled, 0, "Are large page mappings enabled?");
227
228 #define PAT_INDEX_SIZE 8
229 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
230
231 /*
232 * pmap_mapdev support pre initialization (i.e. console)
233 */
234 #define PMAP_PREINIT_MAPPING_COUNT 8
235 static struct pmap_preinit_mapping {
236 vm_paddr_t pa;
237 vm_offset_t va;
238 vm_size_t sz;
239 int mode;
240 } pmap_preinit_mapping[PMAP_PREINIT_MAPPING_COUNT];
241 static int pmap_initialized;
242
243 static struct rwlock_padalign pvh_global_lock;
244
245 /*
246 * Data for the pv entry allocation mechanism
247 */
248 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
249 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
250 static struct md_page *pv_table;
251 static int shpgperproc = PMAP_SHPGPERPROC;
252
253 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
254 int pv_maxchunks; /* How many chunks we have KVA for */
255 vm_offset_t pv_vafree; /* freelist stored in the PTE */
256
257 /*
258 * All those kernel PT submaps that BSD is so fond of
259 */
260 struct sysmaps {
261 struct mtx lock;
262 pt_entry_t *CMAP1;
263 pt_entry_t *CMAP2;
264 caddr_t CADDR1;
265 caddr_t CADDR2;
266 };
267 static struct sysmaps sysmaps_pcpu[MAXCPU];
268 pt_entry_t *CMAP3;
269 static pd_entry_t *KPTD;
270 caddr_t ptvmmap = 0;
271 caddr_t CADDR3;
272 struct msgbuf *msgbufp = NULL;
273
274 /*
275 * Crashdump maps.
276 */
277 static caddr_t crashdumpmap;
278
279 static pt_entry_t *PMAP1 = NULL, *PMAP2;
280 static pt_entry_t *PADDR1 = NULL, *PADDR2;
281 #ifdef SMP
282 static int PMAP1cpu;
283 static int PMAP1changedcpu;
284 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
285 &PMAP1changedcpu, 0,
286 "Number of times pmap_pte_quick changed CPU with same PMAP1");
287 #endif
288 static int PMAP1changed;
289 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
290 &PMAP1changed, 0,
291 "Number of times pmap_pte_quick changed PMAP1");
292 static int PMAP1unchanged;
293 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
294 &PMAP1unchanged, 0,
295 "Number of times pmap_pte_quick didn't change PMAP1");
296 static struct mtx PMAP2mutex;
297
298 static void free_pv_chunk(struct pv_chunk *pc);
299 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
300 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
301 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
302 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
303 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
304 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
305 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
306 vm_offset_t va);
307 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
308
309 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
310 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
311 vm_prot_t prot);
312 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
313 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
314 static void pmap_flush_page(vm_page_t m);
315 static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
316 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
317 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
318 static boolean_t pmap_is_referenced_pvh(struct md_page *pvh);
319 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
320 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
321 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
322 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
323 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
324 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
325 vm_prot_t prot);
326 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
327 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
328 struct spglist *free);
329 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
330 struct spglist *free);
331 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
332 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
333 struct spglist *free);
334 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
335 vm_offset_t va);
336 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
337 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
338 vm_page_t m);
339 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
340 pd_entry_t newpde);
341 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
342
343 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
344
345 static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags);
346 static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free);
347 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
348 static void pmap_pte_release(pt_entry_t *pte);
349 static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *);
350 #if defined(PAE) || defined(PAE_TABLES)
351 static void *pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags,
352 int wait);
353 #endif
354 static void pmap_set_pg(void);
355
356 static __inline void pagezero(void *page);
357
358 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
359 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
360
361 /*
362 * If you get an error here, then you set KVA_PAGES wrong! See the
363 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
364 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
365 */
366 CTASSERT(KERNBASE % (1 << 24) == 0);
367
368 /*
369 * Bootstrap the system enough to run with virtual memory.
370 *
371 * On the i386 this is called after mapping has already been enabled
372 * and just syncs the pmap module with what has already been done.
373 * [We can't call it easily with mapping off since the kernel is not
374 * mapped with PA == VA, hence we would have to relocate every address
375 * from the linked base (virtual) address "KERNBASE" to the actual
376 * (physical) address starting relative to 0]
377 */
378 void
379 pmap_bootstrap(vm_paddr_t firstaddr)
380 {
381 vm_offset_t va;
382 pt_entry_t *pte, *unused;
383 struct sysmaps *sysmaps;
384 int i;
385
386 /*
387 * Add a physical memory segment (vm_phys_seg) corresponding to the
388 * preallocated kernel page table pages so that vm_page structures
389 * representing these pages will be created. The vm_page structures
390 * are required for promotion of the corresponding kernel virtual
391 * addresses to superpage mappings.
392 */
393 vm_phys_add_seg(KPTphys, KPTphys + ptoa(nkpt));
394
395 /*
396 * Initialize the first available kernel virtual address. However,
397 * using "firstaddr" may waste a few pages of the kernel virtual
398 * address space, because locore may not have mapped every physical
399 * page that it allocated. Preferably, locore would provide a first
400 * unused virtual address in addition to "firstaddr".
401 */
402 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
403
404 virtual_end = VM_MAX_KERNEL_ADDRESS;
405
406 /*
407 * Initialize the kernel pmap (which is statically allocated).
408 */
409 PMAP_LOCK_INIT(kernel_pmap);
410 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
411 #if defined(PAE) || defined(PAE_TABLES)
412 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
413 #endif
414 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */
415 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
416
417 /*
418 * Initialize the global pv list lock.
419 */
420 rw_init(&pvh_global_lock, "pmap pv global");
421
422 LIST_INIT(&allpmaps);
423
424 /*
425 * Request a spin mutex so that changes to allpmaps cannot be
426 * preempted by smp_rendezvous_cpus(). Otherwise,
427 * pmap_update_pde_kernel() could access allpmaps while it is
428 * being changed.
429 */
430 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
431 mtx_lock_spin(&allpmaps_lock);
432 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
433 mtx_unlock_spin(&allpmaps_lock);
434
435 /*
436 * Reserve some special page table entries/VA space for temporary
437 * mapping of pages.
438 */
439 #define SYSMAP(c, p, v, n) \
440 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
441
442 va = virtual_avail;
443 pte = vtopte(va);
444
445 /*
446 * CMAP1/CMAP2 are used for zeroing and copying pages.
447 * CMAP3 is used for the idle process page zeroing.
448 */
449 for (i = 0; i < MAXCPU; i++) {
450 sysmaps = &sysmaps_pcpu[i];
451 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
452 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
453 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
454 }
455 SYSMAP(caddr_t, CMAP3, CADDR3, 1)
456
457 /*
458 * Crashdump maps.
459 */
460 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
461
462 /*
463 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
464 */
465 SYSMAP(caddr_t, unused, ptvmmap, 1)
466
467 /*
468 * msgbufp is used to map the system message buffer.
469 */
470 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
471
472 /*
473 * KPTmap is used by pmap_kextract().
474 *
475 * KPTmap is first initialized by locore. However, that initial
476 * KPTmap can only support NKPT page table pages. Here, a larger
477 * KPTmap is created that can support KVA_PAGES page table pages.
478 */
479 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
480
481 for (i = 0; i < NKPT; i++)
482 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
483
484 /*
485 * Adjust the start of the KPTD and KPTmap so that the implementation
486 * of pmap_kextract() and pmap_growkernel() can be made simpler.
487 */
488 KPTD -= KPTDI;
489 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
490
491 /*
492 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(),
493 * respectively.
494 */
495 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
496 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
497
498 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
499
500 virtual_avail = va;
501
502 /*
503 * Leave in place an identity mapping (virt == phys) for the low 1 MB
504 * physical memory region that is used by the ACPI wakeup code. This
505 * mapping must not have PG_G set.
506 */
507 #ifdef XBOX
508 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
509 * an early stadium, we cannot yet neatly map video memory ... :-(
510 * Better fixes are very welcome! */
511 if (!arch_i386_is_xbox)
512 #endif
513 for (i = 1; i < NKPT; i++)
514 PTD[i] = 0;
515
516 /* Initialize the PAT MSR if present. */
517 pmap_init_pat();
518
519 /* Turn on PG_G on kernel page(s) */
520 pmap_set_pg();
521 }
522
523 static void
524 pmap_init_qpages(void)
525 {
526 struct pcpu *pc;
527 int i;
528
529 CPU_FOREACH(i) {
530 pc = pcpu_find(i);
531 pc->pc_qmap_addr = kva_alloc(PAGE_SIZE);
532 if (pc->pc_qmap_addr == 0)
533 panic("pmap_init_qpages: unable to allocate KVA");
534 }
535 }
536
537 SYSINIT(qpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_qpages, NULL);
538
539 /*
540 * Setup the PAT MSR.
541 */
542 void
543 pmap_init_pat(void)
544 {
545 int pat_table[PAT_INDEX_SIZE];
546 uint64_t pat_msr;
547 u_long cr0, cr4;
548 int i;
549
550 /* Set default PAT index table. */
551 for (i = 0; i < PAT_INDEX_SIZE; i++)
552 pat_table[i] = -1;
553 pat_table[PAT_WRITE_BACK] = 0;
554 pat_table[PAT_WRITE_THROUGH] = 1;
555 pat_table[PAT_UNCACHEABLE] = 3;
556 pat_table[PAT_WRITE_COMBINING] = 3;
557 pat_table[PAT_WRITE_PROTECTED] = 3;
558 pat_table[PAT_UNCACHED] = 3;
559
560 /* Bail if this CPU doesn't implement PAT. */
561 if ((cpu_feature & CPUID_PAT) == 0) {
562 for (i = 0; i < PAT_INDEX_SIZE; i++)
563 pat_index[i] = pat_table[i];
564 pat_works = 0;
565 return;
566 }
567
568 /*
569 * Due to some Intel errata, we can only safely use the lower 4
570 * PAT entries.
571 *
572 * Intel Pentium III Processor Specification Update
573 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
574 * or Mode C Paging)
575 *
576 * Intel Pentium IV Processor Specification Update
577 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
578 */
579 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
580 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
581 pat_works = 0;
582
583 /* Initialize default PAT entries. */
584 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
585 PAT_VALUE(1, PAT_WRITE_THROUGH) |
586 PAT_VALUE(2, PAT_UNCACHED) |
587 PAT_VALUE(3, PAT_UNCACHEABLE) |
588 PAT_VALUE(4, PAT_WRITE_BACK) |
589 PAT_VALUE(5, PAT_WRITE_THROUGH) |
590 PAT_VALUE(6, PAT_UNCACHED) |
591 PAT_VALUE(7, PAT_UNCACHEABLE);
592
593 if (pat_works) {
594 /*
595 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
596 * Program 5 and 6 as WP and WC.
597 * Leave 4 and 7 as WB and UC.
598 */
599 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
600 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
601 PAT_VALUE(6, PAT_WRITE_COMBINING);
602 pat_table[PAT_UNCACHED] = 2;
603 pat_table[PAT_WRITE_PROTECTED] = 5;
604 pat_table[PAT_WRITE_COMBINING] = 6;
605 } else {
606 /*
607 * Just replace PAT Index 2 with WC instead of UC-.
608 */
609 pat_msr &= ~PAT_MASK(2);
610 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
611 pat_table[PAT_WRITE_COMBINING] = 2;
612 }
613
614 /* Disable PGE. */
615 cr4 = rcr4();
616 load_cr4(cr4 & ~CR4_PGE);
617
618 /* Disable caches (CD = 1, NW = 0). */
619 cr0 = rcr0();
620 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
621
622 /* Flushes caches and TLBs. */
623 wbinvd();
624 invltlb();
625
626 /* Update PAT and index table. */
627 wrmsr(MSR_PAT, pat_msr);
628 for (i = 0; i < PAT_INDEX_SIZE; i++)
629 pat_index[i] = pat_table[i];
630
631 /* Flush caches and TLBs again. */
632 wbinvd();
633 invltlb();
634
635 /* Restore caches and PGE. */
636 load_cr0(cr0);
637 load_cr4(cr4);
638 }
639
640 /*
641 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
642 */
643 static void
644 pmap_set_pg(void)
645 {
646 pt_entry_t *pte;
647 vm_offset_t va, endva;
648
649 if (pgeflag == 0)
650 return;
651
652 endva = KERNBASE + KERNend;
653
654 if (pseflag) {
655 va = KERNBASE + KERNLOAD;
656 while (va < endva) {
657 pdir_pde(PTD, va) |= pgeflag;
658 invltlb(); /* Flush non-PG_G entries. */
659 va += NBPDR;
660 }
661 } else {
662 va = (vm_offset_t)btext;
663 while (va < endva) {
664 pte = vtopte(va);
665 if (*pte)
666 *pte |= pgeflag;
667 invltlb(); /* Flush non-PG_G entries. */
668 va += PAGE_SIZE;
669 }
670 }
671 }
672
673 /*
674 * Initialize a vm_page's machine-dependent fields.
675 */
676 void
677 pmap_page_init(vm_page_t m)
678 {
679
680 TAILQ_INIT(&m->md.pv_list);
681 m->md.pat_mode = PAT_WRITE_BACK;
682 }
683
684 #if defined(PAE) || defined(PAE_TABLES)
685 static void *
686 pmap_pdpt_allocf(uma_zone_t zone, vm_size_t bytes, uint8_t *flags, int wait)
687 {
688
689 /* Inform UMA that this allocator uses kernel_map/object. */
690 *flags = UMA_SLAB_KERNEL;
691 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL,
692 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
693 }
694 #endif
695
696 /*
697 * Abuse the pte nodes for unmapped kva to thread a kva freelist through.
698 * Requirements:
699 * - Must deal with pages in order to ensure that none of the PG_* bits
700 * are ever set, PG_V in particular.
701 * - Assumes we can write to ptes without pte_store() atomic ops, even
702 * on PAE systems. This should be ok.
703 * - Assumes nothing will ever test these addresses for 0 to indicate
704 * no mapping instead of correctly checking PG_V.
705 * - Assumes a vm_offset_t will fit in a pte (true for i386).
706 * Because PG_V is never set, there can be no mappings to invalidate.
707 */
708 static vm_offset_t
709 pmap_ptelist_alloc(vm_offset_t *head)
710 {
711 pt_entry_t *pte;
712 vm_offset_t va;
713
714 va = *head;
715 if (va == 0)
716 panic("pmap_ptelist_alloc: exhausted ptelist KVA");
717 pte = vtopte(va);
718 *head = *pte;
719 if (*head & PG_V)
720 panic("pmap_ptelist_alloc: va with PG_V set!");
721 *pte = 0;
722 return (va);
723 }
724
725 static void
726 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
727 {
728 pt_entry_t *pte;
729
730 if (va & PG_V)
731 panic("pmap_ptelist_free: freeing va with PG_V set!");
732 pte = vtopte(va);
733 *pte = *head; /* virtual! PG_V is 0 though */
734 *head = va;
735 }
736
737 static void
738 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
739 {
740 int i;
741 vm_offset_t va;
742
743 *head = 0;
744 for (i = npages - 1; i >= 0; i--) {
745 va = (vm_offset_t)base + i * PAGE_SIZE;
746 pmap_ptelist_free(head, va);
747 }
748 }
749
750
751 /*
752 * Initialize the pmap module.
753 * Called by vm_init, to initialize any structures that the pmap
754 * system needs to map virtual memory.
755 */
756 void
757 pmap_init(void)
758 {
759 struct pmap_preinit_mapping *ppim;
760 vm_page_t mpte;
761 vm_size_t s;
762 int i, pv_npg;
763
764 /*
765 * Initialize the vm page array entries for the kernel pmap's
766 * page table pages.
767 */
768 for (i = 0; i < NKPT; i++) {
769 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
770 KASSERT(mpte >= vm_page_array &&
771 mpte < &vm_page_array[vm_page_array_size],
772 ("pmap_init: page table page is out of range"));
773 mpte->pindex = i + KPTDI;
774 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
775 }
776
777 /*
778 * Initialize the address space (zone) for the pv entries. Set a
779 * high water mark so that the system can recover from excessive
780 * numbers of pv entries.
781 */
782 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
783 pv_entry_max = shpgperproc * maxproc + vm_cnt.v_page_count;
784 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
785 pv_entry_max = roundup(pv_entry_max, _NPCPV);
786 pv_entry_high_water = 9 * (pv_entry_max / 10);
787
788 /*
789 * If the kernel is running on a virtual machine, then it must assume
790 * that MCA is enabled by the hypervisor. Moreover, the kernel must
791 * be prepared for the hypervisor changing the vendor and family that
792 * are reported by CPUID. Consequently, the workaround for AMD Family
793 * 10h Erratum 383 is enabled if the processor's feature set does not
794 * include at least one feature that is only supported by older Intel
795 * or newer AMD processors.
796 */
797 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 &&
798 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI |
799 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP |
800 AMDID2_FMA4)) == 0)
801 workaround_erratum383 = 1;
802
803 /*
804 * Are large page mappings supported and enabled?
805 */
806 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
807 if (pseflag == 0)
808 pg_ps_enabled = 0;
809 else if (pg_ps_enabled) {
810 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
811 ("pmap_init: can't assign to pagesizes[1]"));
812 pagesizes[1] = NBPDR;
813 }
814
815 /*
816 * Calculate the size of the pv head table for superpages.
817 * Handle the possibility that "vm_phys_segs[...].end" is zero.
818 */
819 pv_npg = trunc_4mpage(vm_phys_segs[vm_phys_nsegs - 1].end -
820 PAGE_SIZE) / NBPDR + 1;
821
822 /*
823 * Allocate memory for the pv head table for superpages.
824 */
825 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
826 s = round_page(s);
827 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s,
828 M_WAITOK | M_ZERO);
829 for (i = 0; i < pv_npg; i++)
830 TAILQ_INIT(&pv_table[i].pv_list);
831
832 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
833 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks);
834 if (pv_chunkbase == NULL)
835 panic("pmap_init: not enough kvm for pv chunks");
836 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
837 #if defined(PAE) || defined(PAE_TABLES)
838 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
839 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
840 UMA_ZONE_VM | UMA_ZONE_NOFREE);
841 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
842 #endif
843
844 pmap_initialized = 1;
845 if (!bootverbose)
846 return;
847 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
848 ppim = pmap_preinit_mapping + i;
849 if (ppim->va == 0)
850 continue;
851 printf("PPIM %u: PA=%#jx, VA=%#x, size=%#x, mode=%#x\n", i,
852 (uintmax_t)ppim->pa, ppim->va, ppim->sz, ppim->mode);
853 }
854 }
855
856
857 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
858 "Max number of PV entries");
859 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
860 "Page share factor per proc");
861
862 static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
863 "2/4MB page mapping counters");
864
865 static u_long pmap_pde_demotions;
866 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
867 &pmap_pde_demotions, 0, "2/4MB page demotions");
868
869 static u_long pmap_pde_mappings;
870 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
871 &pmap_pde_mappings, 0, "2/4MB page mappings");
872
873 static u_long pmap_pde_p_failures;
874 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
875 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
876
877 static u_long pmap_pde_promotions;
878 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
879 &pmap_pde_promotions, 0, "2/4MB page promotions");
880
881 /***************************************************
882 * Low level helper routines.....
883 ***************************************************/
884
885 /*
886 * Determine the appropriate bits to set in a PTE or PDE for a specified
887 * caching mode.
888 */
889 int
890 pmap_cache_bits(int mode, boolean_t is_pde)
891 {
892 int cache_bits, pat_flag, pat_idx;
893
894 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
895 panic("Unknown caching mode %d\n", mode);
896
897 /* The PAT bit is different for PTE's and PDE's. */
898 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
899
900 /* Map the caching mode to a PAT index. */
901 pat_idx = pat_index[mode];
902
903 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
904 cache_bits = 0;
905 if (pat_idx & 0x4)
906 cache_bits |= pat_flag;
907 if (pat_idx & 0x2)
908 cache_bits |= PG_NC_PCD;
909 if (pat_idx & 0x1)
910 cache_bits |= PG_NC_PWT;
911 return (cache_bits);
912 }
913
914 /*
915 * The caller is responsible for maintaining TLB consistency.
916 */
917 static void
918 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
919 {
920 pd_entry_t *pde;
921 pmap_t pmap;
922 boolean_t PTD_updated;
923
924 PTD_updated = FALSE;
925 mtx_lock_spin(&allpmaps_lock);
926 LIST_FOREACH(pmap, &allpmaps, pm_list) {
927 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
928 PG_FRAME))
929 PTD_updated = TRUE;
930 pde = pmap_pde(pmap, va);
931 pde_store(pde, newpde);
932 }
933 mtx_unlock_spin(&allpmaps_lock);
934 KASSERT(PTD_updated,
935 ("pmap_kenter_pde: current page table is not in allpmaps"));
936 }
937
938 /*
939 * After changing the page size for the specified virtual address in the page
940 * table, flush the corresponding entries from the processor's TLB. Only the
941 * calling processor's TLB is affected.
942 *
943 * The calling thread must be pinned to a processor.
944 */
945 static void
946 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
947 {
948 u_long cr4;
949
950 if ((newpde & PG_PS) == 0)
951 /* Demotion: flush a specific 2MB page mapping. */
952 invlpg(va);
953 else if ((newpde & PG_G) == 0)
954 /*
955 * Promotion: flush every 4KB page mapping from the TLB
956 * because there are too many to flush individually.
957 */
958 invltlb();
959 else {
960 /*
961 * Promotion: flush every 4KB page mapping from the TLB,
962 * including any global (PG_G) mappings.
963 */
964 cr4 = rcr4();
965 load_cr4(cr4 & ~CR4_PGE);
966 /*
967 * Although preemption at this point could be detrimental to
968 * performance, it would not lead to an error. PG_G is simply
969 * ignored if CR4.PGE is clear. Moreover, in case this block
970 * is re-entered, the load_cr4() either above or below will
971 * modify CR4.PGE flushing the TLB.
972 */
973 load_cr4(cr4 | CR4_PGE);
974 }
975 }
976
977 void
978 invltlb_glob(void)
979 {
980 uint64_t cr4;
981
982 if (pgeflag == 0) {
983 invltlb();
984 } else {
985 cr4 = rcr4();
986 load_cr4(cr4 & ~CR4_PGE);
987 load_cr4(cr4 | CR4_PGE);
988 }
989 }
990
991
992 #ifdef SMP
993 /*
994 * For SMP, these functions have to use the IPI mechanism for coherence.
995 *
996 * N.B.: Before calling any of the following TLB invalidation functions,
997 * the calling processor must ensure that all stores updating a non-
998 * kernel page table are globally performed. Otherwise, another
999 * processor could cache an old, pre-update entry without being
1000 * invalidated. This can happen one of two ways: (1) The pmap becomes
1001 * active on another processor after its pm_active field is checked by
1002 * one of the following functions but before a store updating the page
1003 * table is globally performed. (2) The pmap becomes active on another
1004 * processor before its pm_active field is checked but due to
1005 * speculative loads one of the following functions stills reads the
1006 * pmap as inactive on the other processor.
1007 *
1008 * The kernel page table is exempt because its pm_active field is
1009 * immutable. The kernel page table is always active on every
1010 * processor.
1011 */
1012 void
1013 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1014 {
1015 cpuset_t *mask, other_cpus;
1016 u_int cpuid;
1017
1018 sched_pin();
1019 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1020 invlpg(va);
1021 mask = &all_cpus;
1022 } else {
1023 cpuid = PCPU_GET(cpuid);
1024 other_cpus = all_cpus;
1025 CPU_CLR(cpuid, &other_cpus);
1026 if (CPU_ISSET(cpuid, &pmap->pm_active))
1027 invlpg(va);
1028 CPU_AND(&other_cpus, &pmap->pm_active);
1029 mask = &other_cpus;
1030 }
1031 smp_masked_invlpg(*mask, va);
1032 sched_unpin();
1033 }
1034
1035 /* 4k PTEs -- Chosen to exceed the total size of Broadwell L2 TLB */
1036 #define PMAP_INVLPG_THRESHOLD (4 * 1024 * PAGE_SIZE)
1037
1038 void
1039 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1040 {
1041 cpuset_t *mask, other_cpus;
1042 vm_offset_t addr;
1043 u_int cpuid;
1044
1045 if (eva - sva >= PMAP_INVLPG_THRESHOLD) {
1046 pmap_invalidate_all(pmap);
1047 return;
1048 }
1049
1050 sched_pin();
1051 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) {
1052 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1053 invlpg(addr);
1054 mask = &all_cpus;
1055 } else {
1056 cpuid = PCPU_GET(cpuid);
1057 other_cpus = all_cpus;
1058 CPU_CLR(cpuid, &other_cpus);
1059 if (CPU_ISSET(cpuid, &pmap->pm_active))
1060 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1061 invlpg(addr);
1062 CPU_AND(&other_cpus, &pmap->pm_active);
1063 mask = &other_cpus;
1064 }
1065 smp_masked_invlpg_range(*mask, sva, eva);
1066 sched_unpin();
1067 }
1068
1069 void
1070 pmap_invalidate_all(pmap_t pmap)
1071 {
1072 cpuset_t *mask, other_cpus;
1073 u_int cpuid;
1074
1075 sched_pin();
1076 if (pmap == kernel_pmap) {
1077 invltlb_glob();
1078 mask = &all_cpus;
1079 } else if (!CPU_CMP(&pmap->pm_active, &all_cpus)) {
1080 invltlb();
1081 mask = &all_cpus;
1082 } else {
1083 cpuid = PCPU_GET(cpuid);
1084 other_cpus = all_cpus;
1085 CPU_CLR(cpuid, &other_cpus);
1086 if (CPU_ISSET(cpuid, &pmap->pm_active))
1087 invltlb();
1088 CPU_AND(&other_cpus, &pmap->pm_active);
1089 mask = &other_cpus;
1090 }
1091 smp_masked_invltlb(*mask, pmap);
1092 sched_unpin();
1093 }
1094
1095 void
1096 pmap_invalidate_cache(void)
1097 {
1098
1099 sched_pin();
1100 wbinvd();
1101 smp_cache_flush();
1102 sched_unpin();
1103 }
1104
1105 struct pde_action {
1106 cpuset_t invalidate; /* processors that invalidate their TLB */
1107 vm_offset_t va;
1108 pd_entry_t *pde;
1109 pd_entry_t newpde;
1110 u_int store; /* processor that updates the PDE */
1111 };
1112
1113 static void
1114 pmap_update_pde_kernel(void *arg)
1115 {
1116 struct pde_action *act = arg;
1117 pd_entry_t *pde;
1118 pmap_t pmap;
1119
1120 if (act->store == PCPU_GET(cpuid)) {
1121
1122 /*
1123 * Elsewhere, this operation requires allpmaps_lock for
1124 * synchronization. Here, it does not because it is being
1125 * performed in the context of an all_cpus rendezvous.
1126 */
1127 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1128 pde = pmap_pde(pmap, act->va);
1129 pde_store(pde, act->newpde);
1130 }
1131 }
1132 }
1133
1134 static void
1135 pmap_update_pde_user(void *arg)
1136 {
1137 struct pde_action *act = arg;
1138
1139 if (act->store == PCPU_GET(cpuid))
1140 pde_store(act->pde, act->newpde);
1141 }
1142
1143 static void
1144 pmap_update_pde_teardown(void *arg)
1145 {
1146 struct pde_action *act = arg;
1147
1148 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate))
1149 pmap_update_pde_invalidate(act->va, act->newpde);
1150 }
1151
1152 /*
1153 * Change the page size for the specified virtual address in a way that
1154 * prevents any possibility of the TLB ever having two entries that map the
1155 * same virtual address using different page sizes. This is the recommended
1156 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1157 * machine check exception for a TLB state that is improperly diagnosed as a
1158 * hardware error.
1159 */
1160 static void
1161 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1162 {
1163 struct pde_action act;
1164 cpuset_t active, other_cpus;
1165 u_int cpuid;
1166
1167 sched_pin();
1168 cpuid = PCPU_GET(cpuid);
1169 other_cpus = all_cpus;
1170 CPU_CLR(cpuid, &other_cpus);
1171 if (pmap == kernel_pmap)
1172 active = all_cpus;
1173 else
1174 active = pmap->pm_active;
1175 if (CPU_OVERLAP(&active, &other_cpus)) {
1176 act.store = cpuid;
1177 act.invalidate = active;
1178 act.va = va;
1179 act.pde = pde;
1180 act.newpde = newpde;
1181 CPU_SET(cpuid, &active);
1182 smp_rendezvous_cpus(active,
1183 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1184 pmap_update_pde_kernel : pmap_update_pde_user,
1185 pmap_update_pde_teardown, &act);
1186 } else {
1187 if (pmap == kernel_pmap)
1188 pmap_kenter_pde(va, newpde);
1189 else
1190 pde_store(pde, newpde);
1191 if (CPU_ISSET(cpuid, &active))
1192 pmap_update_pde_invalidate(va, newpde);
1193 }
1194 sched_unpin();
1195 }
1196 #else /* !SMP */
1197 /*
1198 * Normal, non-SMP, 486+ invalidation functions.
1199 * We inline these within pmap.c for speed.
1200 */
1201 PMAP_INLINE void
1202 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1203 {
1204
1205 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1206 invlpg(va);
1207 }
1208
1209 PMAP_INLINE void
1210 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1211 {
1212 vm_offset_t addr;
1213
1214 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1215 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1216 invlpg(addr);
1217 }
1218
1219 PMAP_INLINE void
1220 pmap_invalidate_all(pmap_t pmap)
1221 {
1222
1223 if (pmap == kernel_pmap)
1224 invltlb_glob();
1225 else if (!CPU_EMPTY(&pmap->pm_active))
1226 invltlb();
1227 }
1228
1229 PMAP_INLINE void
1230 pmap_invalidate_cache(void)
1231 {
1232
1233 wbinvd();
1234 }
1235
1236 static void
1237 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1238 {
1239
1240 if (pmap == kernel_pmap)
1241 pmap_kenter_pde(va, newpde);
1242 else
1243 pde_store(pde, newpde);
1244 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active))
1245 pmap_update_pde_invalidate(va, newpde);
1246 }
1247 #endif /* !SMP */
1248
1249 #define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024)
1250
1251 void
1252 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva, boolean_t force)
1253 {
1254
1255 if (force) {
1256 sva &= ~(vm_offset_t)cpu_clflush_line_size;
1257 } else {
1258 KASSERT((sva & PAGE_MASK) == 0,
1259 ("pmap_invalidate_cache_range: sva not page-aligned"));
1260 KASSERT((eva & PAGE_MASK) == 0,
1261 ("pmap_invalidate_cache_range: eva not page-aligned"));
1262 }
1263
1264 if ((cpu_feature & CPUID_SS) != 0 && !force)
1265 ; /* If "Self Snoop" is supported and allowed, do nothing. */
1266 else if ((cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0 &&
1267 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1268 #ifdef DEV_APIC
1269 /*
1270 * XXX: Some CPUs fault, hang, or trash the local APIC
1271 * registers if we use CLFLUSH on the local APIC
1272 * range. The local APIC is always uncached, so we
1273 * don't need to flush for that range anyway.
1274 */
1275 if (pmap_kextract(sva) == lapic_paddr)
1276 return;
1277 #endif
1278 /*
1279 * Otherwise, do per-cache line flush. Use the mfence
1280 * instruction to insure that previous stores are
1281 * included in the write-back. The processor
1282 * propagates flush to other processors in the cache
1283 * coherence domain.
1284 */
1285 mfence();
1286 for (; sva < eva; sva += cpu_clflush_line_size)
1287 clflushopt(sva);
1288 mfence();
1289 } else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1290 eva - sva < PMAP_CLFLUSH_THRESHOLD) {
1291 #ifdef DEV_APIC
1292 if (pmap_kextract(sva) == lapic_paddr)
1293 return;
1294 #endif
1295 /*
1296 * Writes are ordered by CLFLUSH on Intel CPUs.
1297 */
1298 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1299 mfence();
1300 for (; sva < eva; sva += cpu_clflush_line_size)
1301 clflush(sva);
1302 if (cpu_vendor_id != CPU_VENDOR_INTEL)
1303 mfence();
1304 } else {
1305
1306 /*
1307 * No targeted cache flush methods are supported by CPU,
1308 * or the supplied range is bigger than 2MB.
1309 * Globally invalidate cache.
1310 */
1311 pmap_invalidate_cache();
1312 }
1313 }
1314
1315 void
1316 pmap_invalidate_cache_pages(vm_page_t *pages, int count)
1317 {
1318 int i;
1319
1320 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE ||
1321 (cpu_feature & CPUID_CLFSH) == 0) {
1322 pmap_invalidate_cache();
1323 } else {
1324 for (i = 0; i < count; i++)
1325 pmap_flush_page(pages[i]);
1326 }
1327 }
1328
1329 /*
1330 * Are we current address space or kernel?
1331 */
1332 static __inline int
1333 pmap_is_current(pmap_t pmap)
1334 {
1335
1336 return (pmap == kernel_pmap || pmap ==
1337 vmspace_pmap(curthread->td_proc->p_vmspace));
1338 }
1339
1340 /*
1341 * If the given pmap is not the current or kernel pmap, the returned pte must
1342 * be released by passing it to pmap_pte_release().
1343 */
1344 pt_entry_t *
1345 pmap_pte(pmap_t pmap, vm_offset_t va)
1346 {
1347 pd_entry_t newpf;
1348 pd_entry_t *pde;
1349
1350 pde = pmap_pde(pmap, va);
1351 if (*pde & PG_PS)
1352 return (pde);
1353 if (*pde != 0) {
1354 /* are we current address space or kernel? */
1355 if (pmap_is_current(pmap))
1356 return (vtopte(va));
1357 mtx_lock(&PMAP2mutex);
1358 newpf = *pde & PG_FRAME;
1359 if ((*PMAP2 & PG_FRAME) != newpf) {
1360 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1361 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1362 }
1363 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1364 }
1365 return (NULL);
1366 }
1367
1368 /*
1369 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1370 * being NULL.
1371 */
1372 static __inline void
1373 pmap_pte_release(pt_entry_t *pte)
1374 {
1375
1376 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1377 mtx_unlock(&PMAP2mutex);
1378 }
1379
1380 /*
1381 * NB: The sequence of updating a page table followed by accesses to the
1382 * corresponding pages is subject to the situation described in the "AMD64
1383 * Architecture Programmer's Manual Volume 2: System Programming" rev. 3.23,
1384 * "7.3.1 Special Coherency Considerations". Therefore, issuing the INVLPG
1385 * right after modifying the PTE bits is crucial.
1386 */
1387 static __inline void
1388 invlcaddr(void *caddr)
1389 {
1390
1391 invlpg((u_int)caddr);
1392 }
1393
1394 /*
1395 * Super fast pmap_pte routine best used when scanning
1396 * the pv lists. This eliminates many coarse-grained
1397 * invltlb calls. Note that many of the pv list
1398 * scans are across different pmaps. It is very wasteful
1399 * to do an entire invltlb for checking a single mapping.
1400 *
1401 * If the given pmap is not the current pmap, pvh_global_lock
1402 * must be held and curthread pinned to a CPU.
1403 */
1404 static pt_entry_t *
1405 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1406 {
1407 pd_entry_t newpf;
1408 pd_entry_t *pde;
1409
1410 pde = pmap_pde(pmap, va);
1411 if (*pde & PG_PS)
1412 return (pde);
1413 if (*pde != 0) {
1414 /* are we current address space or kernel? */
1415 if (pmap_is_current(pmap))
1416 return (vtopte(va));
1417 rw_assert(&pvh_global_lock, RA_WLOCKED);
1418 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1419 newpf = *pde & PG_FRAME;
1420 if ((*PMAP1 & PG_FRAME) != newpf) {
1421 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1422 #ifdef SMP
1423 PMAP1cpu = PCPU_GET(cpuid);
1424 #endif
1425 invlcaddr(PADDR1);
1426 PMAP1changed++;
1427 } else
1428 #ifdef SMP
1429 if (PMAP1cpu != PCPU_GET(cpuid)) {
1430 PMAP1cpu = PCPU_GET(cpuid);
1431 invlcaddr(PADDR1);
1432 PMAP1changedcpu++;
1433 } else
1434 #endif
1435 PMAP1unchanged++;
1436 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1437 }
1438 return (0);
1439 }
1440
1441 /*
1442 * Routine: pmap_extract
1443 * Function:
1444 * Extract the physical page address associated
1445 * with the given map/virtual_address pair.
1446 */
1447 vm_paddr_t
1448 pmap_extract(pmap_t pmap, vm_offset_t va)
1449 {
1450 vm_paddr_t rtval;
1451 pt_entry_t *pte;
1452 pd_entry_t pde;
1453
1454 rtval = 0;
1455 PMAP_LOCK(pmap);
1456 pde = pmap->pm_pdir[va >> PDRSHIFT];
1457 if (pde != 0) {
1458 if ((pde & PG_PS) != 0)
1459 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1460 else {
1461 pte = pmap_pte(pmap, va);
1462 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1463 pmap_pte_release(pte);
1464 }
1465 }
1466 PMAP_UNLOCK(pmap);
1467 return (rtval);
1468 }
1469
1470 /*
1471 * Routine: pmap_extract_and_hold
1472 * Function:
1473 * Atomically extract and hold the physical page
1474 * with the given pmap and virtual address pair
1475 * if that mapping permits the given protection.
1476 */
1477 vm_page_t
1478 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1479 {
1480 pd_entry_t pde;
1481 pt_entry_t pte, *ptep;
1482 vm_page_t m;
1483 vm_paddr_t pa;
1484
1485 pa = 0;
1486 m = NULL;
1487 PMAP_LOCK(pmap);
1488 retry:
1489 pde = *pmap_pde(pmap, va);
1490 if (pde != 0) {
1491 if (pde & PG_PS) {
1492 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1493 if (vm_page_pa_tryrelock(pmap, (pde &
1494 PG_PS_FRAME) | (va & PDRMASK), &pa))
1495 goto retry;
1496 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1497 (va & PDRMASK));
1498 vm_page_hold(m);
1499 }
1500 } else {
1501 ptep = pmap_pte(pmap, va);
1502 pte = *ptep;
1503 pmap_pte_release(ptep);
1504 if (pte != 0 &&
1505 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1506 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME,
1507 &pa))
1508 goto retry;
1509 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1510 vm_page_hold(m);
1511 }
1512 }
1513 }
1514 PA_UNLOCK_COND(pa);
1515 PMAP_UNLOCK(pmap);
1516 return (m);
1517 }
1518
1519 /***************************************************
1520 * Low level mapping routines.....
1521 ***************************************************/
1522
1523 /*
1524 * Add a wired page to the kva.
1525 * Note: not SMP coherent.
1526 *
1527 * This function may be used before pmap_bootstrap() is called.
1528 */
1529 PMAP_INLINE void
1530 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1531 {
1532 pt_entry_t *pte;
1533
1534 pte = vtopte(va);
1535 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1536 }
1537
1538 static __inline void
1539 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1540 {
1541 pt_entry_t *pte;
1542
1543 pte = vtopte(va);
1544 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1545 }
1546
1547 /*
1548 * Remove a page from the kernel pagetables.
1549 * Note: not SMP coherent.
1550 *
1551 * This function may be used before pmap_bootstrap() is called.
1552 */
1553 PMAP_INLINE void
1554 pmap_kremove(vm_offset_t va)
1555 {
1556 pt_entry_t *pte;
1557
1558 pte = vtopte(va);
1559 pte_clear(pte);
1560 }
1561
1562 /*
1563 * Used to map a range of physical addresses into kernel
1564 * virtual address space.
1565 *
1566 * The value passed in '*virt' is a suggested virtual address for
1567 * the mapping. Architectures which can support a direct-mapped
1568 * physical to virtual region can return the appropriate address
1569 * within that region, leaving '*virt' unchanged. Other
1570 * architectures should map the pages starting at '*virt' and
1571 * update '*virt' with the first usable address after the mapped
1572 * region.
1573 */
1574 vm_offset_t
1575 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1576 {
1577 vm_offset_t va, sva;
1578 vm_paddr_t superpage_offset;
1579 pd_entry_t newpde;
1580
1581 va = *virt;
1582 /*
1583 * Does the physical address range's size and alignment permit at
1584 * least one superpage mapping to be created?
1585 */
1586 superpage_offset = start & PDRMASK;
1587 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1588 /*
1589 * Increase the starting virtual address so that its alignment
1590 * does not preclude the use of superpage mappings.
1591 */
1592 if ((va & PDRMASK) < superpage_offset)
1593 va = (va & ~PDRMASK) + superpage_offset;
1594 else if ((va & PDRMASK) > superpage_offset)
1595 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1596 }
1597 sva = va;
1598 while (start < end) {
1599 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1600 pseflag) {
1601 KASSERT((va & PDRMASK) == 0,
1602 ("pmap_map: misaligned va %#x", va));
1603 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1604 pmap_kenter_pde(va, newpde);
1605 va += NBPDR;
1606 start += NBPDR;
1607 } else {
1608 pmap_kenter(va, start);
1609 va += PAGE_SIZE;
1610 start += PAGE_SIZE;
1611 }
1612 }
1613 pmap_invalidate_range(kernel_pmap, sva, va);
1614 *virt = va;
1615 return (sva);
1616 }
1617
1618
1619 /*
1620 * Add a list of wired pages to the kva
1621 * this routine is only used for temporary
1622 * kernel mappings that do not need to have
1623 * page modification or references recorded.
1624 * Note that old mappings are simply written
1625 * over. The page *must* be wired.
1626 * Note: SMP coherent. Uses a ranged shootdown IPI.
1627 */
1628 void
1629 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1630 {
1631 pt_entry_t *endpte, oldpte, pa, *pte;
1632 vm_page_t m;
1633
1634 oldpte = 0;
1635 pte = vtopte(sva);
1636 endpte = pte + count;
1637 while (pte < endpte) {
1638 m = *ma++;
1639 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1640 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1641 oldpte |= *pte;
1642 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1643 }
1644 pte++;
1645 }
1646 if (__predict_false((oldpte & PG_V) != 0))
1647 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1648 PAGE_SIZE);
1649 }
1650
1651 /*
1652 * This routine tears out page mappings from the
1653 * kernel -- it is meant only for temporary mappings.
1654 * Note: SMP coherent. Uses a ranged shootdown IPI.
1655 */
1656 void
1657 pmap_qremove(vm_offset_t sva, int count)
1658 {
1659 vm_offset_t va;
1660
1661 va = sva;
1662 while (count-- > 0) {
1663 pmap_kremove(va);
1664 va += PAGE_SIZE;
1665 }
1666 pmap_invalidate_range(kernel_pmap, sva, va);
1667 }
1668
1669 /***************************************************
1670 * Page table page management routines.....
1671 ***************************************************/
1672 static __inline void
1673 pmap_free_zero_pages(struct spglist *free)
1674 {
1675 vm_page_t m;
1676
1677 while ((m = SLIST_FIRST(free)) != NULL) {
1678 SLIST_REMOVE_HEAD(free, plinks.s.ss);
1679 /* Preserve the page's PG_ZERO setting. */
1680 vm_page_free_toq(m);
1681 }
1682 }
1683
1684 /*
1685 * Schedule the specified unused page table page to be freed. Specifically,
1686 * add the page to the specified list of pages that will be released to the
1687 * physical memory manager after the TLB has been updated.
1688 */
1689 static __inline void
1690 pmap_add_delayed_free_list(vm_page_t m, struct spglist *free,
1691 boolean_t set_PG_ZERO)
1692 {
1693
1694 if (set_PG_ZERO)
1695 m->flags |= PG_ZERO;
1696 else
1697 m->flags &= ~PG_ZERO;
1698 SLIST_INSERT_HEAD(free, m, plinks.s.ss);
1699 }
1700
1701 /*
1702 * Inserts the specified page table page into the specified pmap's collection
1703 * of idle page table pages. Each of a pmap's page table pages is responsible
1704 * for mapping a distinct range of virtual addresses. The pmap's collection is
1705 * ordered by this virtual address range.
1706 */
1707 static __inline int
1708 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1709 {
1710
1711 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1712 return (vm_radix_insert(&pmap->pm_root, mpte));
1713 }
1714
1715 /*
1716 * Looks for a page table page mapping the specified virtual address in the
1717 * specified pmap's collection of idle page table pages. Returns NULL if there
1718 * is no page table page corresponding to the specified virtual address.
1719 */
1720 static __inline vm_page_t
1721 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1722 {
1723
1724 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1725 return (vm_radix_lookup(&pmap->pm_root, va >> PDRSHIFT));
1726 }
1727
1728 /*
1729 * Removes the specified page table page from the specified pmap's collection
1730 * of idle page table pages. The specified page table page must be a member of
1731 * the pmap's collection.
1732 */
1733 static __inline void
1734 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1735 {
1736
1737 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1738 vm_radix_remove(&pmap->pm_root, mpte->pindex);
1739 }
1740
1741 /*
1742 * Decrements a page table page's wire count, which is used to record the
1743 * number of valid page table entries within the page. If the wire count
1744 * drops to zero, then the page table page is unmapped. Returns TRUE if the
1745 * page table page was unmapped and FALSE otherwise.
1746 */
1747 static inline boolean_t
1748 pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1749 {
1750
1751 --m->wire_count;
1752 if (m->wire_count == 0) {
1753 _pmap_unwire_ptp(pmap, m, free);
1754 return (TRUE);
1755 } else
1756 return (FALSE);
1757 }
1758
1759 static void
1760 _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free)
1761 {
1762 vm_offset_t pteva;
1763
1764 /*
1765 * unmap the page table page
1766 */
1767 pmap->pm_pdir[m->pindex] = 0;
1768 --pmap->pm_stats.resident_count;
1769
1770 /*
1771 * This is a release store so that the ordinary store unmapping
1772 * the page table page is globally performed before TLB shoot-
1773 * down is begun.
1774 */
1775 atomic_subtract_rel_int(&vm_cnt.v_wire_count, 1);
1776
1777 /*
1778 * Do an invltlb to make the invalidated mapping
1779 * take effect immediately.
1780 */
1781 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1782 pmap_invalidate_page(pmap, pteva);
1783
1784 /*
1785 * Put page on a list so that it is released after
1786 * *ALL* TLB shootdown is done
1787 */
1788 pmap_add_delayed_free_list(m, free, TRUE);
1789 }
1790
1791 /*
1792 * After removing a page table entry, this routine is used to
1793 * conditionally free the page, and manage the hold/wire counts.
1794 */
1795 static int
1796 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free)
1797 {
1798 pd_entry_t ptepde;
1799 vm_page_t mpte;
1800
1801 if (va >= VM_MAXUSER_ADDRESS)
1802 return (0);
1803 ptepde = *pmap_pde(pmap, va);
1804 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1805 return (pmap_unwire_ptp(pmap, mpte, free));
1806 }
1807
1808 /*
1809 * Initialize the pmap for the swapper process.
1810 */
1811 void
1812 pmap_pinit0(pmap_t pmap)
1813 {
1814
1815 PMAP_LOCK_INIT(pmap);
1816 /*
1817 * Since the page table directory is shared with the kernel pmap,
1818 * which is already included in the list "allpmaps", this pmap does
1819 * not need to be inserted into that list.
1820 */
1821 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1822 #if defined(PAE) || defined(PAE_TABLES)
1823 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1824 #endif
1825 pmap->pm_root.rt_root = 0;
1826 CPU_ZERO(&pmap->pm_active);
1827 PCPU_SET(curpmap, pmap);
1828 TAILQ_INIT(&pmap->pm_pvchunk);
1829 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1830 }
1831
1832 /*
1833 * Initialize a preallocated and zeroed pmap structure,
1834 * such as one in a vmspace structure.
1835 */
1836 int
1837 pmap_pinit(pmap_t pmap)
1838 {
1839 vm_page_t m, ptdpg[NPGPTD];
1840 vm_paddr_t pa;
1841 int i;
1842
1843 /*
1844 * No need to allocate page table space yet but we do need a valid
1845 * page directory table.
1846 */
1847 if (pmap->pm_pdir == NULL) {
1848 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD);
1849 if (pmap->pm_pdir == NULL)
1850 return (0);
1851 #if defined(PAE) || defined(PAE_TABLES)
1852 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1853 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1854 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1855 ("pmap_pinit: pdpt misaligned"));
1856 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1857 ("pmap_pinit: pdpt above 4g"));
1858 #endif
1859 pmap->pm_root.rt_root = 0;
1860 }
1861 KASSERT(vm_radix_is_empty(&pmap->pm_root),
1862 ("pmap_pinit: pmap has reserved page table page(s)"));
1863
1864 /*
1865 * allocate the page directory page(s)
1866 */
1867 for (i = 0; i < NPGPTD;) {
1868 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ |
1869 VM_ALLOC_WIRED | VM_ALLOC_ZERO);
1870 if (m == NULL)
1871 VM_WAIT;
1872 else {
1873 ptdpg[i++] = m;
1874 }
1875 }
1876
1877 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1878
1879 for (i = 0; i < NPGPTD; i++)
1880 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1881 pagezero(pmap->pm_pdir + (i * NPDEPG));
1882
1883 mtx_lock_spin(&allpmaps_lock);
1884 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1885 /* Copy the kernel page table directory entries. */
1886 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1887 mtx_unlock_spin(&allpmaps_lock);
1888
1889 /* install self-referential address mapping entry(s) */
1890 for (i = 0; i < NPGPTD; i++) {
1891 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1892 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1893 #if defined(PAE) || defined(PAE_TABLES)
1894 pmap->pm_pdpt[i] = pa | PG_V;
1895 #endif
1896 }
1897
1898 CPU_ZERO(&pmap->pm_active);
1899 TAILQ_INIT(&pmap->pm_pvchunk);
1900 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1901
1902 return (1);
1903 }
1904
1905 /*
1906 * this routine is called if the page table page is not
1907 * mapped correctly.
1908 */
1909 static vm_page_t
1910 _pmap_allocpte(pmap_t pmap, u_int ptepindex, u_int flags)
1911 {
1912 vm_paddr_t ptepa;
1913 vm_page_t m;
1914
1915 /*
1916 * Allocate a page table page.
1917 */
1918 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1919 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1920 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1921 PMAP_UNLOCK(pmap);
1922 rw_wunlock(&pvh_global_lock);
1923 VM_WAIT;
1924 rw_wlock(&pvh_global_lock);
1925 PMAP_LOCK(pmap);
1926 }
1927
1928 /*
1929 * Indicate the need to retry. While waiting, the page table
1930 * page may have been allocated.
1931 */
1932 return (NULL);
1933 }
1934 if ((m->flags & PG_ZERO) == 0)
1935 pmap_zero_page(m);
1936
1937 /*
1938 * Map the pagetable page into the process address space, if
1939 * it isn't already there.
1940 */
1941
1942 pmap->pm_stats.resident_count++;
1943
1944 ptepa = VM_PAGE_TO_PHYS(m);
1945 pmap->pm_pdir[ptepindex] =
1946 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1947
1948 return (m);
1949 }
1950
1951 static vm_page_t
1952 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1953 {
1954 u_int ptepindex;
1955 pd_entry_t ptepa;
1956 vm_page_t m;
1957
1958 /*
1959 * Calculate pagetable page index
1960 */
1961 ptepindex = va >> PDRSHIFT;
1962 retry:
1963 /*
1964 * Get the page directory entry
1965 */
1966 ptepa = pmap->pm_pdir[ptepindex];
1967
1968 /*
1969 * This supports switching from a 4MB page to a
1970 * normal 4K page.
1971 */
1972 if (ptepa & PG_PS) {
1973 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1974 ptepa = pmap->pm_pdir[ptepindex];
1975 }
1976
1977 /*
1978 * If the page table page is mapped, we just increment the
1979 * hold count, and activate it.
1980 */
1981 if (ptepa) {
1982 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1983 m->wire_count++;
1984 } else {
1985 /*
1986 * Here if the pte page isn't mapped, or if it has
1987 * been deallocated.
1988 */
1989 m = _pmap_allocpte(pmap, ptepindex, flags);
1990 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1991 goto retry;
1992 }
1993 return (m);
1994 }
1995
1996
1997 /***************************************************
1998 * Pmap allocation/deallocation routines.
1999 ***************************************************/
2000
2001 /*
2002 * Release any resources held by the given physical map.
2003 * Called when a pmap initialized by pmap_pinit is being released.
2004 * Should only be called if the map contains no valid mappings.
2005 */
2006 void
2007 pmap_release(pmap_t pmap)
2008 {
2009 vm_page_t m, ptdpg[NPGPTD];
2010 int i;
2011
2012 KASSERT(pmap->pm_stats.resident_count == 0,
2013 ("pmap_release: pmap resident count %ld != 0",
2014 pmap->pm_stats.resident_count));
2015 KASSERT(vm_radix_is_empty(&pmap->pm_root),
2016 ("pmap_release: pmap has reserved page table page(s)"));
2017 KASSERT(CPU_EMPTY(&pmap->pm_active),
2018 ("releasing active pmap %p", pmap));
2019
2020 mtx_lock_spin(&allpmaps_lock);
2021 LIST_REMOVE(pmap, pm_list);
2022 mtx_unlock_spin(&allpmaps_lock);
2023
2024 for (i = 0; i < NPGPTD; i++)
2025 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2026 PG_FRAME);
2027
2028 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2029 sizeof(*pmap->pm_pdir));
2030
2031 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2032
2033 for (i = 0; i < NPGPTD; i++) {
2034 m = ptdpg[i];
2035 #if defined(PAE) || defined(PAE_TABLES)
2036 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2037 ("pmap_release: got wrong ptd page"));
2038 #endif
2039 m->wire_count--;
2040 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2041 vm_page_free_zero(m);
2042 }
2043 }
2044
2045 static int
2046 kvm_size(SYSCTL_HANDLER_ARGS)
2047 {
2048 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2049
2050 return (sysctl_handle_long(oidp, &ksize, 0, req));
2051 }
2052 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2053 0, 0, kvm_size, "IU", "Size of KVM");
2054
2055 static int
2056 kvm_free(SYSCTL_HANDLER_ARGS)
2057 {
2058 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2059
2060 return (sysctl_handle_long(oidp, &kfree, 0, req));
2061 }
2062 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2063 0, 0, kvm_free, "IU", "Amount of KVM free");
2064
2065 /*
2066 * grow the number of kernel page table entries, if needed
2067 */
2068 void
2069 pmap_growkernel(vm_offset_t addr)
2070 {
2071 vm_paddr_t ptppaddr;
2072 vm_page_t nkpg;
2073 pd_entry_t newpdir;
2074
2075 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2076 addr = roundup2(addr, NBPDR);
2077 if (addr - 1 >= kernel_map->max_offset)
2078 addr = kernel_map->max_offset;
2079 while (kernel_vm_end < addr) {
2080 if (pdir_pde(PTD, kernel_vm_end)) {
2081 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2082 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2083 kernel_vm_end = kernel_map->max_offset;
2084 break;
2085 }
2086 continue;
2087 }
2088
2089 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2090 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2091 VM_ALLOC_ZERO);
2092 if (nkpg == NULL)
2093 panic("pmap_growkernel: no memory to grow kernel");
2094
2095 nkpt++;
2096
2097 if ((nkpg->flags & PG_ZERO) == 0)
2098 pmap_zero_page(nkpg);
2099 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2100 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2101 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2102
2103 pmap_kenter_pde(kernel_vm_end, newpdir);
2104 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
2105 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2106 kernel_vm_end = kernel_map->max_offset;
2107 break;
2108 }
2109 }
2110 }
2111
2112
2113 /***************************************************
2114 * page management routines.
2115 ***************************************************/
2116
2117 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2118 CTASSERT(_NPCM == 11);
2119 CTASSERT(_NPCPV == 336);
2120
2121 static __inline struct pv_chunk *
2122 pv_to_chunk(pv_entry_t pv)
2123 {
2124
2125 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
2126 }
2127
2128 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2129
2130 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2131 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2132
2133 static const uint32_t pc_freemask[_NPCM] = {
2134 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2135 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2136 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2137 PC_FREE0_9, PC_FREE10
2138 };
2139
2140 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2141 "Current number of pv entries");
2142
2143 #ifdef PV_STATS
2144 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2145
2146 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2147 "Current number of pv entry chunks");
2148 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2149 "Current number of pv entry chunks allocated");
2150 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2151 "Current number of pv entry chunks frees");
2152 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2153 "Number of times tried to get a chunk page but failed.");
2154
2155 static long pv_entry_frees, pv_entry_allocs;
2156 static int pv_entry_spare;
2157
2158 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2159 "Current number of pv entry frees");
2160 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2161 "Current number of pv entry allocs");
2162 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2163 "Current number of spare pv entries");
2164 #endif
2165
2166 /*
2167 * We are in a serious low memory condition. Resort to
2168 * drastic measures to free some pages so we can allocate
2169 * another pv entry chunk.
2170 */
2171 static vm_page_t
2172 pmap_pv_reclaim(pmap_t locked_pmap)
2173 {
2174 struct pch newtail;
2175 struct pv_chunk *pc;
2176 struct md_page *pvh;
2177 pd_entry_t *pde;
2178 pmap_t pmap;
2179 pt_entry_t *pte, tpte;
2180 pv_entry_t pv;
2181 vm_offset_t va;
2182 vm_page_t m, m_pc;
2183 struct spglist free;
2184 uint32_t inuse;
2185 int bit, field, freed;
2186
2187 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
2188 pmap = NULL;
2189 m_pc = NULL;
2190 SLIST_INIT(&free);
2191 TAILQ_INIT(&newtail);
2192 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 ||
2193 SLIST_EMPTY(&free))) {
2194 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2195 if (pmap != pc->pc_pmap) {
2196 if (pmap != NULL) {
2197 pmap_invalidate_all(pmap);
2198 if (pmap != locked_pmap)
2199 PMAP_UNLOCK(pmap);
2200 }
2201 pmap = pc->pc_pmap;
2202 /* Avoid deadlock and lock recursion. */
2203 if (pmap > locked_pmap)
2204 PMAP_LOCK(pmap);
2205 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
2206 pmap = NULL;
2207 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2208 continue;
2209 }
2210 }
2211
2212 /*
2213 * Destroy every non-wired, 4 KB page mapping in the chunk.
2214 */
2215 freed = 0;
2216 for (field = 0; field < _NPCM; field++) {
2217 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
2218 inuse != 0; inuse &= ~(1UL << bit)) {
2219 bit = bsfl(inuse);
2220 pv = &pc->pc_pventry[field * 32 + bit];
2221 va = pv->pv_va;
2222 pde = pmap_pde(pmap, va);
2223 if ((*pde & PG_PS) != 0)
2224 continue;
2225 pte = pmap_pte(pmap, va);
2226 tpte = *pte;
2227 if ((tpte & PG_W) == 0)
2228 tpte = pte_load_clear(pte);
2229 pmap_pte_release(pte);
2230 if ((tpte & PG_W) != 0)
2231 continue;
2232 KASSERT(tpte != 0,
2233 ("pmap_pv_reclaim: pmap %p va %x zero pte",
2234 pmap, va));
2235 if ((tpte & PG_G) != 0)
2236 pmap_invalidate_page(pmap, va);
2237 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
2238 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2239 vm_page_dirty(m);
2240 if ((tpte & PG_A) != 0)
2241 vm_page_aflag_set(m, PGA_REFERENCED);
2242 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
2243 if (TAILQ_EMPTY(&m->md.pv_list) &&
2244 (m->flags & PG_FICTITIOUS) == 0) {
2245 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2246 if (TAILQ_EMPTY(&pvh->pv_list)) {
2247 vm_page_aflag_clear(m,
2248 PGA_WRITEABLE);
2249 }
2250 }
2251 pc->pc_map[field] |= 1UL << bit;
2252 pmap_unuse_pt(pmap, va, &free);
2253 freed++;
2254 }
2255 }
2256 if (freed == 0) {
2257 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2258 continue;
2259 }
2260 /* Every freed mapping is for a 4 KB page. */
2261 pmap->pm_stats.resident_count -= freed;
2262 PV_STAT(pv_entry_frees += freed);
2263 PV_STAT(pv_entry_spare += freed);
2264 pv_entry_count -= freed;
2265 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2266 for (field = 0; field < _NPCM; field++)
2267 if (pc->pc_map[field] != pc_freemask[field]) {
2268 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2269 pc_list);
2270 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
2271
2272 /*
2273 * One freed pv entry in locked_pmap is
2274 * sufficient.
2275 */
2276 if (pmap == locked_pmap)
2277 goto out;
2278 break;
2279 }
2280 if (field == _NPCM) {
2281 PV_STAT(pv_entry_spare -= _NPCPV);
2282 PV_STAT(pc_chunk_count--);
2283 PV_STAT(pc_chunk_frees++);
2284 /* Entire chunk is free; return it. */
2285 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2286 pmap_qremove((vm_offset_t)pc, 1);
2287 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2288 break;
2289 }
2290 }
2291 out:
2292 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
2293 if (pmap != NULL) {
2294 pmap_invalidate_all(pmap);
2295 if (pmap != locked_pmap)
2296 PMAP_UNLOCK(pmap);
2297 }
2298 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) {
2299 m_pc = SLIST_FIRST(&free);
2300 SLIST_REMOVE_HEAD(&free, plinks.s.ss);
2301 /* Recycle a freed page table page. */
2302 m_pc->wire_count = 1;
2303 atomic_add_int(&vm_cnt.v_wire_count, 1);
2304 }
2305 pmap_free_zero_pages(&free);
2306 return (m_pc);
2307 }
2308
2309 /*
2310 * free the pv_entry back to the free list
2311 */
2312 static void
2313 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2314 {
2315 struct pv_chunk *pc;
2316 int idx, field, bit;
2317
2318 rw_assert(&pvh_global_lock, RA_WLOCKED);
2319 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2320 PV_STAT(pv_entry_frees++);
2321 PV_STAT(pv_entry_spare++);
2322 pv_entry_count--;
2323 pc = pv_to_chunk(pv);
2324 idx = pv - &pc->pc_pventry[0];
2325 field = idx / 32;
2326 bit = idx % 32;
2327 pc->pc_map[field] |= 1ul << bit;
2328 for (idx = 0; idx < _NPCM; idx++)
2329 if (pc->pc_map[idx] != pc_freemask[idx]) {
2330 /*
2331 * 98% of the time, pc is already at the head of the
2332 * list. If it isn't already, move it to the head.
2333 */
2334 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
2335 pc)) {
2336 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2337 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
2338 pc_list);
2339 }
2340 return;
2341 }
2342 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2343 free_pv_chunk(pc);
2344 }
2345
2346 static void
2347 free_pv_chunk(struct pv_chunk *pc)
2348 {
2349 vm_page_t m;
2350
2351 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
2352 PV_STAT(pv_entry_spare -= _NPCPV);
2353 PV_STAT(pc_chunk_count--);
2354 PV_STAT(pc_chunk_frees++);
2355 /* entire chunk is free, return it */
2356 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2357 pmap_qremove((vm_offset_t)pc, 1);
2358 vm_page_unwire(m, PQ_NONE);
2359 vm_page_free(m);
2360 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2361 }
2362
2363 /*
2364 * get a new pv_entry, allocating a block from the system
2365 * when needed.
2366 */
2367 static pv_entry_t
2368 get_pv_entry(pmap_t pmap, boolean_t try)
2369 {
2370 static const struct timeval printinterval = { 60, 0 };
2371 static struct timeval lastprint;
2372 int bit, field;
2373 pv_entry_t pv;
2374 struct pv_chunk *pc;
2375 vm_page_t m;
2376
2377 rw_assert(&pvh_global_lock, RA_WLOCKED);
2378 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2379 PV_STAT(pv_entry_allocs++);
2380 pv_entry_count++;
2381 if (pv_entry_count > pv_entry_high_water)
2382 if (ratecheck(&lastprint, &printinterval))
2383 printf("Approaching the limit on PV entries, consider "
2384 "increasing either the vm.pmap.shpgperproc or the "
2385 "vm.pmap.pv_entry_max tunable.\n");
2386 retry:
2387 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2388 if (pc != NULL) {
2389 for (field = 0; field < _NPCM; field++) {
2390 if (pc->pc_map[field]) {
2391 bit = bsfl(pc->pc_map[field]);
2392 break;
2393 }
2394 }
2395 if (field < _NPCM) {
2396 pv = &pc->pc_pventry[field * 32 + bit];
2397 pc->pc_map[field] &= ~(1ul << bit);
2398 /* If this was the last item, move it to tail */
2399 for (field = 0; field < _NPCM; field++)
2400 if (pc->pc_map[field] != 0) {
2401 PV_STAT(pv_entry_spare--);
2402 return (pv); /* not full, return */
2403 }
2404 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2405 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2406 PV_STAT(pv_entry_spare--);
2407 return (pv);
2408 }
2409 }
2410 /*
2411 * Access to the ptelist "pv_vafree" is synchronized by the pvh
2412 * global lock. If "pv_vafree" is currently non-empty, it will
2413 * remain non-empty until pmap_ptelist_alloc() completes.
2414 */
2415 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL |
2416 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2417 if (try) {
2418 pv_entry_count--;
2419 PV_STAT(pc_chunk_tryfail++);
2420 return (NULL);
2421 }
2422 m = pmap_pv_reclaim(pmap);
2423 if (m == NULL)
2424 goto retry;
2425 }
2426 PV_STAT(pc_chunk_count++);
2427 PV_STAT(pc_chunk_allocs++);
2428 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2429 pmap_qenter((vm_offset_t)pc, &m, 1);
2430 pc->pc_pmap = pmap;
2431 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2432 for (field = 1; field < _NPCM; field++)
2433 pc->pc_map[field] = pc_freemask[field];
2434 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
2435 pv = &pc->pc_pventry[0];
2436 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2437 PV_STAT(pv_entry_spare += _NPCPV - 1);
2438 return (pv);
2439 }
2440
2441 static __inline pv_entry_t
2442 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2443 {
2444 pv_entry_t pv;
2445
2446 rw_assert(&pvh_global_lock, RA_WLOCKED);
2447 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
2448 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2449 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
2450 break;
2451 }
2452 }
2453 return (pv);
2454 }
2455
2456 static void
2457 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2458 {
2459 struct md_page *pvh;
2460 pv_entry_t pv;
2461 vm_offset_t va_last;
2462 vm_page_t m;
2463
2464 rw_assert(&pvh_global_lock, RA_WLOCKED);
2465 KASSERT((pa & PDRMASK) == 0,
2466 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2467
2468 /*
2469 * Transfer the 4mpage's pv entry for this mapping to the first
2470 * page's pv list.
2471 */
2472 pvh = pa_to_pvh(pa);
2473 va = trunc_4mpage(va);
2474 pv = pmap_pvh_remove(pvh, pmap, va);
2475 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2476 m = PHYS_TO_VM_PAGE(pa);
2477 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2478 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2479 va_last = va + NBPDR - PAGE_SIZE;
2480 do {
2481 m++;
2482 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2483 ("pmap_pv_demote_pde: page %p is not managed", m));
2484 va += PAGE_SIZE;
2485 pmap_insert_entry(pmap, va, m);
2486 } while (va < va_last);
2487 }
2488
2489 static void
2490 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2491 {
2492 struct md_page *pvh;
2493 pv_entry_t pv;
2494 vm_offset_t va_last;
2495 vm_page_t m;
2496
2497 rw_assert(&pvh_global_lock, RA_WLOCKED);
2498 KASSERT((pa & PDRMASK) == 0,
2499 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2500
2501 /*
2502 * Transfer the first page's pv entry for this mapping to the
2503 * 4mpage's pv list. Aside from avoiding the cost of a call
2504 * to get_pv_entry(), a transfer avoids the possibility that
2505 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2506 * removes one of the mappings that is being promoted.
2507 */
2508 m = PHYS_TO_VM_PAGE(pa);
2509 va = trunc_4mpage(va);
2510 pv = pmap_pvh_remove(&m->md, pmap, va);
2511 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2512 pvh = pa_to_pvh(pa);
2513 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2514 /* Free the remaining NPTEPG - 1 pv entries. */
2515 va_last = va + NBPDR - PAGE_SIZE;
2516 do {
2517 m++;
2518 va += PAGE_SIZE;
2519 pmap_pvh_free(&m->md, pmap, va);
2520 } while (va < va_last);
2521 }
2522
2523 static void
2524 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2525 {
2526 pv_entry_t pv;
2527
2528 pv = pmap_pvh_remove(pvh, pmap, va);
2529 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2530 free_pv_entry(pmap, pv);
2531 }
2532
2533 static void
2534 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2535 {
2536 struct md_page *pvh;
2537
2538 rw_assert(&pvh_global_lock, RA_WLOCKED);
2539 pmap_pvh_free(&m->md, pmap, va);
2540 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) {
2541 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2542 if (TAILQ_EMPTY(&pvh->pv_list))
2543 vm_page_aflag_clear(m, PGA_WRITEABLE);
2544 }
2545 }
2546
2547 /*
2548 * Create a pv entry for page at pa for
2549 * (pmap, va).
2550 */
2551 static void
2552 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2553 {
2554 pv_entry_t pv;
2555
2556 rw_assert(&pvh_global_lock, RA_WLOCKED);
2557 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2558 pv = get_pv_entry(pmap, FALSE);
2559 pv->pv_va = va;
2560 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2561 }
2562
2563 /*
2564 * Conditionally create a pv entry.
2565 */
2566 static boolean_t
2567 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2568 {
2569 pv_entry_t pv;
2570
2571 rw_assert(&pvh_global_lock, RA_WLOCKED);
2572 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2573 if (pv_entry_count < pv_entry_high_water &&
2574 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2575 pv->pv_va = va;
2576 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
2577 return (TRUE);
2578 } else
2579 return (FALSE);
2580 }
2581
2582 /*
2583 * Create the pv entries for each of the pages within a superpage.
2584 */
2585 static boolean_t
2586 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2587 {
2588 struct md_page *pvh;
2589 pv_entry_t pv;
2590
2591 rw_assert(&pvh_global_lock, RA_WLOCKED);
2592 if (pv_entry_count < pv_entry_high_water &&
2593 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2594 pv->pv_va = va;
2595 pvh = pa_to_pvh(pa);
2596 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
2597 return (TRUE);
2598 } else
2599 return (FALSE);
2600 }
2601
2602 /*
2603 * Fills a page table page with mappings to consecutive physical pages.
2604 */
2605 static void
2606 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2607 {
2608 pt_entry_t *pte;
2609
2610 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2611 *pte = newpte;
2612 newpte += PAGE_SIZE;
2613 }
2614 }
2615
2616 /*
2617 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2618 * 2- or 4MB page mapping is invalidated.
2619 */
2620 static boolean_t
2621 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2622 {
2623 pd_entry_t newpde, oldpde;
2624 pt_entry_t *firstpte, newpte;
2625 vm_paddr_t mptepa;
2626 vm_page_t mpte;
2627 struct spglist free;
2628
2629 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2630 oldpde = *pde;
2631 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2632 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2633 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) !=
2634 NULL)
2635 pmap_remove_pt_page(pmap, mpte);
2636 else {
2637 KASSERT((oldpde & PG_W) == 0,
2638 ("pmap_demote_pde: page table page for a wired mapping"
2639 " is missing"));
2640
2641 /*
2642 * Invalidate the 2- or 4MB page mapping and return
2643 * "failure" if the mapping was never accessed or the
2644 * allocation of the new page table page fails.
2645 */
2646 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2647 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2648 VM_ALLOC_WIRED)) == NULL) {
2649 SLIST_INIT(&free);
2650 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free);
2651 pmap_invalidate_page(pmap, trunc_4mpage(va));
2652 pmap_free_zero_pages(&free);
2653 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2654 " in pmap %p", va, pmap);
2655 return (FALSE);
2656 }
2657 if (va < VM_MAXUSER_ADDRESS)
2658 pmap->pm_stats.resident_count++;
2659 }
2660 mptepa = VM_PAGE_TO_PHYS(mpte);
2661
2662 /*
2663 * If the page mapping is in the kernel's address space, then the
2664 * KPTmap can provide access to the page table page. Otherwise,
2665 * temporarily map the page table page (mpte) into the kernel's
2666 * address space at either PADDR1 or PADDR2.
2667 */
2668 if (va >= KERNBASE)
2669 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2670 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) {
2671 if ((*PMAP1 & PG_FRAME) != mptepa) {
2672 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2673 #ifdef SMP
2674 PMAP1cpu = PCPU_GET(cpuid);
2675 #endif
2676 invlcaddr(PADDR1);
2677 PMAP1changed++;
2678 } else
2679 #ifdef SMP
2680 if (PMAP1cpu != PCPU_GET(cpuid)) {
2681 PMAP1cpu = PCPU_GET(cpuid);
2682 invlcaddr(PADDR1);
2683 PMAP1changedcpu++;
2684 } else
2685 #endif
2686 PMAP1unchanged++;
2687 firstpte = PADDR1;
2688 } else {
2689 mtx_lock(&PMAP2mutex);
2690 if ((*PMAP2 & PG_FRAME) != mptepa) {
2691 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2692 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2693 }
2694 firstpte = PADDR2;
2695 }
2696 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2697 KASSERT((oldpde & PG_A) != 0,
2698 ("pmap_demote_pde: oldpde is missing PG_A"));
2699 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2700 ("pmap_demote_pde: oldpde is missing PG_M"));
2701 newpte = oldpde & ~PG_PS;
2702 if ((newpte & PG_PDE_PAT) != 0)
2703 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2704
2705 /*
2706 * If the page table page is new, initialize it.
2707 */
2708 if (mpte->wire_count == 1) {
2709 mpte->wire_count = NPTEPG;
2710 pmap_fill_ptp(firstpte, newpte);
2711 }
2712 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2713 ("pmap_demote_pde: firstpte and newpte map different physical"
2714 " addresses"));
2715
2716 /*
2717 * If the mapping has changed attributes, update the page table
2718 * entries.
2719 */
2720 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2721 pmap_fill_ptp(firstpte, newpte);
2722
2723 /*
2724 * Demote the mapping. This pmap is locked. The old PDE has
2725 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2726 * set. Thus, there is no danger of a race with another
2727 * processor changing the setting of PG_A and/or PG_M between
2728 * the read above and the store below.
2729 */
2730 if (workaround_erratum383)
2731 pmap_update_pde(pmap, va, pde, newpde);
2732 else if (pmap == kernel_pmap)
2733 pmap_kenter_pde(va, newpde);
2734 else
2735 pde_store(pde, newpde);
2736 if (firstpte == PADDR2)
2737 mtx_unlock(&PMAP2mutex);
2738
2739 /*
2740 * Invalidate the recursive mapping of the page table page.
2741 */
2742 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2743
2744 /*
2745 * Demote the pv entry. This depends on the earlier demotion
2746 * of the mapping. Specifically, the (re)creation of a per-
2747 * page pv entry might trigger the execution of pmap_collect(),
2748 * which might reclaim a newly (re)created per-page pv entry
2749 * and destroy the associated mapping. In order to destroy
2750 * the mapping, the PDE must have already changed from mapping
2751 * the 2mpage to referencing the page table page.
2752 */
2753 if ((oldpde & PG_MANAGED) != 0)
2754 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2755
2756 pmap_pde_demotions++;
2757 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2758 " in pmap %p", va, pmap);
2759 return (TRUE);
2760 }
2761
2762 /*
2763 * Removes a 2- or 4MB page mapping from the kernel pmap.
2764 */
2765 static void
2766 pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2767 {
2768 pd_entry_t newpde;
2769 vm_paddr_t mptepa;
2770 vm_page_t mpte;
2771
2772 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2773 mpte = pmap_lookup_pt_page(pmap, va);
2774 if (mpte == NULL)
2775 panic("pmap_remove_kernel_pde: Missing pt page.");
2776
2777 pmap_remove_pt_page(pmap, mpte);
2778 mptepa = VM_PAGE_TO_PHYS(mpte);
2779 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V;
2780
2781 /*
2782 * Initialize the page table page.
2783 */
2784 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]);
2785
2786 /*
2787 * Remove the mapping.
2788 */
2789 if (workaround_erratum383)
2790 pmap_update_pde(pmap, va, pde, newpde);
2791 else
2792 pmap_kenter_pde(va, newpde);
2793
2794 /*
2795 * Invalidate the recursive mapping of the page table page.
2796 */
2797 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2798 }
2799
2800 /*
2801 * pmap_remove_pde: do the things to unmap a superpage in a process
2802 */
2803 static void
2804 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2805 struct spglist *free)
2806 {
2807 struct md_page *pvh;
2808 pd_entry_t oldpde;
2809 vm_offset_t eva, va;
2810 vm_page_t m, mpte;
2811
2812 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2813 KASSERT((sva & PDRMASK) == 0,
2814 ("pmap_remove_pde: sva is not 4mpage aligned"));
2815 oldpde = pte_load_clear(pdq);
2816 if (oldpde & PG_W)
2817 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2818
2819 /*
2820 * Machines that don't support invlpg, also don't support
2821 * PG_G.
2822 */
2823 if (oldpde & PG_G)
2824 pmap_invalidate_page(kernel_pmap, sva);
2825 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2826 if (oldpde & PG_MANAGED) {
2827 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2828 pmap_pvh_free(pvh, pmap, sva);
2829 eva = sva + NBPDR;
2830 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2831 va < eva; va += PAGE_SIZE, m++) {
2832 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2833 vm_page_dirty(m);
2834 if (oldpde & PG_A)
2835 vm_page_aflag_set(m, PGA_REFERENCED);
2836 if (TAILQ_EMPTY(&m->md.pv_list) &&
2837 TAILQ_EMPTY(&pvh->pv_list))
2838 vm_page_aflag_clear(m, PGA_WRITEABLE);
2839 }
2840 }
2841 if (pmap == kernel_pmap) {
2842 pmap_remove_kernel_pde(pmap, pdq, sva);
2843 } else {
2844 mpte = pmap_lookup_pt_page(pmap, sva);
2845 if (mpte != NULL) {
2846 pmap_remove_pt_page(pmap, mpte);
2847 pmap->pm_stats.resident_count--;
2848 KASSERT(mpte->wire_count == NPTEPG,
2849 ("pmap_remove_pde: pte page wire count error"));
2850 mpte->wire_count = 0;
2851 pmap_add_delayed_free_list(mpte, free, FALSE);
2852 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
2853 }
2854 }
2855 }
2856
2857 /*
2858 * pmap_remove_pte: do the things to unmap a page in a process
2859 */
2860 static int
2861 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va,
2862 struct spglist *free)
2863 {
2864 pt_entry_t oldpte;
2865 vm_page_t m;
2866
2867 rw_assert(&pvh_global_lock, RA_WLOCKED);
2868 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2869 oldpte = pte_load_clear(ptq);
2870 KASSERT(oldpte != 0,
2871 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va));
2872 if (oldpte & PG_W)
2873 pmap->pm_stats.wired_count -= 1;
2874 /*
2875 * Machines that don't support invlpg, also don't support
2876 * PG_G.
2877 */
2878 if (oldpte & PG_G)
2879 pmap_invalidate_page(kernel_pmap, va);
2880 pmap->pm_stats.resident_count -= 1;
2881 if (oldpte & PG_MANAGED) {
2882 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2883 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2884 vm_page_dirty(m);
2885 if (oldpte & PG_A)
2886 vm_page_aflag_set(m, PGA_REFERENCED);
2887 pmap_remove_entry(pmap, m, va);
2888 }
2889 return (pmap_unuse_pt(pmap, va, free));
2890 }
2891
2892 /*
2893 * Remove a single page from a process address space
2894 */
2895 static void
2896 pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free)
2897 {
2898 pt_entry_t *pte;
2899
2900 rw_assert(&pvh_global_lock, RA_WLOCKED);
2901 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2902 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2903 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2904 return;
2905 pmap_remove_pte(pmap, pte, va, free);
2906 pmap_invalidate_page(pmap, va);
2907 }
2908
2909 /*
2910 * Remove the given range of addresses from the specified map.
2911 *
2912 * It is assumed that the start and end are properly
2913 * rounded to the page size.
2914 */
2915 void
2916 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2917 {
2918 vm_offset_t pdnxt;
2919 pd_entry_t ptpaddr;
2920 pt_entry_t *pte;
2921 struct spglist free;
2922 int anyvalid;
2923
2924 /*
2925 * Perform an unsynchronized read. This is, however, safe.
2926 */
2927 if (pmap->pm_stats.resident_count == 0)
2928 return;
2929
2930 anyvalid = 0;
2931 SLIST_INIT(&free);
2932
2933 rw_wlock(&pvh_global_lock);
2934 sched_pin();
2935 PMAP_LOCK(pmap);
2936
2937 /*
2938 * special handling of removing one page. a very
2939 * common operation and easy to short circuit some
2940 * code.
2941 */
2942 if ((sva + PAGE_SIZE == eva) &&
2943 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2944 pmap_remove_page(pmap, sva, &free);
2945 goto out;
2946 }
2947
2948 for (; sva < eva; sva = pdnxt) {
2949 u_int pdirindex;
2950
2951 /*
2952 * Calculate index for next page table.
2953 */
2954 pdnxt = (sva + NBPDR) & ~PDRMASK;
2955 if (pdnxt < sva)
2956 pdnxt = eva;
2957 if (pmap->pm_stats.resident_count == 0)
2958 break;
2959
2960 pdirindex = sva >> PDRSHIFT;
2961 ptpaddr = pmap->pm_pdir[pdirindex];
2962
2963 /*
2964 * Weed out invalid mappings. Note: we assume that the page
2965 * directory table is always allocated, and in kernel virtual.
2966 */
2967 if (ptpaddr == 0)
2968 continue;
2969
2970 /*
2971 * Check for large page.
2972 */
2973 if ((ptpaddr & PG_PS) != 0) {
2974 /*
2975 * Are we removing the entire large page? If not,
2976 * demote the mapping and fall through.
2977 */
2978 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2979 /*
2980 * The TLB entry for a PG_G mapping is
2981 * invalidated by pmap_remove_pde().
2982 */
2983 if ((ptpaddr & PG_G) == 0)
2984 anyvalid = 1;
2985 pmap_remove_pde(pmap,
2986 &pmap->pm_pdir[pdirindex], sva, &free);
2987 continue;
2988 } else if (!pmap_demote_pde(pmap,
2989 &pmap->pm_pdir[pdirindex], sva)) {
2990 /* The large page mapping was destroyed. */
2991 continue;
2992 }
2993 }
2994
2995 /*
2996 * Limit our scan to either the end of the va represented
2997 * by the current page table page, or to the end of the
2998 * range being removed.
2999 */
3000 if (pdnxt > eva)
3001 pdnxt = eva;
3002
3003 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3004 sva += PAGE_SIZE) {
3005 if (*pte == 0)
3006 continue;
3007
3008 /*
3009 * The TLB entry for a PG_G mapping is invalidated
3010 * by pmap_remove_pte().
3011 */
3012 if ((*pte & PG_G) == 0)
3013 anyvalid = 1;
3014 if (pmap_remove_pte(pmap, pte, sva, &free))
3015 break;
3016 }
3017 }
3018 out:
3019 sched_unpin();
3020 if (anyvalid)
3021 pmap_invalidate_all(pmap);
3022 rw_wunlock(&pvh_global_lock);
3023 PMAP_UNLOCK(pmap);
3024 pmap_free_zero_pages(&free);
3025 }
3026
3027 /*
3028 * Routine: pmap_remove_all
3029 * Function:
3030 * Removes this physical page from
3031 * all physical maps in which it resides.
3032 * Reflects back modify bits to the pager.
3033 *
3034 * Notes:
3035 * Original versions of this routine were very
3036 * inefficient because they iteratively called
3037 * pmap_remove (slow...)
3038 */
3039
3040 void
3041 pmap_remove_all(vm_page_t m)
3042 {
3043 struct md_page *pvh;
3044 pv_entry_t pv;
3045 pmap_t pmap;
3046 pt_entry_t *pte, tpte;
3047 pd_entry_t *pde;
3048 vm_offset_t va;
3049 struct spglist free;
3050
3051 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3052 ("pmap_remove_all: page %p is not managed", m));
3053 SLIST_INIT(&free);
3054 rw_wlock(&pvh_global_lock);
3055 sched_pin();
3056 if ((m->flags & PG_FICTITIOUS) != 0)
3057 goto small_mappings;
3058 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
3059 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
3060 va = pv->pv_va;
3061 pmap = PV_PMAP(pv);
3062 PMAP_LOCK(pmap);
3063 pde = pmap_pde(pmap, va);
3064 (void)pmap_demote_pde(pmap, pde, va);
3065 PMAP_UNLOCK(pmap);
3066 }
3067 small_mappings:
3068 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
3069 pmap = PV_PMAP(pv);
3070 PMAP_LOCK(pmap);
3071 pmap->pm_stats.resident_count--;
3072 pde = pmap_pde(pmap, pv->pv_va);
3073 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
3074 " a 4mpage in page %p's pv list", m));
3075 pte = pmap_pte_quick(pmap, pv->pv_va);
3076 tpte = pte_load_clear(pte);
3077 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte",
3078 pmap, pv->pv_va));
3079 if (tpte & PG_W)
3080 pmap->pm_stats.wired_count--;
3081 if (tpte & PG_A)
3082 vm_page_aflag_set(m, PGA_REFERENCED);
3083
3084 /*
3085 * Update the vm_page_t clean and reference bits.
3086 */
3087 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
3088 vm_page_dirty(m);
3089 pmap_unuse_pt(pmap, pv->pv_va, &free);
3090 pmap_invalidate_page(pmap, pv->pv_va);
3091 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
3092 free_pv_entry(pmap, pv);
3093 PMAP_UNLOCK(pmap);
3094 }
3095 vm_page_aflag_clear(m, PGA_WRITEABLE);
3096 sched_unpin();
3097 rw_wunlock(&pvh_global_lock);
3098 pmap_free_zero_pages(&free);
3099 }
3100
3101 /*
3102 * pmap_protect_pde: do the things to protect a 4mpage in a process
3103 */
3104 static boolean_t
3105 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3106 {
3107 pd_entry_t newpde, oldpde;
3108 vm_offset_t eva, va;
3109 vm_page_t m;
3110 boolean_t anychanged;
3111
3112 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3113 KASSERT((sva & PDRMASK) == 0,
3114 ("pmap_protect_pde: sva is not 4mpage aligned"));
3115 anychanged = FALSE;
3116 retry:
3117 oldpde = newpde = *pde;
3118 if (oldpde & PG_MANAGED) {
3119 eva = sva + NBPDR;
3120 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3121 va < eva; va += PAGE_SIZE, m++)
3122 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3123 vm_page_dirty(m);
3124 }
3125 if ((prot & VM_PROT_WRITE) == 0)
3126 newpde &= ~(PG_RW | PG_M);
3127 #if defined(PAE) || defined(PAE_TABLES)
3128 if ((prot & VM_PROT_EXECUTE) == 0)
3129 newpde |= pg_nx;
3130 #endif
3131 if (newpde != oldpde) {
3132 if (!pde_cmpset(pde, oldpde, newpde))
3133 goto retry;
3134 if (oldpde & PG_G)
3135 pmap_invalidate_page(pmap, sva);
3136 else
3137 anychanged = TRUE;
3138 }
3139 return (anychanged);
3140 }
3141
3142 /*
3143 * Set the physical protection on the
3144 * specified range of this map as requested.
3145 */
3146 void
3147 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3148 {
3149 vm_offset_t pdnxt;
3150 pd_entry_t ptpaddr;
3151 pt_entry_t *pte;
3152 boolean_t anychanged, pv_lists_locked;
3153
3154 KASSERT((prot & ~VM_PROT_ALL) == 0, ("invalid prot %x", prot));
3155 if (prot == VM_PROT_NONE) {
3156 pmap_remove(pmap, sva, eva);
3157 return;
3158 }
3159
3160 #if defined(PAE) || defined(PAE_TABLES)
3161 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3162 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3163 return;
3164 #else
3165 if (prot & VM_PROT_WRITE)
3166 return;
3167 #endif
3168
3169 if (pmap_is_current(pmap))
3170 pv_lists_locked = FALSE;
3171 else {
3172 pv_lists_locked = TRUE;
3173 resume:
3174 rw_wlock(&pvh_global_lock);
3175 sched_pin();
3176 }
3177 anychanged = FALSE;
3178
3179 PMAP_LOCK(pmap);
3180 for (; sva < eva; sva = pdnxt) {
3181 pt_entry_t obits, pbits;
3182 u_int pdirindex;
3183
3184 pdnxt = (sva + NBPDR) & ~PDRMASK;
3185 if (pdnxt < sva)
3186 pdnxt = eva;
3187
3188 pdirindex = sva >> PDRSHIFT;
3189 ptpaddr = pmap->pm_pdir[pdirindex];
3190
3191 /*
3192 * Weed out invalid mappings. Note: we assume that the page
3193 * directory table is always allocated, and in kernel virtual.
3194 */
3195 if (ptpaddr == 0)
3196 continue;
3197
3198 /*
3199 * Check for large page.
3200 */
3201 if ((ptpaddr & PG_PS) != 0) {
3202 /*
3203 * Are we protecting the entire large page? If not,
3204 * demote the mapping and fall through.
3205 */
3206 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3207 /*
3208 * The TLB entry for a PG_G mapping is
3209 * invalidated by pmap_protect_pde().
3210 */
3211 if (pmap_protect_pde(pmap,
3212 &pmap->pm_pdir[pdirindex], sva, prot))
3213 anychanged = TRUE;
3214 continue;
3215 } else {
3216 if (!pv_lists_locked) {
3217 pv_lists_locked = TRUE;
3218 if (!rw_try_wlock(&pvh_global_lock)) {
3219 if (anychanged)
3220 pmap_invalidate_all(
3221 pmap);
3222 PMAP_UNLOCK(pmap);
3223 goto resume;
3224 }
3225 sched_pin();
3226 }
3227 if (!pmap_demote_pde(pmap,
3228 &pmap->pm_pdir[pdirindex], sva)) {
3229 /*
3230 * The large page mapping was
3231 * destroyed.
3232 */
3233 continue;
3234 }
3235 }
3236 }
3237
3238 if (pdnxt > eva)
3239 pdnxt = eva;
3240
3241 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3242 sva += PAGE_SIZE) {
3243 vm_page_t m;
3244
3245 retry:
3246 /*
3247 * Regardless of whether a pte is 32 or 64 bits in
3248 * size, PG_RW, PG_A, and PG_M are among the least
3249 * significant 32 bits.
3250 */
3251 obits = pbits = *pte;
3252 if ((pbits & PG_V) == 0)
3253 continue;
3254
3255 if ((prot & VM_PROT_WRITE) == 0) {
3256 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) ==
3257 (PG_MANAGED | PG_M | PG_RW)) {
3258 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3259 vm_page_dirty(m);
3260 }
3261 pbits &= ~(PG_RW | PG_M);
3262 }
3263 #if defined(PAE) || defined(PAE_TABLES)
3264 if ((prot & VM_PROT_EXECUTE) == 0)
3265 pbits |= pg_nx;
3266 #endif
3267
3268 if (pbits != obits) {
3269 #if defined(PAE) || defined(PAE_TABLES)
3270 if (!atomic_cmpset_64(pte, obits, pbits))
3271 goto retry;
3272 #else
3273 if (!atomic_cmpset_int((u_int *)pte, obits,
3274 pbits))
3275 goto retry;
3276 #endif
3277 if (obits & PG_G)
3278 pmap_invalidate_page(pmap, sva);
3279 else
3280 anychanged = TRUE;
3281 }
3282 }
3283 }
3284 if (anychanged)
3285 pmap_invalidate_all(pmap);
3286 if (pv_lists_locked) {
3287 sched_unpin();
3288 rw_wunlock(&pvh_global_lock);
3289 }
3290 PMAP_UNLOCK(pmap);
3291 }
3292
3293 /*
3294 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3295 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3296 * For promotion to occur, two conditions must be met: (1) the 4KB page
3297 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3298 * mappings must have identical characteristics.
3299 *
3300 * Managed (PG_MANAGED) mappings within the kernel address space are not
3301 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3302 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3303 * pmap.
3304 */
3305 static void
3306 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3307 {
3308 pd_entry_t newpde;
3309 pt_entry_t *firstpte, oldpte, pa, *pte;
3310 vm_offset_t oldpteva;
3311 vm_page_t mpte;
3312
3313 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3314
3315 /*
3316 * Examine the first PTE in the specified PTP. Abort if this PTE is
3317 * either invalid, unused, or does not map the first 4KB physical page
3318 * within a 2- or 4MB page.
3319 */
3320 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3321 setpde:
3322 newpde = *firstpte;
3323 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3324 pmap_pde_p_failures++;
3325 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3326 " in pmap %p", va, pmap);
3327 return;
3328 }
3329 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3330 pmap_pde_p_failures++;
3331 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3332 " in pmap %p", va, pmap);
3333 return;
3334 }
3335 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3336 /*
3337 * When PG_M is already clear, PG_RW can be cleared without
3338 * a TLB invalidation.
3339 */
3340 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3341 ~PG_RW))
3342 goto setpde;
3343 newpde &= ~PG_RW;
3344 }
3345
3346 /*
3347 * Examine each of the other PTEs in the specified PTP. Abort if this
3348 * PTE maps an unexpected 4KB physical page or does not have identical
3349 * characteristics to the first PTE.
3350 */
3351 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3352 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3353 setpte:
3354 oldpte = *pte;
3355 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3356 pmap_pde_p_failures++;
3357 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3358 " in pmap %p", va, pmap);
3359 return;
3360 }
3361 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3362 /*
3363 * When PG_M is already clear, PG_RW can be cleared
3364 * without a TLB invalidation.
3365 */
3366 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3367 oldpte & ~PG_RW))
3368 goto setpte;
3369 oldpte &= ~PG_RW;
3370 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3371 (va & ~PDRMASK);
3372 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3373 " in pmap %p", oldpteva, pmap);
3374 }
3375 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3376 pmap_pde_p_failures++;
3377 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3378 " in pmap %p", va, pmap);
3379 return;
3380 }
3381 pa -= PAGE_SIZE;
3382 }
3383
3384 /*
3385 * Save the page table page in its current state until the PDE
3386 * mapping the superpage is demoted by pmap_demote_pde() or
3387 * destroyed by pmap_remove_pde().
3388 */
3389 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3390 KASSERT(mpte >= vm_page_array &&
3391 mpte < &vm_page_array[vm_page_array_size],
3392 ("pmap_promote_pde: page table page is out of range"));
3393 KASSERT(mpte->pindex == va >> PDRSHIFT,
3394 ("pmap_promote_pde: page table page's pindex is wrong"));
3395 if (pmap_insert_pt_page(pmap, mpte)) {
3396 pmap_pde_p_failures++;
3397 CTR2(KTR_PMAP,
3398 "pmap_promote_pde: failure for va %#x in pmap %p", va,
3399 pmap);
3400 return;
3401 }
3402
3403 /*
3404 * Promote the pv entries.
3405 */
3406 if ((newpde & PG_MANAGED) != 0)
3407 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3408
3409 /*
3410 * Propagate the PAT index to its proper position.
3411 */
3412 if ((newpde & PG_PTE_PAT) != 0)
3413 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3414
3415 /*
3416 * Map the superpage.
3417 */
3418 if (workaround_erratum383)
3419 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3420 else if (pmap == kernel_pmap)
3421 pmap_kenter_pde(va, PG_PS | newpde);
3422 else
3423 pde_store(pde, PG_PS | newpde);
3424
3425 pmap_pde_promotions++;
3426 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3427 " in pmap %p", va, pmap);
3428 }
3429
3430 /*
3431 * Insert the given physical page (p) at
3432 * the specified virtual address (v) in the
3433 * target physical map with the protection requested.
3434 *
3435 * If specified, the page will be wired down, meaning
3436 * that the related pte can not be reclaimed.
3437 *
3438 * NB: This is the only routine which MAY NOT lazy-evaluate
3439 * or lose information. That is, this routine must actually
3440 * insert this page into the given map NOW.
3441 */
3442 int
3443 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
3444 u_int flags, int8_t psind)
3445 {
3446 pd_entry_t *pde;
3447 pt_entry_t *pte;
3448 pt_entry_t newpte, origpte;
3449 pv_entry_t pv;
3450 vm_paddr_t opa, pa;
3451 vm_page_t mpte, om;
3452 boolean_t invlva, wired;
3453
3454 va = trunc_page(va);
3455 mpte = NULL;
3456 wired = (flags & PMAP_ENTER_WIRED) != 0;
3457
3458 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3459 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3460 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)",
3461 va));
3462 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
3463 VM_OBJECT_ASSERT_LOCKED(m->object);
3464
3465 rw_wlock(&pvh_global_lock);
3466 PMAP_LOCK(pmap);
3467 sched_pin();
3468
3469 /*
3470 * In the case that a page table page is not
3471 * resident, we are creating it here.
3472 */
3473 if (va < VM_MAXUSER_ADDRESS) {
3474 mpte = pmap_allocpte(pmap, va, flags);
3475 if (mpte == NULL) {
3476 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
3477 ("pmap_allocpte failed with sleep allowed"));
3478 sched_unpin();
3479 rw_wunlock(&pvh_global_lock);
3480 PMAP_UNLOCK(pmap);
3481 return (KERN_RESOURCE_SHORTAGE);
3482 }
3483 }
3484
3485 pde = pmap_pde(pmap, va);
3486 if ((*pde & PG_PS) != 0)
3487 panic("pmap_enter: attempted pmap_enter on 4MB page");
3488 pte = pmap_pte_quick(pmap, va);
3489
3490 /*
3491 * Page Directory table entry not valid, we need a new PT page
3492 */
3493 if (pte == NULL) {
3494 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3495 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3496 }
3497
3498 pa = VM_PAGE_TO_PHYS(m);
3499 om = NULL;
3500 origpte = *pte;
3501 opa = origpte & PG_FRAME;
3502
3503 /*
3504 * Mapping has not changed, must be protection or wiring change.
3505 */
3506 if (origpte && (opa == pa)) {
3507 /*
3508 * Wiring change, just update stats. We don't worry about
3509 * wiring PT pages as they remain resident as long as there
3510 * are valid mappings in them. Hence, if a user page is wired,
3511 * the PT page will be also.
3512 */
3513 if (wired && ((origpte & PG_W) == 0))
3514 pmap->pm_stats.wired_count++;
3515 else if (!wired && (origpte & PG_W))
3516 pmap->pm_stats.wired_count--;
3517
3518 /*
3519 * Remove extra pte reference
3520 */
3521 if (mpte)
3522 mpte->wire_count--;
3523
3524 if (origpte & PG_MANAGED) {
3525 om = m;
3526 pa |= PG_MANAGED;
3527 }
3528 goto validate;
3529 }
3530
3531 pv = NULL;
3532
3533 /*
3534 * Mapping has changed, invalidate old range and fall through to
3535 * handle validating new mapping.
3536 */
3537 if (opa) {
3538 if (origpte & PG_W)
3539 pmap->pm_stats.wired_count--;
3540 if (origpte & PG_MANAGED) {
3541 om = PHYS_TO_VM_PAGE(opa);
3542 pv = pmap_pvh_remove(&om->md, pmap, va);
3543 }
3544 if (mpte != NULL) {
3545 mpte->wire_count--;
3546 KASSERT(mpte->wire_count > 0,
3547 ("pmap_enter: missing reference to page table page,"
3548 " va: 0x%x", va));
3549 }
3550 } else
3551 pmap->pm_stats.resident_count++;
3552
3553 /*
3554 * Enter on the PV list if part of our managed memory.
3555 */
3556 if ((m->oflags & VPO_UNMANAGED) == 0) {
3557 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3558 ("pmap_enter: managed mapping within the clean submap"));
3559 if (pv == NULL)
3560 pv = get_pv_entry(pmap, FALSE);
3561 pv->pv_va = va;
3562 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
3563 pa |= PG_MANAGED;
3564 } else if (pv != NULL)
3565 free_pv_entry(pmap, pv);
3566
3567 /*
3568 * Increment counters
3569 */
3570 if (wired)
3571 pmap->pm_stats.wired_count++;
3572
3573 validate:
3574 /*
3575 * Now validate mapping with desired protection/wiring.
3576 */
3577 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3578 if ((prot & VM_PROT_WRITE) != 0) {
3579 newpte |= PG_RW;
3580 if ((newpte & PG_MANAGED) != 0)
3581 vm_page_aflag_set(m, PGA_WRITEABLE);
3582 }
3583 #if defined(PAE) || defined(PAE_TABLES)
3584 if ((prot & VM_PROT_EXECUTE) == 0)
3585 newpte |= pg_nx;
3586 #endif
3587 if (wired)
3588 newpte |= PG_W;
3589 if (va < VM_MAXUSER_ADDRESS)
3590 newpte |= PG_U;
3591 if (pmap == kernel_pmap)
3592 newpte |= pgeflag;
3593
3594 /*
3595 * if the mapping or permission bits are different, we need
3596 * to update the pte.
3597 */
3598 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3599 newpte |= PG_A;
3600 if ((flags & VM_PROT_WRITE) != 0)
3601 newpte |= PG_M;
3602 if (origpte & PG_V) {
3603 invlva = FALSE;
3604 origpte = pte_load_store(pte, newpte);
3605 if (origpte & PG_A) {
3606 if (origpte & PG_MANAGED)
3607 vm_page_aflag_set(om, PGA_REFERENCED);
3608 if (opa != VM_PAGE_TO_PHYS(m))
3609 invlva = TRUE;
3610 #if defined(PAE) || defined(PAE_TABLES)
3611 if ((origpte & PG_NX) == 0 &&
3612 (newpte & PG_NX) != 0)
3613 invlva = TRUE;
3614 #endif
3615 }
3616 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3617 if ((origpte & PG_MANAGED) != 0)
3618 vm_page_dirty(om);
3619 if ((prot & VM_PROT_WRITE) == 0)
3620 invlva = TRUE;
3621 }
3622 if ((origpte & PG_MANAGED) != 0 &&
3623 TAILQ_EMPTY(&om->md.pv_list) &&
3624 ((om->flags & PG_FICTITIOUS) != 0 ||
3625 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list)))
3626 vm_page_aflag_clear(om, PGA_WRITEABLE);
3627 if (invlva)
3628 pmap_invalidate_page(pmap, va);
3629 } else
3630 pte_store(pte, newpte);
3631 }
3632
3633 /*
3634 * If both the page table page and the reservation are fully
3635 * populated, then attempt promotion.
3636 */
3637 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3638 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 &&
3639 vm_reserv_level_iffullpop(m) == 0)
3640 pmap_promote_pde(pmap, pde, va);
3641
3642 sched_unpin();
3643 rw_wunlock(&pvh_global_lock);
3644 PMAP_UNLOCK(pmap);
3645 return (KERN_SUCCESS);
3646 }
3647
3648 /*
3649 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3650 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3651 * blocking, (2) a mapping already exists at the specified virtual address, or
3652 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3653 */
3654 static boolean_t
3655 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3656 {
3657 pd_entry_t *pde, newpde;
3658
3659 rw_assert(&pvh_global_lock, RA_WLOCKED);
3660 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3661 pde = pmap_pde(pmap, va);
3662 if (*pde != 0) {
3663 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3664 " in pmap %p", va, pmap);
3665 return (FALSE);
3666 }
3667 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3668 PG_PS | PG_V;
3669 if ((m->oflags & VPO_UNMANAGED) == 0) {
3670 newpde |= PG_MANAGED;
3671
3672 /*
3673 * Abort this mapping if its PV entry could not be created.
3674 */
3675 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3676 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3677 " in pmap %p", va, pmap);
3678 return (FALSE);
3679 }
3680 }
3681 #if defined(PAE) || defined(PAE_TABLES)
3682 if ((prot & VM_PROT_EXECUTE) == 0)
3683 newpde |= pg_nx;
3684 #endif
3685 if (va < VM_MAXUSER_ADDRESS)
3686 newpde |= PG_U;
3687
3688 /*
3689 * Increment counters.
3690 */
3691 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3692
3693 /*
3694 * Map the superpage.
3695 */
3696 pde_store(pde, newpde);
3697
3698 pmap_pde_mappings++;
3699 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3700 " in pmap %p", va, pmap);
3701 return (TRUE);
3702 }
3703
3704 /*
3705 * Maps a sequence of resident pages belonging to the same object.
3706 * The sequence begins with the given page m_start. This page is
3707 * mapped at the given virtual address start. Each subsequent page is
3708 * mapped at a virtual address that is offset from start by the same
3709 * amount as the page is offset from m_start within the object. The
3710 * last page in the sequence is the page with the largest offset from
3711 * m_start that can be mapped at a virtual address less than the given
3712 * virtual address end. Not every virtual page between start and end
3713 * is mapped; only those for which a resident page exists with the
3714 * corresponding offset from m_start are mapped.
3715 */
3716 void
3717 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3718 vm_page_t m_start, vm_prot_t prot)
3719 {
3720 vm_offset_t va;
3721 vm_page_t m, mpte;
3722 vm_pindex_t diff, psize;
3723
3724 VM_OBJECT_ASSERT_LOCKED(m_start->object);
3725
3726 psize = atop(end - start);
3727 mpte = NULL;
3728 m = m_start;
3729 rw_wlock(&pvh_global_lock);
3730 PMAP_LOCK(pmap);
3731 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3732 va = start + ptoa(diff);
3733 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3734 m->psind == 1 && pg_ps_enabled &&
3735 pmap_enter_pde(pmap, va, m, prot))
3736 m = &m[NBPDR / PAGE_SIZE - 1];
3737 else
3738 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3739 mpte);
3740 m = TAILQ_NEXT(m, listq);
3741 }
3742 rw_wunlock(&pvh_global_lock);
3743 PMAP_UNLOCK(pmap);
3744 }
3745
3746 /*
3747 * this code makes some *MAJOR* assumptions:
3748 * 1. Current pmap & pmap exists.
3749 * 2. Not wired.
3750 * 3. Read access.
3751 * 4. No page table pages.
3752 * but is *MUCH* faster than pmap_enter...
3753 */
3754
3755 void
3756 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3757 {
3758
3759 rw_wlock(&pvh_global_lock);
3760 PMAP_LOCK(pmap);
3761 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3762 rw_wunlock(&pvh_global_lock);
3763 PMAP_UNLOCK(pmap);
3764 }
3765
3766 static vm_page_t
3767 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3768 vm_prot_t prot, vm_page_t mpte)
3769 {
3770 pt_entry_t *pte;
3771 vm_paddr_t pa;
3772 struct spglist free;
3773
3774 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3775 (m->oflags & VPO_UNMANAGED) != 0,
3776 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3777 rw_assert(&pvh_global_lock, RA_WLOCKED);
3778 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3779
3780 /*
3781 * In the case that a page table page is not
3782 * resident, we are creating it here.
3783 */
3784 if (va < VM_MAXUSER_ADDRESS) {
3785 u_int ptepindex;
3786 pd_entry_t ptepa;
3787
3788 /*
3789 * Calculate pagetable page index
3790 */
3791 ptepindex = va >> PDRSHIFT;
3792 if (mpte && (mpte->pindex == ptepindex)) {
3793 mpte->wire_count++;
3794 } else {
3795 /*
3796 * Get the page directory entry
3797 */
3798 ptepa = pmap->pm_pdir[ptepindex];
3799
3800 /*
3801 * If the page table page is mapped, we just increment
3802 * the hold count, and activate it.
3803 */
3804 if (ptepa) {
3805 if (ptepa & PG_PS)
3806 return (NULL);
3807 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3808 mpte->wire_count++;
3809 } else {
3810 mpte = _pmap_allocpte(pmap, ptepindex,
3811 PMAP_ENTER_NOSLEEP);
3812 if (mpte == NULL)
3813 return (mpte);
3814 }
3815 }
3816 } else {
3817 mpte = NULL;
3818 }
3819
3820 /*
3821 * This call to vtopte makes the assumption that we are
3822 * entering the page into the current pmap. In order to support
3823 * quick entry into any pmap, one would likely use pmap_pte_quick.
3824 * But that isn't as quick as vtopte.
3825 */
3826 pte = vtopte(va);
3827 if (*pte) {
3828 if (mpte != NULL) {
3829 mpte->wire_count--;
3830 mpte = NULL;
3831 }
3832 return (mpte);
3833 }
3834
3835 /*
3836 * Enter on the PV list if part of our managed memory.
3837 */
3838 if ((m->oflags & VPO_UNMANAGED) == 0 &&
3839 !pmap_try_insert_pv_entry(pmap, va, m)) {
3840 if (mpte != NULL) {
3841 SLIST_INIT(&free);
3842 if (pmap_unwire_ptp(pmap, mpte, &free)) {
3843 pmap_invalidate_page(pmap, va);
3844 pmap_free_zero_pages(&free);
3845 }
3846
3847 mpte = NULL;
3848 }
3849 return (mpte);
3850 }
3851
3852 /*
3853 * Increment counters
3854 */
3855 pmap->pm_stats.resident_count++;
3856
3857 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3858 #if defined(PAE) || defined(PAE_TABLES)
3859 if ((prot & VM_PROT_EXECUTE) == 0)
3860 pa |= pg_nx;
3861 #endif
3862
3863 /*
3864 * Now validate mapping with RO protection
3865 */
3866 if ((m->oflags & VPO_UNMANAGED) != 0)
3867 pte_store(pte, pa | PG_V | PG_U);
3868 else
3869 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3870 return (mpte);
3871 }
3872
3873 /*
3874 * Make a temporary mapping for a physical address. This is only intended
3875 * to be used for panic dumps.
3876 */
3877 void *
3878 pmap_kenter_temporary(vm_paddr_t pa, int i)
3879 {
3880 vm_offset_t va;
3881
3882 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3883 pmap_kenter(va, pa);
3884 invlpg(va);
3885 return ((void *)crashdumpmap);
3886 }
3887
3888 /*
3889 * This code maps large physical mmap regions into the
3890 * processor address space. Note that some shortcuts
3891 * are taken, but the code works.
3892 */
3893 void
3894 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3895 vm_pindex_t pindex, vm_size_t size)
3896 {
3897 pd_entry_t *pde;
3898 vm_paddr_t pa, ptepa;
3899 vm_page_t p;
3900 int pat_mode;
3901
3902 VM_OBJECT_ASSERT_WLOCKED(object);
3903 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3904 ("pmap_object_init_pt: non-device object"));
3905 if (pseflag &&
3906 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3907 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3908 return;
3909 p = vm_page_lookup(object, pindex);
3910 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3911 ("pmap_object_init_pt: invalid page %p", p));
3912 pat_mode = p->md.pat_mode;
3913
3914 /*
3915 * Abort the mapping if the first page is not physically
3916 * aligned to a 2/4MB page boundary.
3917 */
3918 ptepa = VM_PAGE_TO_PHYS(p);
3919 if (ptepa & (NBPDR - 1))
3920 return;
3921
3922 /*
3923 * Skip the first page. Abort the mapping if the rest of
3924 * the pages are not physically contiguous or have differing
3925 * memory attributes.
3926 */
3927 p = TAILQ_NEXT(p, listq);
3928 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3929 pa += PAGE_SIZE) {
3930 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3931 ("pmap_object_init_pt: invalid page %p", p));
3932 if (pa != VM_PAGE_TO_PHYS(p) ||
3933 pat_mode != p->md.pat_mode)
3934 return;
3935 p = TAILQ_NEXT(p, listq);
3936 }
3937
3938 /*
3939 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3940 * "size" is a multiple of 2/4M, adding the PAT setting to
3941 * "pa" will not affect the termination of this loop.
3942 */
3943 PMAP_LOCK(pmap);
3944 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3945 size; pa += NBPDR) {
3946 pde = pmap_pde(pmap, addr);
3947 if (*pde == 0) {
3948 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3949 PG_U | PG_RW | PG_V);
3950 pmap->pm_stats.resident_count += NBPDR /
3951 PAGE_SIZE;
3952 pmap_pde_mappings++;
3953 }
3954 /* Else continue on if the PDE is already valid. */
3955 addr += NBPDR;
3956 }
3957 PMAP_UNLOCK(pmap);
3958 }
3959 }
3960
3961 /*
3962 * Clear the wired attribute from the mappings for the specified range of
3963 * addresses in the given pmap. Every valid mapping within that range
3964 * must have the wired attribute set. In contrast, invalid mappings
3965 * cannot have the wired attribute set, so they are ignored.
3966 *
3967 * The wired attribute of the page table entry is not a hardware feature,
3968 * so there is no need to invalidate any TLB entries.
3969 */
3970 void
3971 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
3972 {
3973 vm_offset_t pdnxt;
3974 pd_entry_t *pde;
3975 pt_entry_t *pte;
3976 boolean_t pv_lists_locked;
3977
3978 if (pmap_is_current(pmap))
3979 pv_lists_locked = FALSE;
3980 else {
3981 pv_lists_locked = TRUE;
3982 resume:
3983 rw_wlock(&pvh_global_lock);
3984 sched_pin();
3985 }
3986 PMAP_LOCK(pmap);
3987 for (; sva < eva; sva = pdnxt) {
3988 pdnxt = (sva + NBPDR) & ~PDRMASK;
3989 if (pdnxt < sva)
3990 pdnxt = eva;
3991 pde = pmap_pde(pmap, sva);
3992 if ((*pde & PG_V) == 0)
3993 continue;
3994 if ((*pde & PG_PS) != 0) {
3995 if ((*pde & PG_W) == 0)
3996 panic("pmap_unwire: pde %#jx is missing PG_W",
3997 (uintmax_t)*pde);
3998
3999 /*
4000 * Are we unwiring the entire large page? If not,
4001 * demote the mapping and fall through.
4002 */
4003 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
4004 /*
4005 * Regardless of whether a pde (or pte) is 32
4006 * or 64 bits in size, PG_W is among the least
4007 * significant 32 bits.
4008 */
4009 atomic_clear_int((u_int *)pde, PG_W);
4010 pmap->pm_stats.wired_count -= NBPDR /
4011 PAGE_SIZE;
4012 continue;
4013 } else {
4014 if (!pv_lists_locked) {
4015 pv_lists_locked = TRUE;
4016 if (!rw_try_wlock(&pvh_global_lock)) {
4017 PMAP_UNLOCK(pmap);
4018 /* Repeat sva. */
4019 goto resume;
4020 }
4021 sched_pin();
4022 }
4023 if (!pmap_demote_pde(pmap, pde, sva))
4024 panic("pmap_unwire: demotion failed");
4025 }
4026 }
4027 if (pdnxt > eva)
4028 pdnxt = eva;
4029 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4030 sva += PAGE_SIZE) {
4031 if ((*pte & PG_V) == 0)
4032 continue;
4033 if ((*pte & PG_W) == 0)
4034 panic("pmap_unwire: pte %#jx is missing PG_W",
4035 (uintmax_t)*pte);
4036
4037 /*
4038 * PG_W must be cleared atomically. Although the pmap
4039 * lock synchronizes access to PG_W, another processor
4040 * could be setting PG_M and/or PG_A concurrently.
4041 *
4042 * PG_W is among the least significant 32 bits.
4043 */
4044 atomic_clear_int((u_int *)pte, PG_W);
4045 pmap->pm_stats.wired_count--;
4046 }
4047 }
4048 if (pv_lists_locked) {
4049 sched_unpin();
4050 rw_wunlock(&pvh_global_lock);
4051 }
4052 PMAP_UNLOCK(pmap);
4053 }
4054
4055
4056 /*
4057 * Copy the range specified by src_addr/len
4058 * from the source map to the range dst_addr/len
4059 * in the destination map.
4060 *
4061 * This routine is only advisory and need not do anything.
4062 */
4063
4064 void
4065 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
4066 vm_offset_t src_addr)
4067 {
4068 struct spglist free;
4069 vm_offset_t addr;
4070 vm_offset_t end_addr = src_addr + len;
4071 vm_offset_t pdnxt;
4072
4073 if (dst_addr != src_addr)
4074 return;
4075
4076 if (!pmap_is_current(src_pmap))
4077 return;
4078
4079 rw_wlock(&pvh_global_lock);
4080 if (dst_pmap < src_pmap) {
4081 PMAP_LOCK(dst_pmap);
4082 PMAP_LOCK(src_pmap);
4083 } else {
4084 PMAP_LOCK(src_pmap);
4085 PMAP_LOCK(dst_pmap);
4086 }
4087 sched_pin();
4088 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
4089 pt_entry_t *src_pte, *dst_pte;
4090 vm_page_t dstmpte, srcmpte;
4091 pd_entry_t srcptepaddr;
4092 u_int ptepindex;
4093
4094 KASSERT(addr < UPT_MIN_ADDRESS,
4095 ("pmap_copy: invalid to pmap_copy page tables"));
4096
4097 pdnxt = (addr + NBPDR) & ~PDRMASK;
4098 if (pdnxt < addr)
4099 pdnxt = end_addr;
4100 ptepindex = addr >> PDRSHIFT;
4101
4102 srcptepaddr = src_pmap->pm_pdir[ptepindex];
4103 if (srcptepaddr == 0)
4104 continue;
4105
4106 if (srcptepaddr & PG_PS) {
4107 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr)
4108 continue;
4109 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
4110 ((srcptepaddr & PG_MANAGED) == 0 ||
4111 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
4112 PG_PS_FRAME))) {
4113 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
4114 ~PG_W;
4115 dst_pmap->pm_stats.resident_count +=
4116 NBPDR / PAGE_SIZE;
4117 pmap_pde_mappings++;
4118 }
4119 continue;
4120 }
4121
4122 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
4123 KASSERT(srcmpte->wire_count > 0,
4124 ("pmap_copy: source page table page is unused"));
4125
4126 if (pdnxt > end_addr)
4127 pdnxt = end_addr;
4128
4129 src_pte = vtopte(addr);
4130 while (addr < pdnxt) {
4131 pt_entry_t ptetemp;
4132 ptetemp = *src_pte;
4133 /*
4134 * we only virtual copy managed pages
4135 */
4136 if ((ptetemp & PG_MANAGED) != 0) {
4137 dstmpte = pmap_allocpte(dst_pmap, addr,
4138 PMAP_ENTER_NOSLEEP);
4139 if (dstmpte == NULL)
4140 goto out;
4141 dst_pte = pmap_pte_quick(dst_pmap, addr);
4142 if (*dst_pte == 0 &&
4143 pmap_try_insert_pv_entry(dst_pmap, addr,
4144 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
4145 /*
4146 * Clear the wired, modified, and
4147 * accessed (referenced) bits
4148 * during the copy.
4149 */
4150 *dst_pte = ptetemp & ~(PG_W | PG_M |
4151 PG_A);
4152 dst_pmap->pm_stats.resident_count++;
4153 } else {
4154 SLIST_INIT(&free);
4155 if (pmap_unwire_ptp(dst_pmap, dstmpte,
4156 &free)) {
4157 pmap_invalidate_page(dst_pmap,
4158 addr);
4159 pmap_free_zero_pages(&free);
4160 }
4161 goto out;
4162 }
4163 if (dstmpte->wire_count >= srcmpte->wire_count)
4164 break;
4165 }
4166 addr += PAGE_SIZE;
4167 src_pte++;
4168 }
4169 }
4170 out:
4171 sched_unpin();
4172 rw_wunlock(&pvh_global_lock);
4173 PMAP_UNLOCK(src_pmap);
4174 PMAP_UNLOCK(dst_pmap);
4175 }
4176
4177 static __inline void
4178 pagezero(void *page)
4179 {
4180 #if defined(I686_CPU)
4181 if (cpu_class == CPUCLASS_686) {
4182 #if defined(CPU_ENABLE_SSE)
4183 if (cpu_feature & CPUID_SSE2)
4184 sse2_pagezero(page);
4185 else
4186 #endif
4187 i686_pagezero(page);
4188 } else
4189 #endif
4190 bzero(page, PAGE_SIZE);
4191 }
4192
4193 /*
4194 * pmap_zero_page zeros the specified hardware page by mapping
4195 * the page into KVM and using bzero to clear its contents.
4196 */
4197 void
4198 pmap_zero_page(vm_page_t m)
4199 {
4200 struct sysmaps *sysmaps;
4201
4202 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4203 mtx_lock(&sysmaps->lock);
4204 if (*sysmaps->CMAP2)
4205 panic("pmap_zero_page: CMAP2 busy");
4206 sched_pin();
4207 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4208 pmap_cache_bits(m->md.pat_mode, 0);
4209 invlcaddr(sysmaps->CADDR2);
4210 pagezero(sysmaps->CADDR2);
4211 *sysmaps->CMAP2 = 0;
4212 sched_unpin();
4213 mtx_unlock(&sysmaps->lock);
4214 }
4215
4216 /*
4217 * pmap_zero_page_area zeros the specified hardware page by mapping
4218 * the page into KVM and using bzero to clear its contents.
4219 *
4220 * off and size may not cover an area beyond a single hardware page.
4221 */
4222 void
4223 pmap_zero_page_area(vm_page_t m, int off, int size)
4224 {
4225 struct sysmaps *sysmaps;
4226
4227 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4228 mtx_lock(&sysmaps->lock);
4229 if (*sysmaps->CMAP2)
4230 panic("pmap_zero_page_area: CMAP2 busy");
4231 sched_pin();
4232 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4233 pmap_cache_bits(m->md.pat_mode, 0);
4234 invlcaddr(sysmaps->CADDR2);
4235 if (off == 0 && size == PAGE_SIZE)
4236 pagezero(sysmaps->CADDR2);
4237 else
4238 bzero((char *)sysmaps->CADDR2 + off, size);
4239 *sysmaps->CMAP2 = 0;
4240 sched_unpin();
4241 mtx_unlock(&sysmaps->lock);
4242 }
4243
4244 /*
4245 * pmap_zero_page_idle zeros the specified hardware page by mapping
4246 * the page into KVM and using bzero to clear its contents. This
4247 * is intended to be called from the vm_pagezero process only and
4248 * outside of Giant.
4249 */
4250 void
4251 pmap_zero_page_idle(vm_page_t m)
4252 {
4253
4254 if (*CMAP3)
4255 panic("pmap_zero_page_idle: CMAP3 busy");
4256 sched_pin();
4257 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4258 pmap_cache_bits(m->md.pat_mode, 0);
4259 invlcaddr(CADDR3);
4260 pagezero(CADDR3);
4261 *CMAP3 = 0;
4262 sched_unpin();
4263 }
4264
4265 /*
4266 * pmap_copy_page copies the specified (machine independent)
4267 * page by mapping the page into virtual memory and using
4268 * bcopy to copy the page, one machine dependent page at a
4269 * time.
4270 */
4271 void
4272 pmap_copy_page(vm_page_t src, vm_page_t dst)
4273 {
4274 struct sysmaps *sysmaps;
4275
4276 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4277 mtx_lock(&sysmaps->lock);
4278 if (*sysmaps->CMAP1)
4279 panic("pmap_copy_page: CMAP1 busy");
4280 if (*sysmaps->CMAP2)
4281 panic("pmap_copy_page: CMAP2 busy");
4282 sched_pin();
4283 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4284 pmap_cache_bits(src->md.pat_mode, 0);
4285 invlcaddr(sysmaps->CADDR1);
4286 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4287 pmap_cache_bits(dst->md.pat_mode, 0);
4288 invlcaddr(sysmaps->CADDR2);
4289 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
4290 *sysmaps->CMAP1 = 0;
4291 *sysmaps->CMAP2 = 0;
4292 sched_unpin();
4293 mtx_unlock(&sysmaps->lock);
4294 }
4295
4296 int unmapped_buf_allowed = 1;
4297
4298 void
4299 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
4300 vm_offset_t b_offset, int xfersize)
4301 {
4302 struct sysmaps *sysmaps;
4303 vm_page_t a_pg, b_pg;
4304 char *a_cp, *b_cp;
4305 vm_offset_t a_pg_offset, b_pg_offset;
4306 int cnt;
4307
4308 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4309 mtx_lock(&sysmaps->lock);
4310 if (*sysmaps->CMAP1 != 0)
4311 panic("pmap_copy_pages: CMAP1 busy");
4312 if (*sysmaps->CMAP2 != 0)
4313 panic("pmap_copy_pages: CMAP2 busy");
4314 sched_pin();
4315 while (xfersize > 0) {
4316 a_pg = ma[a_offset >> PAGE_SHIFT];
4317 a_pg_offset = a_offset & PAGE_MASK;
4318 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
4319 b_pg = mb[b_offset >> PAGE_SHIFT];
4320 b_pg_offset = b_offset & PAGE_MASK;
4321 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
4322 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A |
4323 pmap_cache_bits(a_pg->md.pat_mode, 0);
4324 invlcaddr(sysmaps->CADDR1);
4325 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A |
4326 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0);
4327 invlcaddr(sysmaps->CADDR2);
4328 a_cp = sysmaps->CADDR1 + a_pg_offset;
4329 b_cp = sysmaps->CADDR2 + b_pg_offset;
4330 bcopy(a_cp, b_cp, cnt);
4331 a_offset += cnt;
4332 b_offset += cnt;
4333 xfersize -= cnt;
4334 }
4335 *sysmaps->CMAP1 = 0;
4336 *sysmaps->CMAP2 = 0;
4337 sched_unpin();
4338 mtx_unlock(&sysmaps->lock);
4339 }
4340
4341 /*
4342 * Returns true if the pmap's pv is one of the first
4343 * 16 pvs linked to from this page. This count may
4344 * be changed upwards or downwards in the future; it
4345 * is only necessary that true be returned for a small
4346 * subset of pmaps for proper page aging.
4347 */
4348 boolean_t
4349 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4350 {
4351 struct md_page *pvh;
4352 pv_entry_t pv;
4353 int loops = 0;
4354 boolean_t rv;
4355
4356 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4357 ("pmap_page_exists_quick: page %p is not managed", m));
4358 rv = FALSE;
4359 rw_wlock(&pvh_global_lock);
4360 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4361 if (PV_PMAP(pv) == pmap) {
4362 rv = TRUE;
4363 break;
4364 }
4365 loops++;
4366 if (loops >= 16)
4367 break;
4368 }
4369 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) {
4370 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4371 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4372 if (PV_PMAP(pv) == pmap) {
4373 rv = TRUE;
4374 break;
4375 }
4376 loops++;
4377 if (loops >= 16)
4378 break;
4379 }
4380 }
4381 rw_wunlock(&pvh_global_lock);
4382 return (rv);
4383 }
4384
4385 /*
4386 * pmap_page_wired_mappings:
4387 *
4388 * Return the number of managed mappings to the given physical page
4389 * that are wired.
4390 */
4391 int
4392 pmap_page_wired_mappings(vm_page_t m)
4393 {
4394 int count;
4395
4396 count = 0;
4397 if ((m->oflags & VPO_UNMANAGED) != 0)
4398 return (count);
4399 rw_wlock(&pvh_global_lock);
4400 count = pmap_pvh_wired_mappings(&m->md, count);
4401 if ((m->flags & PG_FICTITIOUS) == 0) {
4402 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)),
4403 count);
4404 }
4405 rw_wunlock(&pvh_global_lock);
4406 return (count);
4407 }
4408
4409 /*
4410 * pmap_pvh_wired_mappings:
4411 *
4412 * Return the updated number "count" of managed mappings that are wired.
4413 */
4414 static int
4415 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4416 {
4417 pmap_t pmap;
4418 pt_entry_t *pte;
4419 pv_entry_t pv;
4420
4421 rw_assert(&pvh_global_lock, RA_WLOCKED);
4422 sched_pin();
4423 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4424 pmap = PV_PMAP(pv);
4425 PMAP_LOCK(pmap);
4426 pte = pmap_pte_quick(pmap, pv->pv_va);
4427 if ((*pte & PG_W) != 0)
4428 count++;
4429 PMAP_UNLOCK(pmap);
4430 }
4431 sched_unpin();
4432 return (count);
4433 }
4434
4435 /*
4436 * Returns TRUE if the given page is mapped individually or as part of
4437 * a 4mpage. Otherwise, returns FALSE.
4438 */
4439 boolean_t
4440 pmap_page_is_mapped(vm_page_t m)
4441 {
4442 boolean_t rv;
4443
4444 if ((m->oflags & VPO_UNMANAGED) != 0)
4445 return (FALSE);
4446 rw_wlock(&pvh_global_lock);
4447 rv = !TAILQ_EMPTY(&m->md.pv_list) ||
4448 ((m->flags & PG_FICTITIOUS) == 0 &&
4449 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list));
4450 rw_wunlock(&pvh_global_lock);
4451 return (rv);
4452 }
4453
4454 /*
4455 * Remove all pages from specified address space
4456 * this aids process exit speeds. Also, this code
4457 * is special cased for current process only, but
4458 * can have the more generic (and slightly slower)
4459 * mode enabled. This is much faster than pmap_remove
4460 * in the case of running down an entire address space.
4461 */
4462 void
4463 pmap_remove_pages(pmap_t pmap)
4464 {
4465 pt_entry_t *pte, tpte;
4466 vm_page_t m, mpte, mt;
4467 pv_entry_t pv;
4468 struct md_page *pvh;
4469 struct pv_chunk *pc, *npc;
4470 struct spglist free;
4471 int field, idx;
4472 int32_t bit;
4473 uint32_t inuse, bitmask;
4474 int allfree;
4475
4476 if (pmap != PCPU_GET(curpmap)) {
4477 printf("warning: pmap_remove_pages called with non-current pmap\n");
4478 return;
4479 }
4480 SLIST_INIT(&free);
4481 rw_wlock(&pvh_global_lock);
4482 PMAP_LOCK(pmap);
4483 sched_pin();
4484 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4485 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap,
4486 pc->pc_pmap));
4487 allfree = 1;
4488 for (field = 0; field < _NPCM; field++) {
4489 inuse = ~pc->pc_map[field] & pc_freemask[field];
4490 while (inuse != 0) {
4491 bit = bsfl(inuse);
4492 bitmask = 1UL << bit;
4493 idx = field * 32 + bit;
4494 pv = &pc->pc_pventry[idx];
4495 inuse &= ~bitmask;
4496
4497 pte = pmap_pde(pmap, pv->pv_va);
4498 tpte = *pte;
4499 if ((tpte & PG_PS) == 0) {
4500 pte = vtopte(pv->pv_va);
4501 tpte = *pte & ~PG_PTE_PAT;
4502 }
4503
4504 if (tpte == 0) {
4505 printf(
4506 "TPTE at %p IS ZERO @ VA %08x\n",
4507 pte, pv->pv_va);
4508 panic("bad pte");
4509 }
4510
4511 /*
4512 * We cannot remove wired pages from a process' mapping at this time
4513 */
4514 if (tpte & PG_W) {
4515 allfree = 0;
4516 continue;
4517 }
4518
4519 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4520 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4521 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4522 m, (uintmax_t)m->phys_addr,
4523 (uintmax_t)tpte));
4524
4525 KASSERT((m->flags & PG_FICTITIOUS) != 0 ||
4526 m < &vm_page_array[vm_page_array_size],
4527 ("pmap_remove_pages: bad tpte %#jx",
4528 (uintmax_t)tpte));
4529
4530 pte_clear(pte);
4531
4532 /*
4533 * Update the vm_page_t clean/reference bits.
4534 */
4535 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4536 if ((tpte & PG_PS) != 0) {
4537 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4538 vm_page_dirty(mt);
4539 } else
4540 vm_page_dirty(m);
4541 }
4542
4543 /* Mark free */
4544 PV_STAT(pv_entry_frees++);
4545 PV_STAT(pv_entry_spare++);
4546 pv_entry_count--;
4547 pc->pc_map[field] |= bitmask;
4548 if ((tpte & PG_PS) != 0) {
4549 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4550 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4551 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4552 if (TAILQ_EMPTY(&pvh->pv_list)) {
4553 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4554 if (TAILQ_EMPTY(&mt->md.pv_list))
4555 vm_page_aflag_clear(mt, PGA_WRITEABLE);
4556 }
4557 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4558 if (mpte != NULL) {
4559 pmap_remove_pt_page(pmap, mpte);
4560 pmap->pm_stats.resident_count--;
4561 KASSERT(mpte->wire_count == NPTEPG,
4562 ("pmap_remove_pages: pte page wire count error"));
4563 mpte->wire_count = 0;
4564 pmap_add_delayed_free_list(mpte, &free, FALSE);
4565 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
4566 }
4567 } else {
4568 pmap->pm_stats.resident_count--;
4569 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4570 if (TAILQ_EMPTY(&m->md.pv_list) &&
4571 (m->flags & PG_FICTITIOUS) == 0) {
4572 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4573 if (TAILQ_EMPTY(&pvh->pv_list))
4574 vm_page_aflag_clear(m, PGA_WRITEABLE);
4575 }
4576 pmap_unuse_pt(pmap, pv->pv_va, &free);
4577 }
4578 }
4579 }
4580 if (allfree) {
4581 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4582 free_pv_chunk(pc);
4583 }
4584 }
4585 sched_unpin();
4586 pmap_invalidate_all(pmap);
4587 rw_wunlock(&pvh_global_lock);
4588 PMAP_UNLOCK(pmap);
4589 pmap_free_zero_pages(&free);
4590 }
4591
4592 /*
4593 * pmap_is_modified:
4594 *
4595 * Return whether or not the specified physical page was modified
4596 * in any physical maps.
4597 */
4598 boolean_t
4599 pmap_is_modified(vm_page_t m)
4600 {
4601 boolean_t rv;
4602
4603 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4604 ("pmap_is_modified: page %p is not managed", m));
4605
4606 /*
4607 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4608 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
4609 * is clear, no PTEs can have PG_M set.
4610 */
4611 VM_OBJECT_ASSERT_WLOCKED(m->object);
4612 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4613 return (FALSE);
4614 rw_wlock(&pvh_global_lock);
4615 rv = pmap_is_modified_pvh(&m->md) ||
4616 ((m->flags & PG_FICTITIOUS) == 0 &&
4617 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4618 rw_wunlock(&pvh_global_lock);
4619 return (rv);
4620 }
4621
4622 /*
4623 * Returns TRUE if any of the given mappings were used to modify
4624 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4625 * mappings are supported.
4626 */
4627 static boolean_t
4628 pmap_is_modified_pvh(struct md_page *pvh)
4629 {
4630 pv_entry_t pv;
4631 pt_entry_t *pte;
4632 pmap_t pmap;
4633 boolean_t rv;
4634
4635 rw_assert(&pvh_global_lock, RA_WLOCKED);
4636 rv = FALSE;
4637 sched_pin();
4638 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4639 pmap = PV_PMAP(pv);
4640 PMAP_LOCK(pmap);
4641 pte = pmap_pte_quick(pmap, pv->pv_va);
4642 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4643 PMAP_UNLOCK(pmap);
4644 if (rv)
4645 break;
4646 }
4647 sched_unpin();
4648 return (rv);
4649 }
4650
4651 /*
4652 * pmap_is_prefaultable:
4653 *
4654 * Return whether or not the specified virtual address is elgible
4655 * for prefault.
4656 */
4657 boolean_t
4658 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4659 {
4660 pd_entry_t *pde;
4661 pt_entry_t *pte;
4662 boolean_t rv;
4663
4664 rv = FALSE;
4665 PMAP_LOCK(pmap);
4666 pde = pmap_pde(pmap, addr);
4667 if (*pde != 0 && (*pde & PG_PS) == 0) {
4668 pte = vtopte(addr);
4669 rv = *pte == 0;
4670 }
4671 PMAP_UNLOCK(pmap);
4672 return (rv);
4673 }
4674
4675 /*
4676 * pmap_is_referenced:
4677 *
4678 * Return whether or not the specified physical page was referenced
4679 * in any physical maps.
4680 */
4681 boolean_t
4682 pmap_is_referenced(vm_page_t m)
4683 {
4684 boolean_t rv;
4685
4686 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4687 ("pmap_is_referenced: page %p is not managed", m));
4688 rw_wlock(&pvh_global_lock);
4689 rv = pmap_is_referenced_pvh(&m->md) ||
4690 ((m->flags & PG_FICTITIOUS) == 0 &&
4691 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4692 rw_wunlock(&pvh_global_lock);
4693 return (rv);
4694 }
4695
4696 /*
4697 * Returns TRUE if any of the given mappings were referenced and FALSE
4698 * otherwise. Both page and 4mpage mappings are supported.
4699 */
4700 static boolean_t
4701 pmap_is_referenced_pvh(struct md_page *pvh)
4702 {
4703 pv_entry_t pv;
4704 pt_entry_t *pte;
4705 pmap_t pmap;
4706 boolean_t rv;
4707
4708 rw_assert(&pvh_global_lock, RA_WLOCKED);
4709 rv = FALSE;
4710 sched_pin();
4711 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) {
4712 pmap = PV_PMAP(pv);
4713 PMAP_LOCK(pmap);
4714 pte = pmap_pte_quick(pmap, pv->pv_va);
4715 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V);
4716 PMAP_UNLOCK(pmap);
4717 if (rv)
4718 break;
4719 }
4720 sched_unpin();
4721 return (rv);
4722 }
4723
4724 /*
4725 * Clear the write and modified bits in each of the given page's mappings.
4726 */
4727 void
4728 pmap_remove_write(vm_page_t m)
4729 {
4730 struct md_page *pvh;
4731 pv_entry_t next_pv, pv;
4732 pmap_t pmap;
4733 pd_entry_t *pde;
4734 pt_entry_t oldpte, *pte;
4735 vm_offset_t va;
4736
4737 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4738 ("pmap_remove_write: page %p is not managed", m));
4739
4740 /*
4741 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
4742 * set by another thread while the object is locked. Thus,
4743 * if PGA_WRITEABLE is clear, no page table entries need updating.
4744 */
4745 VM_OBJECT_ASSERT_WLOCKED(m->object);
4746 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
4747 return;
4748 rw_wlock(&pvh_global_lock);
4749 sched_pin();
4750 if ((m->flags & PG_FICTITIOUS) != 0)
4751 goto small_mappings;
4752 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4753 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
4754 va = pv->pv_va;
4755 pmap = PV_PMAP(pv);
4756 PMAP_LOCK(pmap);
4757 pde = pmap_pde(pmap, va);
4758 if ((*pde & PG_RW) != 0)
4759 (void)pmap_demote_pde(pmap, pde, va);
4760 PMAP_UNLOCK(pmap);
4761 }
4762 small_mappings:
4763 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
4764 pmap = PV_PMAP(pv);
4765 PMAP_LOCK(pmap);
4766 pde = pmap_pde(pmap, pv->pv_va);
4767 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4768 " a 4mpage in page %p's pv list", m));
4769 pte = pmap_pte_quick(pmap, pv->pv_va);
4770 retry:
4771 oldpte = *pte;
4772 if ((oldpte & PG_RW) != 0) {
4773 /*
4774 * Regardless of whether a pte is 32 or 64 bits
4775 * in size, PG_RW and PG_M are among the least
4776 * significant 32 bits.
4777 */
4778 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4779 oldpte & ~(PG_RW | PG_M)))
4780 goto retry;
4781 if ((oldpte & PG_M) != 0)
4782 vm_page_dirty(m);
4783 pmap_invalidate_page(pmap, pv->pv_va);
4784 }
4785 PMAP_UNLOCK(pmap);
4786 }
4787 vm_page_aflag_clear(m, PGA_WRITEABLE);
4788 sched_unpin();
4789 rw_wunlock(&pvh_global_lock);
4790 }
4791
4792 #define PMAP_TS_REFERENCED_MAX 5
4793
4794 /*
4795 * pmap_ts_referenced:
4796 *
4797 * Return a count of reference bits for a page, clearing those bits.
4798 * It is not necessary for every reference bit to be cleared, but it
4799 * is necessary that 0 only be returned when there are truly no
4800 * reference bits set.
4801 *
4802 * XXX: The exact number of bits to check and clear is a matter that
4803 * should be tested and standardized at some point in the future for
4804 * optimal aging of shared pages.
4805 */
4806 int
4807 pmap_ts_referenced(vm_page_t m)
4808 {
4809 struct md_page *pvh;
4810 pv_entry_t pv, pvf;
4811 pmap_t pmap;
4812 pd_entry_t *pde;
4813 pt_entry_t *pte;
4814 vm_paddr_t pa;
4815 int rtval = 0;
4816
4817 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
4818 ("pmap_ts_referenced: page %p is not managed", m));
4819 pa = VM_PAGE_TO_PHYS(m);
4820 pvh = pa_to_pvh(pa);
4821 rw_wlock(&pvh_global_lock);
4822 sched_pin();
4823 if ((m->flags & PG_FICTITIOUS) != 0 ||
4824 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL)
4825 goto small_mappings;
4826 pv = pvf;
4827 do {
4828 pmap = PV_PMAP(pv);
4829 PMAP_LOCK(pmap);
4830 pde = pmap_pde(pmap, pv->pv_va);
4831 if ((*pde & PG_A) != 0) {
4832 /*
4833 * Since this reference bit is shared by either 1024
4834 * or 512 4KB pages, it should not be cleared every
4835 * time it is tested. Apply a simple "hash" function
4836 * on the physical page number, the virtual superpage
4837 * number, and the pmap address to select one 4KB page
4838 * out of the 1024 or 512 on which testing the
4839 * reference bit will result in clearing that bit.
4840 * This function is designed to avoid the selection of
4841 * the same 4KB page for every 2- or 4MB page mapping.
4842 *
4843 * On demotion, a mapping that hasn't been referenced
4844 * is simply destroyed. To avoid the possibility of a
4845 * subsequent page fault on a demoted wired mapping,
4846 * always leave its reference bit set. Moreover,
4847 * since the superpage is wired, the current state of
4848 * its reference bit won't affect page replacement.
4849 */
4850 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^
4851 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 &&
4852 (*pde & PG_W) == 0) {
4853 atomic_clear_int((u_int *)pde, PG_A);
4854 pmap_invalidate_page(pmap, pv->pv_va);
4855 }
4856 rtval++;
4857 }
4858 PMAP_UNLOCK(pmap);
4859 /* Rotate the PV list if it has more than one entry. */
4860 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4861 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next);
4862 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next);
4863 }
4864 if (rtval >= PMAP_TS_REFERENCED_MAX)
4865 goto out;
4866 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf);
4867 small_mappings:
4868 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL)
4869 goto out;
4870 pv = pvf;
4871 do {
4872 pmap = PV_PMAP(pv);
4873 PMAP_LOCK(pmap);
4874 pde = pmap_pde(pmap, pv->pv_va);
4875 KASSERT((*pde & PG_PS) == 0,
4876 ("pmap_ts_referenced: found a 4mpage in page %p's pv list",
4877 m));
4878 pte = pmap_pte_quick(pmap, pv->pv_va);
4879 if ((*pte & PG_A) != 0) {
4880 atomic_clear_int((u_int *)pte, PG_A);
4881 pmap_invalidate_page(pmap, pv->pv_va);
4882 rtval++;
4883 }
4884 PMAP_UNLOCK(pmap);
4885 /* Rotate the PV list if it has more than one entry. */
4886 if (TAILQ_NEXT(pv, pv_next) != NULL) {
4887 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next);
4888 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next);
4889 }
4890 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval <
4891 PMAP_TS_REFERENCED_MAX);
4892 out:
4893 sched_unpin();
4894 rw_wunlock(&pvh_global_lock);
4895 return (rtval);
4896 }
4897
4898 /*
4899 * Apply the given advice to the specified range of addresses within the
4900 * given pmap. Depending on the advice, clear the referenced and/or
4901 * modified flags in each mapping and set the mapped page's dirty field.
4902 */
4903 void
4904 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
4905 {
4906 pd_entry_t oldpde, *pde;
4907 pt_entry_t *pte;
4908 vm_offset_t pdnxt;
4909 vm_page_t m;
4910 boolean_t anychanged, pv_lists_locked;
4911
4912 if (advice != MADV_DONTNEED && advice != MADV_FREE)
4913 return;
4914 if (pmap_is_current(pmap))
4915 pv_lists_locked = FALSE;
4916 else {
4917 pv_lists_locked = TRUE;
4918 resume:
4919 rw_wlock(&pvh_global_lock);
4920 sched_pin();
4921 }
4922 anychanged = FALSE;
4923 PMAP_LOCK(pmap);
4924 for (; sva < eva; sva = pdnxt) {
4925 pdnxt = (sva + NBPDR) & ~PDRMASK;
4926 if (pdnxt < sva)
4927 pdnxt = eva;
4928 pde = pmap_pde(pmap, sva);
4929 oldpde = *pde;
4930 if ((oldpde & PG_V) == 0)
4931 continue;
4932 else if ((oldpde & PG_PS) != 0) {
4933 if ((oldpde & PG_MANAGED) == 0)
4934 continue;
4935 if (!pv_lists_locked) {
4936 pv_lists_locked = TRUE;
4937 if (!rw_try_wlock(&pvh_global_lock)) {
4938 if (anychanged)
4939 pmap_invalidate_all(pmap);
4940 PMAP_UNLOCK(pmap);
4941 goto resume;
4942 }
4943 sched_pin();
4944 }
4945 if (!pmap_demote_pde(pmap, pde, sva)) {
4946 /*
4947 * The large page mapping was destroyed.
4948 */
4949 continue;
4950 }
4951
4952 /*
4953 * Unless the page mappings are wired, remove the
4954 * mapping to a single page so that a subsequent
4955 * access may repromote. Since the underlying page
4956 * table page is fully populated, this removal never
4957 * frees a page table page.
4958 */
4959 if ((oldpde & PG_W) == 0) {
4960 pte = pmap_pte_quick(pmap, sva);
4961 KASSERT((*pte & PG_V) != 0,
4962 ("pmap_advise: invalid PTE"));
4963 pmap_remove_pte(pmap, pte, sva, NULL);
4964 anychanged = TRUE;
4965 }
4966 }
4967 if (pdnxt > eva)
4968 pdnxt = eva;
4969 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
4970 sva += PAGE_SIZE) {
4971 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED |
4972 PG_V))
4973 continue;
4974 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4975 if (advice == MADV_DONTNEED) {
4976 /*
4977 * Future calls to pmap_is_modified()
4978 * can be avoided by making the page
4979 * dirty now.
4980 */
4981 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME);
4982 vm_page_dirty(m);
4983 }
4984 atomic_clear_int((u_int *)pte, PG_M | PG_A);
4985 } else if ((*pte & PG_A) != 0)
4986 atomic_clear_int((u_int *)pte, PG_A);
4987 else
4988 continue;
4989 if ((*pte & PG_G) != 0)
4990 pmap_invalidate_page(pmap, sva);
4991 else
4992 anychanged = TRUE;
4993 }
4994 }
4995 if (anychanged)
4996 pmap_invalidate_all(pmap);
4997 if (pv_lists_locked) {
4998 sched_unpin();
4999 rw_wunlock(&pvh_global_lock);
5000 }
5001 PMAP_UNLOCK(pmap);
5002 }
5003
5004 /*
5005 * Clear the modify bits on the specified physical page.
5006 */
5007 void
5008 pmap_clear_modify(vm_page_t m)
5009 {
5010 struct md_page *pvh;
5011 pv_entry_t next_pv, pv;
5012 pmap_t pmap;
5013 pd_entry_t oldpde, *pde;
5014 pt_entry_t oldpte, *pte;
5015 vm_offset_t va;
5016
5017 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
5018 ("pmap_clear_modify: page %p is not managed", m));
5019 VM_OBJECT_ASSERT_WLOCKED(m->object);
5020 KASSERT(!vm_page_xbusied(m),
5021 ("pmap_clear_modify: page %p is exclusive busied", m));
5022
5023 /*
5024 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set.
5025 * If the object containing the page is locked and the page is not
5026 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
5027 */
5028 if ((m->aflags & PGA_WRITEABLE) == 0)
5029 return;
5030 rw_wlock(&pvh_global_lock);
5031 sched_pin();
5032 if ((m->flags & PG_FICTITIOUS) != 0)
5033 goto small_mappings;
5034 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
5035 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) {
5036 va = pv->pv_va;
5037 pmap = PV_PMAP(pv);
5038 PMAP_LOCK(pmap);
5039 pde = pmap_pde(pmap, va);
5040 oldpde = *pde;
5041 if ((oldpde & PG_RW) != 0) {
5042 if (pmap_demote_pde(pmap, pde, va)) {
5043 if ((oldpde & PG_W) == 0) {
5044 /*
5045 * Write protect the mapping to a
5046 * single page so that a subsequent
5047 * write access may repromote.
5048 */
5049 va += VM_PAGE_TO_PHYS(m) - (oldpde &
5050 PG_PS_FRAME);
5051 pte = pmap_pte_quick(pmap, va);
5052 oldpte = *pte;
5053 if ((oldpte & PG_V) != 0) {
5054 /*
5055 * Regardless of whether a pte is 32 or 64 bits
5056 * in size, PG_RW and PG_M are among the least
5057 * significant 32 bits.
5058 */
5059 while (!atomic_cmpset_int((u_int *)pte,
5060 oldpte,
5061 oldpte & ~(PG_M | PG_RW)))
5062 oldpte = *pte;
5063 vm_page_dirty(m);
5064 pmap_invalidate_page(pmap, va);
5065 }
5066 }
5067 }
5068 }
5069 PMAP_UNLOCK(pmap);
5070 }
5071 small_mappings:
5072 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) {
5073 pmap = PV_PMAP(pv);
5074 PMAP_LOCK(pmap);
5075 pde = pmap_pde(pmap, pv->pv_va);
5076 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
5077 " a 4mpage in page %p's pv list", m));
5078 pte = pmap_pte_quick(pmap, pv->pv_va);
5079 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
5080 /*
5081 * Regardless of whether a pte is 32 or 64 bits
5082 * in size, PG_M is among the least significant
5083 * 32 bits.
5084 */
5085 atomic_clear_int((u_int *)pte, PG_M);
5086 pmap_invalidate_page(pmap, pv->pv_va);
5087 }
5088 PMAP_UNLOCK(pmap);
5089 }
5090 sched_unpin();
5091 rw_wunlock(&pvh_global_lock);
5092 }
5093
5094 /*
5095 * Miscellaneous support routines follow
5096 */
5097
5098 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
5099 static __inline void
5100 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
5101 {
5102 u_int opte, npte;
5103
5104 /*
5105 * The cache mode bits are all in the low 32-bits of the
5106 * PTE, so we can just spin on updating the low 32-bits.
5107 */
5108 do {
5109 opte = *(u_int *)pte;
5110 npte = opte & ~PG_PTE_CACHE;
5111 npte |= cache_bits;
5112 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
5113 }
5114
5115 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
5116 static __inline void
5117 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
5118 {
5119 u_int opde, npde;
5120
5121 /*
5122 * The cache mode bits are all in the low 32-bits of the
5123 * PDE, so we can just spin on updating the low 32-bits.
5124 */
5125 do {
5126 opde = *(u_int *)pde;
5127 npde = opde & ~PG_PDE_CACHE;
5128 npde |= cache_bits;
5129 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
5130 }
5131
5132 /*
5133 * Map a set of physical memory pages into the kernel virtual
5134 * address space. Return a pointer to where it is mapped. This
5135 * routine is intended to be used for mapping device memory,
5136 * NOT real memory.
5137 */
5138 void *
5139 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
5140 {
5141 struct pmap_preinit_mapping *ppim;
5142 vm_offset_t va, offset;
5143 vm_size_t tmpsize;
5144 int i;
5145
5146 offset = pa & PAGE_MASK;
5147 size = round_page(offset + size);
5148 pa = pa & PG_FRAME;
5149
5150 if (pa < KERNLOAD && pa + size <= KERNLOAD)
5151 va = KERNBASE + pa;
5152 else if (!pmap_initialized) {
5153 va = 0;
5154 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5155 ppim = pmap_preinit_mapping + i;
5156 if (ppim->va == 0) {
5157 ppim->pa = pa;
5158 ppim->sz = size;
5159 ppim->mode = mode;
5160 ppim->va = virtual_avail;
5161 virtual_avail += size;
5162 va = ppim->va;
5163 break;
5164 }
5165 }
5166 if (va == 0)
5167 panic("%s: too many preinit mappings", __func__);
5168 } else {
5169 /*
5170 * If we have a preinit mapping, re-use it.
5171 */
5172 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5173 ppim = pmap_preinit_mapping + i;
5174 if (ppim->pa == pa && ppim->sz == size &&
5175 ppim->mode == mode)
5176 return ((void *)(ppim->va + offset));
5177 }
5178 va = kva_alloc(size);
5179 if (va == 0)
5180 panic("%s: Couldn't allocate KVA", __func__);
5181 }
5182 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
5183 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
5184 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
5185 pmap_invalidate_cache_range(va, va + size, FALSE);
5186 return ((void *)(va + offset));
5187 }
5188
5189 void *
5190 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
5191 {
5192
5193 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
5194 }
5195
5196 void *
5197 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
5198 {
5199
5200 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
5201 }
5202
5203 void
5204 pmap_unmapdev(vm_offset_t va, vm_size_t size)
5205 {
5206 struct pmap_preinit_mapping *ppim;
5207 vm_offset_t offset;
5208 int i;
5209
5210 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
5211 return;
5212 offset = va & PAGE_MASK;
5213 size = round_page(offset + size);
5214 va = trunc_page(va);
5215 for (i = 0; i < PMAP_PREINIT_MAPPING_COUNT; i++) {
5216 ppim = pmap_preinit_mapping + i;
5217 if (ppim->va == va && ppim->sz == size) {
5218 if (pmap_initialized)
5219 return;
5220 ppim->pa = 0;
5221 ppim->va = 0;
5222 ppim->sz = 0;
5223 ppim->mode = 0;
5224 if (va + size == virtual_avail)
5225 virtual_avail = va;
5226 return;
5227 }
5228 }
5229 if (pmap_initialized)
5230 kva_free(va, size);
5231 }
5232
5233 /*
5234 * Sets the memory attribute for the specified page.
5235 */
5236 void
5237 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
5238 {
5239
5240 m->md.pat_mode = ma;
5241 if ((m->flags & PG_FICTITIOUS) != 0)
5242 return;
5243
5244 /*
5245 * If "m" is a normal page, flush it from the cache.
5246 * See pmap_invalidate_cache_range().
5247 *
5248 * First, try to find an existing mapping of the page by sf
5249 * buffer. sf_buf_invalidate_cache() modifies mapping and
5250 * flushes the cache.
5251 */
5252 if (sf_buf_invalidate_cache(m))
5253 return;
5254
5255 /*
5256 * If page is not mapped by sf buffer, but CPU does not
5257 * support self snoop, map the page transient and do
5258 * invalidation. In the worst case, whole cache is flushed by
5259 * pmap_invalidate_cache_range().
5260 */
5261 if ((cpu_feature & CPUID_SS) == 0)
5262 pmap_flush_page(m);
5263 }
5264
5265 static void
5266 pmap_flush_page(vm_page_t m)
5267 {
5268 struct sysmaps *sysmaps;
5269 vm_offset_t sva, eva;
5270 bool useclflushopt;
5271
5272 useclflushopt = (cpu_stdext_feature & CPUID_STDEXT_CLFLUSHOPT) != 0;
5273 if (useclflushopt || (cpu_feature & CPUID_CLFSH) != 0) {
5274 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
5275 mtx_lock(&sysmaps->lock);
5276 if (*sysmaps->CMAP2)
5277 panic("pmap_flush_page: CMAP2 busy");
5278 sched_pin();
5279 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
5280 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
5281 invlcaddr(sysmaps->CADDR2);
5282 sva = (vm_offset_t)sysmaps->CADDR2;
5283 eva = sva + PAGE_SIZE;
5284
5285 /*
5286 * Use mfence despite the ordering implied by
5287 * mtx_{un,}lock() because clflush on non-Intel CPUs
5288 * and clflushopt are not guaranteed to be ordered by
5289 * any other instruction.
5290 */
5291 if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL)
5292 mfence();
5293 for (; sva < eva; sva += cpu_clflush_line_size) {
5294 if (useclflushopt)
5295 clflushopt(sva);
5296 else
5297 clflush(sva);
5298 }
5299 if (useclflushopt || cpu_vendor_id != CPU_VENDOR_INTEL)
5300 mfence();
5301 *sysmaps->CMAP2 = 0;
5302 sched_unpin();
5303 mtx_unlock(&sysmaps->lock);
5304 } else
5305 pmap_invalidate_cache();
5306 }
5307
5308 /*
5309 * Changes the specified virtual address range's memory type to that given by
5310 * the parameter "mode". The specified virtual address range must be
5311 * completely contained within either the kernel map.
5312 *
5313 * Returns zero if the change completed successfully, and either EINVAL or
5314 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
5315 * of the virtual address range was not mapped, and ENOMEM is returned if
5316 * there was insufficient memory available to complete the change.
5317 */
5318 int
5319 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
5320 {
5321 vm_offset_t base, offset, tmpva;
5322 pd_entry_t *pde;
5323 pt_entry_t *pte;
5324 int cache_bits_pte, cache_bits_pde;
5325 boolean_t changed;
5326
5327 base = trunc_page(va);
5328 offset = va & PAGE_MASK;
5329 size = round_page(offset + size);
5330
5331 /*
5332 * Only supported on kernel virtual addresses above the recursive map.
5333 */
5334 if (base < VM_MIN_KERNEL_ADDRESS)
5335 return (EINVAL);
5336
5337 cache_bits_pde = pmap_cache_bits(mode, 1);
5338 cache_bits_pte = pmap_cache_bits(mode, 0);
5339 changed = FALSE;
5340
5341 /*
5342 * Pages that aren't mapped aren't supported. Also break down
5343 * 2/4MB pages into 4KB pages if required.
5344 */
5345 PMAP_LOCK(kernel_pmap);
5346 for (tmpva = base; tmpva < base + size; ) {
5347 pde = pmap_pde(kernel_pmap, tmpva);
5348 if (*pde == 0) {
5349 PMAP_UNLOCK(kernel_pmap);
5350 return (EINVAL);
5351 }
5352 if (*pde & PG_PS) {
5353 /*
5354 * If the current 2/4MB page already has
5355 * the required memory type, then we need not
5356 * demote this page. Just increment tmpva to
5357 * the next 2/4MB page frame.
5358 */
5359 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
5360 tmpva = trunc_4mpage(tmpva) + NBPDR;
5361 continue;
5362 }
5363
5364 /*
5365 * If the current offset aligns with a 2/4MB
5366 * page frame and there is at least 2/4MB left
5367 * within the range, then we need not break
5368 * down this page into 4KB pages.
5369 */
5370 if ((tmpva & PDRMASK) == 0 &&
5371 tmpva + PDRMASK < base + size) {
5372 tmpva += NBPDR;
5373 continue;
5374 }
5375 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
5376 PMAP_UNLOCK(kernel_pmap);
5377 return (ENOMEM);
5378 }
5379 }
5380 pte = vtopte(tmpva);
5381 if (*pte == 0) {
5382 PMAP_UNLOCK(kernel_pmap);
5383 return (EINVAL);
5384 }
5385 tmpva += PAGE_SIZE;
5386 }
5387 PMAP_UNLOCK(kernel_pmap);
5388
5389 /*
5390 * Ok, all the pages exist, so run through them updating their
5391 * cache mode if required.
5392 */
5393 for (tmpva = base; tmpva < base + size; ) {
5394 pde = pmap_pde(kernel_pmap, tmpva);
5395 if (*pde & PG_PS) {
5396 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
5397 pmap_pde_attr(pde, cache_bits_pde);
5398 changed = TRUE;
5399 }
5400 tmpva = trunc_4mpage(tmpva) + NBPDR;
5401 } else {
5402 pte = vtopte(tmpva);
5403 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
5404 pmap_pte_attr(pte, cache_bits_pte);
5405 changed = TRUE;
5406 }
5407 tmpva += PAGE_SIZE;
5408 }
5409 }
5410
5411 /*
5412 * Flush CPU caches to make sure any data isn't cached that
5413 * shouldn't be, etc.
5414 */
5415 if (changed) {
5416 pmap_invalidate_range(kernel_pmap, base, tmpva);
5417 pmap_invalidate_cache_range(base, tmpva, FALSE);
5418 }
5419 return (0);
5420 }
5421
5422 /*
5423 * perform the pmap work for mincore
5424 */
5425 int
5426 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
5427 {
5428 pd_entry_t *pdep;
5429 pt_entry_t *ptep, pte;
5430 vm_paddr_t pa;
5431 int val;
5432
5433 PMAP_LOCK(pmap);
5434 retry:
5435 pdep = pmap_pde(pmap, addr);
5436 if (*pdep != 0) {
5437 if (*pdep & PG_PS) {
5438 pte = *pdep;
5439 /* Compute the physical address of the 4KB page. */
5440 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
5441 PG_FRAME;
5442 val = MINCORE_SUPER;
5443 } else {
5444 ptep = pmap_pte(pmap, addr);
5445 pte = *ptep;
5446 pmap_pte_release(ptep);
5447 pa = pte & PG_FRAME;
5448 val = 0;
5449 }
5450 } else {
5451 pte = 0;
5452 pa = 0;
5453 val = 0;
5454 }
5455 if ((pte & PG_V) != 0) {
5456 val |= MINCORE_INCORE;
5457 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5458 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
5459 if ((pte & PG_A) != 0)
5460 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
5461 }
5462 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
5463 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
5464 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) {
5465 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
5466 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
5467 goto retry;
5468 } else
5469 PA_UNLOCK_COND(*locked_pa);
5470 PMAP_UNLOCK(pmap);
5471 return (val);
5472 }
5473
5474 void
5475 pmap_activate(struct thread *td)
5476 {
5477 pmap_t pmap, oldpmap;
5478 u_int cpuid;
5479 u_int32_t cr3;
5480
5481 critical_enter();
5482 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5483 oldpmap = PCPU_GET(curpmap);
5484 cpuid = PCPU_GET(cpuid);
5485 #if defined(SMP)
5486 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
5487 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
5488 #else
5489 CPU_CLR(cpuid, &oldpmap->pm_active);
5490 CPU_SET(cpuid, &pmap->pm_active);
5491 #endif
5492 #if defined(PAE) || defined(PAE_TABLES)
5493 cr3 = vtophys(pmap->pm_pdpt);
5494 #else
5495 cr3 = vtophys(pmap->pm_pdir);
5496 #endif
5497 /*
5498 * pmap_activate is for the current thread on the current cpu
5499 */
5500 td->td_pcb->pcb_cr3 = cr3;
5501 load_cr3(cr3);
5502 PCPU_SET(curpmap, pmap);
5503 critical_exit();
5504 }
5505
5506 void
5507 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5508 {
5509 }
5510
5511 /*
5512 * Increase the starting virtual address of the given mapping if a
5513 * different alignment might result in more superpage mappings.
5514 */
5515 void
5516 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5517 vm_offset_t *addr, vm_size_t size)
5518 {
5519 vm_offset_t superpage_offset;
5520
5521 if (size < NBPDR)
5522 return;
5523 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5524 offset += ptoa(object->pg_color);
5525 superpage_offset = offset & PDRMASK;
5526 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5527 (*addr & PDRMASK) == superpage_offset)
5528 return;
5529 if ((*addr & PDRMASK) < superpage_offset)
5530 *addr = (*addr & ~PDRMASK) + superpage_offset;
5531 else
5532 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5533 }
5534
5535 vm_offset_t
5536 pmap_quick_enter_page(vm_page_t m)
5537 {
5538 vm_offset_t qaddr;
5539 pt_entry_t *pte;
5540
5541 critical_enter();
5542 qaddr = PCPU_GET(qmap_addr);
5543 pte = vtopte(qaddr);
5544
5545 KASSERT(*pte == 0, ("pmap_quick_enter_page: PTE busy"));
5546 *pte = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
5547 pmap_cache_bits(pmap_page_get_memattr(m), 0);
5548 invlpg(qaddr);
5549
5550 return (qaddr);
5551 }
5552
5553 void
5554 pmap_quick_remove_page(vm_offset_t addr)
5555 {
5556 vm_offset_t qaddr;
5557 pt_entry_t *pte;
5558
5559 qaddr = PCPU_GET(qmap_addr);
5560 pte = vtopte(qaddr);
5561
5562 KASSERT(*pte != 0, ("pmap_quick_remove_page: PTE not in use"));
5563 KASSERT(addr == qaddr, ("pmap_quick_remove_page: invalid address"));
5564
5565 *pte = 0;
5566 critical_exit();
5567 }
5568
5569 #if defined(PMAP_DEBUG)
5570 pmap_pid_dump(int pid)
5571 {
5572 pmap_t pmap;
5573 struct proc *p;
5574 int npte = 0;
5575 int index;
5576
5577 sx_slock(&allproc_lock);
5578 FOREACH_PROC_IN_SYSTEM(p) {
5579 if (p->p_pid != pid)
5580 continue;
5581
5582 if (p->p_vmspace) {
5583 int i,j;
5584 index = 0;
5585 pmap = vmspace_pmap(p->p_vmspace);
5586 for (i = 0; i < NPDEPTD; i++) {
5587 pd_entry_t *pde;
5588 pt_entry_t *pte;
5589 vm_offset_t base = i << PDRSHIFT;
5590
5591 pde = &pmap->pm_pdir[i];
5592 if (pde && pmap_pde_v(pde)) {
5593 for (j = 0; j < NPTEPG; j++) {
5594 vm_offset_t va = base + (j << PAGE_SHIFT);
5595 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5596 if (index) {
5597 index = 0;
5598 printf("\n");
5599 }
5600 sx_sunlock(&allproc_lock);
5601 return (npte);
5602 }
5603 pte = pmap_pte(pmap, va);
5604 if (pte && pmap_pte_v(pte)) {
5605 pt_entry_t pa;
5606 vm_page_t m;
5607 pa = *pte;
5608 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5609 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5610 va, pa, m->hold_count, m->wire_count, m->flags);
5611 npte++;
5612 index++;
5613 if (index >= 2) {
5614 index = 0;
5615 printf("\n");
5616 } else {
5617 printf(" ");
5618 }
5619 }
5620 }
5621 }
5622 }
5623 }
5624 }
5625 sx_sunlock(&allproc_lock);
5626 return (npte);
5627 }
5628 #endif
Cache object: 4d7c0df02ad76bce08f6e79f26c8b05c
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