FreeBSD/Linux Kernel Cross Reference
sys/i386/i386/pmap.c
1 /*-
2 * Copyright (c) 1991 Regents of the University of California.
3 * All rights reserved.
4 * Copyright (c) 1994 John S. Dyson
5 * All rights reserved.
6 * Copyright (c) 1994 David Greenman
7 * All rights reserved.
8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu>
9 * All rights reserved.
10 *
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
14 *
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
17 * are met:
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the University of
26 * California, Berkeley and its contributors.
27 * 4. Neither the name of the University nor the names of its contributors
28 * may be used to endorse or promote products derived from this software
29 * without specific prior written permission.
30 *
31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
41 * SUCH DAMAGE.
42 *
43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
44 */
45 /*-
46 * Copyright (c) 2003 Networks Associates Technology, Inc.
47 * All rights reserved.
48 *
49 * This software was developed for the FreeBSD Project by Jake Burkholder,
50 * Safeport Network Services, and Network Associates Laboratories, the
51 * Security Research Division of Network Associates, Inc. under
52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA
53 * CHATS research program.
54 *
55 * Redistribution and use in source and binary forms, with or without
56 * modification, are permitted provided that the following conditions
57 * are met:
58 * 1. Redistributions of source code must retain the above copyright
59 * notice, this list of conditions and the following disclaimer.
60 * 2. Redistributions in binary form must reproduce the above copyright
61 * notice, this list of conditions and the following disclaimer in the
62 * documentation and/or other materials provided with the distribution.
63 *
64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
74 * SUCH DAMAGE.
75 */
76
77 #include <sys/cdefs.h>
78 __FBSDID("$FreeBSD: releng/8.4/sys/i386/i386/pmap.c 247548 2013-03-01 14:54:37Z jhb $");
79
80 /*
81 * Manages physical address maps.
82 *
83 * In addition to hardware address maps, this
84 * module is called upon to provide software-use-only
85 * maps which may or may not be stored in the same
86 * form as hardware maps. These pseudo-maps are
87 * used to store intermediate results from copy
88 * operations to and from address spaces.
89 *
90 * Since the information managed by this module is
91 * also stored by the logical address mapping module,
92 * this module may throw away valid virtual-to-physical
93 * mappings at almost any time. However, invalidations
94 * of virtual-to-physical mappings must be done as
95 * requested.
96 *
97 * In order to cope with hardware architectures which
98 * make virtual-to-physical map invalidates expensive,
99 * this module may delay invalidate or reduced protection
100 * operations until such time as they are actually
101 * necessary. This module is given full information as
102 * to which processors are currently using which maps,
103 * and to when physical maps must be made correct.
104 */
105
106 #include "opt_apic.h"
107 #include "opt_cpu.h"
108 #include "opt_pmap.h"
109 #include "opt_smp.h"
110 #include "opt_xbox.h"
111
112 #include <sys/param.h>
113 #include <sys/systm.h>
114 #include <sys/kernel.h>
115 #include <sys/ktr.h>
116 #include <sys/lock.h>
117 #include <sys/malloc.h>
118 #include <sys/mman.h>
119 #include <sys/msgbuf.h>
120 #include <sys/mutex.h>
121 #include <sys/proc.h>
122 #include <sys/sf_buf.h>
123 #include <sys/sx.h>
124 #include <sys/vmmeter.h>
125 #include <sys/sched.h>
126 #include <sys/sysctl.h>
127 #ifdef SMP
128 #include <sys/smp.h>
129 #endif
130
131 #include <vm/vm.h>
132 #include <vm/vm_param.h>
133 #include <vm/vm_kern.h>
134 #include <vm/vm_page.h>
135 #include <vm/vm_map.h>
136 #include <vm/vm_object.h>
137 #include <vm/vm_extern.h>
138 #include <vm/vm_pageout.h>
139 #include <vm/vm_pager.h>
140 #include <vm/vm_reserv.h>
141 #include <vm/uma.h>
142
143 #ifdef DEV_APIC
144 #include <sys/bus.h>
145 #include <machine/intr_machdep.h>
146 #include <machine/apicvar.h>
147 #endif
148 #include <machine/cpu.h>
149 #include <machine/cputypes.h>
150 #include <machine/md_var.h>
151 #include <machine/pcb.h>
152 #include <machine/specialreg.h>
153 #ifdef SMP
154 #include <machine/smp.h>
155 #endif
156
157 #ifdef XBOX
158 #include <machine/xbox.h>
159 #endif
160
161 #if !defined(CPU_DISABLE_SSE) && defined(I686_CPU)
162 #define CPU_ENABLE_SSE
163 #endif
164
165 #ifndef PMAP_SHPGPERPROC
166 #define PMAP_SHPGPERPROC 200
167 #endif
168
169 #if !defined(DIAGNOSTIC)
170 #define PMAP_INLINE __gnu89_inline
171 #else
172 #define PMAP_INLINE
173 #endif
174
175 #ifdef PV_STATS
176 #define PV_STAT(x) do { x ; } while (0)
177 #else
178 #define PV_STAT(x) do { } while (0)
179 #endif
180
181 #define pa_index(pa) ((pa) >> PDRSHIFT)
182 #define pa_to_pvh(pa) (&pv_table[pa_index(pa)])
183
184 /*
185 * Get PDEs and PTEs for user/kernel address space
186 */
187 #define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT]))
188 #define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT])
189
190 #define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0)
191 #define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0)
192 #define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0)
193 #define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0)
194 #define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0)
195
196 #define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \
197 atomic_clear_int((u_int *)(pte), PG_W))
198 #define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v)))
199
200 struct pmap kernel_pmap_store;
201 LIST_HEAD(pmaplist, pmap);
202 static struct pmaplist allpmaps;
203 static struct mtx allpmaps_lock;
204
205 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
206 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
207 int pgeflag = 0; /* PG_G or-in */
208 int pseflag = 0; /* PG_PS or-in */
209
210 static int nkpt;
211 vm_offset_t kernel_vm_end;
212 extern u_int32_t KERNend;
213 extern u_int32_t KPTphys;
214
215 #ifdef PAE
216 pt_entry_t pg_nx;
217 static uma_zone_t pdptzone;
218 #endif
219
220 SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
221
222 static int pat_works = 1;
223 SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1,
224 "Is page attribute table fully functional?");
225
226 static int pg_ps_enabled;
227 SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0,
228 "Are large page mappings enabled?");
229
230 #define PAT_INDEX_SIZE 8
231 static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */
232
233 /*
234 * Data for the pv entry allocation mechanism
235 */
236 static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0;
237 static struct md_page *pv_table;
238 static int shpgperproc = PMAP_SHPGPERPROC;
239
240 struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */
241 int pv_maxchunks; /* How many chunks we have KVA for */
242 vm_offset_t pv_vafree; /* freelist stored in the PTE */
243
244 /*
245 * All those kernel PT submaps that BSD is so fond of
246 */
247 struct sysmaps {
248 struct mtx lock;
249 pt_entry_t *CMAP1;
250 pt_entry_t *CMAP2;
251 caddr_t CADDR1;
252 caddr_t CADDR2;
253 };
254 static struct sysmaps sysmaps_pcpu[MAXCPU];
255 pt_entry_t *CMAP1 = 0;
256 static pt_entry_t *CMAP3;
257 static pd_entry_t *KPTD;
258 caddr_t CADDR1 = 0, ptvmmap = 0;
259 static caddr_t CADDR3;
260 struct msgbuf *msgbufp = 0;
261
262 /*
263 * Crashdump maps.
264 */
265 static caddr_t crashdumpmap;
266
267 static pt_entry_t *PMAP1 = 0, *PMAP2;
268 static pt_entry_t *PADDR1 = 0, *PADDR2;
269 #ifdef SMP
270 static int PMAP1cpu;
271 static int PMAP1changedcpu;
272 SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD,
273 &PMAP1changedcpu, 0,
274 "Number of times pmap_pte_quick changed CPU with same PMAP1");
275 #endif
276 static int PMAP1changed;
277 SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD,
278 &PMAP1changed, 0,
279 "Number of times pmap_pte_quick changed PMAP1");
280 static int PMAP1unchanged;
281 SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD,
282 &PMAP1unchanged, 0,
283 "Number of times pmap_pte_quick didn't change PMAP1");
284 static struct mtx PMAP2mutex;
285
286 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
287 static pv_entry_t get_pv_entry(pmap_t locked_pmap, int try);
288 static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
289 static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
290 static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa);
291 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
292 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
293 vm_offset_t va);
294 static int pmap_pvh_wired_mappings(struct md_page *pvh, int count);
295
296 static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
297 static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m,
298 vm_prot_t prot);
299 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
300 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
301 static void pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte);
302 static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte);
303 static boolean_t pmap_is_modified_pvh(struct md_page *pvh);
304 static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode);
305 static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde);
306 static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va);
307 static void pmap_pde_attr(pd_entry_t *pde, int cache_bits);
308 static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va);
309 static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva,
310 vm_prot_t prot);
311 static void pmap_pte_attr(pt_entry_t *pte, int cache_bits);
312 static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
313 vm_page_t *free);
314 static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva,
315 vm_page_t *free);
316 static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte);
317 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va,
318 vm_page_t *free);
319 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m,
320 vm_offset_t va);
321 static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m);
322 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va,
323 vm_page_t m);
324 static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde,
325 pd_entry_t newpde);
326 static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde);
327
328 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags);
329
330 static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags);
331 static int _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free);
332 static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va);
333 static void pmap_pte_release(pt_entry_t *pte);
334 static int pmap_unuse_pt(pmap_t, vm_offset_t, vm_page_t *);
335 static vm_offset_t pmap_kmem_choose(vm_offset_t addr);
336 #ifdef PAE
337 static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait);
338 #endif
339
340 CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t));
341 CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t));
342
343 /*
344 * If you get an error here, then you set KVA_PAGES wrong! See the
345 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be
346 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE.
347 */
348 CTASSERT(KERNBASE % (1 << 24) == 0);
349
350 /*
351 * Move the kernel virtual free pointer to the next
352 * 4MB. This is used to help improve performance
353 * by using a large (4MB) page for much of the kernel
354 * (.text, .data, .bss)
355 */
356 static vm_offset_t
357 pmap_kmem_choose(vm_offset_t addr)
358 {
359 vm_offset_t newaddr = addr;
360
361 #ifndef DISABLE_PSE
362 if (cpu_feature & CPUID_PSE)
363 newaddr = (addr + PDRMASK) & ~PDRMASK;
364 #endif
365 return newaddr;
366 }
367
368 /*
369 * Bootstrap the system enough to run with virtual memory.
370 *
371 * On the i386 this is called after mapping has already been enabled
372 * and just syncs the pmap module with what has already been done.
373 * [We can't call it easily with mapping off since the kernel is not
374 * mapped with PA == VA, hence we would have to relocate every address
375 * from the linked base (virtual) address "KERNBASE" to the actual
376 * (physical) address starting relative to 0]
377 */
378 void
379 pmap_bootstrap(vm_paddr_t firstaddr)
380 {
381 vm_offset_t va;
382 pt_entry_t *pte, *unused;
383 struct sysmaps *sysmaps;
384 int i;
385
386 /*
387 * Initialize the first available kernel virtual address. However,
388 * using "firstaddr" may waste a few pages of the kernel virtual
389 * address space, because locore may not have mapped every physical
390 * page that it allocated. Preferably, locore would provide a first
391 * unused virtual address in addition to "firstaddr".
392 */
393 virtual_avail = (vm_offset_t) KERNBASE + firstaddr;
394 virtual_avail = pmap_kmem_choose(virtual_avail);
395
396 virtual_end = VM_MAX_KERNEL_ADDRESS;
397
398 /*
399 * Initialize the kernel pmap (which is statically allocated).
400 */
401 PMAP_LOCK_INIT(kernel_pmap);
402 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD);
403 #ifdef PAE
404 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT);
405 #endif
406 kernel_pmap->pm_root = NULL;
407 kernel_pmap->pm_active = -1; /* don't allow deactivation */
408 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
409 LIST_INIT(&allpmaps);
410
411 /*
412 * Request a spin mutex so that changes to allpmaps cannot be
413 * preempted by smp_rendezvous_cpus(). Otherwise,
414 * pmap_update_pde_kernel() could access allpmaps while it is
415 * being changed.
416 */
417 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN);
418 mtx_lock_spin(&allpmaps_lock);
419 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list);
420 mtx_unlock_spin(&allpmaps_lock);
421 nkpt = NKPT;
422
423 /*
424 * Reserve some special page table entries/VA space for temporary
425 * mapping of pages.
426 */
427 #define SYSMAP(c, p, v, n) \
428 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n);
429
430 va = virtual_avail;
431 pte = vtopte(va);
432
433 /*
434 * CMAP1/CMAP2 are used for zeroing and copying pages.
435 * CMAP3 is used for the idle process page zeroing.
436 */
437 for (i = 0; i < MAXCPU; i++) {
438 sysmaps = &sysmaps_pcpu[i];
439 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF);
440 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1)
441 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1)
442 }
443 SYSMAP(caddr_t, CMAP1, CADDR1, 1)
444 SYSMAP(caddr_t, CMAP3, CADDR3, 1)
445
446 /*
447 * Crashdump maps.
448 */
449 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS)
450
451 /*
452 * ptvmmap is used for reading arbitrary physical pages via /dev/mem.
453 */
454 SYSMAP(caddr_t, unused, ptvmmap, 1)
455
456 /*
457 * msgbufp is used to map the system message buffer.
458 */
459 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize)))
460
461 /*
462 * KPTmap is used by pmap_kextract().
463 *
464 * KPTmap is first initialized by locore. However, that initial
465 * KPTmap can only support NKPT page table pages. Here, a larger
466 * KPTmap is created that can support KVA_PAGES page table pages.
467 */
468 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES)
469
470 for (i = 0; i < NKPT; i++)
471 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V;
472
473 /*
474 * Adjust the start of the KPTD and KPTmap so that the implementation
475 * of pmap_kextract() and pmap_growkernel() can be made simpler.
476 */
477 KPTD -= KPTDI;
478 KPTmap -= i386_btop(KPTDI << PDRSHIFT);
479
480 /*
481 * ptemap is used for pmap_pte_quick
482 */
483 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1)
484 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1)
485
486 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF);
487
488 virtual_avail = va;
489
490 /*
491 * Leave in place an identity mapping (virt == phys) for the low 1 MB
492 * physical memory region that is used by the ACPI wakeup code. This
493 * mapping must not have PG_G set.
494 */
495 #ifdef XBOX
496 /* FIXME: This is gross, but needed for the XBOX. Since we are in such
497 * an early stadium, we cannot yet neatly map video memory ... :-(
498 * Better fixes are very welcome! */
499 if (!arch_i386_is_xbox)
500 #endif
501 for (i = 1; i < NKPT; i++)
502 PTD[i] = 0;
503
504 /* Initialize the PAT MSR if present. */
505 pmap_init_pat();
506
507 /* Turn on PG_G on kernel page(s) */
508 pmap_set_pg();
509 }
510
511 /*
512 * Setup the PAT MSR.
513 */
514 void
515 pmap_init_pat(void)
516 {
517 int pat_table[PAT_INDEX_SIZE];
518 uint64_t pat_msr;
519 u_long cr0, cr4;
520 int i;
521
522 /* Set default PAT index table. */
523 for (i = 0; i < PAT_INDEX_SIZE; i++)
524 pat_table[i] = -1;
525 pat_table[PAT_WRITE_BACK] = 0;
526 pat_table[PAT_WRITE_THROUGH] = 1;
527 pat_table[PAT_UNCACHEABLE] = 3;
528 pat_table[PAT_WRITE_COMBINING] = 3;
529 pat_table[PAT_WRITE_PROTECTED] = 3;
530 pat_table[PAT_UNCACHED] = 3;
531
532 /* Bail if this CPU doesn't implement PAT. */
533 if ((cpu_feature & CPUID_PAT) == 0) {
534 for (i = 0; i < PAT_INDEX_SIZE; i++)
535 pat_index[i] = pat_table[i];
536 pat_works = 0;
537 return;
538 }
539
540 /*
541 * Due to some Intel errata, we can only safely use the lower 4
542 * PAT entries.
543 *
544 * Intel Pentium III Processor Specification Update
545 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B
546 * or Mode C Paging)
547 *
548 * Intel Pentium IV Processor Specification Update
549 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly)
550 */
551 if (cpu_vendor_id == CPU_VENDOR_INTEL &&
552 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe))
553 pat_works = 0;
554
555 /* Initialize default PAT entries. */
556 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) |
557 PAT_VALUE(1, PAT_WRITE_THROUGH) |
558 PAT_VALUE(2, PAT_UNCACHED) |
559 PAT_VALUE(3, PAT_UNCACHEABLE) |
560 PAT_VALUE(4, PAT_WRITE_BACK) |
561 PAT_VALUE(5, PAT_WRITE_THROUGH) |
562 PAT_VALUE(6, PAT_UNCACHED) |
563 PAT_VALUE(7, PAT_UNCACHEABLE);
564
565 if (pat_works) {
566 /*
567 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC.
568 * Program 5 and 6 as WP and WC.
569 * Leave 4 and 7 as WB and UC.
570 */
571 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6));
572 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) |
573 PAT_VALUE(6, PAT_WRITE_COMBINING);
574 pat_table[PAT_UNCACHED] = 2;
575 pat_table[PAT_WRITE_PROTECTED] = 5;
576 pat_table[PAT_WRITE_COMBINING] = 6;
577 } else {
578 /*
579 * Just replace PAT Index 2 with WC instead of UC-.
580 */
581 pat_msr &= ~PAT_MASK(2);
582 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING);
583 pat_table[PAT_WRITE_COMBINING] = 2;
584 }
585
586 /* Disable PGE. */
587 cr4 = rcr4();
588 load_cr4(cr4 & ~CR4_PGE);
589
590 /* Disable caches (CD = 1, NW = 0). */
591 cr0 = rcr0();
592 load_cr0((cr0 & ~CR0_NW) | CR0_CD);
593
594 /* Flushes caches and TLBs. */
595 wbinvd();
596 invltlb();
597
598 /* Update PAT and index table. */
599 wrmsr(MSR_PAT, pat_msr);
600 for (i = 0; i < PAT_INDEX_SIZE; i++)
601 pat_index[i] = pat_table[i];
602
603 /* Flush caches and TLBs again. */
604 wbinvd();
605 invltlb();
606
607 /* Restore caches and PGE. */
608 load_cr0(cr0);
609 load_cr4(cr4);
610 }
611
612 /*
613 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on.
614 */
615 void
616 pmap_set_pg(void)
617 {
618 pt_entry_t *pte;
619 vm_offset_t va, endva;
620
621 if (pgeflag == 0)
622 return;
623
624 endva = KERNBASE + KERNend;
625
626 if (pseflag) {
627 va = KERNBASE + KERNLOAD;
628 while (va < endva) {
629 pdir_pde(PTD, va) |= pgeflag;
630 invltlb(); /* Play it safe, invltlb() every time */
631 va += NBPDR;
632 }
633 } else {
634 va = (vm_offset_t)btext;
635 while (va < endva) {
636 pte = vtopte(va);
637 if (*pte)
638 *pte |= pgeflag;
639 invltlb(); /* Play it safe, invltlb() every time */
640 va += PAGE_SIZE;
641 }
642 }
643 }
644
645 /*
646 * Initialize a vm_page's machine-dependent fields.
647 */
648 void
649 pmap_page_init(vm_page_t m)
650 {
651
652 TAILQ_INIT(&m->md.pv_list);
653 m->md.pat_mode = PAT_WRITE_BACK;
654 }
655
656 #ifdef PAE
657 static void *
658 pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait)
659 {
660
661 /* Inform UMA that this allocator uses kernel_map/object. */
662 *flags = UMA_SLAB_KERNEL;
663 return ((void *)kmem_alloc_contig(kernel_map, bytes, wait, 0x0ULL,
664 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT));
665 }
666 #endif
667
668 /*
669 * ABuse the pte nodes for unmapped kva to thread a kva freelist through.
670 * Requirements:
671 * - Must deal with pages in order to ensure that none of the PG_* bits
672 * are ever set, PG_V in particular.
673 * - Assumes we can write to ptes without pte_store() atomic ops, even
674 * on PAE systems. This should be ok.
675 * - Assumes nothing will ever test these addresses for 0 to indicate
676 * no mapping instead of correctly checking PG_V.
677 * - Assumes a vm_offset_t will fit in a pte (true for i386).
678 * Because PG_V is never set, there can be no mappings to invalidate.
679 */
680 static vm_offset_t
681 pmap_ptelist_alloc(vm_offset_t *head)
682 {
683 pt_entry_t *pte;
684 vm_offset_t va;
685
686 va = *head;
687 if (va == 0)
688 return (va); /* Out of memory */
689 pte = vtopte(va);
690 *head = *pte;
691 if (*head & PG_V)
692 panic("pmap_ptelist_alloc: va with PG_V set!");
693 *pte = 0;
694 return (va);
695 }
696
697 static void
698 pmap_ptelist_free(vm_offset_t *head, vm_offset_t va)
699 {
700 pt_entry_t *pte;
701
702 if (va & PG_V)
703 panic("pmap_ptelist_free: freeing va with PG_V set!");
704 pte = vtopte(va);
705 *pte = *head; /* virtual! PG_V is 0 though */
706 *head = va;
707 }
708
709 static void
710 pmap_ptelist_init(vm_offset_t *head, void *base, int npages)
711 {
712 int i;
713 vm_offset_t va;
714
715 *head = 0;
716 for (i = npages - 1; i >= 0; i--) {
717 va = (vm_offset_t)base + i * PAGE_SIZE;
718 pmap_ptelist_free(head, va);
719 }
720 }
721
722
723 /*
724 * Initialize the pmap module.
725 * Called by vm_init, to initialize any structures that the pmap
726 * system needs to map virtual memory.
727 */
728 void
729 pmap_init(void)
730 {
731 vm_page_t mpte;
732 vm_size_t s;
733 int i, pv_npg;
734
735 /*
736 * Initialize the vm page array entries for the kernel pmap's
737 * page table pages.
738 */
739 for (i = 0; i < NKPT; i++) {
740 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT));
741 KASSERT(mpte >= vm_page_array &&
742 mpte < &vm_page_array[vm_page_array_size],
743 ("pmap_init: page table page is out of range"));
744 mpte->pindex = i + KPTDI;
745 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT);
746 }
747
748 /*
749 * Initialize the address space (zone) for the pv entries. Set a
750 * high water mark so that the system can recover from excessive
751 * numbers of pv entries.
752 */
753 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc);
754 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count;
755 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max);
756 pv_entry_max = roundup(pv_entry_max, _NPCPV);
757 pv_entry_high_water = 9 * (pv_entry_max / 10);
758
759 /*
760 * If the kernel is running in a virtual machine on an AMD Family 10h
761 * processor, then it must assume that MCA is enabled by the virtual
762 * machine monitor.
763 */
764 if (vm_guest == VM_GUEST_VM && cpu_vendor_id == CPU_VENDOR_AMD &&
765 CPUID_TO_FAMILY(cpu_id) == 0x10)
766 workaround_erratum383 = 1;
767
768 /*
769 * Are large page mappings supported and enabled?
770 */
771 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled);
772 if (pseflag == 0)
773 pg_ps_enabled = 0;
774 else if (pg_ps_enabled) {
775 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0,
776 ("pmap_init: can't assign to pagesizes[1]"));
777 pagesizes[1] = NBPDR;
778 }
779
780 /*
781 * Calculate the size of the pv head table for superpages.
782 */
783 for (i = 0; phys_avail[i + 1]; i += 2);
784 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR;
785
786 /*
787 * Allocate memory for the pv head table for superpages.
788 */
789 s = (vm_size_t)(pv_npg * sizeof(struct md_page));
790 s = round_page(s);
791 pv_table = (struct md_page *)kmem_alloc(kernel_map, s);
792 for (i = 0; i < pv_npg; i++)
793 TAILQ_INIT(&pv_table[i].pv_list);
794
795 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc);
796 pv_chunkbase = (struct pv_chunk *)kmem_alloc_nofault(kernel_map,
797 PAGE_SIZE * pv_maxchunks);
798 if (pv_chunkbase == NULL)
799 panic("pmap_init: not enough kvm for pv chunks");
800 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks);
801 #ifdef PAE
802 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL,
803 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1,
804 UMA_ZONE_VM | UMA_ZONE_NOFREE);
805 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf);
806 #endif
807 }
808
809
810 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0,
811 "Max number of PV entries");
812 SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0,
813 "Page share factor per proc");
814
815 SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0,
816 "2/4MB page mapping counters");
817
818 static u_long pmap_pde_demotions;
819 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD,
820 &pmap_pde_demotions, 0, "2/4MB page demotions");
821
822 static u_long pmap_pde_mappings;
823 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD,
824 &pmap_pde_mappings, 0, "2/4MB page mappings");
825
826 static u_long pmap_pde_p_failures;
827 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD,
828 &pmap_pde_p_failures, 0, "2/4MB page promotion failures");
829
830 static u_long pmap_pde_promotions;
831 SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD,
832 &pmap_pde_promotions, 0, "2/4MB page promotions");
833
834 /***************************************************
835 * Low level helper routines.....
836 ***************************************************/
837
838 /*
839 * Determine the appropriate bits to set in a PTE or PDE for a specified
840 * caching mode.
841 */
842 int
843 pmap_cache_bits(int mode, boolean_t is_pde)
844 {
845 int cache_bits, pat_flag, pat_idx;
846
847 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0)
848 panic("Unknown caching mode %d\n", mode);
849
850 /* The PAT bit is different for PTE's and PDE's. */
851 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT;
852
853 /* Map the caching mode to a PAT index. */
854 pat_idx = pat_index[mode];
855
856 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */
857 cache_bits = 0;
858 if (pat_idx & 0x4)
859 cache_bits |= pat_flag;
860 if (pat_idx & 0x2)
861 cache_bits |= PG_NC_PCD;
862 if (pat_idx & 0x1)
863 cache_bits |= PG_NC_PWT;
864 return (cache_bits);
865 }
866
867 /*
868 * The caller is responsible for maintaining TLB consistency.
869 */
870 static void
871 pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde)
872 {
873 pd_entry_t *pde;
874 pmap_t pmap;
875 boolean_t PTD_updated;
876
877 PTD_updated = FALSE;
878 mtx_lock_spin(&allpmaps_lock);
879 LIST_FOREACH(pmap, &allpmaps, pm_list) {
880 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] &
881 PG_FRAME))
882 PTD_updated = TRUE;
883 pde = pmap_pde(pmap, va);
884 pde_store(pde, newpde);
885 }
886 mtx_unlock_spin(&allpmaps_lock);
887 KASSERT(PTD_updated,
888 ("pmap_kenter_pde: current page table is not in allpmaps"));
889 }
890
891 /*
892 * After changing the page size for the specified virtual address in the page
893 * table, flush the corresponding entries from the processor's TLB. Only the
894 * calling processor's TLB is affected.
895 *
896 * The calling thread must be pinned to a processor.
897 */
898 static void
899 pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde)
900 {
901 u_long cr4;
902
903 if ((newpde & PG_PS) == 0)
904 /* Demotion: flush a specific 2MB page mapping. */
905 invlpg(va);
906 else if ((newpde & PG_G) == 0)
907 /*
908 * Promotion: flush every 4KB page mapping from the TLB
909 * because there are too many to flush individually.
910 */
911 invltlb();
912 else {
913 /*
914 * Promotion: flush every 4KB page mapping from the TLB,
915 * including any global (PG_G) mappings.
916 */
917 cr4 = rcr4();
918 load_cr4(cr4 & ~CR4_PGE);
919 /*
920 * Although preemption at this point could be detrimental to
921 * performance, it would not lead to an error. PG_G is simply
922 * ignored if CR4.PGE is clear. Moreover, in case this block
923 * is re-entered, the load_cr4() either above or below will
924 * modify CR4.PGE flushing the TLB.
925 */
926 load_cr4(cr4 | CR4_PGE);
927 }
928 }
929 #ifdef SMP
930 /*
931 * For SMP, these functions have to use the IPI mechanism for coherence.
932 *
933 * N.B.: Before calling any of the following TLB invalidation functions,
934 * the calling processor must ensure that all stores updating a non-
935 * kernel page table are globally performed. Otherwise, another
936 * processor could cache an old, pre-update entry without being
937 * invalidated. This can happen one of two ways: (1) The pmap becomes
938 * active on another processor after its pm_active field is checked by
939 * one of the following functions but before a store updating the page
940 * table is globally performed. (2) The pmap becomes active on another
941 * processor before its pm_active field is checked but due to
942 * speculative loads one of the following functions stills reads the
943 * pmap as inactive on the other processor.
944 *
945 * The kernel page table is exempt because its pm_active field is
946 * immutable. The kernel page table is always active on every
947 * processor.
948 */
949 void
950 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
951 {
952 cpumask_t cpumask, other_cpus;
953
954 sched_pin();
955 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) {
956 invlpg(va);
957 smp_invlpg(va);
958 } else {
959 cpumask = PCPU_GET(cpumask);
960 other_cpus = PCPU_GET(other_cpus);
961 if (pmap->pm_active & cpumask)
962 invlpg(va);
963 if (pmap->pm_active & other_cpus)
964 smp_masked_invlpg(pmap->pm_active & other_cpus, va);
965 }
966 sched_unpin();
967 }
968
969 void
970 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
971 {
972 cpumask_t cpumask, other_cpus;
973 vm_offset_t addr;
974
975 sched_pin();
976 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) {
977 for (addr = sva; addr < eva; addr += PAGE_SIZE)
978 invlpg(addr);
979 smp_invlpg_range(sva, eva);
980 } else {
981 cpumask = PCPU_GET(cpumask);
982 other_cpus = PCPU_GET(other_cpus);
983 if (pmap->pm_active & cpumask)
984 for (addr = sva; addr < eva; addr += PAGE_SIZE)
985 invlpg(addr);
986 if (pmap->pm_active & other_cpus)
987 smp_masked_invlpg_range(pmap->pm_active & other_cpus,
988 sva, eva);
989 }
990 sched_unpin();
991 }
992
993 void
994 pmap_invalidate_all(pmap_t pmap)
995 {
996 cpumask_t cpumask, other_cpus;
997
998 sched_pin();
999 if (pmap == kernel_pmap || pmap->pm_active == all_cpus) {
1000 invltlb();
1001 smp_invltlb();
1002 } else {
1003 cpumask = PCPU_GET(cpumask);
1004 other_cpus = PCPU_GET(other_cpus);
1005 if (pmap->pm_active & cpumask)
1006 invltlb();
1007 if (pmap->pm_active & other_cpus)
1008 smp_masked_invltlb(pmap->pm_active & other_cpus);
1009 }
1010 sched_unpin();
1011 }
1012
1013 void
1014 pmap_invalidate_cache(void)
1015 {
1016
1017 sched_pin();
1018 wbinvd();
1019 smp_cache_flush();
1020 sched_unpin();
1021 }
1022
1023 struct pde_action {
1024 cpumask_t store; /* processor that updates the PDE */
1025 cpumask_t invalidate; /* processors that invalidate their TLB */
1026 vm_offset_t va;
1027 pd_entry_t *pde;
1028 pd_entry_t newpde;
1029 };
1030
1031 static void
1032 pmap_update_pde_kernel(void *arg)
1033 {
1034 struct pde_action *act = arg;
1035 pd_entry_t *pde;
1036 pmap_t pmap;
1037
1038 if (act->store == PCPU_GET(cpumask))
1039 /*
1040 * Elsewhere, this operation requires allpmaps_lock for
1041 * synchronization. Here, it does not because it is being
1042 * performed in the context of an all_cpus rendezvous.
1043 */
1044 LIST_FOREACH(pmap, &allpmaps, pm_list) {
1045 pde = pmap_pde(pmap, act->va);
1046 pde_store(pde, act->newpde);
1047 }
1048 }
1049
1050 static void
1051 pmap_update_pde_user(void *arg)
1052 {
1053 struct pde_action *act = arg;
1054
1055 if (act->store == PCPU_GET(cpumask))
1056 pde_store(act->pde, act->newpde);
1057 }
1058
1059 static void
1060 pmap_update_pde_teardown(void *arg)
1061 {
1062 struct pde_action *act = arg;
1063
1064 if ((act->invalidate & PCPU_GET(cpumask)) != 0)
1065 pmap_update_pde_invalidate(act->va, act->newpde);
1066 }
1067
1068 /*
1069 * Change the page size for the specified virtual address in a way that
1070 * prevents any possibility of the TLB ever having two entries that map the
1071 * same virtual address using different page sizes. This is the recommended
1072 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a
1073 * machine check exception for a TLB state that is improperly diagnosed as a
1074 * hardware error.
1075 */
1076 static void
1077 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1078 {
1079 struct pde_action act;
1080 cpumask_t active, cpumask;
1081
1082 sched_pin();
1083 cpumask = PCPU_GET(cpumask);
1084 if (pmap == kernel_pmap)
1085 active = all_cpus;
1086 else
1087 active = pmap->pm_active;
1088 if ((active & PCPU_GET(other_cpus)) != 0) {
1089 act.store = cpumask;
1090 act.invalidate = active;
1091 act.va = va;
1092 act.pde = pde;
1093 act.newpde = newpde;
1094 smp_rendezvous_cpus(cpumask | active,
1095 smp_no_rendevous_barrier, pmap == kernel_pmap ?
1096 pmap_update_pde_kernel : pmap_update_pde_user,
1097 pmap_update_pde_teardown, &act);
1098 } else {
1099 if (pmap == kernel_pmap)
1100 pmap_kenter_pde(va, newpde);
1101 else
1102 pde_store(pde, newpde);
1103 if ((active & cpumask) != 0)
1104 pmap_update_pde_invalidate(va, newpde);
1105 }
1106 sched_unpin();
1107 }
1108 #else /* !SMP */
1109 /*
1110 * Normal, non-SMP, 486+ invalidation functions.
1111 * We inline these within pmap.c for speed.
1112 */
1113 PMAP_INLINE void
1114 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
1115 {
1116
1117 if (pmap == kernel_pmap || pmap->pm_active)
1118 invlpg(va);
1119 }
1120
1121 PMAP_INLINE void
1122 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1123 {
1124 vm_offset_t addr;
1125
1126 if (pmap == kernel_pmap || pmap->pm_active)
1127 for (addr = sva; addr < eva; addr += PAGE_SIZE)
1128 invlpg(addr);
1129 }
1130
1131 PMAP_INLINE void
1132 pmap_invalidate_all(pmap_t pmap)
1133 {
1134
1135 if (pmap == kernel_pmap || pmap->pm_active)
1136 invltlb();
1137 }
1138
1139 PMAP_INLINE void
1140 pmap_invalidate_cache(void)
1141 {
1142
1143 wbinvd();
1144 }
1145
1146 static void
1147 pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde)
1148 {
1149
1150 if (pmap == kernel_pmap)
1151 pmap_kenter_pde(va, newpde);
1152 else
1153 pde_store(pde, newpde);
1154 if (pmap == kernel_pmap || pmap->pm_active)
1155 pmap_update_pde_invalidate(va, newpde);
1156 }
1157 #endif /* !SMP */
1158
1159 void
1160 pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva)
1161 {
1162
1163 KASSERT((sva & PAGE_MASK) == 0,
1164 ("pmap_invalidate_cache_range: sva not page-aligned"));
1165 KASSERT((eva & PAGE_MASK) == 0,
1166 ("pmap_invalidate_cache_range: eva not page-aligned"));
1167
1168 if (cpu_feature & CPUID_SS)
1169 ; /* If "Self Snoop" is supported, do nothing. */
1170 else if ((cpu_feature & CPUID_CLFSH) != 0 &&
1171 eva - sva < 2 * 1024 * 1024) {
1172
1173 #ifdef DEV_APIC
1174 /*
1175 * XXX: Some CPUs fault, hang, or trash the local APIC
1176 * registers if we use CLFLUSH on the local APIC
1177 * range. The local APIC is always uncached, so we
1178 * don't need to flush for that range anyway.
1179 */
1180 if (pmap_kextract(sva) == lapic_paddr)
1181 return;
1182 #endif
1183 /*
1184 * Otherwise, do per-cache line flush. Use the mfence
1185 * instruction to insure that previous stores are
1186 * included in the write-back. The processor
1187 * propagates flush to other processors in the cache
1188 * coherence domain.
1189 */
1190 mfence();
1191 for (; sva < eva; sva += cpu_clflush_line_size)
1192 clflush(sva);
1193 mfence();
1194 } else {
1195
1196 /*
1197 * No targeted cache flush methods are supported by CPU,
1198 * or the supplied range is bigger than 2MB.
1199 * Globally invalidate cache.
1200 */
1201 pmap_invalidate_cache();
1202 }
1203 }
1204
1205 /*
1206 * Are we current address space or kernel? N.B. We return FALSE when
1207 * a pmap's page table is in use because a kernel thread is borrowing
1208 * it. The borrowed page table can change spontaneously, making any
1209 * dependence on its continued use subject to a race condition.
1210 */
1211 static __inline int
1212 pmap_is_current(pmap_t pmap)
1213 {
1214
1215 return (pmap == kernel_pmap ||
1216 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) &&
1217 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME)));
1218 }
1219
1220 /*
1221 * If the given pmap is not the current or kernel pmap, the returned pte must
1222 * be released by passing it to pmap_pte_release().
1223 */
1224 pt_entry_t *
1225 pmap_pte(pmap_t pmap, vm_offset_t va)
1226 {
1227 pd_entry_t newpf;
1228 pd_entry_t *pde;
1229
1230 pde = pmap_pde(pmap, va);
1231 if (*pde & PG_PS)
1232 return (pde);
1233 if (*pde != 0) {
1234 /* are we current address space or kernel? */
1235 if (pmap_is_current(pmap))
1236 return (vtopte(va));
1237 mtx_lock(&PMAP2mutex);
1238 newpf = *pde & PG_FRAME;
1239 if ((*PMAP2 & PG_FRAME) != newpf) {
1240 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M;
1241 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
1242 }
1243 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1)));
1244 }
1245 return (0);
1246 }
1247
1248 /*
1249 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte
1250 * being NULL.
1251 */
1252 static __inline void
1253 pmap_pte_release(pt_entry_t *pte)
1254 {
1255
1256 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2)
1257 mtx_unlock(&PMAP2mutex);
1258 }
1259
1260 static __inline void
1261 invlcaddr(void *caddr)
1262 {
1263
1264 invlpg((u_int)caddr);
1265 }
1266
1267 /*
1268 * Super fast pmap_pte routine best used when scanning
1269 * the pv lists. This eliminates many coarse-grained
1270 * invltlb calls. Note that many of the pv list
1271 * scans are across different pmaps. It is very wasteful
1272 * to do an entire invltlb for checking a single mapping.
1273 *
1274 * If the given pmap is not the current pmap, vm_page_queue_mtx
1275 * must be held and curthread pinned to a CPU.
1276 */
1277 static pt_entry_t *
1278 pmap_pte_quick(pmap_t pmap, vm_offset_t va)
1279 {
1280 pd_entry_t newpf;
1281 pd_entry_t *pde;
1282
1283 pde = pmap_pde(pmap, va);
1284 if (*pde & PG_PS)
1285 return (pde);
1286 if (*pde != 0) {
1287 /* are we current address space or kernel? */
1288 if (pmap_is_current(pmap))
1289 return (vtopte(va));
1290 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
1291 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
1292 newpf = *pde & PG_FRAME;
1293 if ((*PMAP1 & PG_FRAME) != newpf) {
1294 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M;
1295 #ifdef SMP
1296 PMAP1cpu = PCPU_GET(cpuid);
1297 #endif
1298 invlcaddr(PADDR1);
1299 PMAP1changed++;
1300 } else
1301 #ifdef SMP
1302 if (PMAP1cpu != PCPU_GET(cpuid)) {
1303 PMAP1cpu = PCPU_GET(cpuid);
1304 invlcaddr(PADDR1);
1305 PMAP1changedcpu++;
1306 } else
1307 #endif
1308 PMAP1unchanged++;
1309 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1)));
1310 }
1311 return (0);
1312 }
1313
1314 /*
1315 * Routine: pmap_extract
1316 * Function:
1317 * Extract the physical page address associated
1318 * with the given map/virtual_address pair.
1319 */
1320 vm_paddr_t
1321 pmap_extract(pmap_t pmap, vm_offset_t va)
1322 {
1323 vm_paddr_t rtval;
1324 pt_entry_t *pte;
1325 pd_entry_t pde;
1326
1327 rtval = 0;
1328 PMAP_LOCK(pmap);
1329 pde = pmap->pm_pdir[va >> PDRSHIFT];
1330 if (pde != 0) {
1331 if ((pde & PG_PS) != 0)
1332 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK);
1333 else {
1334 pte = pmap_pte(pmap, va);
1335 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK);
1336 pmap_pte_release(pte);
1337 }
1338 }
1339 PMAP_UNLOCK(pmap);
1340 return (rtval);
1341 }
1342
1343 /*
1344 * Routine: pmap_extract_and_hold
1345 * Function:
1346 * Atomically extract and hold the physical page
1347 * with the given pmap and virtual address pair
1348 * if that mapping permits the given protection.
1349 */
1350 vm_page_t
1351 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1352 {
1353 pd_entry_t pde;
1354 pt_entry_t pte;
1355 vm_page_t m;
1356
1357 m = NULL;
1358 vm_page_lock_queues();
1359 PMAP_LOCK(pmap);
1360 pde = *pmap_pde(pmap, va);
1361 if (pde != 0) {
1362 if (pde & PG_PS) {
1363 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) {
1364 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) |
1365 (va & PDRMASK));
1366 vm_page_hold(m);
1367 }
1368 } else {
1369 sched_pin();
1370 pte = *pmap_pte_quick(pmap, va);
1371 if (pte != 0 &&
1372 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) {
1373 m = PHYS_TO_VM_PAGE(pte & PG_FRAME);
1374 vm_page_hold(m);
1375 }
1376 sched_unpin();
1377 }
1378 }
1379 vm_page_unlock_queues();
1380 PMAP_UNLOCK(pmap);
1381 return (m);
1382 }
1383
1384 /***************************************************
1385 * Low level mapping routines.....
1386 ***************************************************/
1387
1388 /*
1389 * Add a wired page to the kva.
1390 * Note: not SMP coherent.
1391 *
1392 * This function may be used before pmap_bootstrap() is called.
1393 */
1394 PMAP_INLINE void
1395 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
1396 {
1397 pt_entry_t *pte;
1398
1399 pte = vtopte(va);
1400 pte_store(pte, pa | PG_RW | PG_V | pgeflag);
1401 }
1402
1403 static __inline void
1404 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode)
1405 {
1406 pt_entry_t *pte;
1407
1408 pte = vtopte(va);
1409 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0));
1410 }
1411
1412 /*
1413 * Remove a page from the kernel pagetables.
1414 * Note: not SMP coherent.
1415 *
1416 * This function may be used before pmap_bootstrap() is called.
1417 */
1418 PMAP_INLINE void
1419 pmap_kremove(vm_offset_t va)
1420 {
1421 pt_entry_t *pte;
1422
1423 pte = vtopte(va);
1424 pte_clear(pte);
1425 }
1426
1427 /*
1428 * Used to map a range of physical addresses into kernel
1429 * virtual address space.
1430 *
1431 * The value passed in '*virt' is a suggested virtual address for
1432 * the mapping. Architectures which can support a direct-mapped
1433 * physical to virtual region can return the appropriate address
1434 * within that region, leaving '*virt' unchanged. Other
1435 * architectures should map the pages starting at '*virt' and
1436 * update '*virt' with the first usable address after the mapped
1437 * region.
1438 */
1439 vm_offset_t
1440 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
1441 {
1442 vm_offset_t va, sva;
1443 vm_paddr_t superpage_offset;
1444 pd_entry_t newpde;
1445
1446 va = *virt;
1447 /*
1448 * Does the physical address range's size and alignment permit at
1449 * least one superpage mapping to be created?
1450 */
1451 superpage_offset = start & PDRMASK;
1452 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) {
1453 /*
1454 * Increase the starting virtual address so that its alignment
1455 * does not preclude the use of superpage mappings.
1456 */
1457 if ((va & PDRMASK) < superpage_offset)
1458 va = (va & ~PDRMASK) + superpage_offset;
1459 else if ((va & PDRMASK) > superpage_offset)
1460 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset;
1461 }
1462 sva = va;
1463 while (start < end) {
1464 if ((start & PDRMASK) == 0 && end - start >= NBPDR &&
1465 pseflag) {
1466 KASSERT((va & PDRMASK) == 0,
1467 ("pmap_map: misaligned va %#x", va));
1468 newpde = start | PG_PS | pgeflag | PG_RW | PG_V;
1469 pmap_kenter_pde(va, newpde);
1470 va += NBPDR;
1471 start += NBPDR;
1472 } else {
1473 pmap_kenter(va, start);
1474 va += PAGE_SIZE;
1475 start += PAGE_SIZE;
1476 }
1477 }
1478 pmap_invalidate_range(kernel_pmap, sva, va);
1479 *virt = va;
1480 return (sva);
1481 }
1482
1483
1484 /*
1485 * Add a list of wired pages to the kva
1486 * this routine is only used for temporary
1487 * kernel mappings that do not need to have
1488 * page modification or references recorded.
1489 * Note that old mappings are simply written
1490 * over. The page *must* be wired.
1491 * Note: SMP coherent. Uses a ranged shootdown IPI.
1492 */
1493 void
1494 pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count)
1495 {
1496 pt_entry_t *endpte, oldpte, pa, *pte;
1497 vm_page_t m;
1498
1499 oldpte = 0;
1500 pte = vtopte(sva);
1501 endpte = pte + count;
1502 while (pte < endpte) {
1503 m = *ma++;
1504 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
1505 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) {
1506 oldpte |= *pte;
1507 pte_store(pte, pa | pgeflag | PG_RW | PG_V);
1508 }
1509 pte++;
1510 }
1511 if (__predict_false((oldpte & PG_V) != 0))
1512 pmap_invalidate_range(kernel_pmap, sva, sva + count *
1513 PAGE_SIZE);
1514 }
1515
1516 /*
1517 * This routine tears out page mappings from the
1518 * kernel -- it is meant only for temporary mappings.
1519 * Note: SMP coherent. Uses a ranged shootdown IPI.
1520 */
1521 void
1522 pmap_qremove(vm_offset_t sva, int count)
1523 {
1524 vm_offset_t va;
1525
1526 va = sva;
1527 while (count-- > 0) {
1528 pmap_kremove(va);
1529 va += PAGE_SIZE;
1530 }
1531 pmap_invalidate_range(kernel_pmap, sva, va);
1532 }
1533
1534 /***************************************************
1535 * Page table page management routines.....
1536 ***************************************************/
1537 static __inline void
1538 pmap_free_zero_pages(vm_page_t free)
1539 {
1540 vm_page_t m;
1541
1542 while (free != NULL) {
1543 m = free;
1544 free = m->right;
1545 /* Preserve the page's PG_ZERO setting. */
1546 vm_page_free_toq(m);
1547 }
1548 }
1549
1550 /*
1551 * Schedule the specified unused page table page to be freed. Specifically,
1552 * add the page to the specified list of pages that will be released to the
1553 * physical memory manager after the TLB has been updated.
1554 */
1555 static __inline void
1556 pmap_add_delayed_free_list(vm_page_t m, vm_page_t *free, boolean_t set_PG_ZERO)
1557 {
1558
1559 if (set_PG_ZERO)
1560 m->flags |= PG_ZERO;
1561 else
1562 m->flags &= ~PG_ZERO;
1563 m->right = *free;
1564 *free = m;
1565 }
1566
1567 /*
1568 * Inserts the specified page table page into the specified pmap's collection
1569 * of idle page table pages. Each of a pmap's page table pages is responsible
1570 * for mapping a distinct range of virtual addresses. The pmap's collection is
1571 * ordered by this virtual address range.
1572 */
1573 static void
1574 pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte)
1575 {
1576 vm_page_t root;
1577
1578 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1579 root = pmap->pm_root;
1580 if (root == NULL) {
1581 mpte->left = NULL;
1582 mpte->right = NULL;
1583 } else {
1584 root = vm_page_splay(mpte->pindex, root);
1585 if (mpte->pindex < root->pindex) {
1586 mpte->left = root->left;
1587 mpte->right = root;
1588 root->left = NULL;
1589 } else if (mpte->pindex == root->pindex)
1590 panic("pmap_insert_pt_page: pindex already inserted");
1591 else {
1592 mpte->right = root->right;
1593 mpte->left = root;
1594 root->right = NULL;
1595 }
1596 }
1597 pmap->pm_root = mpte;
1598 }
1599
1600 /*
1601 * Looks for a page table page mapping the specified virtual address in the
1602 * specified pmap's collection of idle page table pages. Returns NULL if there
1603 * is no page table page corresponding to the specified virtual address.
1604 */
1605 static vm_page_t
1606 pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va)
1607 {
1608 vm_page_t mpte;
1609 vm_pindex_t pindex = va >> PDRSHIFT;
1610
1611 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1612 if ((mpte = pmap->pm_root) != NULL && mpte->pindex != pindex) {
1613 mpte = vm_page_splay(pindex, mpte);
1614 if ((pmap->pm_root = mpte)->pindex != pindex)
1615 mpte = NULL;
1616 }
1617 return (mpte);
1618 }
1619
1620 /*
1621 * Removes the specified page table page from the specified pmap's collection
1622 * of idle page table pages. The specified page table page must be a member of
1623 * the pmap's collection.
1624 */
1625 static void
1626 pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte)
1627 {
1628 vm_page_t root;
1629
1630 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1631 if (mpte != pmap->pm_root)
1632 vm_page_splay(mpte->pindex, pmap->pm_root);
1633 if (mpte->left == NULL)
1634 root = mpte->right;
1635 else {
1636 root = vm_page_splay(mpte->pindex, mpte->left);
1637 root->right = mpte->right;
1638 }
1639 pmap->pm_root = root;
1640 }
1641
1642 /*
1643 * This routine unholds page table pages, and if the hold count
1644 * drops to zero, then it decrements the wire count.
1645 */
1646 static __inline int
1647 pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free)
1648 {
1649
1650 --m->wire_count;
1651 if (m->wire_count == 0)
1652 return _pmap_unwire_pte_hold(pmap, m, free);
1653 else
1654 return 0;
1655 }
1656
1657 static int
1658 _pmap_unwire_pte_hold(pmap_t pmap, vm_page_t m, vm_page_t *free)
1659 {
1660 vm_offset_t pteva;
1661
1662 /*
1663 * unmap the page table page
1664 */
1665 pmap->pm_pdir[m->pindex] = 0;
1666 --pmap->pm_stats.resident_count;
1667
1668 /*
1669 * This is a release store so that the ordinary store unmapping
1670 * the page table page is globally performed before TLB shoot-
1671 * down is begun.
1672 */
1673 atomic_subtract_rel_int(&cnt.v_wire_count, 1);
1674
1675 /*
1676 * Do an invltlb to make the invalidated mapping
1677 * take effect immediately.
1678 */
1679 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex);
1680 pmap_invalidate_page(pmap, pteva);
1681
1682 /*
1683 * Put page on a list so that it is released after
1684 * *ALL* TLB shootdown is done
1685 */
1686 pmap_add_delayed_free_list(m, free, TRUE);
1687
1688 return 1;
1689 }
1690
1691 /*
1692 * After removing a page table entry, this routine is used to
1693 * conditionally free the page, and manage the hold/wire counts.
1694 */
1695 static int
1696 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, vm_page_t *free)
1697 {
1698 pd_entry_t ptepde;
1699 vm_page_t mpte;
1700
1701 if (va >= VM_MAXUSER_ADDRESS)
1702 return 0;
1703 ptepde = *pmap_pde(pmap, va);
1704 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME);
1705 return pmap_unwire_pte_hold(pmap, mpte, free);
1706 }
1707
1708 /*
1709 * Initialize the pmap for the swapper process.
1710 */
1711 void
1712 pmap_pinit0(pmap_t pmap)
1713 {
1714
1715 PMAP_LOCK_INIT(pmap);
1716 /*
1717 * Since the page table directory is shared with the kernel pmap,
1718 * which is already included in the list "allpmaps", this pmap does
1719 * not need to be inserted into that list.
1720 */
1721 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD);
1722 #ifdef PAE
1723 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT);
1724 #endif
1725 pmap->pm_root = NULL;
1726 pmap->pm_active = 0;
1727 PCPU_SET(curpmap, pmap);
1728 TAILQ_INIT(&pmap->pm_pvchunk);
1729 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1730 }
1731
1732 /*
1733 * Initialize a preallocated and zeroed pmap structure,
1734 * such as one in a vmspace structure.
1735 */
1736 int
1737 pmap_pinit(pmap_t pmap)
1738 {
1739 vm_page_t m, ptdpg[NPGPTD];
1740 vm_paddr_t pa;
1741 static int color;
1742 int i;
1743
1744 PMAP_LOCK_INIT(pmap);
1745
1746 /*
1747 * No need to allocate page table space yet but we do need a valid
1748 * page directory table.
1749 */
1750 if (pmap->pm_pdir == NULL) {
1751 pmap->pm_pdir = (pd_entry_t *)kmem_alloc_nofault(kernel_map,
1752 NBPTD);
1753
1754 if (pmap->pm_pdir == NULL) {
1755 PMAP_LOCK_DESTROY(pmap);
1756 return (0);
1757 }
1758 #ifdef PAE
1759 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO);
1760 KASSERT(((vm_offset_t)pmap->pm_pdpt &
1761 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0,
1762 ("pmap_pinit: pdpt misaligned"));
1763 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30),
1764 ("pmap_pinit: pdpt above 4g"));
1765 #endif
1766 pmap->pm_root = NULL;
1767 }
1768 KASSERT(pmap->pm_root == NULL,
1769 ("pmap_pinit: pmap has reserved page table page(s)"));
1770
1771 /*
1772 * allocate the page directory page(s)
1773 */
1774 for (i = 0; i < NPGPTD;) {
1775 m = vm_page_alloc(NULL, color++,
1776 VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
1777 VM_ALLOC_ZERO);
1778 if (m == NULL)
1779 VM_WAIT;
1780 else {
1781 ptdpg[i++] = m;
1782 }
1783 }
1784
1785 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD);
1786
1787 for (i = 0; i < NPGPTD; i++) {
1788 if ((ptdpg[i]->flags & PG_ZERO) == 0)
1789 bzero(pmap->pm_pdir + (i * NPDEPG), PAGE_SIZE);
1790 }
1791
1792 mtx_lock_spin(&allpmaps_lock);
1793 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list);
1794 /* Copy the kernel page table directory entries. */
1795 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t));
1796 mtx_unlock_spin(&allpmaps_lock);
1797
1798 /* install self-referential address mapping entry(s) */
1799 for (i = 0; i < NPGPTD; i++) {
1800 pa = VM_PAGE_TO_PHYS(ptdpg[i]);
1801 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M;
1802 #ifdef PAE
1803 pmap->pm_pdpt[i] = pa | PG_V;
1804 #endif
1805 }
1806
1807 pmap->pm_active = 0;
1808 TAILQ_INIT(&pmap->pm_pvchunk);
1809 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1810
1811 return (1);
1812 }
1813
1814 /*
1815 * this routine is called if the page table page is not
1816 * mapped correctly.
1817 */
1818 static vm_page_t
1819 _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags)
1820 {
1821 vm_paddr_t ptepa;
1822 vm_page_t m;
1823
1824 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1825 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1826 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1827
1828 /*
1829 * Allocate a page table page.
1830 */
1831 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ |
1832 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) {
1833 if (flags & M_WAITOK) {
1834 PMAP_UNLOCK(pmap);
1835 vm_page_unlock_queues();
1836 VM_WAIT;
1837 vm_page_lock_queues();
1838 PMAP_LOCK(pmap);
1839 }
1840
1841 /*
1842 * Indicate the need to retry. While waiting, the page table
1843 * page may have been allocated.
1844 */
1845 return (NULL);
1846 }
1847 if ((m->flags & PG_ZERO) == 0)
1848 pmap_zero_page(m);
1849
1850 /*
1851 * Map the pagetable page into the process address space, if
1852 * it isn't already there.
1853 */
1854
1855 pmap->pm_stats.resident_count++;
1856
1857 ptepa = VM_PAGE_TO_PHYS(m);
1858 pmap->pm_pdir[ptepindex] =
1859 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M);
1860
1861 return m;
1862 }
1863
1864 static vm_page_t
1865 pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags)
1866 {
1867 unsigned ptepindex;
1868 pd_entry_t ptepa;
1869 vm_page_t m;
1870
1871 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1872 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1873 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1874
1875 /*
1876 * Calculate pagetable page index
1877 */
1878 ptepindex = va >> PDRSHIFT;
1879 retry:
1880 /*
1881 * Get the page directory entry
1882 */
1883 ptepa = pmap->pm_pdir[ptepindex];
1884
1885 /*
1886 * This supports switching from a 4MB page to a
1887 * normal 4K page.
1888 */
1889 if (ptepa & PG_PS) {
1890 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va);
1891 ptepa = pmap->pm_pdir[ptepindex];
1892 }
1893
1894 /*
1895 * If the page table page is mapped, we just increment the
1896 * hold count, and activate it.
1897 */
1898 if (ptepa) {
1899 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
1900 m->wire_count++;
1901 } else {
1902 /*
1903 * Here if the pte page isn't mapped, or if it has
1904 * been deallocated.
1905 */
1906 m = _pmap_allocpte(pmap, ptepindex, flags);
1907 if (m == NULL && (flags & M_WAITOK))
1908 goto retry;
1909 }
1910 return (m);
1911 }
1912
1913
1914 /***************************************************
1915 * Pmap allocation/deallocation routines.
1916 ***************************************************/
1917
1918 #ifdef SMP
1919 /*
1920 * Deal with a SMP shootdown of other users of the pmap that we are
1921 * trying to dispose of. This can be a bit hairy.
1922 */
1923 static cpumask_t *lazymask;
1924 static u_int lazyptd;
1925 static volatile u_int lazywait;
1926
1927 void pmap_lazyfix_action(void);
1928
1929 void
1930 pmap_lazyfix_action(void)
1931 {
1932 cpumask_t mymask = PCPU_GET(cpumask);
1933
1934 #ifdef COUNT_IPIS
1935 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++;
1936 #endif
1937 if (rcr3() == lazyptd)
1938 load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1939 atomic_clear_int(lazymask, mymask);
1940 atomic_store_rel_int(&lazywait, 1);
1941 }
1942
1943 static void
1944 pmap_lazyfix_self(cpumask_t mymask)
1945 {
1946
1947 if (rcr3() == lazyptd)
1948 load_cr3(PCPU_GET(curpcb)->pcb_cr3);
1949 atomic_clear_int(lazymask, mymask);
1950 }
1951
1952
1953 static void
1954 pmap_lazyfix(pmap_t pmap)
1955 {
1956 cpumask_t mymask, mask;
1957 u_int spins;
1958
1959 while ((mask = pmap->pm_active) != 0) {
1960 spins = 50000000;
1961 mask = mask & -mask; /* Find least significant set bit */
1962 mtx_lock_spin(&smp_ipi_mtx);
1963 #ifdef PAE
1964 lazyptd = vtophys(pmap->pm_pdpt);
1965 #else
1966 lazyptd = vtophys(pmap->pm_pdir);
1967 #endif
1968 mymask = PCPU_GET(cpumask);
1969 if (mask == mymask) {
1970 lazymask = &pmap->pm_active;
1971 pmap_lazyfix_self(mymask);
1972 } else {
1973 atomic_store_rel_int((u_int *)&lazymask,
1974 (u_int)&pmap->pm_active);
1975 atomic_store_rel_int(&lazywait, 0);
1976 ipi_selected(mask, IPI_LAZYPMAP);
1977 while (lazywait == 0) {
1978 ia32_pause();
1979 if (--spins == 0)
1980 break;
1981 }
1982 }
1983 mtx_unlock_spin(&smp_ipi_mtx);
1984 if (spins == 0)
1985 printf("pmap_lazyfix: spun for 50000000\n");
1986 }
1987 }
1988
1989 #else /* SMP */
1990
1991 /*
1992 * Cleaning up on uniprocessor is easy. For various reasons, we're
1993 * unlikely to have to even execute this code, including the fact
1994 * that the cleanup is deferred until the parent does a wait(2), which
1995 * means that another userland process has run.
1996 */
1997 static void
1998 pmap_lazyfix(pmap_t pmap)
1999 {
2000 u_int cr3;
2001
2002 cr3 = vtophys(pmap->pm_pdir);
2003 if (cr3 == rcr3()) {
2004 load_cr3(PCPU_GET(curpcb)->pcb_cr3);
2005 pmap->pm_active &= ~(PCPU_GET(cpumask));
2006 }
2007 }
2008 #endif /* SMP */
2009
2010 /*
2011 * Release any resources held by the given physical map.
2012 * Called when a pmap initialized by pmap_pinit is being released.
2013 * Should only be called if the map contains no valid mappings.
2014 */
2015 void
2016 pmap_release(pmap_t pmap)
2017 {
2018 vm_page_t m, ptdpg[NPGPTD];
2019 int i;
2020
2021 KASSERT(pmap->pm_stats.resident_count == 0,
2022 ("pmap_release: pmap resident count %ld != 0",
2023 pmap->pm_stats.resident_count));
2024 KASSERT(pmap->pm_root == NULL,
2025 ("pmap_release: pmap has reserved page table page(s)"));
2026
2027 pmap_lazyfix(pmap);
2028 mtx_lock_spin(&allpmaps_lock);
2029 LIST_REMOVE(pmap, pm_list);
2030 mtx_unlock_spin(&allpmaps_lock);
2031
2032 for (i = 0; i < NPGPTD; i++)
2033 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] &
2034 PG_FRAME);
2035
2036 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) *
2037 sizeof(*pmap->pm_pdir));
2038
2039 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD);
2040
2041 for (i = 0; i < NPGPTD; i++) {
2042 m = ptdpg[i];
2043 #ifdef PAE
2044 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME),
2045 ("pmap_release: got wrong ptd page"));
2046 #endif
2047 m->wire_count--;
2048 atomic_subtract_int(&cnt.v_wire_count, 1);
2049 vm_page_free_zero(m);
2050 }
2051 PMAP_LOCK_DESTROY(pmap);
2052 }
2053
2054 static int
2055 kvm_size(SYSCTL_HANDLER_ARGS)
2056 {
2057 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE;
2058
2059 return sysctl_handle_long(oidp, &ksize, 0, req);
2060 }
2061 SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD,
2062 0, 0, kvm_size, "IU", "Size of KVM");
2063
2064 static int
2065 kvm_free(SYSCTL_HANDLER_ARGS)
2066 {
2067 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end;
2068
2069 return sysctl_handle_long(oidp, &kfree, 0, req);
2070 }
2071 SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD,
2072 0, 0, kvm_free, "IU", "Amount of KVM free");
2073
2074 /*
2075 * grow the number of kernel page table entries, if needed
2076 */
2077 void
2078 pmap_growkernel(vm_offset_t addr)
2079 {
2080 vm_paddr_t ptppaddr;
2081 vm_page_t nkpg;
2082 pd_entry_t newpdir;
2083
2084 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
2085 if (kernel_vm_end == 0) {
2086 kernel_vm_end = KERNBASE;
2087 nkpt = 0;
2088 while (pdir_pde(PTD, kernel_vm_end)) {
2089 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1);
2090 nkpt++;
2091 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2092 kernel_vm_end = kernel_map->max_offset;
2093 break;
2094 }
2095 }
2096 }
2097 addr = roundup2(addr, PAGE_SIZE * NPTEPG);
2098 if (addr - 1 >= kernel_map->max_offset)
2099 addr = kernel_map->max_offset;
2100 while (kernel_vm_end < addr) {
2101 if (pdir_pde(PTD, kernel_vm_end)) {
2102 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1);
2103 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2104 kernel_vm_end = kernel_map->max_offset;
2105 break;
2106 }
2107 continue;
2108 }
2109
2110 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT,
2111 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED |
2112 VM_ALLOC_ZERO);
2113 if (nkpg == NULL)
2114 panic("pmap_growkernel: no memory to grow kernel");
2115
2116 nkpt++;
2117
2118 if ((nkpg->flags & PG_ZERO) == 0)
2119 pmap_zero_page(nkpg);
2120 ptppaddr = VM_PAGE_TO_PHYS(nkpg);
2121 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M);
2122 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir;
2123
2124 pmap_kenter_pde(kernel_vm_end, newpdir);
2125 kernel_vm_end = (kernel_vm_end + PAGE_SIZE * NPTEPG) & ~(PAGE_SIZE * NPTEPG - 1);
2126 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
2127 kernel_vm_end = kernel_map->max_offset;
2128 break;
2129 }
2130 }
2131 }
2132
2133
2134 /***************************************************
2135 * page management routines.
2136 ***************************************************/
2137
2138 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
2139 CTASSERT(_NPCM == 11);
2140
2141 static __inline struct pv_chunk *
2142 pv_to_chunk(pv_entry_t pv)
2143 {
2144
2145 return (struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK);
2146 }
2147
2148 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
2149
2150 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
2151 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
2152
2153 static uint32_t pc_freemask[11] = {
2154 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2155 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2156 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
2157 PC_FREE0_9, PC_FREE10
2158 };
2159
2160 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
2161 "Current number of pv entries");
2162
2163 #ifdef PV_STATS
2164 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
2165
2166 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
2167 "Current number of pv entry chunks");
2168 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
2169 "Current number of pv entry chunks allocated");
2170 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
2171 "Current number of pv entry chunks frees");
2172 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
2173 "Number of times tried to get a chunk page but failed.");
2174
2175 static long pv_entry_frees, pv_entry_allocs;
2176 static int pv_entry_spare;
2177
2178 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
2179 "Current number of pv entry frees");
2180 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
2181 "Current number of pv entry allocs");
2182 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
2183 "Current number of spare pv entries");
2184
2185 static int pmap_collect_inactive, pmap_collect_active;
2186
2187 SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_inactive, CTLFLAG_RD, &pmap_collect_inactive, 0,
2188 "Current number times pmap_collect called on inactive queue");
2189 SYSCTL_INT(_vm_pmap, OID_AUTO, pmap_collect_active, CTLFLAG_RD, &pmap_collect_active, 0,
2190 "Current number times pmap_collect called on active queue");
2191 #endif
2192
2193 /*
2194 * We are in a serious low memory condition. Resort to
2195 * drastic measures to free some pages so we can allocate
2196 * another pv entry chunk. This is normally called to
2197 * unmap inactive pages, and if necessary, active pages.
2198 */
2199 static void
2200 pmap_collect(pmap_t locked_pmap, struct vpgqueues *vpq)
2201 {
2202 struct md_page *pvh;
2203 pd_entry_t *pde;
2204 pmap_t pmap;
2205 pt_entry_t *pte, tpte;
2206 pv_entry_t next_pv, pv;
2207 vm_offset_t va;
2208 vm_page_t m, free;
2209
2210 sched_pin();
2211 TAILQ_FOREACH(m, &vpq->pl, pageq) {
2212 if ((m->flags & PG_MARKER) != 0 || m->hold_count || m->busy)
2213 continue;
2214 TAILQ_FOREACH_SAFE(pv, &m->md.pv_list, pv_list, next_pv) {
2215 va = pv->pv_va;
2216 pmap = PV_PMAP(pv);
2217 /* Avoid deadlock and lock recursion. */
2218 if (pmap > locked_pmap)
2219 PMAP_LOCK(pmap);
2220 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap))
2221 continue;
2222 pmap->pm_stats.resident_count--;
2223 pde = pmap_pde(pmap, va);
2224 KASSERT((*pde & PG_PS) == 0, ("pmap_collect: found"
2225 " a 4mpage in page %p's pv list", m));
2226 pte = pmap_pte_quick(pmap, va);
2227 tpte = pte_load_clear(pte);
2228 KASSERT((tpte & PG_W) == 0,
2229 ("pmap_collect: wired pte %#jx", (uintmax_t)tpte));
2230 if (tpte & PG_A)
2231 vm_page_flag_set(m, PG_REFERENCED);
2232 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2233 vm_page_dirty(m);
2234 free = NULL;
2235 pmap_unuse_pt(pmap, va, &free);
2236 pmap_invalidate_page(pmap, va);
2237 pmap_free_zero_pages(free);
2238 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2239 if (TAILQ_EMPTY(&m->md.pv_list)) {
2240 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2241 if (TAILQ_EMPTY(&pvh->pv_list))
2242 vm_page_flag_clear(m, PG_WRITEABLE);
2243 }
2244 free_pv_entry(pmap, pv);
2245 if (pmap != locked_pmap)
2246 PMAP_UNLOCK(pmap);
2247 }
2248 }
2249 sched_unpin();
2250 }
2251
2252
2253 /*
2254 * free the pv_entry back to the free list
2255 */
2256 static void
2257 free_pv_entry(pmap_t pmap, pv_entry_t pv)
2258 {
2259 vm_page_t m;
2260 struct pv_chunk *pc;
2261 int idx, field, bit;
2262
2263 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2264 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2265 PV_STAT(pv_entry_frees++);
2266 PV_STAT(pv_entry_spare++);
2267 pv_entry_count--;
2268 pc = pv_to_chunk(pv);
2269 idx = pv - &pc->pc_pventry[0];
2270 field = idx / 32;
2271 bit = idx % 32;
2272 pc->pc_map[field] |= 1ul << bit;
2273 /* move to head of list */
2274 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2275 for (idx = 0; idx < _NPCM; idx++)
2276 if (pc->pc_map[idx] != pc_freemask[idx]) {
2277 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2278 return;
2279 }
2280 PV_STAT(pv_entry_spare -= _NPCPV);
2281 PV_STAT(pc_chunk_count--);
2282 PV_STAT(pc_chunk_frees++);
2283 /* entire chunk is free, return it */
2284 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
2285 pmap_qremove((vm_offset_t)pc, 1);
2286 vm_page_unwire(m, 0);
2287 vm_page_free(m);
2288 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
2289 }
2290
2291 /*
2292 * get a new pv_entry, allocating a block from the system
2293 * when needed.
2294 */
2295 static pv_entry_t
2296 get_pv_entry(pmap_t pmap, int try)
2297 {
2298 static const struct timeval printinterval = { 60, 0 };
2299 static struct timeval lastprint;
2300 static vm_pindex_t colour;
2301 struct vpgqueues *pq;
2302 int bit, field;
2303 pv_entry_t pv;
2304 struct pv_chunk *pc;
2305 vm_page_t m;
2306
2307 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2308 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2309 PV_STAT(pv_entry_allocs++);
2310 pv_entry_count++;
2311 if (pv_entry_count > pv_entry_high_water)
2312 if (ratecheck(&lastprint, &printinterval))
2313 printf("Approaching the limit on PV entries, consider "
2314 "increasing either the vm.pmap.shpgperproc or the "
2315 "vm.pmap.pv_entry_max tunable.\n");
2316 pq = NULL;
2317 retry:
2318 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
2319 if (pc != NULL) {
2320 for (field = 0; field < _NPCM; field++) {
2321 if (pc->pc_map[field]) {
2322 bit = bsfl(pc->pc_map[field]);
2323 break;
2324 }
2325 }
2326 if (field < _NPCM) {
2327 pv = &pc->pc_pventry[field * 32 + bit];
2328 pc->pc_map[field] &= ~(1ul << bit);
2329 /* If this was the last item, move it to tail */
2330 for (field = 0; field < _NPCM; field++)
2331 if (pc->pc_map[field] != 0) {
2332 PV_STAT(pv_entry_spare--);
2333 return (pv); /* not full, return */
2334 }
2335 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2336 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
2337 PV_STAT(pv_entry_spare--);
2338 return (pv);
2339 }
2340 }
2341 /*
2342 * Access to the ptelist "pv_vafree" is synchronized by the page
2343 * queues lock. If "pv_vafree" is currently non-empty, it will
2344 * remain non-empty until pmap_ptelist_alloc() completes.
2345 */
2346 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, colour, (pq ==
2347 &vm_page_queues[PQ_ACTIVE] ? VM_ALLOC_SYSTEM : VM_ALLOC_NORMAL) |
2348 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) {
2349 if (try) {
2350 pv_entry_count--;
2351 PV_STAT(pc_chunk_tryfail++);
2352 return (NULL);
2353 }
2354 /*
2355 * Reclaim pv entries: At first, destroy mappings to
2356 * inactive pages. After that, if a pv chunk entry
2357 * is still needed, destroy mappings to active pages.
2358 */
2359 if (pq == NULL) {
2360 PV_STAT(pmap_collect_inactive++);
2361 pq = &vm_page_queues[PQ_INACTIVE];
2362 } else if (pq == &vm_page_queues[PQ_INACTIVE]) {
2363 PV_STAT(pmap_collect_active++);
2364 pq = &vm_page_queues[PQ_ACTIVE];
2365 } else
2366 panic("get_pv_entry: increase vm.pmap.shpgperproc");
2367 pmap_collect(pmap, pq);
2368 goto retry;
2369 }
2370 PV_STAT(pc_chunk_count++);
2371 PV_STAT(pc_chunk_allocs++);
2372 colour++;
2373 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree);
2374 pmap_qenter((vm_offset_t)pc, &m, 1);
2375 pc->pc_pmap = pmap;
2376 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
2377 for (field = 1; field < _NPCM; field++)
2378 pc->pc_map[field] = pc_freemask[field];
2379 pv = &pc->pc_pventry[0];
2380 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
2381 PV_STAT(pv_entry_spare += _NPCPV - 1);
2382 return (pv);
2383 }
2384
2385 static __inline pv_entry_t
2386 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2387 {
2388 pv_entry_t pv;
2389
2390 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2391 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
2392 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
2393 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
2394 break;
2395 }
2396 }
2397 return (pv);
2398 }
2399
2400 static void
2401 pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2402 {
2403 struct md_page *pvh;
2404 pv_entry_t pv;
2405 vm_offset_t va_last;
2406 vm_page_t m;
2407
2408 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2409 KASSERT((pa & PDRMASK) == 0,
2410 ("pmap_pv_demote_pde: pa is not 4mpage aligned"));
2411
2412 /*
2413 * Transfer the 4mpage's pv entry for this mapping to the first
2414 * page's pv list.
2415 */
2416 pvh = pa_to_pvh(pa);
2417 va = trunc_4mpage(va);
2418 pv = pmap_pvh_remove(pvh, pmap, va);
2419 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found"));
2420 m = PHYS_TO_VM_PAGE(pa);
2421 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2422 /* Instantiate the remaining NPTEPG - 1 pv entries. */
2423 va_last = va + NBPDR - PAGE_SIZE;
2424 do {
2425 m++;
2426 KASSERT((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0,
2427 ("pmap_pv_demote_pde: page %p is not managed", m));
2428 va += PAGE_SIZE;
2429 pmap_insert_entry(pmap, va, m);
2430 } while (va < va_last);
2431 }
2432
2433 static void
2434 pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2435 {
2436 struct md_page *pvh;
2437 pv_entry_t pv;
2438 vm_offset_t va_last;
2439 vm_page_t m;
2440
2441 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2442 KASSERT((pa & PDRMASK) == 0,
2443 ("pmap_pv_promote_pde: pa is not 4mpage aligned"));
2444
2445 /*
2446 * Transfer the first page's pv entry for this mapping to the
2447 * 4mpage's pv list. Aside from avoiding the cost of a call
2448 * to get_pv_entry(), a transfer avoids the possibility that
2449 * get_pv_entry() calls pmap_collect() and that pmap_collect()
2450 * removes one of the mappings that is being promoted.
2451 */
2452 m = PHYS_TO_VM_PAGE(pa);
2453 va = trunc_4mpage(va);
2454 pv = pmap_pvh_remove(&m->md, pmap, va);
2455 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found"));
2456 pvh = pa_to_pvh(pa);
2457 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2458 /* Free the remaining NPTEPG - 1 pv entries. */
2459 va_last = va + NBPDR - PAGE_SIZE;
2460 do {
2461 m++;
2462 va += PAGE_SIZE;
2463 pmap_pvh_free(&m->md, pmap, va);
2464 } while (va < va_last);
2465 }
2466
2467 static void
2468 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
2469 {
2470 pv_entry_t pv;
2471
2472 pv = pmap_pvh_remove(pvh, pmap, va);
2473 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found"));
2474 free_pv_entry(pmap, pv);
2475 }
2476
2477 static void
2478 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
2479 {
2480 struct md_page *pvh;
2481
2482 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2483 pmap_pvh_free(&m->md, pmap, va);
2484 if (TAILQ_EMPTY(&m->md.pv_list)) {
2485 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2486 if (TAILQ_EMPTY(&pvh->pv_list))
2487 vm_page_flag_clear(m, PG_WRITEABLE);
2488 }
2489 }
2490
2491 /*
2492 * Create a pv entry for page at pa for
2493 * (pmap, va).
2494 */
2495 static void
2496 pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2497 {
2498 pv_entry_t pv;
2499
2500 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2501 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2502 pv = get_pv_entry(pmap, FALSE);
2503 pv->pv_va = va;
2504 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2505 }
2506
2507 /*
2508 * Conditionally create a pv entry.
2509 */
2510 static boolean_t
2511 pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m)
2512 {
2513 pv_entry_t pv;
2514
2515 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2516 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2517 if (pv_entry_count < pv_entry_high_water &&
2518 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2519 pv->pv_va = va;
2520 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2521 return (TRUE);
2522 } else
2523 return (FALSE);
2524 }
2525
2526 /*
2527 * Create the pv entries for each of the pages within a superpage.
2528 */
2529 static boolean_t
2530 pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa)
2531 {
2532 struct md_page *pvh;
2533 pv_entry_t pv;
2534
2535 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2536 if (pv_entry_count < pv_entry_high_water &&
2537 (pv = get_pv_entry(pmap, TRUE)) != NULL) {
2538 pv->pv_va = va;
2539 pvh = pa_to_pvh(pa);
2540 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_list);
2541 return (TRUE);
2542 } else
2543 return (FALSE);
2544 }
2545
2546 /*
2547 * Fills a page table page with mappings to consecutive physical pages.
2548 */
2549 static void
2550 pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte)
2551 {
2552 pt_entry_t *pte;
2553
2554 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) {
2555 *pte = newpte;
2556 newpte += PAGE_SIZE;
2557 }
2558 }
2559
2560 /*
2561 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the
2562 * 2- or 4MB page mapping is invalidated.
2563 */
2564 static boolean_t
2565 pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
2566 {
2567 pd_entry_t newpde, oldpde;
2568 pt_entry_t *firstpte, newpte;
2569 vm_paddr_t mptepa;
2570 vm_page_t free, mpte;
2571
2572 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2573 oldpde = *pde;
2574 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V),
2575 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V"));
2576 mpte = pmap_lookup_pt_page(pmap, va);
2577 if (mpte != NULL)
2578 pmap_remove_pt_page(pmap, mpte);
2579 else {
2580 KASSERT((oldpde & PG_W) == 0,
2581 ("pmap_demote_pde: page table page for a wired mapping"
2582 " is missing"));
2583
2584 /*
2585 * Invalidate the 2- or 4MB page mapping and return
2586 * "failure" if the mapping was never accessed or the
2587 * allocation of the new page table page fails.
2588 */
2589 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL,
2590 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL |
2591 VM_ALLOC_WIRED)) == NULL) {
2592 free = NULL;
2593 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free);
2594 pmap_invalidate_page(pmap, trunc_4mpage(va));
2595 pmap_free_zero_pages(free);
2596 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x"
2597 " in pmap %p", va, pmap);
2598 return (FALSE);
2599 }
2600 if (va < VM_MAXUSER_ADDRESS)
2601 pmap->pm_stats.resident_count++;
2602 }
2603 mptepa = VM_PAGE_TO_PHYS(mpte);
2604
2605 /*
2606 * If the page mapping is in the kernel's address space, then the
2607 * KPTmap can provide access to the page table page. Otherwise,
2608 * temporarily map the page table page (mpte) into the kernel's
2609 * address space at either PADDR1 or PADDR2.
2610 */
2611 if (va >= KERNBASE)
2612 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))];
2613 else if (curthread->td_pinned > 0 && mtx_owned(&vm_page_queue_mtx)) {
2614 if ((*PMAP1 & PG_FRAME) != mptepa) {
2615 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2616 #ifdef SMP
2617 PMAP1cpu = PCPU_GET(cpuid);
2618 #endif
2619 invlcaddr(PADDR1);
2620 PMAP1changed++;
2621 } else
2622 #ifdef SMP
2623 if (PMAP1cpu != PCPU_GET(cpuid)) {
2624 PMAP1cpu = PCPU_GET(cpuid);
2625 invlcaddr(PADDR1);
2626 PMAP1changedcpu++;
2627 } else
2628 #endif
2629 PMAP1unchanged++;
2630 firstpte = PADDR1;
2631 } else {
2632 mtx_lock(&PMAP2mutex);
2633 if ((*PMAP2 & PG_FRAME) != mptepa) {
2634 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M;
2635 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2);
2636 }
2637 firstpte = PADDR2;
2638 }
2639 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V;
2640 KASSERT((oldpde & PG_A) != 0,
2641 ("pmap_demote_pde: oldpde is missing PG_A"));
2642 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW,
2643 ("pmap_demote_pde: oldpde is missing PG_M"));
2644 newpte = oldpde & ~PG_PS;
2645 if ((newpte & PG_PDE_PAT) != 0)
2646 newpte ^= PG_PDE_PAT | PG_PTE_PAT;
2647
2648 /*
2649 * If the page table page is new, initialize it.
2650 */
2651 if (mpte->wire_count == 1) {
2652 mpte->wire_count = NPTEPG;
2653 pmap_fill_ptp(firstpte, newpte);
2654 }
2655 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME),
2656 ("pmap_demote_pde: firstpte and newpte map different physical"
2657 " addresses"));
2658
2659 /*
2660 * If the mapping has changed attributes, update the page table
2661 * entries.
2662 */
2663 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE))
2664 pmap_fill_ptp(firstpte, newpte);
2665
2666 /*
2667 * Demote the mapping. This pmap is locked. The old PDE has
2668 * PG_A set. If the old PDE has PG_RW set, it also has PG_M
2669 * set. Thus, there is no danger of a race with another
2670 * processor changing the setting of PG_A and/or PG_M between
2671 * the read above and the store below.
2672 */
2673 if (workaround_erratum383)
2674 pmap_update_pde(pmap, va, pde, newpde);
2675 else if (pmap == kernel_pmap)
2676 pmap_kenter_pde(va, newpde);
2677 else
2678 pde_store(pde, newpde);
2679 if (firstpte == PADDR2)
2680 mtx_unlock(&PMAP2mutex);
2681
2682 /*
2683 * Invalidate the recursive mapping of the page table page.
2684 */
2685 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va));
2686
2687 /*
2688 * Demote the pv entry. This depends on the earlier demotion
2689 * of the mapping. Specifically, the (re)creation of a per-
2690 * page pv entry might trigger the execution of pmap_collect(),
2691 * which might reclaim a newly (re)created per-page pv entry
2692 * and destroy the associated mapping. In order to destroy
2693 * the mapping, the PDE must have already changed from mapping
2694 * the 2mpage to referencing the page table page.
2695 */
2696 if ((oldpde & PG_MANAGED) != 0)
2697 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME);
2698
2699 pmap_pde_demotions++;
2700 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x"
2701 " in pmap %p", va, pmap);
2702 return (TRUE);
2703 }
2704
2705 /*
2706 * pmap_remove_pde: do the things to unmap a superpage in a process
2707 */
2708 static void
2709 pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva,
2710 vm_page_t *free)
2711 {
2712 struct md_page *pvh;
2713 pd_entry_t oldpde;
2714 vm_offset_t eva, va;
2715 vm_page_t m, mpte;
2716
2717 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2718 KASSERT((sva & PDRMASK) == 0,
2719 ("pmap_remove_pde: sva is not 4mpage aligned"));
2720 oldpde = pte_load_clear(pdq);
2721 if (oldpde & PG_W)
2722 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE;
2723
2724 /*
2725 * Machines that don't support invlpg, also don't support
2726 * PG_G.
2727 */
2728 if (oldpde & PG_G)
2729 pmap_invalidate_page(kernel_pmap, sva);
2730 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
2731 if (oldpde & PG_MANAGED) {
2732 pvh = pa_to_pvh(oldpde & PG_PS_FRAME);
2733 pmap_pvh_free(pvh, pmap, sva);
2734 eva = sva + NBPDR;
2735 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
2736 va < eva; va += PAGE_SIZE, m++) {
2737 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
2738 vm_page_dirty(m);
2739 if (oldpde & PG_A)
2740 vm_page_flag_set(m, PG_REFERENCED);
2741 if (TAILQ_EMPTY(&m->md.pv_list) &&
2742 TAILQ_EMPTY(&pvh->pv_list))
2743 vm_page_flag_clear(m, PG_WRITEABLE);
2744 }
2745 }
2746 if (pmap == kernel_pmap) {
2747 if (!pmap_demote_pde(pmap, pdq, sva))
2748 panic("pmap_remove_pde: failed demotion");
2749 } else {
2750 mpte = pmap_lookup_pt_page(pmap, sva);
2751 if (mpte != NULL) {
2752 pmap_remove_pt_page(pmap, mpte);
2753 pmap->pm_stats.resident_count--;
2754 KASSERT(mpte->wire_count == NPTEPG,
2755 ("pmap_remove_pde: pte page wire count error"));
2756 mpte->wire_count = 0;
2757 pmap_add_delayed_free_list(mpte, free, FALSE);
2758 atomic_subtract_int(&cnt.v_wire_count, 1);
2759 }
2760 }
2761 }
2762
2763 /*
2764 * pmap_remove_pte: do the things to unmap a page in a process
2765 */
2766 static int
2767 pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, vm_page_t *free)
2768 {
2769 pt_entry_t oldpte;
2770 vm_page_t m;
2771
2772 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2773 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2774 oldpte = pte_load_clear(ptq);
2775 if (oldpte & PG_W)
2776 pmap->pm_stats.wired_count -= 1;
2777 /*
2778 * Machines that don't support invlpg, also don't support
2779 * PG_G.
2780 */
2781 if (oldpte & PG_G)
2782 pmap_invalidate_page(kernel_pmap, va);
2783 pmap->pm_stats.resident_count -= 1;
2784 if (oldpte & PG_MANAGED) {
2785 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME);
2786 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2787 vm_page_dirty(m);
2788 if (oldpte & PG_A)
2789 vm_page_flag_set(m, PG_REFERENCED);
2790 pmap_remove_entry(pmap, m, va);
2791 }
2792 return (pmap_unuse_pt(pmap, va, free));
2793 }
2794
2795 /*
2796 * Remove a single page from a process address space
2797 */
2798 static void
2799 pmap_remove_page(pmap_t pmap, vm_offset_t va, vm_page_t *free)
2800 {
2801 pt_entry_t *pte;
2802
2803 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2804 KASSERT(curthread->td_pinned > 0, ("curthread not pinned"));
2805 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2806 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0)
2807 return;
2808 pmap_remove_pte(pmap, pte, va, free);
2809 pmap_invalidate_page(pmap, va);
2810 }
2811
2812 /*
2813 * Remove the given range of addresses from the specified map.
2814 *
2815 * It is assumed that the start and end are properly
2816 * rounded to the page size.
2817 */
2818 void
2819 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2820 {
2821 vm_offset_t pdnxt;
2822 pd_entry_t ptpaddr;
2823 pt_entry_t *pte;
2824 vm_page_t free = NULL;
2825 int anyvalid;
2826
2827 /*
2828 * Perform an unsynchronized read. This is, however, safe.
2829 */
2830 if (pmap->pm_stats.resident_count == 0)
2831 return;
2832
2833 anyvalid = 0;
2834
2835 vm_page_lock_queues();
2836 sched_pin();
2837 PMAP_LOCK(pmap);
2838
2839 /*
2840 * special handling of removing one page. a very
2841 * common operation and easy to short circuit some
2842 * code.
2843 */
2844 if ((sva + PAGE_SIZE == eva) &&
2845 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) {
2846 pmap_remove_page(pmap, sva, &free);
2847 goto out;
2848 }
2849
2850 for (; sva < eva; sva = pdnxt) {
2851 unsigned pdirindex;
2852
2853 /*
2854 * Calculate index for next page table.
2855 */
2856 pdnxt = (sva + NBPDR) & ~PDRMASK;
2857 if (pdnxt < sva)
2858 pdnxt = eva;
2859 if (pmap->pm_stats.resident_count == 0)
2860 break;
2861
2862 pdirindex = sva >> PDRSHIFT;
2863 ptpaddr = pmap->pm_pdir[pdirindex];
2864
2865 /*
2866 * Weed out invalid mappings. Note: we assume that the page
2867 * directory table is always allocated, and in kernel virtual.
2868 */
2869 if (ptpaddr == 0)
2870 continue;
2871
2872 /*
2873 * Check for large page.
2874 */
2875 if ((ptpaddr & PG_PS) != 0) {
2876 /*
2877 * Are we removing the entire large page? If not,
2878 * demote the mapping and fall through.
2879 */
2880 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
2881 /*
2882 * The TLB entry for a PG_G mapping is
2883 * invalidated by pmap_remove_pde().
2884 */
2885 if ((ptpaddr & PG_G) == 0)
2886 anyvalid = 1;
2887 pmap_remove_pde(pmap,
2888 &pmap->pm_pdir[pdirindex], sva, &free);
2889 continue;
2890 } else if (!pmap_demote_pde(pmap,
2891 &pmap->pm_pdir[pdirindex], sva)) {
2892 /* The large page mapping was destroyed. */
2893 continue;
2894 }
2895 }
2896
2897 /*
2898 * Limit our scan to either the end of the va represented
2899 * by the current page table page, or to the end of the
2900 * range being removed.
2901 */
2902 if (pdnxt > eva)
2903 pdnxt = eva;
2904
2905 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
2906 sva += PAGE_SIZE) {
2907 if (*pte == 0)
2908 continue;
2909
2910 /*
2911 * The TLB entry for a PG_G mapping is invalidated
2912 * by pmap_remove_pte().
2913 */
2914 if ((*pte & PG_G) == 0)
2915 anyvalid = 1;
2916 if (pmap_remove_pte(pmap, pte, sva, &free))
2917 break;
2918 }
2919 }
2920 out:
2921 sched_unpin();
2922 if (anyvalid)
2923 pmap_invalidate_all(pmap);
2924 vm_page_unlock_queues();
2925 PMAP_UNLOCK(pmap);
2926 pmap_free_zero_pages(free);
2927 }
2928
2929 /*
2930 * Routine: pmap_remove_all
2931 * Function:
2932 * Removes this physical page from
2933 * all physical maps in which it resides.
2934 * Reflects back modify bits to the pager.
2935 *
2936 * Notes:
2937 * Original versions of this routine were very
2938 * inefficient because they iteratively called
2939 * pmap_remove (slow...)
2940 */
2941
2942 void
2943 pmap_remove_all(vm_page_t m)
2944 {
2945 struct md_page *pvh;
2946 pv_entry_t pv;
2947 pmap_t pmap;
2948 pt_entry_t *pte, tpte;
2949 pd_entry_t *pde;
2950 vm_offset_t va;
2951 vm_page_t free;
2952
2953 KASSERT((m->flags & PG_FICTITIOUS) == 0,
2954 ("pmap_remove_all: page %p is fictitious", m));
2955 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
2956 sched_pin();
2957 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
2958 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) {
2959 va = pv->pv_va;
2960 pmap = PV_PMAP(pv);
2961 PMAP_LOCK(pmap);
2962 pde = pmap_pde(pmap, va);
2963 (void)pmap_demote_pde(pmap, pde, va);
2964 PMAP_UNLOCK(pmap);
2965 }
2966 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
2967 pmap = PV_PMAP(pv);
2968 PMAP_LOCK(pmap);
2969 pmap->pm_stats.resident_count--;
2970 pde = pmap_pde(pmap, pv->pv_va);
2971 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found"
2972 " a 4mpage in page %p's pv list", m));
2973 pte = pmap_pte_quick(pmap, pv->pv_va);
2974 tpte = pte_load_clear(pte);
2975 if (tpte & PG_W)
2976 pmap->pm_stats.wired_count--;
2977 if (tpte & PG_A)
2978 vm_page_flag_set(m, PG_REFERENCED);
2979
2980 /*
2981 * Update the vm_page_t clean and reference bits.
2982 */
2983 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW))
2984 vm_page_dirty(m);
2985 free = NULL;
2986 pmap_unuse_pt(pmap, pv->pv_va, &free);
2987 pmap_invalidate_page(pmap, pv->pv_va);
2988 pmap_free_zero_pages(free);
2989 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2990 free_pv_entry(pmap, pv);
2991 PMAP_UNLOCK(pmap);
2992 }
2993 vm_page_flag_clear(m, PG_WRITEABLE);
2994 sched_unpin();
2995 }
2996
2997 /*
2998 * pmap_protect_pde: do the things to protect a 4mpage in a process
2999 */
3000 static boolean_t
3001 pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot)
3002 {
3003 pd_entry_t newpde, oldpde;
3004 vm_offset_t eva, va;
3005 vm_page_t m;
3006 boolean_t anychanged;
3007
3008 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3009 KASSERT((sva & PDRMASK) == 0,
3010 ("pmap_protect_pde: sva is not 4mpage aligned"));
3011 anychanged = FALSE;
3012 retry:
3013 oldpde = newpde = *pde;
3014 if (oldpde & PG_MANAGED) {
3015 eva = sva + NBPDR;
3016 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME);
3017 va < eva; va += PAGE_SIZE, m++) {
3018 /*
3019 * In contrast to the analogous operation on a 4KB page
3020 * mapping, the mapping's PG_A flag is not cleared and
3021 * the page's PG_REFERENCED flag is not set. The
3022 * reason is that pmap_demote_pde() expects that a 2/4MB
3023 * page mapping with a stored page table page has PG_A
3024 * set.
3025 */
3026 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW))
3027 vm_page_dirty(m);
3028 }
3029 }
3030 if ((prot & VM_PROT_WRITE) == 0)
3031 newpde &= ~(PG_RW | PG_M);
3032 #ifdef PAE
3033 if ((prot & VM_PROT_EXECUTE) == 0)
3034 newpde |= pg_nx;
3035 #endif
3036 if (newpde != oldpde) {
3037 if (!pde_cmpset(pde, oldpde, newpde))
3038 goto retry;
3039 if (oldpde & PG_G)
3040 pmap_invalidate_page(pmap, sva);
3041 else
3042 anychanged = TRUE;
3043 }
3044 return (anychanged);
3045 }
3046
3047 /*
3048 * Set the physical protection on the
3049 * specified range of this map as requested.
3050 */
3051 void
3052 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
3053 {
3054 vm_offset_t pdnxt;
3055 pd_entry_t ptpaddr;
3056 pt_entry_t *pte;
3057 int anychanged;
3058
3059 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
3060 pmap_remove(pmap, sva, eva);
3061 return;
3062 }
3063
3064 #ifdef PAE
3065 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) ==
3066 (VM_PROT_WRITE|VM_PROT_EXECUTE))
3067 return;
3068 #else
3069 if (prot & VM_PROT_WRITE)
3070 return;
3071 #endif
3072
3073 anychanged = 0;
3074
3075 vm_page_lock_queues();
3076 sched_pin();
3077 PMAP_LOCK(pmap);
3078 for (; sva < eva; sva = pdnxt) {
3079 pt_entry_t obits, pbits;
3080 unsigned pdirindex;
3081
3082 pdnxt = (sva + NBPDR) & ~PDRMASK;
3083 if (pdnxt < sva)
3084 pdnxt = eva;
3085
3086 pdirindex = sva >> PDRSHIFT;
3087 ptpaddr = pmap->pm_pdir[pdirindex];
3088
3089 /*
3090 * Weed out invalid mappings. Note: we assume that the page
3091 * directory table is always allocated, and in kernel virtual.
3092 */
3093 if (ptpaddr == 0)
3094 continue;
3095
3096 /*
3097 * Check for large page.
3098 */
3099 if ((ptpaddr & PG_PS) != 0) {
3100 /*
3101 * Are we protecting the entire large page? If not,
3102 * demote the mapping and fall through.
3103 */
3104 if (sva + NBPDR == pdnxt && eva >= pdnxt) {
3105 /*
3106 * The TLB entry for a PG_G mapping is
3107 * invalidated by pmap_protect_pde().
3108 */
3109 if (pmap_protect_pde(pmap,
3110 &pmap->pm_pdir[pdirindex], sva, prot))
3111 anychanged = 1;
3112 continue;
3113 } else if (!pmap_demote_pde(pmap,
3114 &pmap->pm_pdir[pdirindex], sva)) {
3115 /* The large page mapping was destroyed. */
3116 continue;
3117 }
3118 }
3119
3120 if (pdnxt > eva)
3121 pdnxt = eva;
3122
3123 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++,
3124 sva += PAGE_SIZE) {
3125 vm_page_t m;
3126
3127 retry:
3128 /*
3129 * Regardless of whether a pte is 32 or 64 bits in
3130 * size, PG_RW, PG_A, and PG_M are among the least
3131 * significant 32 bits.
3132 */
3133 obits = pbits = *pte;
3134 if ((pbits & PG_V) == 0)
3135 continue;
3136 if (pbits & PG_MANAGED) {
3137 m = NULL;
3138 if (pbits & PG_A) {
3139 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3140 vm_page_flag_set(m, PG_REFERENCED);
3141 pbits &= ~PG_A;
3142 }
3143 if ((pbits & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3144 if (m == NULL)
3145 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME);
3146 vm_page_dirty(m);
3147 }
3148 }
3149
3150 if ((prot & VM_PROT_WRITE) == 0)
3151 pbits &= ~(PG_RW | PG_M);
3152 #ifdef PAE
3153 if ((prot & VM_PROT_EXECUTE) == 0)
3154 pbits |= pg_nx;
3155 #endif
3156
3157 if (pbits != obits) {
3158 #ifdef PAE
3159 if (!atomic_cmpset_64(pte, obits, pbits))
3160 goto retry;
3161 #else
3162 if (!atomic_cmpset_int((u_int *)pte, obits,
3163 pbits))
3164 goto retry;
3165 #endif
3166 if (obits & PG_G)
3167 pmap_invalidate_page(pmap, sva);
3168 else
3169 anychanged = 1;
3170 }
3171 }
3172 }
3173 sched_unpin();
3174 if (anychanged)
3175 pmap_invalidate_all(pmap);
3176 vm_page_unlock_queues();
3177 PMAP_UNLOCK(pmap);
3178 }
3179
3180 /*
3181 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are
3182 * within a single page table page (PTP) to a single 2- or 4MB page mapping.
3183 * For promotion to occur, two conditions must be met: (1) the 4KB page
3184 * mappings must map aligned, contiguous physical memory and (2) the 4KB page
3185 * mappings must have identical characteristics.
3186 *
3187 * Managed (PG_MANAGED) mappings within the kernel address space are not
3188 * promoted. The reason is that kernel PDEs are replicated in each pmap but
3189 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel
3190 * pmap.
3191 */
3192 static void
3193 pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va)
3194 {
3195 pd_entry_t newpde;
3196 pt_entry_t *firstpte, oldpte, pa, *pte;
3197 vm_offset_t oldpteva;
3198 vm_page_t mpte;
3199
3200 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3201
3202 /*
3203 * Examine the first PTE in the specified PTP. Abort if this PTE is
3204 * either invalid, unused, or does not map the first 4KB physical page
3205 * within a 2- or 4MB page.
3206 */
3207 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va));
3208 setpde:
3209 newpde = *firstpte;
3210 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) {
3211 pmap_pde_p_failures++;
3212 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3213 " in pmap %p", va, pmap);
3214 return;
3215 }
3216 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) {
3217 pmap_pde_p_failures++;
3218 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3219 " in pmap %p", va, pmap);
3220 return;
3221 }
3222 if ((newpde & (PG_M | PG_RW)) == PG_RW) {
3223 /*
3224 * When PG_M is already clear, PG_RW can be cleared without
3225 * a TLB invalidation.
3226 */
3227 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde &
3228 ~PG_RW))
3229 goto setpde;
3230 newpde &= ~PG_RW;
3231 }
3232
3233 /*
3234 * Examine each of the other PTEs in the specified PTP. Abort if this
3235 * PTE maps an unexpected 4KB physical page or does not have identical
3236 * characteristics to the first PTE.
3237 */
3238 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE;
3239 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) {
3240 setpte:
3241 oldpte = *pte;
3242 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) {
3243 pmap_pde_p_failures++;
3244 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3245 " in pmap %p", va, pmap);
3246 return;
3247 }
3248 if ((oldpte & (PG_M | PG_RW)) == PG_RW) {
3249 /*
3250 * When PG_M is already clear, PG_RW can be cleared
3251 * without a TLB invalidation.
3252 */
3253 if (!atomic_cmpset_int((u_int *)pte, oldpte,
3254 oldpte & ~PG_RW))
3255 goto setpte;
3256 oldpte &= ~PG_RW;
3257 oldpteva = (oldpte & PG_FRAME & PDRMASK) |
3258 (va & ~PDRMASK);
3259 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x"
3260 " in pmap %p", oldpteva, pmap);
3261 }
3262 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) {
3263 pmap_pde_p_failures++;
3264 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x"
3265 " in pmap %p", va, pmap);
3266 return;
3267 }
3268 pa -= PAGE_SIZE;
3269 }
3270
3271 /*
3272 * Save the page table page in its current state until the PDE
3273 * mapping the superpage is demoted by pmap_demote_pde() or
3274 * destroyed by pmap_remove_pde().
3275 */
3276 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME);
3277 KASSERT(mpte >= vm_page_array &&
3278 mpte < &vm_page_array[vm_page_array_size],
3279 ("pmap_promote_pde: page table page is out of range"));
3280 KASSERT(mpte->pindex == va >> PDRSHIFT,
3281 ("pmap_promote_pde: page table page's pindex is wrong"));
3282 pmap_insert_pt_page(pmap, mpte);
3283
3284 /*
3285 * Promote the pv entries.
3286 */
3287 if ((newpde & PG_MANAGED) != 0)
3288 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME);
3289
3290 /*
3291 * Propagate the PAT index to its proper position.
3292 */
3293 if ((newpde & PG_PTE_PAT) != 0)
3294 newpde ^= PG_PDE_PAT | PG_PTE_PAT;
3295
3296 /*
3297 * Map the superpage.
3298 */
3299 if (workaround_erratum383)
3300 pmap_update_pde(pmap, va, pde, PG_PS | newpde);
3301 else if (pmap == kernel_pmap)
3302 pmap_kenter_pde(va, PG_PS | newpde);
3303 else
3304 pde_store(pde, PG_PS | newpde);
3305
3306 pmap_pde_promotions++;
3307 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x"
3308 " in pmap %p", va, pmap);
3309 }
3310
3311 /*
3312 * Insert the given physical page (p) at
3313 * the specified virtual address (v) in the
3314 * target physical map with the protection requested.
3315 *
3316 * If specified, the page will be wired down, meaning
3317 * that the related pte can not be reclaimed.
3318 *
3319 * NB: This is the only routine which MAY NOT lazy-evaluate
3320 * or lose information. That is, this routine must actually
3321 * insert this page into the given map NOW.
3322 */
3323 void
3324 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
3325 vm_prot_t prot, boolean_t wired)
3326 {
3327 vm_paddr_t pa;
3328 pd_entry_t *pde;
3329 pt_entry_t *pte;
3330 vm_paddr_t opa;
3331 pt_entry_t origpte, newpte;
3332 vm_page_t mpte, om;
3333 boolean_t invlva;
3334
3335 va = trunc_page(va);
3336 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
3337 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS,
3338 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", va));
3339
3340 mpte = NULL;
3341
3342 vm_page_lock_queues();
3343 PMAP_LOCK(pmap);
3344 sched_pin();
3345
3346 /*
3347 * In the case that a page table page is not
3348 * resident, we are creating it here.
3349 */
3350 if (va < VM_MAXUSER_ADDRESS) {
3351 mpte = pmap_allocpte(pmap, va, M_WAITOK);
3352 }
3353
3354 pde = pmap_pde(pmap, va);
3355 if ((*pde & PG_PS) != 0)
3356 panic("pmap_enter: attempted pmap_enter on 4MB page");
3357 pte = pmap_pte_quick(pmap, va);
3358
3359 /*
3360 * Page Directory table entry not valid, we need a new PT page
3361 */
3362 if (pte == NULL) {
3363 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x",
3364 (uintmax_t)pmap->pm_pdir[PTDPTDI], va);
3365 }
3366
3367 pa = VM_PAGE_TO_PHYS(m);
3368 om = NULL;
3369 origpte = *pte;
3370 opa = origpte & PG_FRAME;
3371
3372 /*
3373 * Mapping has not changed, must be protection or wiring change.
3374 */
3375 if (origpte && (opa == pa)) {
3376 /*
3377 * Wiring change, just update stats. We don't worry about
3378 * wiring PT pages as they remain resident as long as there
3379 * are valid mappings in them. Hence, if a user page is wired,
3380 * the PT page will be also.
3381 */
3382 if (wired && ((origpte & PG_W) == 0))
3383 pmap->pm_stats.wired_count++;
3384 else if (!wired && (origpte & PG_W))
3385 pmap->pm_stats.wired_count--;
3386
3387 /*
3388 * Remove extra pte reference
3389 */
3390 if (mpte)
3391 mpte->wire_count--;
3392
3393 /*
3394 * We might be turning off write access to the page,
3395 * so we go ahead and sense modify status.
3396 */
3397 if (origpte & PG_MANAGED) {
3398 om = m;
3399 pa |= PG_MANAGED;
3400 }
3401 goto validate;
3402 }
3403 /*
3404 * Mapping has changed, invalidate old range and fall through to
3405 * handle validating new mapping.
3406 */
3407 if (opa) {
3408 if (origpte & PG_W)
3409 pmap->pm_stats.wired_count--;
3410 if (origpte & PG_MANAGED) {
3411 om = PHYS_TO_VM_PAGE(opa);
3412 pmap_remove_entry(pmap, om, va);
3413 }
3414 if (mpte != NULL) {
3415 mpte->wire_count--;
3416 KASSERT(mpte->wire_count > 0,
3417 ("pmap_enter: missing reference to page table page,"
3418 " va: 0x%x", va));
3419 }
3420 } else
3421 pmap->pm_stats.resident_count++;
3422
3423 /*
3424 * Enter on the PV list if part of our managed memory.
3425 */
3426 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) {
3427 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva,
3428 ("pmap_enter: managed mapping within the clean submap"));
3429 pmap_insert_entry(pmap, va, m);
3430 pa |= PG_MANAGED;
3431 }
3432
3433 /*
3434 * Increment counters
3435 */
3436 if (wired)
3437 pmap->pm_stats.wired_count++;
3438
3439 validate:
3440 /*
3441 * Now validate mapping with desired protection/wiring.
3442 */
3443 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V);
3444 if ((prot & VM_PROT_WRITE) != 0) {
3445 newpte |= PG_RW;
3446 vm_page_flag_set(m, PG_WRITEABLE);
3447 }
3448 #ifdef PAE
3449 if ((prot & VM_PROT_EXECUTE) == 0)
3450 newpte |= pg_nx;
3451 #endif
3452 if (wired)
3453 newpte |= PG_W;
3454 if (va < VM_MAXUSER_ADDRESS)
3455 newpte |= PG_U;
3456 if (pmap == kernel_pmap)
3457 newpte |= pgeflag;
3458
3459 /*
3460 * if the mapping or permission bits are different, we need
3461 * to update the pte.
3462 */
3463 if ((origpte & ~(PG_M|PG_A)) != newpte) {
3464 newpte |= PG_A;
3465 if ((access & VM_PROT_WRITE) != 0)
3466 newpte |= PG_M;
3467 if (origpte & PG_V) {
3468 invlva = FALSE;
3469 origpte = pte_load_store(pte, newpte);
3470 if (origpte & PG_A) {
3471 if (origpte & PG_MANAGED)
3472 vm_page_flag_set(om, PG_REFERENCED);
3473 if (opa != VM_PAGE_TO_PHYS(m))
3474 invlva = TRUE;
3475 #ifdef PAE
3476 if ((origpte & PG_NX) == 0 &&
3477 (newpte & PG_NX) != 0)
3478 invlva = TRUE;
3479 #endif
3480 }
3481 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
3482 if ((origpte & PG_MANAGED) != 0)
3483 vm_page_dirty(om);
3484 if ((prot & VM_PROT_WRITE) == 0)
3485 invlva = TRUE;
3486 }
3487 if (invlva)
3488 pmap_invalidate_page(pmap, va);
3489 } else
3490 pte_store(pte, newpte);
3491 }
3492
3493 /*
3494 * If both the page table page and the reservation are fully
3495 * populated, then attempt promotion.
3496 */
3497 if ((mpte == NULL || mpte->wire_count == NPTEPG) &&
3498 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0)
3499 pmap_promote_pde(pmap, pde, va);
3500
3501 sched_unpin();
3502 vm_page_unlock_queues();
3503 PMAP_UNLOCK(pmap);
3504 }
3505
3506 /*
3507 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and
3508 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without
3509 * blocking, (2) a mapping already exists at the specified virtual address, or
3510 * (3) a pv entry cannot be allocated without reclaiming another pv entry.
3511 */
3512 static boolean_t
3513 pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3514 {
3515 pd_entry_t *pde, newpde;
3516
3517 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3518 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3519 pde = pmap_pde(pmap, va);
3520 if (*pde != 0) {
3521 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3522 " in pmap %p", va, pmap);
3523 return (FALSE);
3524 }
3525 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) |
3526 PG_PS | PG_V;
3527 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0) {
3528 newpde |= PG_MANAGED;
3529
3530 /*
3531 * Abort this mapping if its PV entry could not be created.
3532 */
3533 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) {
3534 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx"
3535 " in pmap %p", va, pmap);
3536 return (FALSE);
3537 }
3538 }
3539 #ifdef PAE
3540 if ((prot & VM_PROT_EXECUTE) == 0)
3541 newpde |= pg_nx;
3542 #endif
3543 if (va < VM_MAXUSER_ADDRESS)
3544 newpde |= PG_U;
3545
3546 /*
3547 * Increment counters.
3548 */
3549 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE;
3550
3551 /*
3552 * Map the superpage.
3553 */
3554 pde_store(pde, newpde);
3555
3556 pmap_pde_mappings++;
3557 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx"
3558 " in pmap %p", va, pmap);
3559 return (TRUE);
3560 }
3561
3562 /*
3563 * Maps a sequence of resident pages belonging to the same object.
3564 * The sequence begins with the given page m_start. This page is
3565 * mapped at the given virtual address start. Each subsequent page is
3566 * mapped at a virtual address that is offset from start by the same
3567 * amount as the page is offset from m_start within the object. The
3568 * last page in the sequence is the page with the largest offset from
3569 * m_start that can be mapped at a virtual address less than the given
3570 * virtual address end. Not every virtual page between start and end
3571 * is mapped; only those for which a resident page exists with the
3572 * corresponding offset from m_start are mapped.
3573 */
3574 void
3575 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
3576 vm_page_t m_start, vm_prot_t prot)
3577 {
3578 vm_offset_t va;
3579 vm_page_t m, mpte;
3580 vm_pindex_t diff, psize;
3581
3582 VM_OBJECT_LOCK_ASSERT(m_start->object, MA_OWNED);
3583 psize = atop(end - start);
3584 mpte = NULL;
3585 m = m_start;
3586 PMAP_LOCK(pmap);
3587 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
3588 va = start + ptoa(diff);
3589 if ((va & PDRMASK) == 0 && va + NBPDR <= end &&
3590 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 &&
3591 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 &&
3592 pmap_enter_pde(pmap, va, m, prot))
3593 m = &m[NBPDR / PAGE_SIZE - 1];
3594 else
3595 mpte = pmap_enter_quick_locked(pmap, va, m, prot,
3596 mpte);
3597 m = TAILQ_NEXT(m, listq);
3598 }
3599 PMAP_UNLOCK(pmap);
3600 }
3601
3602 /*
3603 * this code makes some *MAJOR* assumptions:
3604 * 1. Current pmap & pmap exists.
3605 * 2. Not wired.
3606 * 3. Read access.
3607 * 4. No page table pages.
3608 * but is *MUCH* faster than pmap_enter...
3609 */
3610
3611 void
3612 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
3613 {
3614
3615 PMAP_LOCK(pmap);
3616 (void) pmap_enter_quick_locked(pmap, va, m, prot, NULL);
3617 PMAP_UNLOCK(pmap);
3618 }
3619
3620 static vm_page_t
3621 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
3622 vm_prot_t prot, vm_page_t mpte)
3623 {
3624 pt_entry_t *pte;
3625 vm_paddr_t pa;
3626 vm_page_t free;
3627
3628 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
3629 (m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0,
3630 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
3631 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
3632 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
3633
3634 /*
3635 * In the case that a page table page is not
3636 * resident, we are creating it here.
3637 */
3638 if (va < VM_MAXUSER_ADDRESS) {
3639 unsigned ptepindex;
3640 pd_entry_t ptepa;
3641
3642 /*
3643 * Calculate pagetable page index
3644 */
3645 ptepindex = va >> PDRSHIFT;
3646 if (mpte && (mpte->pindex == ptepindex)) {
3647 mpte->wire_count++;
3648 } else {
3649 /*
3650 * Get the page directory entry
3651 */
3652 ptepa = pmap->pm_pdir[ptepindex];
3653
3654 /*
3655 * If the page table page is mapped, we just increment
3656 * the hold count, and activate it.
3657 */
3658 if (ptepa) {
3659 if (ptepa & PG_PS)
3660 return (NULL);
3661 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME);
3662 mpte->wire_count++;
3663 } else {
3664 mpte = _pmap_allocpte(pmap, ptepindex,
3665 M_NOWAIT);
3666 if (mpte == NULL)
3667 return (mpte);
3668 }
3669 }
3670 } else {
3671 mpte = NULL;
3672 }
3673
3674 /*
3675 * This call to vtopte makes the assumption that we are
3676 * entering the page into the current pmap. In order to support
3677 * quick entry into any pmap, one would likely use pmap_pte_quick.
3678 * But that isn't as quick as vtopte.
3679 */
3680 pte = vtopte(va);
3681 if (*pte) {
3682 if (mpte != NULL) {
3683 mpte->wire_count--;
3684 mpte = NULL;
3685 }
3686 return (mpte);
3687 }
3688
3689 /*
3690 * Enter on the PV list if part of our managed memory.
3691 */
3692 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) == 0 &&
3693 !pmap_try_insert_pv_entry(pmap, va, m)) {
3694 if (mpte != NULL) {
3695 free = NULL;
3696 if (pmap_unwire_pte_hold(pmap, mpte, &free)) {
3697 pmap_invalidate_page(pmap, va);
3698 pmap_free_zero_pages(free);
3699 }
3700
3701 mpte = NULL;
3702 }
3703 return (mpte);
3704 }
3705
3706 /*
3707 * Increment counters
3708 */
3709 pmap->pm_stats.resident_count++;
3710
3711 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0);
3712 #ifdef PAE
3713 if ((prot & VM_PROT_EXECUTE) == 0)
3714 pa |= pg_nx;
3715 #endif
3716
3717 /*
3718 * Now validate mapping with RO protection
3719 */
3720 if (m->flags & (PG_FICTITIOUS|PG_UNMANAGED))
3721 pte_store(pte, pa | PG_V | PG_U);
3722 else
3723 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED);
3724 return mpte;
3725 }
3726
3727 /*
3728 * Make a temporary mapping for a physical address. This is only intended
3729 * to be used for panic dumps.
3730 */
3731 void *
3732 pmap_kenter_temporary(vm_paddr_t pa, int i)
3733 {
3734 vm_offset_t va;
3735
3736 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE);
3737 pmap_kenter(va, pa);
3738 invlpg(va);
3739 return ((void *)crashdumpmap);
3740 }
3741
3742 /*
3743 * This code maps large physical mmap regions into the
3744 * processor address space. Note that some shortcuts
3745 * are taken, but the code works.
3746 */
3747 void
3748 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object,
3749 vm_pindex_t pindex, vm_size_t size)
3750 {
3751 pd_entry_t *pde;
3752 vm_paddr_t pa, ptepa;
3753 vm_page_t p;
3754 int pat_mode;
3755
3756 VM_OBJECT_LOCK_ASSERT(object, MA_OWNED);
3757 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
3758 ("pmap_object_init_pt: non-device object"));
3759 if (pseflag &&
3760 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) {
3761 if (!vm_object_populate(object, pindex, pindex + atop(size)))
3762 return;
3763 p = vm_page_lookup(object, pindex);
3764 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3765 ("pmap_object_init_pt: invalid page %p", p));
3766 pat_mode = p->md.pat_mode;
3767
3768 /*
3769 * Abort the mapping if the first page is not physically
3770 * aligned to a 2/4MB page boundary.
3771 */
3772 ptepa = VM_PAGE_TO_PHYS(p);
3773 if (ptepa & (NBPDR - 1))
3774 return;
3775
3776 /*
3777 * Skip the first page. Abort the mapping if the rest of
3778 * the pages are not physically contiguous or have differing
3779 * memory attributes.
3780 */
3781 p = TAILQ_NEXT(p, listq);
3782 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size;
3783 pa += PAGE_SIZE) {
3784 KASSERT(p->valid == VM_PAGE_BITS_ALL,
3785 ("pmap_object_init_pt: invalid page %p", p));
3786 if (pa != VM_PAGE_TO_PHYS(p) ||
3787 pat_mode != p->md.pat_mode)
3788 return;
3789 p = TAILQ_NEXT(p, listq);
3790 }
3791
3792 /*
3793 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and
3794 * "size" is a multiple of 2/4M, adding the PAT setting to
3795 * "pa" will not affect the termination of this loop.
3796 */
3797 PMAP_LOCK(pmap);
3798 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa +
3799 size; pa += NBPDR) {
3800 pde = pmap_pde(pmap, addr);
3801 if (*pde == 0) {
3802 pde_store(pde, pa | PG_PS | PG_M | PG_A |
3803 PG_U | PG_RW | PG_V);
3804 pmap->pm_stats.resident_count += NBPDR /
3805 PAGE_SIZE;
3806 pmap_pde_mappings++;
3807 }
3808 /* Else continue on if the PDE is already valid. */
3809 addr += NBPDR;
3810 }
3811 PMAP_UNLOCK(pmap);
3812 }
3813 }
3814
3815 /*
3816 * Routine: pmap_change_wiring
3817 * Function: Change the wiring attribute for a map/virtual-address
3818 * pair.
3819 * In/out conditions:
3820 * The mapping must already exist in the pmap.
3821 */
3822 void
3823 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
3824 {
3825 pd_entry_t *pde;
3826 pt_entry_t *pte;
3827 boolean_t are_queues_locked;
3828
3829 are_queues_locked = FALSE;
3830 retry:
3831 PMAP_LOCK(pmap);
3832 pde = pmap_pde(pmap, va);
3833 if ((*pde & PG_PS) != 0) {
3834 if (!wired != ((*pde & PG_W) == 0)) {
3835 if (!are_queues_locked) {
3836 are_queues_locked = TRUE;
3837 if (!mtx_trylock(&vm_page_queue_mtx)) {
3838 PMAP_UNLOCK(pmap);
3839 vm_page_lock_queues();
3840 goto retry;
3841 }
3842 }
3843 if (!pmap_demote_pde(pmap, pde, va))
3844 panic("pmap_change_wiring: demotion failed");
3845 } else
3846 goto out;
3847 }
3848 pte = pmap_pte(pmap, va);
3849
3850 if (wired && !pmap_pte_w(pte))
3851 pmap->pm_stats.wired_count++;
3852 else if (!wired && pmap_pte_w(pte))
3853 pmap->pm_stats.wired_count--;
3854
3855 /*
3856 * Wiring is not a hardware characteristic so there is no need to
3857 * invalidate TLB.
3858 */
3859 pmap_pte_set_w(pte, wired);
3860 pmap_pte_release(pte);
3861 out:
3862 if (are_queues_locked)
3863 vm_page_unlock_queues();
3864 PMAP_UNLOCK(pmap);
3865 }
3866
3867
3868
3869 /*
3870 * Copy the range specified by src_addr/len
3871 * from the source map to the range dst_addr/len
3872 * in the destination map.
3873 *
3874 * This routine is only advisory and need not do anything.
3875 */
3876
3877 void
3878 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len,
3879 vm_offset_t src_addr)
3880 {
3881 vm_page_t free;
3882 vm_offset_t addr;
3883 vm_offset_t end_addr = src_addr + len;
3884 vm_offset_t pdnxt;
3885
3886 if (dst_addr != src_addr)
3887 return;
3888
3889 if (!pmap_is_current(src_pmap))
3890 return;
3891
3892 vm_page_lock_queues();
3893 if (dst_pmap < src_pmap) {
3894 PMAP_LOCK(dst_pmap);
3895 PMAP_LOCK(src_pmap);
3896 } else {
3897 PMAP_LOCK(src_pmap);
3898 PMAP_LOCK(dst_pmap);
3899 }
3900 sched_pin();
3901 for (addr = src_addr; addr < end_addr; addr = pdnxt) {
3902 pt_entry_t *src_pte, *dst_pte;
3903 vm_page_t dstmpte, srcmpte;
3904 pd_entry_t srcptepaddr;
3905 unsigned ptepindex;
3906
3907 KASSERT(addr < UPT_MIN_ADDRESS,
3908 ("pmap_copy: invalid to pmap_copy page tables"));
3909
3910 pdnxt = (addr + NBPDR) & ~PDRMASK;
3911 if (pdnxt < addr)
3912 pdnxt = end_addr;
3913 ptepindex = addr >> PDRSHIFT;
3914
3915 srcptepaddr = src_pmap->pm_pdir[ptepindex];
3916 if (srcptepaddr == 0)
3917 continue;
3918
3919 if (srcptepaddr & PG_PS) {
3920 if (dst_pmap->pm_pdir[ptepindex] == 0 &&
3921 ((srcptepaddr & PG_MANAGED) == 0 ||
3922 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr &
3923 PG_PS_FRAME))) {
3924 dst_pmap->pm_pdir[ptepindex] = srcptepaddr &
3925 ~PG_W;
3926 dst_pmap->pm_stats.resident_count +=
3927 NBPDR / PAGE_SIZE;
3928 }
3929 continue;
3930 }
3931
3932 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME);
3933 KASSERT(srcmpte->wire_count > 0,
3934 ("pmap_copy: source page table page is unused"));
3935
3936 if (pdnxt > end_addr)
3937 pdnxt = end_addr;
3938
3939 src_pte = vtopte(addr);
3940 while (addr < pdnxt) {
3941 pt_entry_t ptetemp;
3942 ptetemp = *src_pte;
3943 /*
3944 * we only virtual copy managed pages
3945 */
3946 if ((ptetemp & PG_MANAGED) != 0) {
3947 dstmpte = pmap_allocpte(dst_pmap, addr,
3948 M_NOWAIT);
3949 if (dstmpte == NULL)
3950 goto out;
3951 dst_pte = pmap_pte_quick(dst_pmap, addr);
3952 if (*dst_pte == 0 &&
3953 pmap_try_insert_pv_entry(dst_pmap, addr,
3954 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) {
3955 /*
3956 * Clear the wired, modified, and
3957 * accessed (referenced) bits
3958 * during the copy.
3959 */
3960 *dst_pte = ptetemp & ~(PG_W | PG_M |
3961 PG_A);
3962 dst_pmap->pm_stats.resident_count++;
3963 } else {
3964 free = NULL;
3965 if (pmap_unwire_pte_hold(dst_pmap,
3966 dstmpte, &free)) {
3967 pmap_invalidate_page(dst_pmap,
3968 addr);
3969 pmap_free_zero_pages(free);
3970 }
3971 goto out;
3972 }
3973 if (dstmpte->wire_count >= srcmpte->wire_count)
3974 break;
3975 }
3976 addr += PAGE_SIZE;
3977 src_pte++;
3978 }
3979 }
3980 out:
3981 sched_unpin();
3982 vm_page_unlock_queues();
3983 PMAP_UNLOCK(src_pmap);
3984 PMAP_UNLOCK(dst_pmap);
3985 }
3986
3987 static __inline void
3988 pagezero(void *page)
3989 {
3990 #if defined(I686_CPU)
3991 if (cpu_class == CPUCLASS_686) {
3992 #if defined(CPU_ENABLE_SSE)
3993 if (cpu_feature & CPUID_SSE2)
3994 sse2_pagezero(page);
3995 else
3996 #endif
3997 i686_pagezero(page);
3998 } else
3999 #endif
4000 bzero(page, PAGE_SIZE);
4001 }
4002
4003 /*
4004 * pmap_zero_page zeros the specified hardware page by mapping
4005 * the page into KVM and using bzero to clear its contents.
4006 */
4007 void
4008 pmap_zero_page(vm_page_t m)
4009 {
4010 struct sysmaps *sysmaps;
4011
4012 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4013 mtx_lock(&sysmaps->lock);
4014 if (*sysmaps->CMAP2)
4015 panic("pmap_zero_page: CMAP2 busy");
4016 sched_pin();
4017 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4018 pmap_cache_bits(m->md.pat_mode, 0);
4019 invlcaddr(sysmaps->CADDR2);
4020 pagezero(sysmaps->CADDR2);
4021 *sysmaps->CMAP2 = 0;
4022 sched_unpin();
4023 mtx_unlock(&sysmaps->lock);
4024 }
4025
4026 /*
4027 * pmap_zero_page_area zeros the specified hardware page by mapping
4028 * the page into KVM and using bzero to clear its contents.
4029 *
4030 * off and size may not cover an area beyond a single hardware page.
4031 */
4032 void
4033 pmap_zero_page_area(vm_page_t m, int off, int size)
4034 {
4035 struct sysmaps *sysmaps;
4036
4037 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4038 mtx_lock(&sysmaps->lock);
4039 if (*sysmaps->CMAP2)
4040 panic("pmap_zero_page_area: CMAP2 busy");
4041 sched_pin();
4042 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4043 pmap_cache_bits(m->md.pat_mode, 0);
4044 invlcaddr(sysmaps->CADDR2);
4045 if (off == 0 && size == PAGE_SIZE)
4046 pagezero(sysmaps->CADDR2);
4047 else
4048 bzero((char *)sysmaps->CADDR2 + off, size);
4049 *sysmaps->CMAP2 = 0;
4050 sched_unpin();
4051 mtx_unlock(&sysmaps->lock);
4052 }
4053
4054 /*
4055 * pmap_zero_page_idle zeros the specified hardware page by mapping
4056 * the page into KVM and using bzero to clear its contents. This
4057 * is intended to be called from the vm_pagezero process only and
4058 * outside of Giant.
4059 */
4060 void
4061 pmap_zero_page_idle(vm_page_t m)
4062 {
4063
4064 if (*CMAP3)
4065 panic("pmap_zero_page_idle: CMAP3 busy");
4066 sched_pin();
4067 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M |
4068 pmap_cache_bits(m->md.pat_mode, 0);
4069 invlcaddr(CADDR3);
4070 pagezero(CADDR3);
4071 *CMAP3 = 0;
4072 sched_unpin();
4073 }
4074
4075 /*
4076 * pmap_copy_page copies the specified (machine independent)
4077 * page by mapping the page into virtual memory and using
4078 * bcopy to copy the page, one machine dependent page at a
4079 * time.
4080 */
4081 void
4082 pmap_copy_page(vm_page_t src, vm_page_t dst)
4083 {
4084 struct sysmaps *sysmaps;
4085
4086 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4087 mtx_lock(&sysmaps->lock);
4088 if (*sysmaps->CMAP1)
4089 panic("pmap_copy_page: CMAP1 busy");
4090 if (*sysmaps->CMAP2)
4091 panic("pmap_copy_page: CMAP2 busy");
4092 sched_pin();
4093 invlpg((u_int)sysmaps->CADDR1);
4094 invlpg((u_int)sysmaps->CADDR2);
4095 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A |
4096 pmap_cache_bits(src->md.pat_mode, 0);
4097 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M |
4098 pmap_cache_bits(dst->md.pat_mode, 0);
4099 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE);
4100 *sysmaps->CMAP1 = 0;
4101 *sysmaps->CMAP2 = 0;
4102 sched_unpin();
4103 mtx_unlock(&sysmaps->lock);
4104 }
4105
4106 /*
4107 * Returns true if the pmap's pv is one of the first
4108 * 16 pvs linked to from this page. This count may
4109 * be changed upwards or downwards in the future; it
4110 * is only necessary that true be returned for a small
4111 * subset of pmaps for proper page aging.
4112 */
4113 boolean_t
4114 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
4115 {
4116 struct md_page *pvh;
4117 pv_entry_t pv;
4118 int loops = 0;
4119
4120 if (m->flags & PG_FICTITIOUS)
4121 return FALSE;
4122
4123 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4124 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4125 if (PV_PMAP(pv) == pmap) {
4126 return TRUE;
4127 }
4128 loops++;
4129 if (loops >= 16)
4130 break;
4131 }
4132 if (loops < 16) {
4133 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4134 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4135 if (PV_PMAP(pv) == pmap)
4136 return (TRUE);
4137 loops++;
4138 if (loops >= 16)
4139 break;
4140 }
4141 }
4142 return (FALSE);
4143 }
4144
4145 /*
4146 * pmap_page_wired_mappings:
4147 *
4148 * Return the number of managed mappings to the given physical page
4149 * that are wired.
4150 */
4151 int
4152 pmap_page_wired_mappings(vm_page_t m)
4153 {
4154 int count;
4155
4156 count = 0;
4157 if ((m->flags & PG_FICTITIOUS) != 0)
4158 return (count);
4159 count = pmap_pvh_wired_mappings(&m->md, count);
4160 return (pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), count));
4161 }
4162
4163 /*
4164 * pmap_pvh_wired_mappings:
4165 *
4166 * Return the updated number "count" of managed mappings that are wired.
4167 */
4168 static int
4169 pmap_pvh_wired_mappings(struct md_page *pvh, int count)
4170 {
4171 pmap_t pmap;
4172 pt_entry_t *pte;
4173 pv_entry_t pv;
4174
4175 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4176 sched_pin();
4177 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4178 pmap = PV_PMAP(pv);
4179 PMAP_LOCK(pmap);
4180 pte = pmap_pte_quick(pmap, pv->pv_va);
4181 if ((*pte & PG_W) != 0)
4182 count++;
4183 PMAP_UNLOCK(pmap);
4184 }
4185 sched_unpin();
4186 return (count);
4187 }
4188
4189 /*
4190 * Returns TRUE if the given page is mapped individually or as part of
4191 * a 4mpage. Otherwise, returns FALSE.
4192 */
4193 boolean_t
4194 pmap_page_is_mapped(vm_page_t m)
4195 {
4196 struct md_page *pvh;
4197
4198 if ((m->flags & (PG_FICTITIOUS | PG_UNMANAGED)) != 0)
4199 return (FALSE);
4200 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4201 if (TAILQ_EMPTY(&m->md.pv_list)) {
4202 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4203 return (!TAILQ_EMPTY(&pvh->pv_list));
4204 } else
4205 return (TRUE);
4206 }
4207
4208 /*
4209 * Remove all pages from specified address space
4210 * this aids process exit speeds. Also, this code
4211 * is special cased for current process only, but
4212 * can have the more generic (and slightly slower)
4213 * mode enabled. This is much faster than pmap_remove
4214 * in the case of running down an entire address space.
4215 */
4216 void
4217 pmap_remove_pages(pmap_t pmap)
4218 {
4219 pt_entry_t *pte, tpte;
4220 vm_page_t free = NULL;
4221 vm_page_t m, mpte, mt;
4222 pv_entry_t pv;
4223 struct md_page *pvh;
4224 struct pv_chunk *pc, *npc;
4225 int field, idx;
4226 int32_t bit;
4227 uint32_t inuse, bitmask;
4228 int allfree;
4229
4230 if (pmap != PCPU_GET(curpmap)) {
4231 printf("warning: pmap_remove_pages called with non-current pmap\n");
4232 return;
4233 }
4234 vm_page_lock_queues();
4235 PMAP_LOCK(pmap);
4236 sched_pin();
4237 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
4238 allfree = 1;
4239 for (field = 0; field < _NPCM; field++) {
4240 inuse = (~(pc->pc_map[field])) & pc_freemask[field];
4241 while (inuse != 0) {
4242 bit = bsfl(inuse);
4243 bitmask = 1UL << bit;
4244 idx = field * 32 + bit;
4245 pv = &pc->pc_pventry[idx];
4246 inuse &= ~bitmask;
4247
4248 pte = pmap_pde(pmap, pv->pv_va);
4249 tpte = *pte;
4250 if ((tpte & PG_PS) == 0) {
4251 pte = vtopte(pv->pv_va);
4252 tpte = *pte & ~PG_PTE_PAT;
4253 }
4254
4255 if (tpte == 0) {
4256 printf(
4257 "TPTE at %p IS ZERO @ VA %08x\n",
4258 pte, pv->pv_va);
4259 panic("bad pte");
4260 }
4261
4262 /*
4263 * We cannot remove wired pages from a process' mapping at this time
4264 */
4265 if (tpte & PG_W) {
4266 allfree = 0;
4267 continue;
4268 }
4269
4270 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME);
4271 KASSERT(m->phys_addr == (tpte & PG_FRAME),
4272 ("vm_page_t %p phys_addr mismatch %016jx %016jx",
4273 m, (uintmax_t)m->phys_addr,
4274 (uintmax_t)tpte));
4275
4276 KASSERT(m < &vm_page_array[vm_page_array_size],
4277 ("pmap_remove_pages: bad tpte %#jx",
4278 (uintmax_t)tpte));
4279
4280 pte_clear(pte);
4281
4282 /*
4283 * Update the vm_page_t clean/reference bits.
4284 */
4285 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4286 if ((tpte & PG_PS) != 0) {
4287 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4288 vm_page_dirty(mt);
4289 } else
4290 vm_page_dirty(m);
4291 }
4292
4293 /* Mark free */
4294 PV_STAT(pv_entry_frees++);
4295 PV_STAT(pv_entry_spare++);
4296 pv_entry_count--;
4297 pc->pc_map[field] |= bitmask;
4298 if ((tpte & PG_PS) != 0) {
4299 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE;
4300 pvh = pa_to_pvh(tpte & PG_PS_FRAME);
4301 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
4302 if (TAILQ_EMPTY(&pvh->pv_list)) {
4303 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++)
4304 if (TAILQ_EMPTY(&mt->md.pv_list))
4305 vm_page_flag_clear(mt, PG_WRITEABLE);
4306 }
4307 mpte = pmap_lookup_pt_page(pmap, pv->pv_va);
4308 if (mpte != NULL) {
4309 pmap_remove_pt_page(pmap, mpte);
4310 pmap->pm_stats.resident_count--;
4311 KASSERT(mpte->wire_count == NPTEPG,
4312 ("pmap_remove_pages: pte page wire count error"));
4313 mpte->wire_count = 0;
4314 pmap_add_delayed_free_list(mpte, &free, FALSE);
4315 atomic_subtract_int(&cnt.v_wire_count, 1);
4316 }
4317 } else {
4318 pmap->pm_stats.resident_count--;
4319 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4320 if (TAILQ_EMPTY(&m->md.pv_list)) {
4321 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4322 if (TAILQ_EMPTY(&pvh->pv_list))
4323 vm_page_flag_clear(m, PG_WRITEABLE);
4324 }
4325 pmap_unuse_pt(pmap, pv->pv_va, &free);
4326 }
4327 }
4328 }
4329 if (allfree) {
4330 PV_STAT(pv_entry_spare -= _NPCPV);
4331 PV_STAT(pc_chunk_count--);
4332 PV_STAT(pc_chunk_frees++);
4333 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
4334 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc));
4335 pmap_qremove((vm_offset_t)pc, 1);
4336 vm_page_unwire(m, 0);
4337 vm_page_free(m);
4338 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc);
4339 }
4340 }
4341 sched_unpin();
4342 pmap_invalidate_all(pmap);
4343 vm_page_unlock_queues();
4344 PMAP_UNLOCK(pmap);
4345 pmap_free_zero_pages(free);
4346 }
4347
4348 /*
4349 * pmap_is_modified:
4350 *
4351 * Return whether or not the specified physical page was modified
4352 * in any physical maps.
4353 */
4354 boolean_t
4355 pmap_is_modified(vm_page_t m)
4356 {
4357
4358 if (m->flags & PG_FICTITIOUS)
4359 return (FALSE);
4360 if (pmap_is_modified_pvh(&m->md))
4361 return (TRUE);
4362 return (pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m))));
4363 }
4364
4365 /*
4366 * Returns TRUE if any of the given mappings were used to modify
4367 * physical memory. Otherwise, returns FALSE. Both page and 2mpage
4368 * mappings are supported.
4369 */
4370 static boolean_t
4371 pmap_is_modified_pvh(struct md_page *pvh)
4372 {
4373 pv_entry_t pv;
4374 pt_entry_t *pte;
4375 pmap_t pmap;
4376 boolean_t rv;
4377
4378 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4379 rv = FALSE;
4380 sched_pin();
4381 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
4382 pmap = PV_PMAP(pv);
4383 PMAP_LOCK(pmap);
4384 pte = pmap_pte_quick(pmap, pv->pv_va);
4385 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW);
4386 PMAP_UNLOCK(pmap);
4387 if (rv)
4388 break;
4389 }
4390 sched_unpin();
4391 return (rv);
4392 }
4393
4394 /*
4395 * pmap_is_prefaultable:
4396 *
4397 * Return whether or not the specified virtual address is elgible
4398 * for prefault.
4399 */
4400 boolean_t
4401 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
4402 {
4403 pd_entry_t *pde;
4404 pt_entry_t *pte;
4405 boolean_t rv;
4406
4407 rv = FALSE;
4408 PMAP_LOCK(pmap);
4409 pde = pmap_pde(pmap, addr);
4410 if (*pde != 0 && (*pde & PG_PS) == 0) {
4411 pte = vtopte(addr);
4412 rv = *pte == 0;
4413 }
4414 PMAP_UNLOCK(pmap);
4415 return (rv);
4416 }
4417
4418 /*
4419 * Clear the write and modified bits in each of the given page's mappings.
4420 */
4421 void
4422 pmap_remove_write(vm_page_t m)
4423 {
4424 struct md_page *pvh;
4425 pv_entry_t next_pv, pv;
4426 pmap_t pmap;
4427 pd_entry_t *pde;
4428 pt_entry_t oldpte, *pte;
4429 vm_offset_t va;
4430
4431 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4432 if ((m->flags & PG_FICTITIOUS) != 0 ||
4433 (m->flags & PG_WRITEABLE) == 0)
4434 return;
4435 sched_pin();
4436 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4437 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4438 va = pv->pv_va;
4439 pmap = PV_PMAP(pv);
4440 PMAP_LOCK(pmap);
4441 pde = pmap_pde(pmap, va);
4442 if ((*pde & PG_RW) != 0)
4443 (void)pmap_demote_pde(pmap, pde, va);
4444 PMAP_UNLOCK(pmap);
4445 }
4446 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4447 pmap = PV_PMAP(pv);
4448 PMAP_LOCK(pmap);
4449 pde = pmap_pde(pmap, pv->pv_va);
4450 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found"
4451 " a 4mpage in page %p's pv list", m));
4452 pte = pmap_pte_quick(pmap, pv->pv_va);
4453 retry:
4454 oldpte = *pte;
4455 if ((oldpte & PG_RW) != 0) {
4456 /*
4457 * Regardless of whether a pte is 32 or 64 bits
4458 * in size, PG_RW and PG_M are among the least
4459 * significant 32 bits.
4460 */
4461 if (!atomic_cmpset_int((u_int *)pte, oldpte,
4462 oldpte & ~(PG_RW | PG_M)))
4463 goto retry;
4464 if ((oldpte & PG_M) != 0)
4465 vm_page_dirty(m);
4466 pmap_invalidate_page(pmap, pv->pv_va);
4467 }
4468 PMAP_UNLOCK(pmap);
4469 }
4470 vm_page_flag_clear(m, PG_WRITEABLE);
4471 sched_unpin();
4472 }
4473
4474 /*
4475 * pmap_ts_referenced:
4476 *
4477 * Return a count of reference bits for a page, clearing those bits.
4478 * It is not necessary for every reference bit to be cleared, but it
4479 * is necessary that 0 only be returned when there are truly no
4480 * reference bits set.
4481 *
4482 * XXX: The exact number of bits to check and clear is a matter that
4483 * should be tested and standardized at some point in the future for
4484 * optimal aging of shared pages.
4485 */
4486 int
4487 pmap_ts_referenced(vm_page_t m)
4488 {
4489 struct md_page *pvh;
4490 pv_entry_t pv, pvf, pvn;
4491 pmap_t pmap;
4492 pd_entry_t oldpde, *pde;
4493 pt_entry_t *pte;
4494 vm_offset_t va;
4495 int rtval = 0;
4496
4497 if (m->flags & PG_FICTITIOUS)
4498 return (rtval);
4499 sched_pin();
4500 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4501 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4502 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, pvn) {
4503 va = pv->pv_va;
4504 pmap = PV_PMAP(pv);
4505 PMAP_LOCK(pmap);
4506 pde = pmap_pde(pmap, va);
4507 oldpde = *pde;
4508 if ((oldpde & PG_A) != 0) {
4509 if (pmap_demote_pde(pmap, pde, va)) {
4510 if ((oldpde & PG_W) == 0) {
4511 /*
4512 * Remove the mapping to a single page
4513 * so that a subsequent access may
4514 * repromote. Since the underlying
4515 * page table page is fully populated,
4516 * this removal never frees a page
4517 * table page.
4518 */
4519 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4520 PG_PS_FRAME);
4521 pmap_remove_page(pmap, va, NULL);
4522 rtval++;
4523 if (rtval > 4) {
4524 PMAP_UNLOCK(pmap);
4525 goto out;
4526 }
4527 }
4528 }
4529 }
4530 PMAP_UNLOCK(pmap);
4531 }
4532 if ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
4533 pvf = pv;
4534 do {
4535 pvn = TAILQ_NEXT(pv, pv_list);
4536 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
4537 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
4538 pmap = PV_PMAP(pv);
4539 PMAP_LOCK(pmap);
4540 pde = pmap_pde(pmap, pv->pv_va);
4541 KASSERT((*pde & PG_PS) == 0, ("pmap_ts_referenced:"
4542 " found a 4mpage in page %p's pv list", m));
4543 pte = pmap_pte_quick(pmap, pv->pv_va);
4544 if ((*pte & PG_A) != 0) {
4545 atomic_clear_int((u_int *)pte, PG_A);
4546 pmap_invalidate_page(pmap, pv->pv_va);
4547 rtval++;
4548 if (rtval > 4)
4549 pvn = NULL;
4550 }
4551 PMAP_UNLOCK(pmap);
4552 } while ((pv = pvn) != NULL && pv != pvf);
4553 }
4554 out:
4555 sched_unpin();
4556 return (rtval);
4557 }
4558
4559 /*
4560 * Clear the modify bits on the specified physical page.
4561 */
4562 void
4563 pmap_clear_modify(vm_page_t m)
4564 {
4565 struct md_page *pvh;
4566 pv_entry_t next_pv, pv;
4567 pmap_t pmap;
4568 pd_entry_t oldpde, *pde;
4569 pt_entry_t oldpte, *pte;
4570 vm_offset_t va;
4571
4572 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4573 if ((m->flags & PG_FICTITIOUS) != 0)
4574 return;
4575 sched_pin();
4576 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4577 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4578 va = pv->pv_va;
4579 pmap = PV_PMAP(pv);
4580 PMAP_LOCK(pmap);
4581 pde = pmap_pde(pmap, va);
4582 oldpde = *pde;
4583 if ((oldpde & PG_RW) != 0) {
4584 if (pmap_demote_pde(pmap, pde, va)) {
4585 if ((oldpde & PG_W) == 0) {
4586 /*
4587 * Write protect the mapping to a
4588 * single page so that a subsequent
4589 * write access may repromote.
4590 */
4591 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4592 PG_PS_FRAME);
4593 pte = pmap_pte_quick(pmap, va);
4594 oldpte = *pte;
4595 if ((oldpte & PG_V) != 0) {
4596 /*
4597 * Regardless of whether a pte is 32 or 64 bits
4598 * in size, PG_RW and PG_M are among the least
4599 * significant 32 bits.
4600 */
4601 while (!atomic_cmpset_int((u_int *)pte,
4602 oldpte,
4603 oldpte & ~(PG_M | PG_RW)))
4604 oldpte = *pte;
4605 vm_page_dirty(m);
4606 pmap_invalidate_page(pmap, va);
4607 }
4608 }
4609 }
4610 }
4611 PMAP_UNLOCK(pmap);
4612 }
4613 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4614 pmap = PV_PMAP(pv);
4615 PMAP_LOCK(pmap);
4616 pde = pmap_pde(pmap, pv->pv_va);
4617 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found"
4618 " a 4mpage in page %p's pv list", m));
4619 pte = pmap_pte_quick(pmap, pv->pv_va);
4620 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) {
4621 /*
4622 * Regardless of whether a pte is 32 or 64 bits
4623 * in size, PG_M is among the least significant
4624 * 32 bits.
4625 */
4626 atomic_clear_int((u_int *)pte, PG_M);
4627 pmap_invalidate_page(pmap, pv->pv_va);
4628 }
4629 PMAP_UNLOCK(pmap);
4630 }
4631 sched_unpin();
4632 }
4633
4634 /*
4635 * pmap_clear_reference:
4636 *
4637 * Clear the reference bit on the specified physical page.
4638 */
4639 void
4640 pmap_clear_reference(vm_page_t m)
4641 {
4642 struct md_page *pvh;
4643 pv_entry_t next_pv, pv;
4644 pmap_t pmap;
4645 pd_entry_t oldpde, *pde;
4646 pt_entry_t *pte;
4647 vm_offset_t va;
4648
4649 mtx_assert(&vm_page_queue_mtx, MA_OWNED);
4650 if ((m->flags & PG_FICTITIOUS) != 0)
4651 return;
4652 sched_pin();
4653 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m));
4654 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_list, next_pv) {
4655 va = pv->pv_va;
4656 pmap = PV_PMAP(pv);
4657 PMAP_LOCK(pmap);
4658 pde = pmap_pde(pmap, va);
4659 oldpde = *pde;
4660 if ((oldpde & PG_A) != 0) {
4661 if (pmap_demote_pde(pmap, pde, va)) {
4662 /*
4663 * Remove the mapping to a single page so
4664 * that a subsequent access may repromote.
4665 * Since the underlying page table page is
4666 * fully populated, this removal never frees
4667 * a page table page.
4668 */
4669 va += VM_PAGE_TO_PHYS(m) - (oldpde &
4670 PG_PS_FRAME);
4671 pmap_remove_page(pmap, va, NULL);
4672 }
4673 }
4674 PMAP_UNLOCK(pmap);
4675 }
4676 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
4677 pmap = PV_PMAP(pv);
4678 PMAP_LOCK(pmap);
4679 pde = pmap_pde(pmap, pv->pv_va);
4680 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_reference: found"
4681 " a 4mpage in page %p's pv list", m));
4682 pte = pmap_pte_quick(pmap, pv->pv_va);
4683 if ((*pte & PG_A) != 0) {
4684 /*
4685 * Regardless of whether a pte is 32 or 64 bits
4686 * in size, PG_A is among the least significant
4687 * 32 bits.
4688 */
4689 atomic_clear_int((u_int *)pte, PG_A);
4690 pmap_invalidate_page(pmap, pv->pv_va);
4691 }
4692 PMAP_UNLOCK(pmap);
4693 }
4694 sched_unpin();
4695 }
4696
4697 /*
4698 * Miscellaneous support routines follow
4699 */
4700
4701 /* Adjust the cache mode for a 4KB page mapped via a PTE. */
4702 static __inline void
4703 pmap_pte_attr(pt_entry_t *pte, int cache_bits)
4704 {
4705 u_int opte, npte;
4706
4707 /*
4708 * The cache mode bits are all in the low 32-bits of the
4709 * PTE, so we can just spin on updating the low 32-bits.
4710 */
4711 do {
4712 opte = *(u_int *)pte;
4713 npte = opte & ~PG_PTE_CACHE;
4714 npte |= cache_bits;
4715 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte));
4716 }
4717
4718 /* Adjust the cache mode for a 2/4MB page mapped via a PDE. */
4719 static __inline void
4720 pmap_pde_attr(pd_entry_t *pde, int cache_bits)
4721 {
4722 u_int opde, npde;
4723
4724 /*
4725 * The cache mode bits are all in the low 32-bits of the
4726 * PDE, so we can just spin on updating the low 32-bits.
4727 */
4728 do {
4729 opde = *(u_int *)pde;
4730 npde = opde & ~PG_PDE_CACHE;
4731 npde |= cache_bits;
4732 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde));
4733 }
4734
4735 /*
4736 * Map a set of physical memory pages into the kernel virtual
4737 * address space. Return a pointer to where it is mapped. This
4738 * routine is intended to be used for mapping device memory,
4739 * NOT real memory.
4740 */
4741 void *
4742 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode)
4743 {
4744 vm_offset_t va, offset;
4745 vm_size_t tmpsize;
4746
4747 offset = pa & PAGE_MASK;
4748 size = roundup(offset + size, PAGE_SIZE);
4749 pa = pa & PG_FRAME;
4750
4751 if (pa < KERNLOAD && pa + size <= KERNLOAD)
4752 va = KERNBASE + pa;
4753 else
4754 va = kmem_alloc_nofault(kernel_map, size);
4755 if (!va)
4756 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
4757
4758 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE)
4759 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode);
4760 pmap_invalidate_range(kernel_pmap, va, va + tmpsize);
4761 pmap_invalidate_cache_range(va, va + size);
4762 return ((void *)(va + offset));
4763 }
4764
4765 void *
4766 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
4767 {
4768
4769 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE));
4770 }
4771
4772 void *
4773 pmap_mapbios(vm_paddr_t pa, vm_size_t size)
4774 {
4775
4776 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK));
4777 }
4778
4779 void
4780 pmap_unmapdev(vm_offset_t va, vm_size_t size)
4781 {
4782 vm_offset_t base, offset, tmpva;
4783
4784 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD)
4785 return;
4786 base = trunc_page(va);
4787 offset = va & PAGE_MASK;
4788 size = roundup(offset + size, PAGE_SIZE);
4789 for (tmpva = base; tmpva < (base + size); tmpva += PAGE_SIZE)
4790 pmap_kremove(tmpva);
4791 pmap_invalidate_range(kernel_pmap, va, tmpva);
4792 kmem_free(kernel_map, base, size);
4793 }
4794
4795 /*
4796 * Sets the memory attribute for the specified page.
4797 */
4798 void
4799 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
4800 {
4801 struct sysmaps *sysmaps;
4802 vm_offset_t sva, eva;
4803
4804 m->md.pat_mode = ma;
4805 if ((m->flags & PG_FICTITIOUS) != 0)
4806 return;
4807
4808 /*
4809 * If "m" is a normal page, flush it from the cache.
4810 * See pmap_invalidate_cache_range().
4811 *
4812 * First, try to find an existing mapping of the page by sf
4813 * buffer. sf_buf_invalidate_cache() modifies mapping and
4814 * flushes the cache.
4815 */
4816 if (sf_buf_invalidate_cache(m))
4817 return;
4818
4819 /*
4820 * If page is not mapped by sf buffer, but CPU does not
4821 * support self snoop, map the page transient and do
4822 * invalidation. In the worst case, whole cache is flushed by
4823 * pmap_invalidate_cache_range().
4824 */
4825 if ((cpu_feature & (CPUID_SS|CPUID_CLFSH)) == CPUID_CLFSH) {
4826 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)];
4827 mtx_lock(&sysmaps->lock);
4828 if (*sysmaps->CMAP2)
4829 panic("pmap_page_set_memattr: CMAP2 busy");
4830 sched_pin();
4831 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) |
4832 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0);
4833 invlcaddr(sysmaps->CADDR2);
4834 sva = (vm_offset_t)sysmaps->CADDR2;
4835 eva = sva + PAGE_SIZE;
4836 } else
4837 sva = eva = 0; /* gcc */
4838 pmap_invalidate_cache_range(sva, eva);
4839 if (sva != 0) {
4840 *sysmaps->CMAP2 = 0;
4841 sched_unpin();
4842 mtx_unlock(&sysmaps->lock);
4843 }
4844 }
4845
4846 /*
4847 * Changes the specified virtual address range's memory type to that given by
4848 * the parameter "mode". The specified virtual address range must be
4849 * completely contained within either the kernel map.
4850 *
4851 * Returns zero if the change completed successfully, and either EINVAL or
4852 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part
4853 * of the virtual address range was not mapped, and ENOMEM is returned if
4854 * there was insufficient memory available to complete the change.
4855 */
4856 int
4857 pmap_change_attr(vm_offset_t va, vm_size_t size, int mode)
4858 {
4859 vm_offset_t base, offset, tmpva;
4860 pd_entry_t *pde;
4861 pt_entry_t *pte;
4862 int cache_bits_pte, cache_bits_pde;
4863 boolean_t changed;
4864
4865 base = trunc_page(va);
4866 offset = va & PAGE_MASK;
4867 size = roundup(offset + size, PAGE_SIZE);
4868
4869 /*
4870 * Only supported on kernel virtual addresses above the recursive map.
4871 */
4872 if (base < VM_MIN_KERNEL_ADDRESS)
4873 return (EINVAL);
4874
4875 cache_bits_pde = pmap_cache_bits(mode, 1);
4876 cache_bits_pte = pmap_cache_bits(mode, 0);
4877 changed = FALSE;
4878
4879 /*
4880 * Pages that aren't mapped aren't supported. Also break down
4881 * 2/4MB pages into 4KB pages if required.
4882 */
4883 PMAP_LOCK(kernel_pmap);
4884 for (tmpva = base; tmpva < base + size; ) {
4885 pde = pmap_pde(kernel_pmap, tmpva);
4886 if (*pde == 0) {
4887 PMAP_UNLOCK(kernel_pmap);
4888 return (EINVAL);
4889 }
4890 if (*pde & PG_PS) {
4891 /*
4892 * If the current 2/4MB page already has
4893 * the required memory type, then we need not
4894 * demote this page. Just increment tmpva to
4895 * the next 2/4MB page frame.
4896 */
4897 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) {
4898 tmpva = trunc_4mpage(tmpva) + NBPDR;
4899 continue;
4900 }
4901
4902 /*
4903 * If the current offset aligns with a 2/4MB
4904 * page frame and there is at least 2/4MB left
4905 * within the range, then we need not break
4906 * down this page into 4KB pages.
4907 */
4908 if ((tmpva & PDRMASK) == 0 &&
4909 tmpva + PDRMASK < base + size) {
4910 tmpva += NBPDR;
4911 continue;
4912 }
4913 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) {
4914 PMAP_UNLOCK(kernel_pmap);
4915 return (ENOMEM);
4916 }
4917 }
4918 pte = vtopte(tmpva);
4919 if (*pte == 0) {
4920 PMAP_UNLOCK(kernel_pmap);
4921 return (EINVAL);
4922 }
4923 tmpva += PAGE_SIZE;
4924 }
4925 PMAP_UNLOCK(kernel_pmap);
4926
4927 /*
4928 * Ok, all the pages exist, so run through them updating their
4929 * cache mode if required.
4930 */
4931 for (tmpva = base; tmpva < base + size; ) {
4932 pde = pmap_pde(kernel_pmap, tmpva);
4933 if (*pde & PG_PS) {
4934 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) {
4935 pmap_pde_attr(pde, cache_bits_pde);
4936 changed = TRUE;
4937 }
4938 tmpva = trunc_4mpage(tmpva) + NBPDR;
4939 } else {
4940 pte = vtopte(tmpva);
4941 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) {
4942 pmap_pte_attr(pte, cache_bits_pte);
4943 changed = TRUE;
4944 }
4945 tmpva += PAGE_SIZE;
4946 }
4947 }
4948
4949 /*
4950 * Flush CPU caches to make sure any data isn't cached that
4951 * shouldn't be, etc.
4952 */
4953 if (changed) {
4954 pmap_invalidate_range(kernel_pmap, base, tmpva);
4955 pmap_invalidate_cache_range(base, tmpva);
4956 }
4957 return (0);
4958 }
4959
4960 /*
4961 * perform the pmap work for mincore
4962 */
4963 int
4964 pmap_mincore(pmap_t pmap, vm_offset_t addr)
4965 {
4966 pd_entry_t *pdep;
4967 pt_entry_t *ptep, pte;
4968 vm_paddr_t pa;
4969 vm_page_t m;
4970 int val = 0;
4971
4972 PMAP_LOCK(pmap);
4973 pdep = pmap_pde(pmap, addr);
4974 if (*pdep != 0) {
4975 if (*pdep & PG_PS) {
4976 pte = *pdep;
4977 val = MINCORE_SUPER;
4978 /* Compute the physical address of the 4KB page. */
4979 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) &
4980 PG_FRAME;
4981 } else {
4982 ptep = pmap_pte(pmap, addr);
4983 pte = *ptep;
4984 pmap_pte_release(ptep);
4985 pa = pte & PG_FRAME;
4986 }
4987 } else {
4988 pte = 0;
4989 pa = 0;
4990 }
4991 PMAP_UNLOCK(pmap);
4992
4993 if (pte != 0) {
4994 val |= MINCORE_INCORE;
4995 if ((pte & PG_MANAGED) == 0)
4996 return val;
4997
4998 m = PHYS_TO_VM_PAGE(pa);
4999
5000 /*
5001 * Modified by us
5002 */
5003 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW))
5004 val |= MINCORE_MODIFIED|MINCORE_MODIFIED_OTHER;
5005 else {
5006 /*
5007 * Modified by someone else
5008 */
5009 vm_page_lock_queues();
5010 if (m->dirty || pmap_is_modified(m))
5011 val |= MINCORE_MODIFIED_OTHER;
5012 vm_page_unlock_queues();
5013 }
5014 /*
5015 * Referenced by us
5016 */
5017 if (pte & PG_A)
5018 val |= MINCORE_REFERENCED|MINCORE_REFERENCED_OTHER;
5019 else {
5020 /*
5021 * Referenced by someone else
5022 */
5023 vm_page_lock_queues();
5024 if ((m->flags & PG_REFERENCED) ||
5025 pmap_ts_referenced(m)) {
5026 val |= MINCORE_REFERENCED_OTHER;
5027 vm_page_flag_set(m, PG_REFERENCED);
5028 }
5029 vm_page_unlock_queues();
5030 }
5031 }
5032 return val;
5033 }
5034
5035 void
5036 pmap_activate(struct thread *td)
5037 {
5038 pmap_t pmap, oldpmap;
5039 u_int32_t cr3;
5040
5041 critical_enter();
5042 pmap = vmspace_pmap(td->td_proc->p_vmspace);
5043 oldpmap = PCPU_GET(curpmap);
5044 #if defined(SMP)
5045 atomic_clear_int(&oldpmap->pm_active, PCPU_GET(cpumask));
5046 atomic_set_int(&pmap->pm_active, PCPU_GET(cpumask));
5047 #else
5048 oldpmap->pm_active &= ~1;
5049 pmap->pm_active |= 1;
5050 #endif
5051 #ifdef PAE
5052 cr3 = vtophys(pmap->pm_pdpt);
5053 #else
5054 cr3 = vtophys(pmap->pm_pdir);
5055 #endif
5056 /*
5057 * pmap_activate is for the current thread on the current cpu
5058 */
5059 td->td_pcb->pcb_cr3 = cr3;
5060 load_cr3(cr3);
5061 PCPU_SET(curpmap, pmap);
5062 critical_exit();
5063 }
5064
5065 void
5066 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
5067 {
5068 }
5069
5070 /*
5071 * Increase the starting virtual address of the given mapping if a
5072 * different alignment might result in more superpage mappings.
5073 */
5074 void
5075 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
5076 vm_offset_t *addr, vm_size_t size)
5077 {
5078 vm_offset_t superpage_offset;
5079
5080 if (size < NBPDR)
5081 return;
5082 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
5083 offset += ptoa(object->pg_color);
5084 superpage_offset = offset & PDRMASK;
5085 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR ||
5086 (*addr & PDRMASK) == superpage_offset)
5087 return;
5088 if ((*addr & PDRMASK) < superpage_offset)
5089 *addr = (*addr & ~PDRMASK) + superpage_offset;
5090 else
5091 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
5092 }
5093
5094
5095 #if defined(PMAP_DEBUG)
5096 pmap_pid_dump(int pid)
5097 {
5098 pmap_t pmap;
5099 struct proc *p;
5100 int npte = 0;
5101 int index;
5102
5103 sx_slock(&allproc_lock);
5104 FOREACH_PROC_IN_SYSTEM(p) {
5105 if (p->p_pid != pid)
5106 continue;
5107
5108 if (p->p_vmspace) {
5109 int i,j;
5110 index = 0;
5111 pmap = vmspace_pmap(p->p_vmspace);
5112 for (i = 0; i < NPDEPTD; i++) {
5113 pd_entry_t *pde;
5114 pt_entry_t *pte;
5115 vm_offset_t base = i << PDRSHIFT;
5116
5117 pde = &pmap->pm_pdir[i];
5118 if (pde && pmap_pde_v(pde)) {
5119 for (j = 0; j < NPTEPG; j++) {
5120 vm_offset_t va = base + (j << PAGE_SHIFT);
5121 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) {
5122 if (index) {
5123 index = 0;
5124 printf("\n");
5125 }
5126 sx_sunlock(&allproc_lock);
5127 return npte;
5128 }
5129 pte = pmap_pte(pmap, va);
5130 if (pte && pmap_pte_v(pte)) {
5131 pt_entry_t pa;
5132 vm_page_t m;
5133 pa = *pte;
5134 m = PHYS_TO_VM_PAGE(pa & PG_FRAME);
5135 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x",
5136 va, pa, m->hold_count, m->wire_count, m->flags);
5137 npte++;
5138 index++;
5139 if (index >= 2) {
5140 index = 0;
5141 printf("\n");
5142 } else {
5143 printf(" ");
5144 }
5145 }
5146 }
5147 }
5148 }
5149 }
5150 }
5151 sx_sunlock(&allproc_lock);
5152 return npte;
5153 }
5154 #endif
5155
5156 #if defined(DEBUG)
5157
5158 static void pads(pmap_t pm);
5159 void pmap_pvdump(vm_offset_t pa);
5160
5161 /* print address space of pmap*/
5162 static void
5163 pads(pmap_t pm)
5164 {
5165 int i, j;
5166 vm_paddr_t va;
5167 pt_entry_t *ptep;
5168
5169 if (pm == kernel_pmap)
5170 return;
5171 for (i = 0; i < NPDEPTD; i++)
5172 if (pm->pm_pdir[i])
5173 for (j = 0; j < NPTEPG; j++) {
5174 va = (i << PDRSHIFT) + (j << PAGE_SHIFT);
5175 if (pm == kernel_pmap && va < KERNBASE)
5176 continue;
5177 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS)
5178 continue;
5179 ptep = pmap_pte(pm, va);
5180 if (pmap_pte_v(ptep))
5181 printf("%x:%x ", va, *ptep);
5182 };
5183
5184 }
5185
5186 void
5187 pmap_pvdump(vm_paddr_t pa)
5188 {
5189 pv_entry_t pv;
5190 pmap_t pmap;
5191 vm_page_t m;
5192
5193 printf("pa %x", pa);
5194 m = PHYS_TO_VM_PAGE(pa);
5195 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
5196 pmap = PV_PMAP(pv);
5197 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va);
5198 pads(pmap);
5199 }
5200 printf(" ");
5201 }
5202 #endif
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