1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD: releng/5.3/sys/i386/include/apicvar.h 140341 2005-01-16 08:29:13Z kensmith $
30 */
31
32 #ifndef _MACHINE_APICVAR_H_
33 #define _MACHINE_APICVAR_H_
34
35 /*
36 * Local && I/O APIC variable definitions.
37 */
38
39 /*
40 * Layout of local APIC interrupt vectors:
41 *
42 * 0xff (255) +-------------+
43 * | | 15 (Spurious / IPIs / Local Interrupts)
44 * 0xf0 (240) +-------------+
45 * | | 14 (I/O Interrupts)
46 * 0xe0 (224) +-------------+
47 * | | 13 (I/O Interrupts)
48 * 0xd0 (208) +-------------+
49 * | | 12 (I/O Interrupts)
50 * 0xc0 (192) +-------------+
51 * | | 11 (I/O Interrupts)
52 * 0xb0 (176) +-------------+
53 * | | 10 (I/O Interrupts)
54 * 0xa0 (160) +-------------+
55 * | | 9 (I/O Interrupts)
56 * 0x90 (144) +-------------+
57 * | | 8 (I/O Interrupts / System Calls)
58 * 0x80 (128) +-------------+
59 * | | 7 (I/O Interrupts)
60 * 0x70 (112) +-------------+
61 * | | 6 (I/O Interrupts)
62 * 0x60 (96) +-------------+
63 * | | 5 (I/O Interrupts)
64 * 0x50 (80) +-------------+
65 * | | 4 (I/O Interrupts)
66 * 0x40 (64) +-------------+
67 * | | 3 (I/O Interrupts)
68 * 0x30 (48) +-------------+
69 * | | 2 (ATPIC Interrupts)
70 * 0x20 (32) +-------------+
71 * | | 1 (Exceptions, traps, faults, etc.)
72 * 0x10 (16) +-------------+
73 * | | 0 (Exceptions, traps, faults, etc.)
74 * 0x00 (0) +-------------+
75 *
76 * Note: 0x80 needs to be handled specially and not allocated to an
77 * I/O device!
78 */
79
80 #define APIC_ID_ALL 0xff
81 #define APIC_IO_INTS (IDT_IO_INTS + 16)
82 #define APIC_NUM_IOINTS 192
83
84 /*
85 ********************* !!! WARNING !!! ******************************
86 * Each local apic has an interrupt receive fifo that is two entries deep
87 * for each interrupt priority class (higher 4 bits of interrupt vector).
88 * Once the fifo is full the APIC can no longer receive interrupts for this
89 * class and sending IPIs from other CPUs will be blocked.
90 * To avoid deadlocks there should be no more than two IPI interrupts
91 * pending at the same time.
92 * Currently this is guaranteed by dividing the IPIs in two groups that have
93 * each at most one IPI interrupt pending. The first group is protected by the
94 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user
95 * at a time) The second group uses a single interrupt and a bitmap to avoid
96 * redundant IPI interrupts.
97 *
98 * Right now IPI_STOP used by kdb shares the interrupt priority class with
99 * the two IPI groups mentioned above. As such IPI_STOP may cause a deadlock.
100 * Eventually IPI_STOP should use NMI IPIs - this would eliminate this and
101 * other deadlocks caused by IPI_STOP.
102 */
103
104 #define APIC_LOCAL_INTS 240
105
106 #if 0
107 #define APIC_TIMER_INT (APIC_LOCAL_INTS + X)
108 #define APIC_ERROR_INT (APIC_LOCAL_INTS + X)
109 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + X)
110 #endif
111
112 #define APIC_IPI_INTS (APIC_LOCAL_INTS + 0)
113 #define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */
114 #define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */
115 #define IPI_INVLPG (APIC_IPI_INTS + 2)
116 #define IPI_INVLRNG (APIC_IPI_INTS + 3)
117 #define IPI_LAZYPMAP (APIC_IPI_INTS + 4) /* Lazy pmap release. */
118 /* Vector to handle bitmap based IPIs */
119 #define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 5)
120
121 /* IPIs handled by IPI_BITMAPED_VECTOR (XXX ups is there a better place?) */
122 #define IPI_AST 0 /* Generate software trap. */
123 #define IPI_HARDCLOCK 1 /* Inter-CPU clock handling. */
124 #define IPI_STATCLOCK 2
125 #define IPI_BITMAP_LAST IPI_STATCLOCK
126 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
127
128 #define IPI_STOP (APIC_IPI_INTS + 6) /* Stop CPU until restarted. */
129
130 /* The spurious interrupt can share the priority class with the IPIs since
131 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo)
132 */
133 #define APIC_SPURIOUS_INT 255
134
135 #define LVT_LINT0 0
136 #define LVT_LINT1 1
137 #define LVT_TIMER 2
138 #define LVT_ERROR 3
139 #define LVT_PMC 4
140 #define LVT_THERMAL 5
141 #define LVT_MAX LVT_THERMAL
142
143 #ifndef LOCORE
144
145 #define APIC_IPI_DEST_SELF -1
146 #define APIC_IPI_DEST_ALL -2
147 #define APIC_IPI_DEST_OTHERS -3
148
149 #define APIC_BUS_UNKNOWN -1
150 #define APIC_BUS_ISA 0
151 #define APIC_BUS_EISA 1
152 #define APIC_BUS_PCI 2
153 #define APIC_BUS_MAX APIC_BUS_PCI
154
155 /*
156 * An APIC enumerator is a psuedo bus driver that enumerates APIC's including
157 * CPU's and I/O APIC's.
158 */
159 struct apic_enumerator {
160 const char *apic_name;
161 int (*apic_probe)(void);
162 int (*apic_probe_cpus)(void);
163 int (*apic_setup_local)(void);
164 int (*apic_setup_io)(void);
165 SLIST_ENTRY(apic_enumerator) apic_next;
166 };
167
168 inthand_t
169 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
170 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
171 IDTVEC(apic_isr7), IDTVEC(spuriousint);
172
173 u_int apic_irq_to_idt(u_int irq);
174 u_int apic_idt_to_irq(u_int vector);
175 void apic_register_enumerator(struct apic_enumerator *enumerator);
176 void *ioapic_create(uintptr_t addr, int32_t id, int intbase);
177 int ioapic_disable_pin(void *cookie, u_int pin);
178 void ioapic_enable_mixed_mode(void);
179 int ioapic_get_vector(void *cookie, u_int pin);
180 int ioapic_next_logical_cluster(void);
181 void ioapic_register(void *cookie);
182 int ioapic_remap_vector(void *cookie, u_int pin, int vector);
183 int ioapic_set_bus(void *cookie, u_int pin, int bus_type);
184 int ioapic_set_extint(void *cookie, u_int pin);
185 int ioapic_set_nmi(void *cookie, u_int pin);
186 int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol);
187 int ioapic_set_triggermode(void *cookie, u_int pin,
188 enum intr_trigger trigger);
189 int ioapic_set_smi(void *cookie, u_int pin);
190 void lapic_create(u_int apic_id, int boot_cpu);
191 void lapic_disable(void);
192 void lapic_dump(const char *str);
193 void lapic_enable_intr(u_int vector);
194 void lapic_eoi(void);
195 int lapic_id(void);
196 void lapic_init(uintptr_t addr);
197 int lapic_intr_pending(u_int vector);
198 void lapic_ipi_raw(register_t icrlo, u_int dest);
199 void lapic_ipi_vectored(u_int vector, int dest);
200 int lapic_ipi_wait(int delay);
201 void lapic_handle_intr(struct intrframe frame);
202 void lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id);
203 int lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked);
204 int lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode);
205 int lapic_set_lvt_polarity(u_int apic_id, u_int lvt,
206 enum intr_polarity pol);
207 int lapic_set_lvt_triggermode(u_int apic_id, u_int lvt,
208 enum intr_trigger trigger);
209 void lapic_setup(void);
210
211 #endif /* !LOCORE */
212 #endif /* _MACHINE_APICVAR_H_ */
Cache object: 482ee2946e8403fce0062bc62d13c7ab
|