The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/include/apicvar.h

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    1 /*-
    2  * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. Neither the name of the author nor the names of any co-contributors
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  * $FreeBSD$
   30  */
   31 
   32 #ifndef _MACHINE_APICVAR_H_
   33 #define _MACHINE_APICVAR_H_
   34 
   35 /*
   36  * Local && I/O APIC variable definitions.
   37  */
   38 
   39 /*
   40  * Layout of local APIC interrupt vectors:
   41  *
   42  *      0xff (255)  +-------------+
   43  *                  |             | 15 (Spurious / IPIs / Local Interrupts)
   44  *      0xf0 (240)  +-------------+
   45  *                  |             | 14 (I/O Interrupts / Timer)
   46  *      0xe0 (224)  +-------------+
   47  *                  |             | 13 (I/O Interrupts)
   48  *      0xd0 (208)  +-------------+
   49  *                  |             | 12 (I/O Interrupts)
   50  *      0xc0 (192)  +-------------+
   51  *                  |             | 11 (I/O Interrupts)
   52  *      0xb0 (176)  +-------------+
   53  *                  |             | 10 (I/O Interrupts)
   54  *      0xa0 (160)  +-------------+
   55  *                  |             | 9 (I/O Interrupts)
   56  *      0x90 (144)  +-------------+
   57  *                  |             | 8 (I/O Interrupts / System Calls)
   58  *      0x80 (128)  +-------------+
   59  *                  |             | 7 (I/O Interrupts)
   60  *      0x70 (112)  +-------------+
   61  *                  |             | 6 (I/O Interrupts)
   62  *      0x60 (96)   +-------------+
   63  *                  |             | 5 (I/O Interrupts)
   64  *      0x50 (80)   +-------------+
   65  *                  |             | 4 (I/O Interrupts)
   66  *      0x40 (64)   +-------------+
   67  *                  |             | 3 (I/O Interrupts)
   68  *      0x30 (48)   +-------------+
   69  *                  |             | 2 (ATPIC Interrupts)
   70  *      0x20 (32)   +-------------+
   71  *                  |             | 1 (Exceptions, traps, faults, etc.)
   72  *      0x10 (16)   +-------------+
   73  *                  |             | 0 (Exceptions, traps, faults, etc.)
   74  *      0x00 (0)    +-------------+
   75  *
   76  * Note: 0x80 needs to be handled specially and not allocated to an
   77  * I/O device!
   78  */
   79 
   80 #define MAX_APIC_ID     0xfe
   81 #define APIC_ID_ALL     0xff
   82 
   83 /* I/O Interrupts are used for external devices such as ISA, PCI, etc. */
   84 #define APIC_IO_INTS    (IDT_IO_INTS + 16)
   85 #define APIC_NUM_IOINTS 191
   86 
   87 /* The timer interrupt is used for clock handling and drives hardclock, etc. */
   88 #define APIC_TIMER_INT  (APIC_IO_INTS + APIC_NUM_IOINTS)
   89 
   90 /*  
   91  ********************* !!! WARNING !!! ******************************
   92  * Each local apic has an interrupt receive fifo that is two entries deep
   93  * for each interrupt priority class (higher 4 bits of interrupt vector).
   94  * Once the fifo is full the APIC can no longer receive interrupts for this
   95  * class and sending IPIs from other CPUs will be blocked.
   96  * To avoid deadlocks there should be no more than two IPI interrupts
   97  * pending at the same time.
   98  * Currently this is guaranteed by dividing the IPIs in two groups that have 
   99  * each at most one IPI interrupt pending. The first group is protected by the
  100  * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user 
  101  * at a time) The second group uses a single interrupt and a bitmap to avoid
  102  * redundant IPI interrupts.
  103  */ 
  104 
  105 /* Interrupts for local APIC LVT entries other than the timer. */
  106 #ifdef XEN
  107 /* These are the Xen i386 APIC definitions */
  108 #define APIC_LOCAL_INTS 240
  109 #define APIC_ERROR_INT  APIC_LOCAL_INTS
  110 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
  111 #define APIC_CMC_INT    (APIC_LOCAL_INTS + 2)
  112 #define APIC_IPI_INTS   (APIC_LOCAL_INTS + 3)
  113 
  114 #define IPI_RENDEZVOUS          (APIC_IPI_INTS) /* Inter-CPU rendezvous. */
  115 #define IPI_INVLTLB             (APIC_IPI_INTS + 1)     /* TLB Shootdown IPIs */
  116 #define IPI_INVLPG              (APIC_IPI_INTS + 2)
  117 #define IPI_INVLRNG             (APIC_IPI_INTS + 3)
  118 #define IPI_INVLCACHE           (APIC_IPI_INTS + 4)
  119 #define IPI_LAZYPMAP            (APIC_IPI_INTS + 5)     /* Lazy pmap release. */
  120 /* Vector to handle bitmap based IPIs */
  121 #define IPI_BITMAP_VECTOR       (APIC_IPI_INTS + 6)
  122 
  123 /* IPIs handled by IPI_BITMAPED_VECTOR  (XXX ups is there a better place?) */
  124 #define IPI_AST         0       /* Generate software trap. */
  125 #define IPI_PREEMPT     1
  126 #define IPI_HARDCLOCK   2 
  127 #define IPI_STATCLOCK   3 
  128 #define IPI_PROFCLOCK   4 
  129 #define IPI_BITMAP_LAST IPI_PROFCLOCK
  130 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
  131 
  132 #define IPI_STOP        (APIC_IPI_INTS + 7)     /* Stop CPU until restarted. */
  133 #define IPI_STOP_HARD   (APIC_IPI_INTS + 8)     /* Stop CPU with a NMI. */
  134 
  135 #else /* XEN */
  136 /* These are the normal i386 APIC definitions */
  137 #define APIC_LOCAL_INTS 240
  138 #define APIC_ERROR_INT  APIC_LOCAL_INTS
  139 #define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1)
  140 #define APIC_CMC_INT    (APIC_LOCAL_INTS + 2)
  141 #define APIC_IPI_INTS   (APIC_LOCAL_INTS + 3)
  142 
  143 #define IPI_RENDEZVOUS  (APIC_IPI_INTS)         /* Inter-CPU rendezvous. */
  144 #define IPI_INVLTLB     (APIC_IPI_INTS + 1)     /* TLB Shootdown IPIs */
  145 #define IPI_INVLPG      (APIC_IPI_INTS + 2)
  146 #define IPI_INVLRNG     (APIC_IPI_INTS + 3)
  147 #define IPI_INVLCACHE   (APIC_IPI_INTS + 4)
  148 #define IPI_LAZYPMAP    (APIC_IPI_INTS + 5)     /* Lazy pmap release. */
  149 /* Vector to handle bitmap based IPIs */
  150 #define IPI_BITMAP_VECTOR       (APIC_IPI_INTS + 6) 
  151 
  152 /* IPIs handled by IPI_BITMAPED_VECTOR  (XXX ups is there a better place?) */
  153 #define IPI_AST         0       /* Generate software trap. */
  154 #define IPI_PREEMPT     1
  155 #define IPI_HARDCLOCK   2 
  156 #define IPI_STATCLOCK   3 
  157 #define IPI_PROFCLOCK   4 
  158 #define IPI_BITMAP_LAST IPI_PROFCLOCK
  159 #define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST)
  160 
  161 #define IPI_STOP        (APIC_IPI_INTS + 7)     /* Stop CPU until restarted. */
  162 #define IPI_STOP_HARD   (APIC_IPI_INTS + 8)     /* Stop CPU with a NMI. */
  163 #endif /* XEN */
  164 
  165 /*
  166  * The spurious interrupt can share the priority class with the IPIs since
  167  * it is not a normal interrupt. (Does not use the APIC's interrupt fifo)
  168  */
  169 #define APIC_SPURIOUS_INT 255
  170 
  171 #define LVT_LINT0       0
  172 #define LVT_LINT1       1
  173 #define LVT_TIMER       2
  174 #define LVT_ERROR       3
  175 #define LVT_PMC         4
  176 #define LVT_THERMAL     5
  177 #define LVT_CMCI        6
  178 #define LVT_MAX         LVT_CMCI
  179 
  180 #ifndef LOCORE
  181 
  182 #define APIC_IPI_DEST_SELF      -1
  183 #define APIC_IPI_DEST_ALL       -2
  184 #define APIC_IPI_DEST_OTHERS    -3
  185 
  186 #define APIC_BUS_UNKNOWN        -1
  187 #define APIC_BUS_ISA            0
  188 #define APIC_BUS_EISA           1
  189 #define APIC_BUS_PCI            2
  190 #define APIC_BUS_MAX            APIC_BUS_PCI
  191 
  192 enum lapic_clock {
  193         LAPIC_CLOCK_NONE,
  194         LAPIC_CLOCK_HARDCLOCK,
  195         LAPIC_CLOCK_ALL
  196 };
  197 
  198 /*
  199  * An APIC enumerator is a psuedo bus driver that enumerates APIC's including
  200  * CPU's and I/O APIC's.
  201  */
  202 struct apic_enumerator {
  203         const char *apic_name;
  204         int (*apic_probe)(void);
  205         int (*apic_probe_cpus)(void);
  206         int (*apic_setup_local)(void);
  207         int (*apic_setup_io)(void);
  208         SLIST_ENTRY(apic_enumerator) apic_next;
  209 };
  210 
  211 inthand_t
  212         IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3),
  213         IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6),
  214         IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint),
  215         IDTVEC(spuriousint), IDTVEC(timerint);
  216 
  217 extern vm_paddr_t lapic_paddr;
  218 extern int apic_cpuids[];
  219 
  220 u_int   apic_alloc_vector(u_int apic_id, u_int irq);
  221 u_int   apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count,
  222             u_int align);
  223 void    apic_disable_vector(u_int apic_id, u_int vector);
  224 void    apic_enable_vector(u_int apic_id, u_int vector);
  225 void    apic_free_vector(u_int apic_id, u_int vector, u_int irq);
  226 u_int   apic_idt_to_irq(u_int apic_id, u_int vector);
  227 void    apic_register_enumerator(struct apic_enumerator *enumerator);
  228 u_int   apic_cpuid(u_int apic_id);
  229 void    *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase);
  230 int     ioapic_disable_pin(void *cookie, u_int pin);
  231 int     ioapic_get_vector(void *cookie, u_int pin);
  232 void    ioapic_register(void *cookie);
  233 int     ioapic_remap_vector(void *cookie, u_int pin, int vector);
  234 int     ioapic_set_bus(void *cookie, u_int pin, int bus_type);
  235 int     ioapic_set_extint(void *cookie, u_int pin);
  236 int     ioapic_set_nmi(void *cookie, u_int pin);
  237 int     ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol);
  238 int     ioapic_set_triggermode(void *cookie, u_int pin,
  239             enum intr_trigger trigger);
  240 int     ioapic_set_smi(void *cookie, u_int pin);
  241 void    lapic_create(u_int apic_id, int boot_cpu);
  242 void    lapic_disable(void);
  243 void    lapic_disable_pmc(void);
  244 void    lapic_dump(const char *str);
  245 void    lapic_enable_cmc(void);
  246 int     lapic_enable_pmc(void);
  247 void    lapic_eoi(void);
  248 int     lapic_id(void);
  249 void    lapic_init(vm_paddr_t addr);
  250 int     lapic_intr_pending(u_int vector);
  251 void    lapic_ipi_raw(register_t icrlo, u_int dest);
  252 void    lapic_ipi_vectored(u_int vector, int dest);
  253 int     lapic_ipi_wait(int delay);
  254 void    lapic_handle_cmc(void);
  255 void    lapic_handle_error(void);
  256 void    lapic_handle_intr(int vector, struct trapframe *frame);
  257 void    lapic_handle_timer(struct trapframe *frame);
  258 void    lapic_reenable_pmc(void);
  259 void    lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id);
  260 int     lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked);
  261 int     lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode);
  262 int     lapic_set_lvt_polarity(u_int apic_id, u_int lvt,
  263             enum intr_polarity pol);
  264 int     lapic_set_lvt_triggermode(u_int apic_id, u_int lvt,
  265             enum intr_trigger trigger);
  266 void    lapic_set_tpr(u_int vector);
  267 void    lapic_setup(int boot);
  268 enum lapic_clock        lapic_setup_clock(enum lapic_clock srcsdes);
  269 
  270 #endif /* !LOCORE */
  271 #endif /* _MACHINE_APICVAR_H_ */

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