1 /*
2 * Defines for Cronyx-Sigma adapter driver.
3 *
4 * Copyright (C) 1994 Cronyx Ltd.
5 * Author: Serge Vakulenko, <vak@zebub.msk.su>
6 *
7 * This software is distributed with NO WARRANTIES, not even the implied
8 * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
9 *
10 * Authors grant any other persons or organizations permission to use
11 * or modify this software as long as this message is kept with the software,
12 * all derivative works or modified versions.
13 *
14 * Version 1.9, Wed Oct 4 18:58:15 MSK 1995
15 */
16 /*
17 * Asynchronous channel mode -------------------------------------------------
18 */
19
20 /* Parity */
21 #define PAR_EVEN 0 /* even parity */
22 #define PAR_ODD 1 /* odd parity */
23
24 /* Parity mode */
25 #define PARM_NOPAR 0 /* no parity */
26 #define PARM_FORCE 1 /* force parity (odd = force 1, even = 0) */
27 #define PARM_NORMAL 2 /* normal parity */
28
29 /* Flow control transparency mode */
30 #define FLOWCC_PASS 0 /* pass flow ctl chars as exceptions */
31 #define FLOWCC_NOTPASS 1 /* don't pass flow ctl chars to the host */
32
33 /* Stop bit length */
34 #define STOPB_1 2 /* 1 stop bit */
35 #define STOPB_15 3 /* 1.5 stop bits */
36 #define STOPB_2 4 /* 2 stop bits */
37
38 /* Action on break condition */
39 #define BRK_INTR 0 /* generate an exception interrupt */
40 #define BRK_NULL 1 /* translate to a NULL character */
41 #define BRK_RESERVED 2 /* reserved */
42 #define BRK_DISCARD 3 /* discard character */
43
44 /* Parity/framing error actions */
45 #define PERR_INTR 0 /* generate an exception interrupt */
46 #define PERR_NULL 1 /* translate to a NULL character */
47 #define PERR_IGNORE 2 /* ignore error; char passed as good data */
48 #define PERR_DISCARD 3 /* discard error character */
49 #define PERR_FFNULL 5 /* translate to FF NULL char */
50
51 typedef struct { /* async channel option register 1 */
52 unsigned charlen : 4; /* character length, 5..8 */
53 unsigned ignpar : 1; /* ignore parity */
54 unsigned parmode : 2; /* parity mode */
55 unsigned parity : 1; /* parity */
56 } cx_cor1_async_t;
57
58 typedef struct { /* async channel option register 2 */
59 unsigned dsrae : 1; /* DSR automatic enable */
60 unsigned ctsae : 1; /* CTS automatic enable */
61 unsigned rtsao : 1; /* RTS automatic output enable */
62 unsigned rlm : 1; /* remote loopback mode enable */
63 unsigned zero : 1;
64 unsigned etc : 1; /* embedded transmitter cmd enable */
65 unsigned ixon : 1; /* in-band XON/XOFF enable */
66 unsigned ixany : 1; /* XON on any character */
67 } cx_cor2_async_t;
68
69 typedef struct { /* async channel option register 3 */
70 unsigned stopb : 3; /* stop bit length */
71 unsigned zero : 1;
72 unsigned scde : 1; /* special char detection enable */
73 unsigned flowct : 1; /* flow control transparency mode */
74 unsigned rngde : 1; /* range detect enable */
75 unsigned escde : 1; /* extended spec. char detect enable */
76 } cx_cor3_async_t;
77
78 typedef struct { /* async channel option register 6 */
79 unsigned parerr : 3; /* parity/framing error actions */
80 unsigned brk : 2; /* action on break condition */
81 unsigned inlcr : 1; /* translate NL to CR on input */
82 unsigned icrnl : 1; /* translate CR to NL on input */
83 unsigned igncr : 1; /* discard CR on input */
84 } cx_cor6_async_t;
85
86 typedef struct { /* async channel option register 7 */
87 unsigned ocrnl : 1; /* translate CR to NL on output */
88 unsigned onlcr : 1; /* translate NL to CR on output */
89 unsigned zero : 3;
90 unsigned fcerr : 1; /* process flow ctl err chars enable */
91 unsigned lnext : 1; /* LNext option enable */
92 unsigned istrip : 1; /* strip 8-bit on input */
93 } cx_cor7_async_t;
94
95 typedef struct { /* async channel options */
96 cx_cor1_async_t cor1; /* channel option register 1 */
97 cx_cor2_async_t cor2; /* channel option register 2 */
98 cx_cor3_async_t cor3; /* option register 3 */
99 cx_cor6_async_t cor6; /* channel option register 6 */
100 cx_cor7_async_t cor7; /* channel option register 7 */
101 unsigned char schr1; /* special character register 1 (XON) */
102 unsigned char schr2; /* special character register 2 (XOFF) */
103 unsigned char schr3; /* special character register 3 */
104 unsigned char schr4; /* special character register 4 */
105 unsigned char scrl; /* special character range low */
106 unsigned char scrh; /* special character range high */
107 unsigned char lnxt; /* LNext character */
108 } cx_opt_async_t;
109
110 /*
111 * HDLC channel mode ---------------------------------------------------------
112 */
113 /* Address field length option */
114 #define AFLO_1OCT 0 /* address field is 1 octet in length */
115 #define AFLO_2OCT 1 /* address field is 2 octet in length */
116
117 /* Clear detect for X.21 data transfer phase */
118 #define CLRDET_DISABLE 0 /* clear detect disabled */
119 #define CLRDET_ENABLE 1 /* clear detect enabled */
120
121 /* Addressing mode */
122 #define ADMODE_NOADDR 0 /* no address */
123 #define ADMODE_4_1 1 /* 4 * 1 byte */
124 #define ADMODE_2_2 2 /* 2 * 2 byte */
125
126 /* FCS append */
127 #define FCS_NOTPASS 0 /* receive CRC is not passed to the host */
128 #define FCS_PASS 1 /* receive CRC is passed to the host */
129
130 /* CRC modes */
131 #define CRC_INVERT 0 /* CRC is transmitted inverted (CRC V.41) */
132 #define CRC_DONT_INVERT 1 /* CRC is not transmitted inverted (CRC-16) */
133
134 /* Send sync pattern */
135 #define SYNC_00 0 /* send 00h as pad char (NRZI encoding) */
136 #define SYNC_AA 1 /* send AAh (Manchester/NRZ encoding) */
137
138 /* FCS preset */
139 #define FCSP_ONES 0 /* FCS is preset to all ones (CRC V.41) */
140 #define FCSP_ZEROS 1 /* FCS is preset to all zeros (CRC-16) */
141
142 /* idle mode */
143 #define IDLE_FLAG 0 /* idle in flag */
144 #define IDLE_MARK 1 /* idle in mark */
145
146 /* CRC polynomial select */
147 #define POLY_V41 0 /* x^16+x^12+x^5+1 (HDLC, preset to 1) */
148 #define POLY_16 1 /* x^16+x^15+x^2+1 (bisync, preset to 0) */
149
150 typedef struct { /* hdlc channel option register 1 */
151 unsigned ifflags : 4; /* number of inter-frame flags sent */
152 unsigned admode : 2; /* addressing mode */
153 unsigned clrdet : 1; /* clear detect for X.21 data transfer phase */
154 unsigned aflo : 1; /* address field length option */
155 } cx_cor1_hdlc_t;
156
157 typedef struct { /* hdlc channel option register 2 */
158 unsigned dsrae : 1; /* DSR automatic enable */
159 unsigned ctsae : 1; /* CTS automatic enable */
160 unsigned rtsao : 1; /* RTS automatic output enable */
161 unsigned zero1 : 1;
162 unsigned crcninv : 1; /* CRC inversion option */
163 unsigned zero2 : 1;
164 unsigned fcsapd : 1; /* FCS append */
165 unsigned zero3 : 1;
166 } cx_cor2_hdlc_t;
167
168 typedef struct { /* hdlc channel option register 3 */
169 unsigned padcnt : 3; /* pad character count */
170 unsigned idle : 1; /* idle mode */
171 unsigned nofcs : 1; /* FCS disable */
172 unsigned fcspre : 1; /* FCS preset */
173 unsigned syncpat : 1; /* send sync pattern */
174 unsigned sndpad : 1; /* send pad characters before flag enable */
175 } cx_cor3_hdlc_t;
176
177 typedef struct { /* hdlc channel options */
178 cx_cor1_hdlc_t cor1; /* hdlc channel option register 1 */
179 cx_cor2_hdlc_t cor2; /* hdlc channel option register 2 */
180 cx_cor3_hdlc_t cor3; /* hdlc channel option register 3 */
181 unsigned char rfar1; /* receive frame address register 1 */
182 unsigned char rfar2; /* receive frame address register 2 */
183 unsigned char rfar3; /* receive frame address register 3 */
184 unsigned char rfar4; /* receive frame address register 4 */
185 unsigned char cpsr; /* CRC polynomial select */
186 } cx_opt_hdlc_t;
187
188 /*
189 * BISYNC channel mode -------------------------------------------------------
190 */
191
192 /* Longitudinal redundancy check */
193 #define BCC_CRC16 0 /* CRC16 is used for BCC */
194 #define BCC_LRC 1 /* LRC is used for BCC */
195
196 /* Send pad pattern */
197 #define PAD_AA 0 /* send AAh as pad character */
198 #define PAD_55 1 /* send 55h as pad character */
199
200 typedef struct { /* channel option register 1 */
201 unsigned charlen : 4; /* character length, 5..8 */
202 unsigned ignpar : 1; /* ignore parity */
203 unsigned parmode : 2; /* parity mode */
204 unsigned parity : 1; /* parity */
205 } cx_cor1_bisync_t;
206
207 typedef struct { /* channel option register 2 */
208 unsigned syns : 4; /* number of extra SYN chars before a frame */
209 unsigned crcninv : 1; /* CRC inversion option */
210 unsigned ebcdic : 1; /* use EBCDIC as char set (instead of ASCII) */
211 unsigned bcc : 1; /* BCC append enable */
212 unsigned lrc : 1; /* longitudinal redundancy check */
213 } cx_cor2_bisync_t;
214
215 typedef struct { /* channel option register 3 */
216 unsigned padcnt : 3; /* pad character count */
217 unsigned idle : 1; /* idle mode */
218 unsigned nofcs : 1; /* FCS disable */
219 unsigned fcspre : 1; /* FCS preset */
220 unsigned padpat : 1; /* send pad pattern */
221 unsigned sndpad : 1; /* send pad characters before SYN enable */
222 } cx_cor3_bisync_t;
223
224 typedef struct { /* channel option register 6 */
225 unsigned char specterm; /* special termination character */
226 } cx_cor6_bisync_t;
227
228 typedef struct { /* bisync channel options */
229 cx_cor1_bisync_t cor1; /* channel option register 1 */
230 cx_cor2_bisync_t cor2; /* channel option register 2 */
231 cx_cor3_bisync_t cor3; /* channel option register 3 */
232 cx_cor6_bisync_t cor6; /* channel option register 6 */
233 unsigned char cpsr; /* CRC polynomial select */
234 } cx_opt_bisync_t;
235
236 /*
237 * X.21 channel mode ---------------------------------------------------------
238 */
239
240 /* The number of SYN chars on receive */
241 #define X21SYN_2 0 /* two SYN characters are required */
242 #define X21SYN_1 1 /* one SYN character is required */
243
244 typedef struct { /* channel option register 1 */
245 unsigned charlen : 4; /* character length, 5..8 */
246 unsigned ignpar : 1; /* ignore parity */
247 unsigned parmode : 2; /* parity mode */
248 unsigned parity : 1; /* parity */
249 } cx_cor1_x21_t;
250
251 typedef struct { /* channel option register 2 */
252 unsigned zero1 : 5;
253 unsigned etc : 1; /* embedded transmitter command enable */
254 unsigned zero2 : 2;
255 } cx_cor2_x21_t;
256
257 typedef struct { /* channel option register 3 */
258 unsigned zero : 4;
259 unsigned scde : 1; /* special character detect enable */
260 unsigned stripsyn : 1; /* treat SYN chars as special condition */
261 unsigned ssde : 1; /* steady state detect enable */
262 unsigned syn : 1; /* the number of SYN chars on receive */
263 } cx_cor3_x21_t;
264
265 typedef struct { /* channel option register 6 */
266 unsigned char synchar; /* syn character */
267 } cx_cor6_x21_t;
268
269 typedef struct { /* x21 channel options */
270 cx_cor1_x21_t cor1; /* channel option register 1 */
271 cx_cor2_x21_t cor2; /* channel option register 2 */
272 cx_cor3_x21_t cor3; /* channel option register 3 */
273 cx_cor6_x21_t cor6; /* channel option register 6 */
274 unsigned char schr1; /* special character register 1 */
275 unsigned char schr2; /* special character register 2 */
276 unsigned char schr3; /* special character register 3 */
277 } cx_opt_x21_t;
278
279 /*
280 * CD2400 channel state structure --------------------------------------------
281 */
282
283 /* Signal encoding */
284 #define ENCOD_NRZ 0 /* NRZ mode */
285 #define ENCOD_NRZI 1 /* NRZI mode */
286 #define ENCOD_MANCHESTER 2 /* Manchester mode */
287
288 /* Clock source */
289 #define CLK_0 0 /* clock 0 */
290 #define CLK_1 1 /* clock 1 */
291 #define CLK_2 2 /* clock 2 */
292 #define CLK_3 3 /* clock 3 */
293 #define CLK_4 4 /* clock 4 */
294 #define CLK_EXT 6 /* external clock */
295 #define CLK_RCV 7 /* receive clock */
296
297 /* Channel type */
298 #define T_NONE 0 /* no channel */
299 #define T_ASYNC 1 /* pure asynchronous RS-232 channel */
300 #define T_SYNC_RS232 2 /* pure synchronous RS-232 channel */
301 #define T_SYNC_V35 3 /* pure synchronous V.35 channel */
302 #define T_SYNC_RS449 4 /* pure synchronous RS-449 channel */
303 #define T_UNIV_RS232 5 /* sync/async RS-232 channel */
304 #define T_UNIV_RS449 6 /* sync/async RS-232/RS-449 channel */
305 #define T_UNIV_V35 7 /* sync/async RS-232/V.35 channel */
306
307 typedef enum { /* channel mode */
308 M_ASYNC, /* asynchronous mode */
309 M_HDLC, /* HDLC mode */
310 M_BISYNC, /* BISYNC mode */
311 M_X21 /* X.21 mode */
312 } cx_chan_mode_t;
313
314 typedef struct { /* channel option register 4 */
315 unsigned thr : 4; /* FIFO threshold */
316 unsigned zero : 1;
317 unsigned cts_zd : 1; /* detect 1 to 0 transition on the CTS */
318 unsigned cd_zd : 1; /* detect 1 to 0 transition on the CD */
319 unsigned dsr_zd : 1; /* detect 1 to 0 transition on the DSR */
320 } cx_cor4_t;
321
322 typedef struct { /* channel option register 5 */
323 unsigned rx_thr : 4; /* receive flow control FIFO threshold */
324 unsigned zero : 1;
325 unsigned cts_od : 1; /* detect 0 to 1 transition on the CTS */
326 unsigned cd_od : 1; /* detect 0 to 1 transition on the CD */
327 unsigned dsr_od : 1; /* detect 0 to 1 transition on the DSR */
328 } cx_cor5_t;
329
330 typedef struct { /* receive clock option register */
331 unsigned clk : 3; /* receive clock source */
332 unsigned encod : 2; /* signal encoding NRZ/NRZI/Manchester */
333 unsigned dpll : 1; /* DPLL enable */
334 unsigned zero : 1;
335 unsigned tlval : 1; /* transmit line value */
336 } cx_rcor_t;
337
338 typedef struct { /* transmit clock option register */
339 unsigned zero1 : 1;
340 unsigned llm : 1; /* local loopback mode */
341 unsigned zero2 : 1;
342 unsigned ext1x : 1; /* external 1x clock mode */
343 unsigned zero3 : 1;
344 unsigned clk : 3; /* transmit clock source */
345 } cx_tcor_t;
346
347 typedef struct {
348 cx_cor4_t cor4; /* channel option register 4 */
349 cx_cor5_t cor5; /* channel option register 5 */
350 cx_rcor_t rcor; /* receive clock option register */
351 cx_tcor_t tcor; /* transmit clock option register */
352 } cx_chan_opt_t;
353
354 typedef enum { /* line break mode */
355 BRK_IDLE, /* normal line mode */
356 BRK_SEND, /* start sending break */
357 BRK_STOP /* stop sending break */
358 } cx_break_t;
359
360 typedef struct {
361 unsigned cisco : 1; /* cisco mode */
362 unsigned keepalive : 1; /* keepalive enable */
363 unsigned ext : 1; /* use external ppp implementation */
364 unsigned lock : 1; /* channel locked for use by driver */
365 unsigned norts : 1; /* disable automatic RTS control */
366 } cx_soft_opt_t;
367
368 #define NCHIP 4 /* the number of controllers per board */
369 #define NCHAN 16 /* the number of channels on the board */
370
371 typedef struct {
372 unsigned char board; /* adapter number, 0..2 */
373 unsigned char channel; /* channel number, 0..15 */
374 unsigned char type; /* channel type (read only) */
375 unsigned char iftype; /* chan0 interface RS-232/RS-449/V.35 */
376 unsigned long rxbaud; /* receiver speed */
377 unsigned long txbaud; /* transmitter speed */
378 cx_chan_mode_t mode; /* channel mode */
379 cx_chan_opt_t opt; /* common channel options */
380 cx_opt_async_t aopt; /* async mode options */
381 cx_opt_hdlc_t hopt; /* hdlc mode options */
382 cx_opt_bisync_t bopt; /* bisync mode options */
383 cx_opt_x21_t xopt; /* x.21 mode options */
384 cx_soft_opt_t sopt; /* software options and state flags */
385 char master[16]; /* master interface name or \0 */
386 } cx_options_t; /* user settable options */
387
388 typedef struct _chan_t {
389 unsigned char type; /* channel type */
390 unsigned char num; /* channel number, 0..15 */
391 struct _board_t *board; /* board pointer */
392 struct _chip_t *chip; /* controller pointer */
393 struct _stat_t *stat; /* statistics */
394 unsigned long rxbaud; /* receiver speed */
395 unsigned long txbaud; /* transmitter speed */
396 cx_chan_mode_t mode; /* channel mode */
397 cx_chan_opt_t opt; /* common channel options */
398 cx_opt_async_t aopt; /* async mode options */
399 cx_opt_hdlc_t hopt; /* hdlc mode options */
400 cx_opt_bisync_t bopt; /* bisync mode options */
401 cx_opt_x21_t xopt; /* x.21 mode options */
402 unsigned char *arbuf; /* receiver A dma buffer */
403 unsigned char *brbuf; /* receiver B dma buffer */
404 unsigned char *atbuf; /* transmitter A dma buffer */
405 unsigned char *btbuf; /* transmitter B dma buffer */
406 unsigned long arphys; /* receiver A phys address */
407 unsigned long brphys; /* receiver B phys address */
408 unsigned long atphys; /* transmitter A phys address */
409 unsigned long btphys; /* transmitter B phys address */
410 unsigned char dtr; /* DTR signal value */
411 unsigned char rts; /* RTS signal value */
412 #ifdef KERNEL
413 struct tty *ttyp; /* tty structure pointer */
414 struct ifnet *ifp; /* network interface data */
415 struct ifnet *master; /* master interface, or ==ifp */
416 struct _chan_t *slaveq; /* slave queue pointer, or NULL */
417 cx_soft_opt_t sopt; /* software options and state flags */
418 cx_break_t brk; /* line break mode */
419 #ifdef __bsdi__
420 struct ttydevice_tmp *ttydev; /* tty statistics structure */
421 #endif
422 #endif
423 } cx_chan_t;
424
425 typedef struct _chip_t {
426 unsigned short port; /* base port address, or 0 if no chip */
427 unsigned char num; /* controller number, 0..3 */
428 struct _board_t *board; /* board pointer */
429 unsigned long oscfreq; /* oscillator frequency in Hz */
430 } cx_chip_t;
431
432 typedef struct _stat_t {
433 unsigned char board; /* adapter number, 0..2 */
434 unsigned char channel; /* channel number, 0..15 */
435 unsigned long rintr; /* receive interrupts */
436 unsigned long tintr; /* transmit interrupts */
437 unsigned long mintr; /* modem interrupts */
438 unsigned long ibytes; /* input bytes */
439 unsigned long ipkts; /* input packets */
440 unsigned long ierrs; /* input errors */
441 unsigned long obytes; /* output bytes */
442 unsigned long opkts; /* output packets */
443 unsigned long oerrs; /* output errors */
444 } cx_stat_t;
445
446 typedef struct _board_t {
447 unsigned short port; /* base board port, 0..3f0 */
448 unsigned short num; /* board number, 0..2 */
449 unsigned char irq; /* interrupt request {3 5 7 10 11 12 15} */
450 unsigned char dma; /* DMA request {5 6 7} */
451 unsigned char if0type; /* chan0 interface RS-232/RS-449/V.35 */
452 unsigned char if8type; /* chan8 interface RS-232/RS-449/V.35 */
453 unsigned short bcr0; /* BCR0 image */
454 unsigned short bcr0b; /* BCR0b image */
455 unsigned short bcr1; /* BCR1 image */
456 unsigned short bcr1b; /* BCR1b image */
457 cx_chip_t chip[NCHIP]; /* controller structures */
458 cx_chan_t chan[NCHAN]; /* channel structures */
459 cx_stat_t stat[NCHAN]; /* channel statistics */
460 char name[16]; /* board version name */
461 unsigned char nuniv; /* number of universal channels */
462 unsigned char nsync; /* number of sync. channels */
463 unsigned char nasync; /* number of async. channels */
464 } cx_board_t;
465
466 #define CX_SPEED_DFLT 9600
467
468 #ifdef KERNEL
469 int cx_probe_board (int port);
470 void cx_init (cx_board_t *b, int num, int port, int irq, int dma);
471 void cx_setup_board (cx_board_t *b);
472 void cx_setup_chan (cx_chan_t *c);
473 void cx_chan_dtr (cx_chan_t *c, int on);
474 void cx_chan_rts (cx_chan_t *c, int on);
475 void cx_cmd (int base, int cmd);
476 int cx_chan_cd (cx_chan_t *c);
477 void cx_clock (long hz, long ba, int *clk, int *div);
478 #endif
479
480 #define CXIOCGETMODE _IOWR('x', 1, cx_options_t) /* get channel options */
481 #define CXIOCSETMODE _IOW('x', 2, cx_options_t) /* set channel options */
482 #define CXIOCGETSTAT _IOWR('x', 3, cx_stat_t) /* get channel stats */
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