The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/include/cronyx.h

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    1 /*
    2  * Defines for Cronyx-Sigma adapter driver.
    3  *
    4  * Copyright (C) 1994 Cronyx Ltd.
    5  * Author: Serge Vakulenko, <vak@zebub.msk.su>
    6  *
    7  * This software is distributed with NO WARRANTIES, not even the implied
    8  * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    9  *
   10  * Authors grant any other persons or organizations permission to use
   11  * or modify this software as long as this message is kept with the software,
   12  * all derivative works or modified versions.
   13  *
   14  * Version 1.9, Wed Oct  4 18:58:15 MSK 1995
   15  *
   16  * $FreeBSD: releng/5.0/sys/i386/include/cronyx.h 55205 1999-12-29 04:46:21Z peter $
   17  */
   18 /*
   19  * Asynchronous channel mode -------------------------------------------------
   20  */
   21 
   22 /* Parity */
   23 #define PAR_EVEN        0       /* even parity */
   24 #define PAR_ODD         1       /* odd parity */
   25 
   26 /* Parity mode */
   27 #define PARM_NOPAR      0       /* no parity */
   28 #define PARM_FORCE      1       /* force parity (odd = force 1, even = 0) */
   29 #define PARM_NORMAL     2       /* normal parity */
   30 
   31 /* Flow control transparency mode */
   32 #define FLOWCC_PASS     0       /* pass flow ctl chars as exceptions */
   33 #define FLOWCC_NOTPASS  1       /* don't pass flow ctl chars to the host */
   34 
   35 /* Stop bit length */
   36 #define STOPB_1         2       /* 1 stop bit */
   37 #define STOPB_15        3       /* 1.5 stop bits */
   38 #define STOPB_2         4       /* 2 stop bits */
   39 
   40 /* Action on break condition */
   41 #define BRK_INTR        0       /* generate an exception interrupt */
   42 #define BRK_NULL        1       /* translate to a NULL character */
   43 #define BRK_RESERVED    2       /* reserved */
   44 #define BRK_DISCARD     3       /* discard character */
   45 
   46 /* Parity/framing error actions */
   47 #define PERR_INTR       0       /* generate an exception interrupt */
   48 #define PERR_NULL       1       /* translate to a NULL character */
   49 #define PERR_IGNORE     2       /* ignore error; char passed as good data */
   50 #define PERR_DISCARD    3       /* discard error character */
   51 #define PERR_FFNULL     5       /* translate to FF NULL char */
   52 
   53 typedef struct {                /* async channel option register 1 */
   54         unsigned charlen : 4;   /* character length, 5..8 */
   55         unsigned ignpar : 1;    /* ignore parity */
   56         unsigned parmode : 2;   /* parity mode */
   57         unsigned parity : 1;    /* parity */
   58 } cx_cor1_async_t;
   59 
   60 typedef struct {                /* async channel option register 2 */
   61         unsigned dsrae : 1;     /* DSR automatic enable */
   62         unsigned ctsae : 1;     /* CTS automatic enable */
   63         unsigned rtsao : 1;     /* RTS automatic output enable */
   64         unsigned rlm : 1;       /* remote loopback mode enable */
   65         unsigned zero : 1;
   66         unsigned etc : 1;       /* embedded transmitter cmd enable */
   67         unsigned ixon : 1;      /* in-band XON/XOFF enable */
   68         unsigned ixany : 1;     /* XON on any character */
   69 } cx_cor2_async_t;
   70 
   71 typedef struct {                /* async channel option register 3 */
   72         unsigned stopb : 3;     /* stop bit length */
   73         unsigned zero : 1;
   74         unsigned scde : 1;      /* special char detection enable */
   75         unsigned flowct : 1;    /* flow control transparency mode */
   76         unsigned rngde : 1;     /* range detect enable */
   77         unsigned escde : 1;     /* extended spec. char detect enable */
   78 } cx_cor3_async_t;
   79 
   80 typedef struct {                /* async channel option register 6 */
   81         unsigned parerr : 3;    /* parity/framing error actions */
   82         unsigned brk : 2;       /* action on break condition */
   83         unsigned inlcr : 1;     /* translate NL to CR on input */
   84         unsigned icrnl : 1;     /* translate CR to NL on input */
   85         unsigned igncr : 1;     /* discard CR on input */
   86 } cx_cor6_async_t;
   87 
   88 typedef struct {                /* async channel option register 7 */
   89         unsigned ocrnl : 1;     /* translate CR to NL on output */
   90         unsigned onlcr : 1;     /* translate NL to CR on output */
   91         unsigned zero : 3;
   92         unsigned fcerr : 1;     /* process flow ctl err chars enable */
   93         unsigned lnext : 1;     /* LNext option enable */
   94         unsigned istrip : 1;    /* strip 8-bit on input */
   95 } cx_cor7_async_t;
   96 
   97 typedef struct {                /* async channel options */
   98         cx_cor1_async_t cor1;   /* channel option register 1 */
   99         cx_cor2_async_t cor2;   /* channel option register 2 */
  100         cx_cor3_async_t cor3;   /* option register 3 */
  101         cx_cor6_async_t cor6;   /* channel option register 6 */
  102         cx_cor7_async_t cor7;   /* channel option register 7 */
  103         unsigned char schr1;    /* special character register 1 (XON) */
  104         unsigned char schr2;    /* special character register 2 (XOFF) */
  105         unsigned char schr3;    /* special character register 3 */
  106         unsigned char schr4;    /* special character register 4 */
  107         unsigned char scrl;     /* special character range low */
  108         unsigned char scrh;     /* special character range high */
  109         unsigned char lnxt;     /* LNext character */
  110 } cx_opt_async_t;
  111 
  112 /*
  113  * HDLC channel mode ---------------------------------------------------------
  114  */
  115 /* Address field length option */
  116 #define AFLO_1OCT       0       /* address field is 1 octet in length */
  117 #define AFLO_2OCT       1       /* address field is 2 octet in length */
  118 
  119 /* Clear detect for X.21 data transfer phase */
  120 #define CLRDET_DISABLE  0       /* clear detect disabled */
  121 #define CLRDET_ENABLE   1       /* clear detect enabled */
  122 
  123 /* Addressing mode */
  124 #define ADMODE_NOADDR   0       /* no address */
  125 #define ADMODE_4_1      1       /* 4 * 1 byte */
  126 #define ADMODE_2_2      2       /* 2 * 2 byte */
  127 
  128 /* FCS append */
  129 #define FCS_NOTPASS     0       /* receive CRC is not passed to the host */
  130 #define FCS_PASS        1       /* receive CRC is passed to the host */
  131 
  132 /* CRC modes */
  133 #define CRC_INVERT      0       /* CRC is transmitted inverted (CRC V.41) */
  134 #define CRC_DONT_INVERT 1       /* CRC is not transmitted inverted (CRC-16) */
  135 
  136 /* Send sync pattern */
  137 #define SYNC_00         0       /* send 00h as pad char (NRZI encoding) */
  138 #define SYNC_AA         1       /* send AAh (Manchester/NRZ encoding) */
  139 
  140 /* FCS preset */
  141 #define FCSP_ONES       0       /* FCS is preset to all ones (CRC V.41) */
  142 #define FCSP_ZEROS      1       /* FCS is preset to all zeros (CRC-16) */
  143 
  144 /* idle mode */
  145 #define IDLE_FLAG       0       /* idle in flag */
  146 #define IDLE_MARK       1       /* idle in mark */
  147 
  148 /* CRC polynomial select */
  149 #define POLY_V41        0       /* x^16+x^12+x^5+1 (HDLC, preset to 1) */
  150 #define POLY_16         1       /* x^16+x^15+x^2+1 (bisync, preset to 0) */
  151 
  152 typedef struct {                /* hdlc channel option register 1 */
  153         unsigned ifflags : 4;   /* number of inter-frame flags sent */
  154         unsigned admode : 2;    /* addressing mode */
  155         unsigned clrdet : 1;    /* clear detect for X.21 data transfer phase */
  156         unsigned aflo : 1;      /* address field length option */
  157 } cx_cor1_hdlc_t;
  158 
  159 typedef struct {                /* hdlc channel option register 2 */
  160         unsigned dsrae : 1;     /* DSR automatic enable */
  161         unsigned ctsae : 1;     /* CTS automatic enable */
  162         unsigned rtsao : 1;     /* RTS automatic output enable */
  163         unsigned zero1 : 1;
  164         unsigned crcninv : 1;   /* CRC inversion option */
  165         unsigned zero2 : 1;
  166         unsigned fcsapd : 1;    /* FCS append */
  167         unsigned zero3 : 1;
  168 } cx_cor2_hdlc_t;
  169 
  170 typedef struct {                /* hdlc channel option register 3 */
  171         unsigned padcnt : 3;    /* pad character count */
  172         unsigned idle : 1;      /* idle mode */
  173         unsigned nofcs : 1;     /* FCS disable */
  174         unsigned fcspre : 1;    /* FCS preset */
  175         unsigned syncpat : 1;   /* send sync pattern */
  176         unsigned sndpad : 1;    /* send pad characters before flag enable */
  177 } cx_cor3_hdlc_t;
  178 
  179 typedef struct {                /* hdlc channel options */
  180         cx_cor1_hdlc_t cor1;    /* hdlc channel option register 1 */
  181         cx_cor2_hdlc_t cor2;    /* hdlc channel option register 2 */
  182         cx_cor3_hdlc_t cor3;    /* hdlc channel option register 3 */
  183         unsigned char rfar1;    /* receive frame address register 1 */
  184         unsigned char rfar2;    /* receive frame address register 2 */
  185         unsigned char rfar3;    /* receive frame address register 3 */
  186         unsigned char rfar4;    /* receive frame address register 4 */
  187         unsigned char cpsr;     /* CRC polynomial select */
  188 } cx_opt_hdlc_t;
  189 
  190 /*
  191  * BISYNC channel mode -------------------------------------------------------
  192  */
  193 
  194 /* Longitudinal redundancy check */
  195 #define BCC_CRC16       0       /* CRC16 is used for BCC */
  196 #define BCC_LRC         1       /* LRC is used for BCC */
  197 
  198 /* Send pad pattern */
  199 #define PAD_AA          0       /* send AAh as pad character */
  200 #define PAD_55          1       /* send 55h as pad character */
  201 
  202 typedef struct {                /* channel option register 1 */
  203         unsigned charlen : 4;   /* character length, 5..8 */
  204         unsigned ignpar : 1;    /* ignore parity */
  205         unsigned parmode : 2;   /* parity mode */
  206         unsigned parity : 1;    /* parity */
  207 } cx_cor1_bisync_t;
  208 
  209 typedef struct {                /* channel option register 2 */
  210         unsigned syns : 4;      /* number of extra SYN chars before a frame */
  211         unsigned crcninv : 1;   /* CRC inversion option */
  212         unsigned ebcdic : 1;    /* use EBCDIC as char set (instead of ASCII) */
  213         unsigned bcc : 1;       /* BCC append enable */
  214         unsigned lrc : 1;       /* longitudinal redundancy check */
  215 } cx_cor2_bisync_t;
  216 
  217 typedef struct {                /* channel option register 3 */
  218         unsigned padcnt : 3;    /* pad character count */
  219         unsigned idle : 1;      /* idle mode */
  220         unsigned nofcs : 1;     /* FCS disable */
  221         unsigned fcspre : 1;    /* FCS preset */
  222         unsigned padpat : 1;    /* send pad pattern */
  223         unsigned sndpad : 1;    /* send pad characters before SYN enable */
  224 } cx_cor3_bisync_t;
  225 
  226 typedef struct {                /* channel option register 6 */
  227         unsigned char specterm; /* special termination character */
  228 } cx_cor6_bisync_t;
  229 
  230 typedef struct {                /* bisync channel options */
  231         cx_cor1_bisync_t cor1;  /* channel option register 1 */
  232         cx_cor2_bisync_t cor2;  /* channel option register 2 */
  233         cx_cor3_bisync_t cor3;  /* channel option register 3 */
  234         cx_cor6_bisync_t cor6;  /* channel option register 6 */
  235         unsigned char cpsr;     /* CRC polynomial select */
  236 } cx_opt_bisync_t;
  237 
  238 /*
  239  * X.21 channel mode ---------------------------------------------------------
  240  */
  241 
  242 /* The number of SYN chars on receive */
  243 #define X21SYN_2        0       /* two SYN characters are required */
  244 #define X21SYN_1        1       /* one SYN character is required */
  245 
  246 typedef struct {                /* channel option register 1 */
  247         unsigned charlen : 4;   /* character length, 5..8 */
  248         unsigned ignpar : 1;    /* ignore parity */
  249         unsigned parmode : 2;   /* parity mode */
  250         unsigned parity : 1;    /* parity */
  251 } cx_cor1_x21_t;
  252 
  253 typedef struct {                /* channel option register 2 */
  254         unsigned zero1 : 5;
  255         unsigned etc : 1;       /* embedded transmitter command enable */
  256         unsigned zero2 : 2;
  257 } cx_cor2_x21_t;
  258 
  259 typedef struct {                /* channel option register 3 */
  260         unsigned zero : 4;
  261         unsigned scde : 1;      /* special character detect enable */
  262         unsigned stripsyn : 1;  /* treat SYN chars as special condition */
  263         unsigned ssde : 1;      /* steady state detect enable */
  264         unsigned syn : 1;       /* the number of SYN chars on receive */
  265 } cx_cor3_x21_t;
  266 
  267 typedef struct {                /* channel option register 6 */
  268         unsigned char synchar;  /* syn character */
  269 } cx_cor6_x21_t;
  270 
  271 typedef struct {                /* x21 channel options */
  272         cx_cor1_x21_t cor1;     /* channel option register 1 */
  273         cx_cor2_x21_t cor2;     /* channel option register 2 */
  274         cx_cor3_x21_t cor3;     /* channel option register 3 */
  275         cx_cor6_x21_t cor6;     /* channel option register 6 */
  276         unsigned char schr1;    /* special character register 1 */
  277         unsigned char schr2;    /* special character register 2 */
  278         unsigned char schr3;    /* special character register 3 */
  279 } cx_opt_x21_t;
  280 
  281 /*
  282  * CD2400 channel state structure --------------------------------------------
  283  */
  284 
  285 /* Signal encoding */
  286 #define ENCOD_NRZ        0      /* NRZ mode */
  287 #define ENCOD_NRZI       1      /* NRZI mode */
  288 #define ENCOD_MANCHESTER 2      /* Manchester mode */
  289 
  290 /* Clock source */
  291 #define CLK_0           0      /* clock 0 */
  292 #define CLK_1           1      /* clock 1 */
  293 #define CLK_2           2      /* clock 2 */
  294 #define CLK_3           3      /* clock 3 */
  295 #define CLK_4           4      /* clock 4 */
  296 #define CLK_EXT         6      /* external clock */
  297 #define CLK_RCV         7      /* receive clock */
  298 
  299 /* Channel type */
  300 #define T_NONE          0       /* no channel */
  301 #define T_ASYNC         1       /* pure asynchronous RS-232 channel */
  302 #define T_SYNC_RS232    2       /* pure synchronous RS-232 channel */
  303 #define T_SYNC_V35      3       /* pure synchronous V.35 channel */
  304 #define T_SYNC_RS449    4       /* pure synchronous RS-449 channel */
  305 #define T_UNIV_RS232    5       /* sync/async RS-232 channel */
  306 #define T_UNIV_RS449    6       /* sync/async RS-232/RS-449 channel */
  307 #define T_UNIV_V35      7       /* sync/async RS-232/V.35 channel */
  308 
  309 typedef enum {                  /* channel mode */
  310         M_ASYNC,                /* asynchronous mode */
  311         M_HDLC,                 /* HDLC mode */
  312         M_BISYNC,               /* BISYNC mode */
  313         M_X21                   /* X.21 mode */
  314 } cx_chan_mode_t;
  315 
  316 typedef struct {                /* channel option register 4 */
  317         unsigned thr : 4;       /* FIFO threshold */
  318         unsigned zero : 1;
  319         unsigned cts_zd : 1;    /* detect 1 to 0 transition on the CTS */
  320         unsigned cd_zd : 1;     /* detect 1 to 0 transition on the CD */
  321         unsigned dsr_zd : 1;    /* detect 1 to 0 transition on the DSR */
  322 } cx_cor4_t;
  323 
  324 typedef struct {                /* channel option register 5 */
  325         unsigned rx_thr : 4;    /* receive flow control FIFO threshold */
  326         unsigned zero : 1;
  327         unsigned cts_od : 1;    /* detect 0 to 1 transition on the CTS */
  328         unsigned cd_od : 1;     /* detect 0 to 1 transition on the CD */
  329         unsigned dsr_od : 1;    /* detect 0 to 1 transition on the DSR */
  330 } cx_cor5_t;
  331 
  332 typedef struct {                /* receive clock option register */
  333         unsigned clk : 3;       /* receive clock source */
  334         unsigned encod : 2;     /* signal encoding NRZ/NRZI/Manchester */
  335         unsigned dpll : 1;      /* DPLL enable */
  336         unsigned zero : 1;
  337         unsigned tlval : 1;     /* transmit line value */
  338 } cx_rcor_t;
  339 
  340 typedef struct {                /* transmit clock option register */
  341         unsigned zero1 : 1;
  342         unsigned llm : 1;       /* local loopback mode */
  343         unsigned zero2 : 1;
  344         unsigned ext1x : 1;     /* external 1x clock mode */
  345         unsigned zero3 : 1;
  346         unsigned clk : 3;       /* transmit clock source */
  347 } cx_tcor_t;
  348 
  349 typedef struct {
  350         cx_cor4_t cor4;         /* channel option register 4 */
  351         cx_cor5_t cor5;         /* channel option register 5 */
  352         cx_rcor_t rcor;         /* receive clock option register */
  353         cx_tcor_t tcor;         /* transmit clock option register */
  354 } cx_chan_opt_t;
  355 
  356 typedef enum {                  /* line break mode */
  357         BRK_IDLE,               /* normal line mode */
  358         BRK_SEND,               /* start sending break */
  359         BRK_STOP                /* stop sending break */
  360 } cx_break_t;
  361 
  362 typedef struct {
  363         unsigned cisco : 1;     /* cisco mode */
  364         unsigned keepalive : 1; /* keepalive enable */
  365         unsigned ext : 1;       /* use external ppp implementation */
  366         unsigned lock : 1;      /* channel locked for use by driver */
  367         unsigned norts : 1;     /* disable automatic RTS control */
  368 } cx_soft_opt_t;
  369 
  370 #define NCHIP    4              /* the number of controllers per board */
  371 #define NCHAN    16             /* the number of channels on the board */
  372 
  373 typedef struct {
  374         unsigned char board;            /* adapter number, 0..2 */
  375         unsigned char channel;          /* channel number, 0..15 */
  376         unsigned char type;             /* channel type (read only) */
  377         unsigned char iftype;           /* chan0 interface RS-232/RS-449/V.35 */
  378         unsigned long rxbaud;           /* receiver speed */
  379         unsigned long txbaud;           /* transmitter speed */
  380         cx_chan_mode_t mode;            /* channel mode */
  381         cx_chan_opt_t opt;              /* common channel options */
  382         cx_opt_async_t aopt;            /* async mode options */
  383         cx_opt_hdlc_t hopt;             /* hdlc mode options */
  384         cx_opt_bisync_t bopt;           /* bisync mode options */
  385         cx_opt_x21_t xopt;              /* x.21 mode options */
  386         cx_soft_opt_t sopt;             /* software options and state flags */
  387         char master[16];                /* master interface name or \0 */
  388 } cx_options_t;                         /* user settable options */
  389 
  390 typedef struct _chan_t {
  391         unsigned char type;             /* channel type */
  392         unsigned char num;              /* channel number, 0..15 */
  393         struct _board_t *board;         /* board pointer */
  394         struct _chip_t *chip;           /* controller pointer */
  395         struct _stat_t *stat;           /* statistics */
  396         unsigned long rxbaud;           /* receiver speed */
  397         unsigned long txbaud;           /* transmitter speed */
  398         cx_chan_mode_t mode;            /* channel mode */
  399         cx_chan_opt_t opt;              /* common channel options */
  400         cx_opt_async_t aopt;            /* async mode options */
  401         cx_opt_hdlc_t hopt;             /* hdlc mode options */
  402         cx_opt_bisync_t bopt;           /* bisync mode options */
  403         cx_opt_x21_t xopt;              /* x.21 mode options */
  404         unsigned char *arbuf;           /* receiver A dma buffer */
  405         unsigned char *brbuf;           /* receiver B dma buffer */
  406         unsigned char *atbuf;           /* transmitter A dma buffer */
  407         unsigned char *btbuf;           /* transmitter B dma buffer */
  408         unsigned long arphys;           /* receiver A phys address */
  409         unsigned long brphys;           /* receiver B phys address */
  410         unsigned long atphys;           /* transmitter A phys address */
  411         unsigned long btphys;           /* transmitter B phys address */
  412         unsigned char dtr;              /* DTR signal value */
  413         unsigned char rts;              /* RTS signal value */
  414 #ifdef _KERNEL
  415         struct tty *ttyp;               /* tty structure pointer */
  416         struct ifnet *ifp;              /* network interface data */
  417         struct ifnet *master;           /* master interface, or ==ifp */
  418         struct _chan_t *slaveq;         /* slave queue pointer, or NULL */
  419         cx_soft_opt_t sopt;             /* software options and state flags */
  420         cx_break_t brk;                 /* line break mode */
  421 #ifdef __bsdi__
  422         struct ttydevice_tmp *ttydev;   /* tty statistics structure */
  423 #endif
  424 #endif
  425 } cx_chan_t;
  426 
  427 typedef struct _chip_t {
  428         unsigned short port;            /* base port address, or 0 if no chip */
  429         unsigned char num;              /* controller number, 0..3 */
  430         struct _board_t *board;         /* board pointer */
  431         unsigned long oscfreq;          /* oscillator frequency in Hz */
  432 } cx_chip_t;
  433 
  434 typedef struct _stat_t {
  435         unsigned char board;            /* adapter number, 0..2 */
  436         unsigned char channel;          /* channel number, 0..15 */
  437         unsigned long rintr;            /* receive interrupts */
  438         unsigned long tintr;            /* transmit interrupts */
  439         unsigned long mintr;            /* modem interrupts */
  440         unsigned long ibytes;           /* input bytes */
  441         unsigned long ipkts;            /* input packets */
  442         unsigned long ierrs;            /* input errors */
  443         unsigned long obytes;           /* output bytes */
  444         unsigned long opkts;            /* output packets */
  445         unsigned long oerrs;            /* output errors */
  446 } cx_stat_t;
  447 
  448 typedef struct _board_t {
  449         unsigned short port;    /* base board port, 0..3f0 */
  450         unsigned short num;     /* board number, 0..2 */
  451         unsigned char irq;      /* interrupt request {3 5 7 10 11 12 15} */
  452         unsigned char dma;      /* DMA request {5 6 7} */
  453         unsigned char if0type;  /* chan0 interface RS-232/RS-449/V.35 */
  454         unsigned char if8type;  /* chan8 interface RS-232/RS-449/V.35 */
  455         unsigned short bcr0;    /* BCR0 image */
  456         unsigned short bcr0b;   /* BCR0b image */
  457         unsigned short bcr1;    /* BCR1 image */
  458         unsigned short bcr1b;   /* BCR1b image */
  459         cx_chip_t chip[NCHIP];  /* controller structures */
  460         cx_chan_t chan[NCHAN];  /* channel structures */
  461         cx_stat_t stat[NCHAN];  /* channel statistics */
  462         char name[16];          /* board version name */
  463         unsigned char nuniv;    /* number of universal channels */
  464         unsigned char nsync;    /* number of sync. channels */
  465         unsigned char nasync;   /* number of async. channels */
  466 } cx_board_t;
  467 
  468 #define CX_SPEED_DFLT   9600
  469 
  470 #ifdef _KERNEL
  471 int cx_probe_board (int port);
  472 void cx_init (cx_board_t *b, int num, int port, int irq, int dma);
  473 void cx_setup_board (cx_board_t *b);
  474 void cx_setup_chan (cx_chan_t *c);
  475 void cx_chan_dtr (cx_chan_t *c, int on);
  476 void cx_chan_rts (cx_chan_t *c, int on);
  477 void cx_cmd (int base, int cmd);
  478 int cx_chan_cd (cx_chan_t *c);
  479 void cx_clock (long hz, long ba, int *clk, int *div);
  480 #endif
  481 
  482 #define CXIOCGETMODE _IOWR('x', 1, cx_options_t)   /* get channel options */
  483 #define CXIOCSETMODE _IOW('x', 2, cx_options_t)    /* set channel options */
  484 #define CXIOCGETSTAT _IOWR('x', 3, cx_stat_t)      /* get channel stats */

Cache object: aedf59a98b9ba1fa369a4115f52724a2


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