Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/i386/include/elan_mmcr.h
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1 /*- 2 * Copyright (c) 2004 John Birrell 3 * All rights reserved. 4 * 5 * Please see src/share/examples/etc/bsd-style-copyright. 6 * 7 * AMD Elan SC520 Memory Mapped Configuration Region (MMCR). 8 * 9 * The layout of this structure is documented by AMD in the Elan SC520 10 * Microcontroller Register Set Manual. The field names match those 11 * described in that document. The overall structure size must be 4096 12 * bytes. Ignore fields with the 'pad' prefix - they are only present for 13 * alignment purposes. 14 * 15 * $FreeBSD: releng/5.3/sys/i386/include/elan_mmcr.h 124144 2004-01-05 12:00:59Z phk $ 16 */ 17 18 #ifndef _MACHINE_ELAN_MMCR_H_ 19 #define _MACHINE_ELAN_MMCR_H_ 1 20 21 struct elan_mmcr { 22 /* CPU */ 23 u_int16_t REVID; 24 u_int8_t CPUCTL; 25 u_int8_t pad_0x003[0xd]; 26 27 /* SDRAM Controller */ 28 u_int16_t DRCCTL; 29 u_int16_t DRCTMCTL; 30 u_int16_t DRCCFG; 31 u_int16_t DRCBENDADR; 32 u_int8_t pad_0x01a[0x6]; 33 u_int8_t ECCCTL; 34 u_int8_t ECCSTA; 35 u_int8_t ECCCKBPOS; 36 u_int8_t ECCCKTEST; 37 u_int32_t ECCSBADD; 38 u_int32_t ECCMBADD; 39 u_int8_t pad_0x02c[0x14]; 40 41 /* SDRAM Buffer */ 42 u_int8_t DBCTL; 43 u_int8_t pad_0x041[0xf]; 44 45 /* ROM/Flash Controller */ 46 u_int16_t BOOTCSCTL; 47 u_int8_t pad_0x052[0x2]; 48 u_int16_t ROMCS1CTL; 49 u_int16_t ROMCS2CTL; 50 u_int8_t pad_0x058[0x8]; 51 52 /* PCI Bus Host Bridge */ 53 u_int16_t HBCTL; 54 u_int16_t HBTGTIRQCTL; 55 u_int16_t HBTGTIRQSTA; 56 u_int16_t HBMSTIRQCTL; 57 u_int16_t HBMSTIRQSTA; 58 u_int8_t pad_0x06a[0x2]; 59 u_int32_t MSTINTADD; 60 61 /* System Arbitration */ 62 u_int8_t SYSARBCTL; 63 u_int8_t PCIARBSTA; 64 u_int16_t SYSARBMENB; 65 u_int32_t ARBPRICTL; 66 u_int8_t pad_0x078[0x8]; 67 68 /* System Address Mapping */ 69 u_int32_t ADDDECCTL; 70 u_int32_t WPVSTA; 71 u_int32_t PAR0; 72 u_int32_t PAR1; 73 u_int32_t PAR2; 74 u_int32_t PAR3; 75 u_int32_t PAR4; 76 u_int32_t PAR5; 77 u_int32_t PAR6; 78 u_int32_t PAR7; 79 u_int32_t PAR8; 80 u_int32_t PAR9; 81 u_int32_t PAR10; 82 u_int32_t PAR11; 83 u_int32_t PAR12; 84 u_int32_t PAR13; 85 u_int32_t PAR14; 86 u_int32_t PAR15; 87 u_int8_t pad_0x0c8[0xb38]; 88 89 /* GP Bus Controller */ 90 u_int8_t GPECHO; 91 u_int8_t GPCSDW; 92 u_int16_t GPCSQUAL; 93 u_int8_t pad_0xc04[0x4]; 94 u_int8_t GPCSRT; 95 u_int8_t GPCSPW; 96 u_int8_t GPCSOFF; 97 u_int8_t GPRDW; 98 u_int8_t GPRDOFF; 99 u_int8_t GPWRW; 100 u_int8_t GPWROFF; 101 u_int8_t GPALEW; 102 u_int8_t GPALEOFF; 103 u_int8_t pad_0xc11[0xf]; 104 105 /* Programmable Input/Output */ 106 u_int16_t PIOPFS15_0; 107 u_int16_t PIOPFS31_16; 108 u_int8_t CSPFS; 109 u_int8_t pad_0xc25; 110 u_int8_t CLKSEL; 111 u_int8_t pad_0xc27; 112 u_int16_t DSCTL; 113 u_int16_t PIODIR15_0; 114 u_int16_t PIODIR31_16; 115 u_int8_t pad_0xc2e[0x2]; 116 u_int16_t PIODATA15_0; 117 u_int16_t PIODATA31_16; 118 u_int16_t PIOSET15_0; 119 u_int16_t PIOSET31_16; 120 u_int16_t PIOCLR15_0; 121 u_int16_t PIOCLR31_16; 122 u_int8_t pad_0xc3c[0x24]; 123 124 /* Software Timer */ 125 u_int16_t SWTMRMILLI; 126 u_int16_t SWTMRMICRO; 127 u_int8_t SWTMRCFG; 128 u_int8_t pad_0xc65[0xb]; 129 130 /* General-Purpose Timers */ 131 u_int8_t GPTMRSTA; 132 u_int8_t pad_0xc71; 133 u_int16_t GPTMR0CTL; 134 u_int16_t GPTMR0CNT; 135 u_int16_t GPTMR0MAXCMPA; 136 u_int16_t GPTMR0MAXCMPB; 137 u_int16_t GPTMR1CTL; 138 u_int16_t GPTMR1CNT; 139 u_int16_t GPTMR1MAXCMPA; 140 u_int16_t GPTMR1MAXCMPB; 141 u_int16_t GPTMR2CTL; 142 u_int16_t GPTMR2CNT; 143 u_int8_t pad_0xc86[0x8]; 144 u_int16_t GPTMR2MAXCMPA; 145 u_int8_t pad_0xc90[0x20]; 146 147 /* Watchdog Timer */ 148 u_int16_t WDTMRCTL; 149 u_int16_t WDTMRCNTL; 150 u_int16_t WDTMRCNTH; 151 u_int8_t pad_0xcb6[0xa]; 152 153 /* UART Serial Ports */ 154 u_int8_t UART1CTL; 155 u_int8_t UART1STA; 156 u_int8_t UART1FCRSHAD; 157 u_int8_t pad_0xcc3; 158 u_int8_t UART2CTL; 159 u_int8_t UART2STA; 160 u_int8_t UART2FCRSHAD; 161 u_int8_t pad_0xcc7[0x9]; 162 163 /* Synchronous Serial Interface */ 164 u_int8_t SSICTL; 165 u_int8_t SSIXMIT; 166 u_int8_t SSICMD; 167 u_int8_t SSISTA; 168 u_int8_t SSIRCV; 169 u_int8_t pad_0xcd5[0x2b]; 170 171 /* Programmable Interrupt Controller */ 172 u_int8_t PICICR; 173 u_int8_t pad_0xd01; 174 u_int8_t MPICMODE; 175 u_int8_t SL1PICMODE; 176 u_int8_t SL2PICMODE; 177 u_int8_t pad_0xd05[0x3]; 178 u_int16_t SWINT16_1; 179 u_int8_t SWINT22_17; 180 u_int8_t pad_0xd0b[0x5]; 181 u_int16_t INTPINPOL; 182 u_int8_t pad_0xd12[0x2]; 183 u_int16_t PCIHOSTMAP; 184 u_int8_t pad_0xd16[0x2]; 185 u_int16_t ECCMAP; 186 u_int8_t GPTMR0MAP; 187 u_int8_t GPTMR1MAP; 188 u_int8_t GPTMR2MAP; 189 u_int8_t pad_0xd1d[0x3]; 190 u_int8_t PIT0MAP; 191 u_int8_t PIT1MAP; 192 u_int8_t PIT2MAP; 193 u_int8_t pad_0xd23[0x5]; 194 u_int8_t UART1MAP; 195 u_int8_t UART2MAP; 196 u_int8_t pad_0xd2a[0x6]; 197 u_int8_t PCIINTAMAP; 198 u_int8_t PCIINTBMAP; 199 u_int8_t PCIINTCMAP; 200 u_int8_t PCIINTDMAP; 201 u_int8_t pad_0xd34[0xc]; 202 u_int8_t DMABCINTMAP; 203 u_int8_t SSIMAP; 204 u_int8_t WDTMAP; 205 u_int8_t RTCMAP; 206 u_int8_t WPVMAP; 207 u_int8_t ICEMAP; 208 u_int8_t FERRMAP; 209 u_int8_t pad_0xd47[0x9]; 210 u_int8_t GP0IMAP; 211 u_int8_t GP1IMAP; 212 u_int8_t GP2IMAP; 213 u_int8_t GP3IMAP; 214 u_int8_t GP4IMAP; 215 u_int8_t GP5IMAP; 216 u_int8_t GP6IMAP; 217 u_int8_t GP7IMAP; 218 u_int8_t GP8IMAP; 219 u_int8_t GP9IMAP; 220 u_int8_t GP10IMAP; 221 u_int8_t pad_0xd5b[0x15]; 222 223 /* Reset Generation */ 224 u_int8_t SYSINFO; 225 u_int8_t pad_0xd71; 226 u_int8_t RESCFG; 227 u_int8_t pad_0xd73; 228 u_int8_t RESSTA; 229 u_int8_t pad_0xd75[0xb]; 230 231 /* GP DMA Controller */ 232 u_int8_t GPDMACTL; 233 u_int8_t GPDMAMMIO; 234 u_int16_t GPDMAEXTCHMAPA; 235 u_int16_t GPDMAEXTCHMAPB; 236 u_int8_t GPDMAEXTPG0; 237 u_int8_t GPDMAEXTPG1; 238 u_int8_t GPDMAEXTPG2; 239 u_int8_t GPDMAEXTPG3; 240 u_int8_t GPDMAEXTPG5; 241 u_int8_t GPDMAEXTPG6; 242 u_int8_t GPDMAEXTPG7; 243 u_int8_t pad_0xd8d[0x3]; 244 u_int8_t GPDMAEXTTC3; 245 u_int8_t GPDMAEXTTC5; 246 u_int8_t GPDMAEXTTC6; 247 u_int8_t GPDMAEXTTC7; 248 u_int8_t pad_0xd94[0x4]; 249 u_int8_t GPDMABCCTL; 250 u_int8_t GPDMABCSTA; 251 u_int8_t GPDMABSINTENB; 252 u_int8_t GPDMABCVAL; 253 u_int8_t pad_0xd9c[0x4]; 254 u_int16_t GPDMANXTADDL3; 255 u_int16_t GPDMANXTADDH3; 256 u_int16_t GPDMANXTADDL5; 257 u_int16_t GPDMANXTADDH5; 258 u_int16_t GPDMANXTADDL6; 259 u_int16_t GPDMANXTADDH6; 260 u_int16_t GPDMANXTADDL7; 261 u_int16_t GPDMANXTADDH7; 262 u_int16_t GPDMANXTTCL3; 263 u_int8_t GPDMANXTTCH3; 264 u_int8_t pad_0xdb3; 265 u_int16_t GPDMANXTTCL5; 266 u_int8_t GPDMANXTTCH5; 267 u_int8_t pad_0xdb7; 268 u_int16_t GPDMANXTTCL6; 269 u_int8_t GPDMANXTTCH6; 270 u_int8_t pad_0xdbb; 271 u_int16_t GPDMANXTTCL7; 272 u_int8_t GPDMANXTTCH7; 273 u_int8_t pad_0xdc0[0x240]; 274 }; 275 276 CTASSERT(sizeof(struct elan_mmcr) == 4096); 277 278 extern volatile struct elan_mmcr * elan_mmcr; 279 280 #endif /* _MACHINE_ELAN_MMCR_H_ */
Cache object: f85d4f3c19e7d357af154579e42f0a3b
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