The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/include/elan_mmcr.h

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    1 /*-
    2  * Copyright (c) 2004 John Birrell
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  */
   26 
   27 /* AMD Elan SC520 Memory Mapped Configuration Region (MMCR).
   28  *
   29  * The layout of this structure is documented by AMD in the Elan SC520
   30  * Microcontroller Register Set Manual. The field names match those
   31  * described in that document. The overall structure size must be 4096
   32  * bytes. Ignore fields with the 'pad' prefix - they are only present for
   33  * alignment purposes.
   34  *
   35  * $FreeBSD$
   36  */
   37 
   38 #ifndef _MACHINE_ELAN_MMCR_H_
   39 #define _MACHINE_ELAN_MMCR_H_ 1
   40 
   41 struct elan_mmcr {
   42         /* CPU */
   43         u_int16_t       REVID;
   44         u_int8_t        CPUCTL;
   45         u_int8_t        pad_0x003[0xd];
   46 
   47         /* SDRAM Controller */
   48         u_int16_t       DRCCTL;
   49         u_int16_t       DRCTMCTL;
   50         u_int16_t       DRCCFG;
   51         u_int16_t       DRCBENDADR;
   52         u_int8_t        pad_0x01a[0x6];
   53         u_int8_t        ECCCTL;
   54         u_int8_t        ECCSTA;
   55         u_int8_t        ECCCKBPOS;
   56         u_int8_t        ECCCKTEST;
   57         u_int32_t       ECCSBADD;
   58         u_int32_t       ECCMBADD;
   59         u_int8_t        pad_0x02c[0x14];
   60 
   61         /* SDRAM Buffer */
   62         u_int8_t        DBCTL;
   63         u_int8_t        pad_0x041[0xf];
   64 
   65         /* ROM/Flash Controller */
   66         u_int16_t       BOOTCSCTL;
   67         u_int8_t        pad_0x052[0x2];
   68         u_int16_t       ROMCS1CTL;
   69         u_int16_t       ROMCS2CTL;
   70         u_int8_t        pad_0x058[0x8];
   71 
   72         /* PCI Bus Host Bridge */
   73         u_int16_t       HBCTL;
   74         u_int16_t       HBTGTIRQCTL;
   75         u_int16_t       HBTGTIRQSTA;
   76         u_int16_t       HBMSTIRQCTL;
   77         u_int16_t       HBMSTIRQSTA;
   78         u_int8_t        pad_0x06a[0x2];
   79         u_int32_t       MSTINTADD;
   80 
   81         /* System Arbitration */
   82         u_int8_t        SYSARBCTL;
   83         u_int8_t        PCIARBSTA;
   84         u_int16_t       SYSARBMENB;
   85         u_int32_t       ARBPRICTL;
   86         u_int8_t        pad_0x078[0x8];
   87 
   88         /* System Address Mapping */
   89         u_int32_t       ADDDECCTL;
   90         u_int32_t       WPVSTA;
   91         u_int32_t       PAR0;
   92         u_int32_t       PAR1;
   93         u_int32_t       PAR2;
   94         u_int32_t       PAR3;
   95         u_int32_t       PAR4;
   96         u_int32_t       PAR5;
   97         u_int32_t       PAR6;
   98         u_int32_t       PAR7;
   99         u_int32_t       PAR8;
  100         u_int32_t       PAR9;
  101         u_int32_t       PAR10;
  102         u_int32_t       PAR11;
  103         u_int32_t       PAR12;
  104         u_int32_t       PAR13;
  105         u_int32_t       PAR14;
  106         u_int32_t       PAR15;
  107         u_int8_t        pad_0x0c8[0xb38];
  108 
  109         /* GP Bus Controller */
  110         u_int8_t        GPECHO;
  111         u_int8_t        GPCSDW;
  112         u_int16_t       GPCSQUAL;
  113         u_int8_t        pad_0xc04[0x4];
  114         u_int8_t        GPCSRT;
  115         u_int8_t        GPCSPW;
  116         u_int8_t        GPCSOFF;
  117         u_int8_t        GPRDW;
  118         u_int8_t        GPRDOFF;
  119         u_int8_t        GPWRW;
  120         u_int8_t        GPWROFF;
  121         u_int8_t        GPALEW;
  122         u_int8_t        GPALEOFF;
  123         u_int8_t        pad_0xc11[0xf];
  124 
  125         /* Programmable Input/Output */
  126         u_int16_t       PIOPFS15_0;
  127         u_int16_t       PIOPFS31_16;
  128         u_int8_t        CSPFS;
  129         u_int8_t        pad_0xc25;
  130         u_int8_t        CLKSEL;
  131         u_int8_t        pad_0xc27;
  132         u_int16_t       DSCTL;
  133         u_int16_t       PIODIR15_0;
  134         u_int16_t       PIODIR31_16;
  135         u_int8_t         pad_0xc2e[0x2];
  136         u_int16_t       PIODATA15_0;
  137         u_int16_t       PIODATA31_16;
  138         u_int16_t       PIOSET15_0;
  139         u_int16_t       PIOSET31_16;
  140         u_int16_t       PIOCLR15_0;
  141         u_int16_t       PIOCLR31_16;
  142         u_int8_t        pad_0xc3c[0x24];
  143 
  144         /* Software Timer */
  145         u_int16_t       SWTMRMILLI;
  146         u_int16_t       SWTMRMICRO;
  147         u_int8_t        SWTMRCFG;
  148         u_int8_t        pad_0xc65[0xb];
  149 
  150         /* General-Purpose Timers */
  151         u_int8_t        GPTMRSTA;
  152         u_int8_t        pad_0xc71;
  153         u_int16_t       GPTMR0CTL;
  154         u_int16_t       GPTMR0CNT;
  155         u_int16_t       GPTMR0MAXCMPA;
  156         u_int16_t       GPTMR0MAXCMPB;
  157         u_int16_t       GPTMR1CTL;
  158         u_int16_t       GPTMR1CNT;
  159         u_int16_t       GPTMR1MAXCMPA;
  160         u_int16_t       GPTMR1MAXCMPB;
  161         u_int16_t       GPTMR2CTL;
  162         u_int16_t       GPTMR2CNT;
  163         u_int8_t        pad_0xc86[0x8];
  164         u_int16_t       GPTMR2MAXCMPA;
  165         u_int8_t        pad_0xc90[0x20];
  166 
  167         /* Watchdog Timer */
  168         u_int16_t       WDTMRCTL;
  169         u_int16_t       WDTMRCNTL;
  170         u_int16_t       WDTMRCNTH;
  171         u_int8_t        pad_0xcb6[0xa];
  172 
  173         /* UART Serial Ports */
  174         u_int8_t        UART1CTL;
  175         u_int8_t        UART1STA;
  176         u_int8_t        UART1FCRSHAD;
  177         u_int8_t        pad_0xcc3;
  178         u_int8_t        UART2CTL;
  179         u_int8_t        UART2STA;
  180         u_int8_t        UART2FCRSHAD;
  181         u_int8_t        pad_0xcc7[0x9];
  182 
  183         /* Synchronous Serial Interface */
  184         u_int8_t        SSICTL;
  185         u_int8_t        SSIXMIT;
  186         u_int8_t        SSICMD;
  187         u_int8_t        SSISTA;
  188         u_int8_t        SSIRCV;
  189         u_int8_t        pad_0xcd5[0x2b];
  190 
  191         /* Programmable Interrupt Controller */
  192         u_int8_t        PICICR;
  193         u_int8_t        pad_0xd01;
  194         u_int8_t        MPICMODE;
  195         u_int8_t        SL1PICMODE;
  196         u_int8_t        SL2PICMODE;
  197         u_int8_t        pad_0xd05[0x3];
  198         u_int16_t       SWINT16_1;
  199         u_int8_t        SWINT22_17;
  200         u_int8_t        pad_0xd0b[0x5];
  201         u_int16_t       INTPINPOL;
  202         u_int8_t        pad_0xd12[0x2];
  203         u_int16_t       PCIHOSTMAP;
  204         u_int8_t        pad_0xd16[0x2];
  205         u_int16_t       ECCMAP;
  206         u_int8_t        GPTMR0MAP;
  207         u_int8_t        GPTMR1MAP;
  208         u_int8_t        GPTMR2MAP;
  209         u_int8_t        pad_0xd1d[0x3];
  210         u_int8_t        PIT0MAP;
  211         u_int8_t        PIT1MAP;
  212         u_int8_t        PIT2MAP;
  213         u_int8_t        pad_0xd23[0x5];
  214         u_int8_t        UART1MAP;
  215         u_int8_t        UART2MAP;
  216         u_int8_t        pad_0xd2a[0x6];
  217         u_int8_t        PCIINTAMAP;
  218         u_int8_t        PCIINTBMAP;
  219         u_int8_t        PCIINTCMAP;
  220         u_int8_t        PCIINTDMAP;
  221         u_int8_t        pad_0xd34[0xc];
  222         u_int8_t        DMABCINTMAP;
  223         u_int8_t        SSIMAP;
  224         u_int8_t        WDTMAP;
  225         u_int8_t        RTCMAP;
  226         u_int8_t        WPVMAP;
  227         u_int8_t        ICEMAP;
  228         u_int8_t        FERRMAP;
  229         u_int8_t        pad_0xd47[0x9];
  230         u_int8_t        GP0IMAP;
  231         u_int8_t        GP1IMAP;
  232         u_int8_t        GP2IMAP;
  233         u_int8_t        GP3IMAP;
  234         u_int8_t        GP4IMAP;
  235         u_int8_t        GP5IMAP;
  236         u_int8_t        GP6IMAP;
  237         u_int8_t        GP7IMAP;
  238         u_int8_t        GP8IMAP;
  239         u_int8_t        GP9IMAP;
  240         u_int8_t        GP10IMAP;
  241         u_int8_t        pad_0xd5b[0x15];
  242 
  243         /* Reset Generation */
  244         u_int8_t        SYSINFO;
  245         u_int8_t        pad_0xd71;
  246         u_int8_t        RESCFG;
  247         u_int8_t        pad_0xd73;
  248         u_int8_t        RESSTA;
  249         u_int8_t        pad_0xd75[0xb];
  250 
  251         /* GP DMA Controller */
  252         u_int8_t        GPDMACTL;
  253         u_int8_t        GPDMAMMIO;
  254         u_int16_t       GPDMAEXTCHMAPA;
  255         u_int16_t       GPDMAEXTCHMAPB;
  256         u_int8_t        GPDMAEXTPG0;
  257         u_int8_t        GPDMAEXTPG1;
  258         u_int8_t        GPDMAEXTPG2;
  259         u_int8_t        GPDMAEXTPG3;
  260         u_int8_t        GPDMAEXTPG5;
  261         u_int8_t        GPDMAEXTPG6;
  262         u_int8_t        GPDMAEXTPG7;
  263         u_int8_t        pad_0xd8d[0x3];
  264         u_int8_t        GPDMAEXTTC3;
  265         u_int8_t        GPDMAEXTTC5;
  266         u_int8_t        GPDMAEXTTC6;
  267         u_int8_t        GPDMAEXTTC7;
  268         u_int8_t        pad_0xd94[0x4];
  269         u_int8_t        GPDMABCCTL;
  270         u_int8_t        GPDMABCSTA;
  271         u_int8_t        GPDMABSINTENB;
  272         u_int8_t        GPDMABCVAL;
  273         u_int8_t        pad_0xd9c[0x4];
  274         u_int16_t       GPDMANXTADDL3;
  275         u_int16_t       GPDMANXTADDH3;
  276         u_int16_t       GPDMANXTADDL5;
  277         u_int16_t       GPDMANXTADDH5;
  278         u_int16_t       GPDMANXTADDL6;
  279         u_int16_t       GPDMANXTADDH6;
  280         u_int16_t       GPDMANXTADDL7;
  281         u_int16_t       GPDMANXTADDH7;
  282         u_int16_t       GPDMANXTTCL3;
  283         u_int8_t        GPDMANXTTCH3;
  284         u_int8_t        pad_0xdb3;
  285         u_int16_t       GPDMANXTTCL5;
  286         u_int8_t        GPDMANXTTCH5;
  287         u_int8_t        pad_0xdb7;
  288         u_int16_t       GPDMANXTTCL6;
  289         u_int8_t        GPDMANXTTCH6;
  290         u_int8_t        pad_0xdbb;
  291         u_int16_t       GPDMANXTTCL7;
  292         u_int8_t        GPDMANXTTCH7;
  293         u_int8_t        pad_0xdc0[0x240];
  294         };
  295 
  296 CTASSERT(sizeof(struct elan_mmcr) == 4096);
  297 
  298 extern volatile struct elan_mmcr * elan_mmcr;
  299 
  300 #endif /* _MACHINE_ELAN_MMCR_H_ */

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