The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]

FreeBSD/Linux Kernel Cross Reference
sys/i386/include/intr_machdep.h

Version: -  FREEBSD  -  FREEBSD-12-STABLE  -  FREEBSD-12-0  -  FREEBSD-11-STABLE  -  FREEBSD-11-2  -  FREEBSD-11-1  -  FREEBSD-11-0  -  FREEBSD-10-STABLE  -  FREEBSD-10-4  -  FREEBSD-10-3  -  FREEBSD-10-2  -  FREEBSD-10-1  -  FREEBSD-10-0  -  FREEBSD-9-STABLE  -  FREEBSD-9-3  -  FREEBSD-9-2  -  FREEBSD-9-1  -  FREEBSD-9-0  -  FREEBSD-8-STABLE  -  FREEBSD-8-4  -  FREEBSD-8-3  -  FREEBSD-8-2  -  FREEBSD-8-1  -  FREEBSD-8-0  -  FREEBSD-7-STABLE  -  FREEBSD-7-4  -  FREEBSD-7-3  -  FREEBSD-7-2  -  FREEBSD-7-1  -  FREEBSD-7-0  -  FREEBSD-6-STABLE  -  FREEBSD-6-4  -  FREEBSD-6-3  -  FREEBSD-6-2  -  FREEBSD-6-1  -  FREEBSD-6-0  -  FREEBSD-5-STABLE  -  FREEBSD-5-5  -  FREEBSD-5-4  -  FREEBSD-5-3  -  FREEBSD-5-2  -  FREEBSD-5-1  -  FREEBSD-5-0  -  FREEBSD-4-STABLE  -  FREEBSD-3-STABLE  -  FREEBSD22  -  linux-2.6  -  linux-2.4.22  -  MK83  -  MK84  -  PLAN9  -  DFBSD  -  NETBSD  -  NETBSD5  -  NETBSD4  -  NETBSD3  -  NETBSD20  -  OPENBSD  -  xnu-517  -  xnu-792  -  xnu-792.6.70  -  xnu-1228  -  xnu-1456.1.26  -  xnu-1699.24.8  -  xnu-2050.18.24  -  OPENSOLARIS  -  minix-3-1-1 
SearchContext: -  none  -  3  -  10 

    1 /*-
    2  * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  *
   14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   24  * SUCH DAMAGE.
   25  *
   26  * $FreeBSD: releng/10.2/sys/i386/include/intr_machdep.h 255726 2013-09-20 05:06:03Z gibbs $
   27  */
   28 
   29 #ifndef __MACHINE_INTR_MACHDEP_H__
   30 #define __MACHINE_INTR_MACHDEP_H__
   31 
   32 #ifdef _KERNEL
   33 
   34 /*
   35  * The maximum number of I/O interrupts we allow.  This number is rather
   36  * arbitrary as it is just the maximum IRQ resource value.  The interrupt
   37  * source for a given IRQ maps that I/O interrupt to device interrupt
   38  * source whether it be a pin on an interrupt controller or an MSI interrupt.
   39  * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device
   40  * interrupts allocate IDT vectors on demand.  Currently we have 191 IDT
   41  * vectors available for device interrupts.  On many systems with I/O APICs,
   42  * a lot of the IRQs are not used, so this number can be much larger than
   43  * 191 and still be safe since only interrupt sources in actual use will
   44  * allocate IDT vectors.
   45  *
   46  * The first 255 IRQs (0 - 254) are reserved for ISA IRQs and PCI intline IRQs.
   47  * IRQ values from 256 to 767 are used by MSI.  When running under the Xen
   48  * Hypervisor, IRQ values from 768 to 4863 are available for binding to
   49  * event channel events.  We leave 255 unused to avoid confusion since 255 is
   50  * used in PCI to indicate an invalid IRQ.
   51  */
   52 #define NUM_MSI_INTS    512
   53 #define FIRST_MSI_INT   256
   54 #ifdef XENHVM
   55 #include <xen/xen-os.h>
   56 #define NUM_EVTCHN_INTS NR_EVENT_CHANNELS
   57 #define FIRST_EVTCHN_INT \
   58     (FIRST_MSI_INT + NUM_MSI_INTS)
   59 #define LAST_EVTCHN_INT \
   60     (FIRST_EVTCHN_INT + NUM_EVTCHN_INTS - 1)
   61 #elif defined(XEN)
   62 #include <xen/xen-os.h>
   63 #define NUM_EVTCHN_INTS NR_EVENT_CHANNELS
   64 #define FIRST_EVTCHN_INT 0
   65 #define LAST_EVTCHN_INT \
   66     (FIRST_EVTCHN_INT + NUM_EVTCHN_INTS - 1)
   67 #else /* !XEN && !XENHVM */
   68 #define NUM_EVTCHN_INTS 0
   69 #endif
   70 #define NUM_IO_INTS     (FIRST_MSI_INT + NUM_MSI_INTS + NUM_EVTCHN_INTS)
   71 
   72 /*
   73  * Default base address for MSI messages on x86 platforms.
   74  */
   75 #define MSI_INTEL_ADDR_BASE             0xfee00000
   76 
   77 /*
   78  * - 1 ??? dummy counter.
   79  * - 2 counters for each I/O interrupt.
   80  * - 1 counter for each CPU for lapic timer.
   81  * - 9 counters for each CPU for IPI counters for SMP.
   82  */
   83 #ifdef SMP
   84 #define INTRCNT_COUNT   (1 + NUM_IO_INTS * 2 + (1 + 9) * MAXCPU)
   85 #else
   86 #define INTRCNT_COUNT   (1 + NUM_IO_INTS * 2 + 1)
   87 #endif
   88 
   89 #ifndef LOCORE
   90 
   91 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
   92 
   93 #define IDTVEC(name)    __CONCAT(X,name)
   94 
   95 struct intsrc;
   96 
   97 /*
   98  * Methods that a PIC provides to mask/unmask a given interrupt source,
   99  * "turn on" the interrupt on the CPU side by setting up an IDT entry, and
  100  * return the vector associated with this source.
  101  */
  102 struct pic {
  103         void (*pic_enable_source)(struct intsrc *);
  104         void (*pic_disable_source)(struct intsrc *, int);
  105         void (*pic_eoi_source)(struct intsrc *);
  106         void (*pic_enable_intr)(struct intsrc *);
  107         void (*pic_disable_intr)(struct intsrc *);
  108         int (*pic_vector)(struct intsrc *);
  109         int (*pic_source_pending)(struct intsrc *);
  110         void (*pic_suspend)(struct pic *);
  111         void (*pic_resume)(struct pic *, bool suspend_cancelled);
  112         int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
  113             enum intr_polarity);
  114         int (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
  115         TAILQ_ENTRY(pic) pics;
  116 };
  117 
  118 /* Flags for pic_disable_source() */
  119 enum {
  120         PIC_EOI,
  121         PIC_NO_EOI,
  122 };
  123 
  124 /*
  125  * An interrupt source.  The upper-layer code uses the PIC methods to
  126  * control a given source.  The lower-layer PIC drivers can store additional
  127  * private data in a given interrupt source such as an interrupt pin number
  128  * or an I/O APIC pointer.
  129  */
  130 struct intsrc {
  131         struct pic *is_pic;
  132         struct intr_event *is_event;
  133         u_long *is_count;
  134         u_long *is_straycount;
  135         u_int is_index;
  136         u_int is_handlers;
  137 };
  138 
  139 struct trapframe;
  140 
  141 extern struct mtx icu_lock;
  142 extern int elcr_found;
  143 
  144 #ifndef DEV_ATPIC
  145 void    atpic_reset(void);
  146 #endif
  147 /* XXX: The elcr_* prototypes probably belong somewhere else. */
  148 int     elcr_probe(void);
  149 enum intr_trigger elcr_read_trigger(u_int irq);
  150 void    elcr_resume(void);
  151 void    elcr_write_trigger(u_int irq, enum intr_trigger trigger);
  152 #ifdef SMP
  153 void    intr_add_cpu(u_int cpu);
  154 #endif
  155 int     intr_add_handler(const char *name, int vector, driver_filter_t filter,
  156     driver_intr_t handler, void *arg, enum intr_type flags, void **cookiep);
  157 #ifdef SMP
  158 int     intr_bind(u_int vector, u_char cpu);
  159 #endif
  160 int     intr_config_intr(int vector, enum intr_trigger trig,
  161     enum intr_polarity pol);
  162 int     intr_describe(u_int vector, void *ih, const char *descr);
  163 void    intr_execute_handlers(struct intsrc *isrc, struct trapframe *frame);
  164 u_int   intr_next_cpu(void);
  165 struct intsrc *intr_lookup_source(int vector);
  166 int     intr_register_pic(struct pic *pic);
  167 int     intr_register_source(struct intsrc *isrc);
  168 int     intr_remove_handler(void *cookie);
  169 void    intr_resume(bool suspend_cancelled);
  170 void    intr_suspend(void);
  171 void    intrcnt_add(const char *name, u_long **countp);
  172 void    nexus_add_irq(u_long irq);
  173 int     msi_alloc(device_t dev, int count, int maxcount, int *irqs);
  174 void    msi_init(void);
  175 int     msi_map(int irq, uint64_t *addr, uint32_t *data);
  176 int     msi_release(int* irqs, int count);
  177 int     msix_alloc(device_t dev, int *irq);
  178 int     msix_release(int irq);
  179 
  180 #endif  /* !LOCORE */
  181 #endif  /* _KERNEL */
  182 #endif  /* !__MACHINE_INTR_MACHDEP_H__ */

Cache object: f4f516463ed3525bec4fd918c0d47fa9


[ source navigation ] [ diff markup ] [ identifier search ] [ freetext search ] [ file search ] [ list types ] [ track identifier ]


This page is part of the FreeBSD/Linux Linux Kernel Cross-Reference, and was automatically generated using a modified version of the LXR engine.