1 /*-
2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: releng/6.2/sys/i386/include/intr_machdep.h 163803 2006-10-30 18:03:04Z jhb $
27 */
28
29 #ifndef __MACHINE_INTR_MACHDEP_H__
30 #define __MACHINE_INTR_MACHDEP_H__
31
32 #ifdef _KERNEL
33
34 /*
35 * The maximum number of I/O interrupts we allow. This number is rather
36 * arbitrary as it is just the maximum IRQ resource value. The interrupt
37 * source for a given IRQ maps that I/O interrupt to device interrupt
38 * source whether it be a pin on an interrupt controller or an MSI interrupt.
39 * The 16 ISA IRQs are assigned fixed IDT vectors, but all other device
40 * interrupts allocate IDT vectors on demand. Currently we have 191 IDT
41 * vectors available for device interrupts. On many systems with I/O APICs,
42 * a lot of the IRQs are not used, so this number can be much larger than
43 * 191 and still be safe since only interrupt sources in actual use will
44 * allocate IDT vectors.
45 *
46 * For now we stick with 255 as ISA IRQs and PCI intline IRQs only allow
47 * for IRQs in the range 0 - 254. When MSI support is added this number
48 * will likely increase.
49 */
50 #define NUM_IO_INTS 255
51
52 /*
53 * - 1 ??? dummy counter.
54 * - 2 counters for each I/O interrupt.
55 * - 1 counter for each CPU for lapic timer.
56 * - 7 counters for each CPU for IPI counters for SMP.
57 */
58 #ifdef SMP
59 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + (1 + 7) * MAXCPU)
60 #else
61 #define INTRCNT_COUNT (1 + NUM_IO_INTS * 2 + 1)
62 #endif
63
64 #ifndef LOCORE
65
66 typedef void inthand_t(u_int cs, u_int ef, u_int esp, u_int ss);
67
68 #define IDTVEC(name) __CONCAT(X,name)
69
70 struct intsrc;
71
72 /*
73 * Methods that a PIC provides to mask/unmask a given interrupt source,
74 * "turn on" the interrupt on the CPU side by setting up an IDT entry, and
75 * return the vector associated with this source.
76 */
77 struct pic {
78 void (*pic_enable_source)(struct intsrc *);
79 void (*pic_disable_source)(struct intsrc *, int);
80 void (*pic_eoi_source)(struct intsrc *);
81 void (*pic_enable_intr)(struct intsrc *);
82 int (*pic_vector)(struct intsrc *);
83 int (*pic_source_pending)(struct intsrc *);
84 void (*pic_suspend)(struct pic *);
85 void (*pic_resume)(struct pic *);
86 int (*pic_config_intr)(struct intsrc *, enum intr_trigger,
87 enum intr_polarity);
88 void (*pic_assign_cpu)(struct intsrc *, u_int apic_id);
89 STAILQ_ENTRY(pic) pics;
90 };
91
92 /* Flags for pic_disable_source() */
93 enum {
94 PIC_EOI,
95 PIC_NO_EOI,
96 };
97
98 /*
99 * An interrupt source. The upper-layer code uses the PIC methods to
100 * control a given source. The lower-layer PIC drivers can store additional
101 * private data in a given interrupt source such as an interrupt pin number
102 * or an I/O APIC pointer.
103 */
104 struct intsrc {
105 struct pic *is_pic;
106 struct intr_event *is_event;
107 u_long *is_count;
108 u_long *is_straycount;
109 u_int is_index;
110 u_int is_enabled:1;
111 };
112
113 struct intrframe;
114
115 extern struct mtx icu_lock;
116 extern int elcr_found;
117
118 /* XXX: The elcr_* prototypes probably belong somewhere else. */
119 int elcr_probe(void);
120 enum intr_trigger elcr_read_trigger(u_int irq);
121 void elcr_resume(void);
122 void elcr_write_trigger(u_int irq, enum intr_trigger trigger);
123 #ifdef SMP
124 void intr_add_cpu(u_int apic_id);
125 #else
126 #define intr_add_cpu(apic_id)
127 #endif
128 int intr_add_handler(const char *name, int vector, driver_intr_t handler,
129 void *arg, enum intr_type flags, void **cookiep);
130 int intr_config_intr(int vector, enum intr_trigger trig,
131 enum intr_polarity pol);
132 void intr_execute_handlers(struct intsrc *isrc, struct intrframe *iframe);
133 struct intsrc *intr_lookup_source(int vector);
134 int intr_register_pic(struct pic *pic);
135 int intr_register_source(struct intsrc *isrc);
136 int intr_remove_handler(void *cookie);
137 void intr_resume(void);
138 void intr_suspend(void);
139 void intrcnt_add(const char *name, u_long **countp);
140
141 #endif /* !LOCORE */
142 #endif /* _KERNEL */
143 #endif /* !__MACHINE_INTR_MACHDEP_H__ */
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