FreeBSD/Linux Kernel Cross Reference
sys/i386/include/pci_cfgreg.h

     /*-
      * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
      * All rights reserved.
      *
      * Redistribution and use in source and binary forms, with or without
      * modification, are permitted provided that the following conditions
      * are met:
      * 1. Redistributions of source code must retain the above copyright
      *    notice unmodified, this list of conditions, and the following
     *    disclaimer.
     * 2. Redistributions in binary form must reproduce the above copyright
     *    notice, this list of conditions and the following disclaimer in the
     *    documentation and/or other materials provided with the distribution.
     *
     * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
     * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
     * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
     * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
     * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
     * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
     *
     * $FreeBSD$
     *
     */
    
    #define CONF1_ADDR_PORT    0x0cf8
    #define CONF1_DATA_PORT    0x0cfc
    
    #define CONF1_ENABLE       0x80000000ul
    #define CONF1_ENABLE_CHK   0x80000000ul
    #define CONF1_ENABLE_MSK   0x7f000000ul
    #define CONF1_ENABLE_CHK1  0xff000001ul
    #define CONF1_ENABLE_MSK1  0x80000001ul
    #define CONF1_ENABLE_RES1  0x80000000ul
    
    #define CONF2_ENABLE_PORT  0x0cf8
    #define CONF2_FORWARD_PORT 0x0cfa
    
    #define CONF2_ENABLE_CHK   0x0e
    #define CONF2_ENABLE_RES   0x0e
    
    int             pcie_cfgregopen(uint64_t base, uint8_t minbus, uint8_t maxbus);
    int             pci_cfgregopen(void);
    u_int32_t       pci_cfgregread(int bus, int slot, int func, int reg, int bytes);
    void            pci_cfgregwrite(int bus, int slot, int func, int reg, u_int32_t data, int bytes);
    void            pci_pir_open(void);
    int             pci_pir_probe(int bus, int require_parse);
    int             pci_pir_route_interrupt(int bus, int device, int func, int pin);

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