1 /*
2 * Copyright 1996 Massachusetts Institute of Technology
3 *
4 * Permission to use, copy, modify, and distribute this software and
5 * its documentation for any purpose and without fee is hereby
6 * granted, provided that both the above copyright notice and this
7 * permission notice appear in all copies, that both the above
8 * copyright notice and this permission notice appear in all
9 * supporting documentation, and that the name of M.I.T. not be used
10 * in advertising or publicity pertaining to distribution of the
11 * software without specific, written prior permission. M.I.T. makes
12 * no representations about the suitability of this software for any
13 * purpose. It is provided "as is" without express or implied
14 * warranty.
15 *
16 * THIS SOFTWARE IS PROVIDED BY M.I.T. ``AS IS''. M.I.T. DISCLAIMS
17 * ALL EXPRESS OR IMPLIED WARRANTIES WITH REGARD TO THIS SOFTWARE,
18 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT
20 * SHALL M.I.T. BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
23 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
24 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
26 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * $FreeBSD: src/sys/i386/include/perfmon.h,v 1.2.2.1 1999/09/05 08:11:57 peter Exp $
30 */
31
32 /*
33 * Interface to performance-monitoring counters for Intel Pentium and
34 * Pentium Pro CPUs.
35 */
36
37 #ifndef _MACHINE_PERFMON_H_
38 #define _MACHINE_PERFMON_H_
39
40 #ifndef KERNEL
41 #include <sys/types.h>
42 #endif
43 #include <sys/ioccom.h>
44
45 #define NPMC 2
46
47 #define PMIOSETUP _IOW('5', 1, struct pmc)
48 #define PMIOGET _IOWR('5', 7, struct pmc)
49 #define PMIOSTART _IOW('5', 2, int)
50 #define PMIOSTOP _IOW('5', 3, int)
51 #define PMIOREAD _IOWR('5', 4, struct pmc_data)
52 #define PMIORESET _IOW('5', 5, int)
53 #define PMIOTSTAMP _IOR('5', 6, struct pmc_tstamp)
54
55 struct pmc {
56 int pmc_num;
57 union {
58 struct {
59 unsigned char pmcus_event;
60 unsigned char pmcus_unit;
61 unsigned char pmcus_flags;
62 unsigned char pmcus_mask;
63 } pmcu_s;
64 unsigned int pmcu_val;
65 } pmc_pmcu;
66 };
67
68 #define PMC_ALL (-1)
69
70 #define pmc_event pmc_pmcu.pmcu_s.pmcus_event
71 #define pmc_unit pmc_pmcu.pmcu_s.pmcus_unit
72 #define pmc_flags pmc_pmcu.pmcu_s.pmcus_flags
73 #define pmc_mask pmc_pmcu.pmcu_s.pmcus_mask
74 #define pmc_val pmc_pmcu.pmcu_val
75
76 #define PMCF_USR 0x01 /* count events in user mode */
77 #define PMCF_OS 0x02 /* count events in kernel mode */
78 #define PMCF_E 0x04 /* use edge-detection mode */
79 #define PMCF_PC 0x08 /* PMx output pin control */
80 #define PMCF_INT 0x10 /* APIC interrupt enable (do not use) */
81 #define PMCF_EN 0x40 /* enable counters */
82 #define PMCF_INV 0x80 /* invert counter mask comparison */
83
84 #define PMCF_SYS_FLAGS (PMCF_INT | PMCF_EN) /* user cannot set */
85
86 struct pmc_data {
87 int pmcd_num;
88 quad_t pmcd_value;
89 };
90
91 struct pmc_tstamp {
92 int pmct_rate;
93 quad_t pmct_value;
94 };
95
96 #ifndef KERNEL
97
98 #define _PATH_PERFMON "/dev/perfmon"
99
100 #else
101
102 /*
103 * Intra-kernel interface to performance monitoring counters
104 */
105 void perfmon_init __P((void));
106 int perfmon_avail __P((void));
107 int perfmon_setup __P((int, unsigned int));
108 int perfmon_get __P((int, unsigned int *));
109 int perfmon_fini __P((int));
110 int perfmon_start __P((int));
111 int perfmon_stop __P((int));
112 int perfmon_read __P((int, quad_t *));
113 int perfmon_reset __P((int));
114
115 /*
116 * We pass the device down this interface because in the future
117 * the different counters might be accessed through separate devices.
118 */
119 int perfmon_close __P((dev_t, int, int, struct proc *));
120 int perfmon_open __P((dev_t, int, int, struct proc *));
121 int perfmon_ioctl __P((dev_t, int, caddr_t, int, struct proc *));
122 #endif /* KERNEL */
123
124 /*
125 * Pentium Pro performance counters, from Appendix B.
126 */
127 /* Data Cache Unit */
128 #define PMC6_DATA_MEM_REFS 0x43
129 #define PMC6_DCU_LINES_IN 0x45
130 #define PMC6_DCU_M_LINES_IN 0x46
131 #define PMC6_DCU_M_LINES_OUT 0x47
132 #define PMC6_DCU_MISS_OUTSTANDING 0x48
133
134 /* Instruction Fetch Unit */
135 #define PMC6_IFU_IFETCH 0x80
136 #define PMC6_IFU_IFETCH_MISS 0x81
137 #define PMC6_ITLB_MISS 0x85
138 #define PMC6_IFU_MEM_STALL 0x86
139 #define PMC6_ILD_STALL 0x87
140
141 /* L2 Cache */
142 #define PMC6_L2_IFETCH 0x28 /* MESI */
143 #define PMC6_L2_LD 0x29 /* MESI */
144 #define PMC6_L2_ST 0x2a /* MESI */
145 #define PMC6_L2_LINES_IN 0x24
146 #define PMC6_L2_LINES_OUT 0x26
147 #define PMC6_L2_M_LINES_INM 0x25
148 #define PMC6_L2_M_LINES_OUTM 0x27
149 #define PMC6_L2_RQSTS 0x2e /* MESI */
150 #define PMC6_L2_ADS 0x21
151 #define PMC6_L2_DBUS_BUSY 0x22
152 #define PMC6_L2_DBUS_BUSY_RD 0x23
153
154 /* External Bus Logic */
155 #define PMC6_BUS_DRDY_CLOCKS 0x62
156 #define PMC6_BUS_LOCK_CLOCKS 0x63
157 #define PMC6_BUS_REQ_OUTSTANDING 0x60
158 #define PMC6_BUS_TRAN_BRD 0x65
159 #define PMC6_BUS_TRAN_RFO 0x66
160 #define PMC6_BUS_TRAN_WB 0x67
161 #define PMC6_BUS_TRAN_IFETCH 0x68
162 #define PMC6_BUS_TRAN_INVAL 0x69
163 #define PMC6_BUS_TRAN_PWR 0x6a
164 #define PMC6_BUS_TRAN_P 0x6b
165 #define PMC6_BUS_TRAN_IO 0x6c
166 #define PMC6_BUS_TRAN_DEF 0x6d
167 #define PMC6_BUS_TRAN_BURST 0x6e
168 #define PMC6_BUS_TRAN_ANY 0x70
169 #define PMC6_BUS_TRAN_MEM 0x6f
170 #define PMC6_BUS_DATA_RCV 0x64
171 #define PMC6_BUS_BNR_DRV 0x61
172 #define PMC6_BUS_HIT_DRV 0x7a
173 #define PMC6_BUS_HITM_DRV 0x7b
174 #define PMC6_BUS_SNOOP_STALL 0x7e
175
176 /* Floating Point Unit */
177 #define PMC6_FLOPS 0xc1 /* counter 0 only */
178 #define PMC6_FP_COMP_OPS_EXE 0x10 /* counter 0 only */
179 #define PMC6_FP_ASSIST 0x11 /* counter 1 only */
180 #define PMC6_MUL 0x12 /* counter 1 only */
181 #define PMC6_DIV 0x13 /* counter 1 only */
182 #define PMC6_CYCLES_DIV_BUSY 0x14 /* counter 0 only */
183
184 /* Memory Ordering */
185 #define PMC6_LD_BLOCKS 0x03
186 #define PMC6_SB_DRAINS 0x04
187 #define PMC6_MISALIGN_MEM_REF 0x05
188
189 /* Instruction Decoding and Retirement */
190 #define PMC6_INST_RETIRED 0xc0
191 #define PMC6_UOPS_RETIRED 0xc2
192 #define PMC6_INST_DECODER 0xd0 /* (sic) */
193
194 /* Interrupts */
195 #define PMC6_HW_INT_RX 0xc8
196 #define PMC6_CYCLES_INT_MASKED 0xc6
197 #define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
198
199 /* Branches */
200 #define PMC6_BR_INST_RETIRED 0xc4
201 #define PMC6_BR_MISS_PRED_RETIRED 0xc5
202 #define PMC6_BR_TAKEN_RETIRED 0xc9
203 #define PMC6_BR_MISS_PRED_TAKEN_RET 0xca
204 #define PMC6_BR_INST_DECODED 0xe0
205 #define PMC6_BTB_MISSES 0xe2
206 #define PMC6_BR_BOGUS 0xe4
207 #define PMC6_BACLEARS 0xe6
208
209 /* Stalls */
210 #define PMC6_RESOURCE_STALLS 0xa2
211 #define PMC6_PARTIAL_RAT_STALLS 0xd2
212
213 /* Segment Register Loads */
214 #define PMC6_SEGMENT_REG_LOADS 0x06
215
216 /* Clocks */
217 #define PMC6_CPU_CLK_UNHALTED 0x79
218
219 /*
220 * Pentium Performance Counters
221 * This list comes from the Harvard people, not Intel.
222 */
223 #define PMC5_DATA_READ 0
224 #define PMC5_DATA_WRITE 1
225 #define PMC5_DATA_TLB_MISS 2
226 #define PMC5_DATA_READ_MISS 3
227 #define PMC5_DATA_WRITE_MISS 4
228 #define PMC5_WRITE_M_E 5
229 #define PMC5_DATA_LINES_WBACK 6
230 #define PMC5_DATA_CACHE_SNOOP 7
231 #define PMC5_DATA_CACHE_SNOOP_HIT 8
232 #define PMC5_MEM_ACCESS_BOTH 9
233 #define PMC5_BANK_CONFLICTS 10
234 #define PMC5_MISALIGNED_DATA 11
235 #define PMC5_INST_READ 12
236 #define PMC5_INST_TLB_MISS 13
237 #define PMC5_INST_CACHE_MISS 14
238 #define PMC5_SEGMENT_REG_LOAD 15
239 #define PMC5_BRANCHES 18
240 #define PMC5_BTB_HITS 19
241 #define PMC5_BRANCH_TAKEN 20
242 #define PMC5_PIPELINE_FLUSH 21
243 #define PMC5_INST_EXECUTED 22
244 #define PMC5_INST_EXECUTED_V 23
245 #define PMC5_BUS_UTILIZATION 24
246 #define PMC5_WRITE_BACKUP_STALL 25
247 #define PMC5_DATA_READ_STALL 26
248 #define PMC5_WRITE_E_M_STALL 27
249 #define PMC5_LOCKED_BUS 28
250 #define PMC5_IO_CYCLE 29
251 #define PMC5_NONCACHE_MEMORY 30
252 #define PMC5_ADDR_GEN_INTERLOCK 31
253 #define PMC5_FLOPS 34
254 #define PMC5_BP0_MATCH 35
255 #define PMC5_BP1_MATCH 36
256 #define PMC5_BP2_MATCH 37
257 #define PMC5_BP3_MATCH 38
258 #define PMC5_HW_INTR 39
259 #define PMC5_DATA_RW 40
260 #define PMC5_DATA_RW_MISS 41
261
262 #endif /* !_MACHINE_PERFMON_H_ */
Cache object: f5414c35c9d70ac104375e07762f12b2
|