1 /*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
34 * $FreeBSD$
35 */
36
37 #ifndef _MACHINE_SPECIALREG_H_
38 #define _MACHINE_SPECIALREG_H_
39
40 /*
41 * Bits in 386 special registers:
42 */
43 #define CR0_PE 0x00000001 /* Protected mode Enable */
44 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
45 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
46 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
47 #ifdef notused
48 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
49 #endif
50 #define CR0_PG 0x80000000 /* PaGing enable */
51
52 /*
53 * Bits in 486 special registers:
54 */
55 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
56 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
57 all modes) */
58 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
59 #define CR0_NW 0x20000000 /* Not Write-through */
60 #define CR0_CD 0x40000000 /* Cache Disable */
61
62 /*
63 * Bits in PPro special registers
64 */
65 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
66 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
67 #define CR4_TSD 0x00000004 /* Time stamp disable */
68 #define CR4_DE 0x00000008 /* Debugging extensions */
69 #define CR4_PSE 0x00000010 /* Page size extensions */
70 #define CR4_PAE 0x00000020 /* Physical address extension */
71 #define CR4_MCE 0x00000040 /* Machine check enable */
72 #define CR4_PGE 0x00000080 /* Page global enable */
73 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
74
75 /*
76 * CPUID instruction features register
77 */
78 #define CPUID_FPU 0x0001
79 #define CPUID_VME 0x0002
80 #define CPUID_DE 0x0004
81 #define CPUID_PSE 0x0008
82 #define CPUID_TSC 0x0010
83 #define CPUID_MSR 0x0020
84 #define CPUID_PAE 0x0040
85 #define CPUID_MCE 0x0080
86 #define CPUID_CX8 0x0100
87 #define CPUID_APIC 0x0200
88 #define CPUID_B10 0x0400
89 #define CPUID_B11 0x0800
90 #define CPUID_MTRR 0x1000
91 #define CPUID_PGE 0x2000
92 #define CPUID_MCA 0x4000
93 #define CPUID_CMOV 0x8000
94
95 /*
96 * Model-specific registers for the i386 family
97 */
98 #define MSR_P5_MC_ADDR 0x000
99 #define MSR_P5_MC_TYPE 0x001
100 #define MSR_TSC 0x010
101 #define MSR_APICBASE 0x01b
102 #define MSR_EBL_CR_POWERON 0x02a
103 #define MSR_BIOS_UPDT_TRIG 0x079
104 #define MSR_BIOS_SIGN 0x08b
105 #define MSR_PERFCTR0 0x0c1
106 #define MSR_PERFCTR1 0x0c2
107 #define MSR_MTRRcap 0x0fe
108 #define MSR_MCG_CAP 0x179
109 #define MSR_MCG_STATUS 0x17a
110 #define MSR_MCG_CTL 0x17b
111 #define MSR_EVNTSEL0 0x186
112 #define MSR_EVNTSEL1 0x187
113 #define MSR_DEBUGCTLMSR 0x1d9
114 #define MSR_LASTBRANCHFROMIP 0x1db
115 #define MSR_LASTBRANCHTOIP 0x1dc
116 #define MSR_LASTINTFROMIP 0x1dd
117 #define MSR_LASTINTTOIP 0x1de
118 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
119 #define MSR_MTRRVarBase 0x200
120 #define MSR_MTRR64kBase 0x250
121 #define MSR_MTRR16kBase 0x258
122 #define MSR_MTRR4kBase 0x268
123 #define MSR_MTRRdefType 0x2ff
124 #define MSR_MC0_CTL 0x400
125 #define MSR_MC0_STATUS 0x401
126 #define MSR_MC0_ADDR 0x402
127 #define MSR_MC0_MISC 0x403
128 #define MSR_MC1_CTL 0x404
129 #define MSR_MC1_STATUS 0x405
130 #define MSR_MC1_ADDR 0x406
131 #define MSR_MC1_MISC 0x407
132 #define MSR_MC2_CTL 0x408
133 #define MSR_MC2_STATUS 0x409
134 #define MSR_MC2_ADDR 0x40a
135 #define MSR_MC2_MISC 0x40b
136 #define MSR_MC4_CTL 0x40c
137 #define MSR_MC4_STATUS 0x40d
138 #define MSR_MC4_ADDR 0x40e
139 #define MSR_MC4_MISC 0x40f
140 #define MSR_MC3_CTL 0x410
141 #define MSR_MC3_STATUS 0x411
142 #define MSR_MC3_ADDR 0x412
143 #define MSR_MC3_MISC 0x413
144
145 /*
146 * Constants related to MTRRs
147 */
148 #define MTRR_N64K 8 /* numbers of fixed-size entries */
149 #define MTRR_N16K 16
150 #define MTRR_N4K 64
151
152 /*
153 * Cyrix configuration registers, accessible as IO ports.
154 */
155 #define CCR0 0xc0 /* Configuration control register 0 */
156 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
157 non-cacheable */
158 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
159 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
160 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
161 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
162 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
163 state */
164 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
165 assoc */
166 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
167
168 #define CCR1 0xc1 /* Configuration control register 1 */
169 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
170 #define CCR1_SMI 0x02 /* Enables SMM pins */
171 #define CCR1_SMAC 0x04 /* System management memory access */
172 #define CCR1_MMAC 0x08 /* Main memory access */
173 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
174 #define CCR1_SM3 0x80 /* SMM address space address region 3 */
175
176 #define CCR2 0xc2
177 #define CCR2_WB 0x02 /* Enables WB cache interface pins */
178 #define CCR2_SADS 0x02 /* Slow ADS */
179 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
180 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
181 #define CCR2_WT1 0x10 /* WT region 1 */
182 #define CCR2_WPR1 0x10 /* Write-protect region 1 */
183 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
184 hold state. */
185 #define CCR2_BWRT 0x40 /* Enables burst write cycles */
186 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
187
188 #define CCR3 0xc3
189 #define CCR3_SMILOCK 0x01 /* SMM register lock */
190 #define CCR3_NMI 0x02 /* Enables NMI during SMM */
191 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */
192 #define CCR3_SMMMODE 0x08 /* SMM Mode */
193 #define CCR3_MAPEN0 0x10 /* Enables Map0 */
194 #define CCR3_MAPEN1 0x20 /* Enables Map1 */
195 #define CCR3_MAPEN2 0x40 /* Enables Map2 */
196 #define CCR3_MAPEN3 0x80 /* Enables Map3 */
197
198 #define CCR4 0xe8
199 #define CCR4_IOMASK 0x07
200 #define CCR4_MEM 0x08 /* Enables momory bypassing */
201 #define CCR4_DTE 0x10 /* Enables directory table entry cache */
202 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */
203 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
204
205 #define CCR5 0xe9
206 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
207 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
208 #define CCR5_LBR1 0x10 /* Local bus region 1 */
209 #define CCR5_ARREN 0x20 /* Enables ARR region */
210
211 #define CCR6 0xea
212
213 #define CCR7 0xeb
214
215 /* Performance Control Register (5x86 only). */
216 #define PCR0 0x20
217 #define PCR0_RSTK 0x01 /* Enables return stack */
218 #define PCR0_BTB 0x02 /* Enables branch target buffer */
219 #define PCR0_LOOP 0x04 /* Enables loop */
220 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
221 serialize pipe. */
222 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
223 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
224 #define PCR0_LSSER 0x80 /* Disable reorder */
225
226 /* Device Identification Registers */
227 #define DIR0 0xfe
228 #define DIR1 0xff
229
230 /*
231 * The following four 3-byte registers control the non-cacheable regions.
232 * These registers must be written as three separate bytes.
233 *
234 * NCRx+0: A31-A24 of starting address
235 * NCRx+1: A23-A16 of starting address
236 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
237 *
238 * The non-cacheable region's starting address must be aligned to the
239 * size indicated by the NCR_SIZE_xx field.
240 */
241 #define NCR1 0xc4
242 #define NCR2 0xc7
243 #define NCR3 0xca
244 #define NCR4 0xcd
245
246 #define NCR_SIZE_0K 0
247 #define NCR_SIZE_4K 1
248 #define NCR_SIZE_8K 2
249 #define NCR_SIZE_16K 3
250 #define NCR_SIZE_32K 4
251 #define NCR_SIZE_64K 5
252 #define NCR_SIZE_128K 6
253 #define NCR_SIZE_256K 7
254 #define NCR_SIZE_512K 8
255 #define NCR_SIZE_1M 9
256 #define NCR_SIZE_2M 10
257 #define NCR_SIZE_4M 11
258 #define NCR_SIZE_8M 12
259 #define NCR_SIZE_16M 13
260 #define NCR_SIZE_32M 14
261 #define NCR_SIZE_4G 15
262
263 /*
264 * The address region registers are used to specify the location and
265 * size for the eight address regions.
266 *
267 * ARRx + 0: A31-A24 of start address
268 * ARRx + 1: A23-A16 of start address
269 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
270 */
271 #define ARR0 0xc4
272 #define ARR1 0xc7
273 #define ARR2 0xca
274 #define ARR3 0xcd
275 #define ARR4 0xd0
276 #define ARR5 0xd3
277 #define ARR6 0xd6
278 #define ARR7 0xd9
279
280 #define ARR_SIZE_0K 0
281 #define ARR_SIZE_4K 1
282 #define ARR_SIZE_8K 2
283 #define ARR_SIZE_16K 3
284 #define ARR_SIZE_32K 4
285 #define ARR_SIZE_64K 5
286 #define ARR_SIZE_128K 6
287 #define ARR_SIZE_256K 7
288 #define ARR_SIZE_512K 8
289 #define ARR_SIZE_1M 9
290 #define ARR_SIZE_2M 10
291 #define ARR_SIZE_4M 11
292 #define ARR_SIZE_8M 12
293 #define ARR_SIZE_16M 13
294 #define ARR_SIZE_32M 14
295 #define ARR_SIZE_4G 15
296
297 /*
298 * The region control registers specify the attributes associated with
299 * the ARRx addres regions.
300 */
301 #define RCR0 0xdc
302 #define RCR1 0xdd
303 #define RCR2 0xde
304 #define RCR3 0xdf
305 #define RCR4 0xe0
306 #define RCR5 0xe1
307 #define RCR6 0xe2
308 #define RCR7 0xe3
309
310 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
311 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
312 #define RCR_WWO 0x02 /* Weak write ordering. */
313 #define RCR_WL 0x04 /* Weak locking. */
314 #define RCR_WG 0x08 /* Write gathering. */
315 #define RCR_WT 0x10 /* Write-through. */
316 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
317
318 /* AMD Write Allocate Top-Of-Memory and Control Register */
319 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
320 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
321 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
322
323
324 #ifndef LOCORE
325 static __inline u_char
326 read_cyrix_reg(u_char reg)
327 {
328 outb(0x22, reg);
329 return inb(0x23);
330 }
331
332 static __inline void
333 write_cyrix_reg(u_char reg, u_char data)
334 {
335 outb(0x22, reg);
336 outb(0x23, data);
337 }
338 #endif
339
340 #endif /* !_MACHINE_SPECIALREG_H_ */
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