1 /*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by the University of
16 * California, Berkeley and its contributors.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 *
33 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
34 * $FreeBSD$
35 */
36
37 #ifndef _MACHINE_SPECIALREG_H_
38 #define _MACHINE_SPECIALREG_H_
39
40 /*
41 * Bits in 386 special registers:
42 */
43 #define CR0_PE 0x00000001 /* Protected mode Enable */
44 #define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
45 #define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
46 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
47 #ifdef notused
48 #define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
49 #endif
50 #define CR0_PG 0x80000000 /* PaGing enable */
51
52 /*
53 * Bits in 486 special registers:
54 */
55 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
56 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
57 all modes) */
58 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
59 #define CR0_NW 0x20000000 /* Not Write-through */
60 #define CR0_CD 0x40000000 /* Cache Disable */
61
62 /*
63 * Bits in PPro special registers
64 */
65 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
66 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
67 #define CR4_TSD 0x00000004 /* Time stamp disable */
68 #define CR4_DE 0x00000008 /* Debugging extensions */
69 #define CR4_PSE 0x00000010 /* Page size extensions */
70 #define CR4_PAE 0x00000020 /* Physical address extension */
71 #define CR4_MCE 0x00000040 /* Machine check enable */
72 #define CR4_PGE 0x00000080 /* Page global enable */
73 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
74 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
75 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
76
77 /*
78 * CPUID instruction features register
79 */
80 #define CPUID_FPU 0x00000001
81 #define CPUID_VME 0x00000002
82 #define CPUID_DE 0x00000004
83 #define CPUID_PSE 0x00000008
84 #define CPUID_TSC 0x00000010
85 #define CPUID_MSR 0x00000020
86 #define CPUID_PAE 0x00000040
87 #define CPUID_MCE 0x00000080
88 #define CPUID_CX8 0x00000100
89 #define CPUID_APIC 0x00000200
90 #define CPUID_B10 0x00000400
91 #define CPUID_SEP 0x00000800
92 #define CPUID_MTRR 0x00001000
93 #define CPUID_PGE 0x00002000
94 #define CPUID_MCA 0x00004000
95 #define CPUID_CMOV 0x00008000
96 #define CPUID_PAT 0x00010000
97 #define CPUID_PSE36 0x00020000
98 #define CPUID_PSN 0x00040000
99 #define CPUID_CLFSH 0x00080000
100 #define CPUID_B20 0x00100000
101 #define CPUID_DS 0x00200000
102 #define CPUID_ACPI 0x00400000
103 #define CPUID_MMX 0x00800000
104 #define CPUID_FXSR 0x01000000
105 #define CPUID_SSE 0x02000000
106 #define CPUID_XMM 0x02000000
107 #define CPUID_SSE2 0x04000000
108 #define CPUID_SS 0x08000000
109 #define CPUID_HTT 0x10000000
110 #define CPUID_TM 0x20000000
111 #define CPUID_B30 0x40000000
112 #define CPUID_PBE 0x80000000
113
114 /*
115 * CPUID instruction 1 ebx info
116 */
117 #define CPUID_BRAND_INDEX 0x000000ff
118 #define CPUID_CLFUSH_SIZE 0x0000ff00
119 #define CPUID_HTT_CORES 0x00ff0000
120 #define CPUID_LOCAL_APIC_ID 0xff000000
121
122 /*
123 * Model-specific registers for the i386 family
124 */
125 #define MSR_P5_MC_ADDR 0x000
126 #define MSR_P5_MC_TYPE 0x001
127 #define MSR_TSC 0x010
128 #define MSR_APICBASE 0x01b
129 #define MSR_EBL_CR_POWERON 0x02a
130 #define MSR_BIOS_UPDT_TRIG 0x079
131 #define MSR_BIOS_SIGN 0x08b
132 #define MSR_PERFCTR0 0x0c1
133 #define MSR_PERFCTR1 0x0c2
134 #define MSR_MTRRcap 0x0fe
135 #define MSR_MCG_CAP 0x179
136 #define MSR_MCG_STATUS 0x17a
137 #define MSR_MCG_CTL 0x17b
138 #define MSR_EVNTSEL0 0x186
139 #define MSR_EVNTSEL1 0x187
140 #define MSR_THERM_CONTROL 0x19a
141 #define MSR_THERM_INTERRUPT 0x19b
142 #define MSR_THERM_STATUS 0x19c
143 #define MSR_DEBUGCTLMSR 0x1d9
144 #define MSR_LASTBRANCHFROMIP 0x1db
145 #define MSR_LASTBRANCHTOIP 0x1dc
146 #define MSR_LASTINTFROMIP 0x1dd
147 #define MSR_LASTINTTOIP 0x1de
148 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
149 #define MSR_MTRRVarBase 0x200
150 #define MSR_MTRR64kBase 0x250
151 #define MSR_MTRR16kBase 0x258
152 #define MSR_MTRR4kBase 0x268
153 #define MSR_MTRRdefType 0x2ff
154 #define MSR_MC0_CTL 0x400
155 #define MSR_MC0_STATUS 0x401
156 #define MSR_MC0_ADDR 0x402
157 #define MSR_MC0_MISC 0x403
158 #define MSR_MC1_CTL 0x404
159 #define MSR_MC1_STATUS 0x405
160 #define MSR_MC1_ADDR 0x406
161 #define MSR_MC1_MISC 0x407
162 #define MSR_MC2_CTL 0x408
163 #define MSR_MC2_STATUS 0x409
164 #define MSR_MC2_ADDR 0x40a
165 #define MSR_MC2_MISC 0x40b
166 #define MSR_MC4_CTL 0x40c
167 #define MSR_MC4_STATUS 0x40d
168 #define MSR_MC4_ADDR 0x40e
169 #define MSR_MC4_MISC 0x40f
170 #define MSR_MC3_CTL 0x410
171 #define MSR_MC3_STATUS 0x411
172 #define MSR_MC3_ADDR 0x412
173 #define MSR_MC3_MISC 0x413
174
175 /*
176 * Constants related to MTRRs
177 */
178 #define MTRR_N64K 8 /* numbers of fixed-size entries */
179 #define MTRR_N16K 16
180 #define MTRR_N4K 64
181
182 /*
183 * Cyrix configuration registers, accessible as IO ports.
184 */
185 #define CCR0 0xc0 /* Configuration control register 0 */
186 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
187 non-cacheable */
188 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
189 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
190 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
191 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
192 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
193 state */
194 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
195 assoc */
196 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
197
198 #define CCR1 0xc1 /* Configuration control register 1 */
199 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
200 #define CCR1_SMI 0x02 /* Enables SMM pins */
201 #define CCR1_SMAC 0x04 /* System management memory access */
202 #define CCR1_MMAC 0x08 /* Main memory access */
203 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
204 #define CCR1_SM3 0x80 /* SMM address space address region 3 */
205
206 #define CCR2 0xc2
207 #define CCR2_WB 0x02 /* Enables WB cache interface pins */
208 #define CCR2_SADS 0x02 /* Slow ADS */
209 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
210 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
211 #define CCR2_WT1 0x10 /* WT region 1 */
212 #define CCR2_WPR1 0x10 /* Write-protect region 1 */
213 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
214 hold state. */
215 #define CCR2_BWRT 0x40 /* Enables burst write cycles */
216 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
217
218 #define CCR3 0xc3
219 #define CCR3_SMILOCK 0x01 /* SMM register lock */
220 #define CCR3_NMI 0x02 /* Enables NMI during SMM */
221 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */
222 #define CCR3_SMMMODE 0x08 /* SMM Mode */
223 #define CCR3_MAPEN0 0x10 /* Enables Map0 */
224 #define CCR3_MAPEN1 0x20 /* Enables Map1 */
225 #define CCR3_MAPEN2 0x40 /* Enables Map2 */
226 #define CCR3_MAPEN3 0x80 /* Enables Map3 */
227
228 #define CCR4 0xe8
229 #define CCR4_IOMASK 0x07
230 #define CCR4_MEM 0x08 /* Enables momory bypassing */
231 #define CCR4_DTE 0x10 /* Enables directory table entry cache */
232 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */
233 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
234
235 #define CCR5 0xe9
236 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
237 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
238 #define CCR5_LBR1 0x10 /* Local bus region 1 */
239 #define CCR5_ARREN 0x20 /* Enables ARR region */
240
241 #define CCR6 0xea
242
243 #define CCR7 0xeb
244
245 /* Performance Control Register (5x86 only). */
246 #define PCR0 0x20
247 #define PCR0_RSTK 0x01 /* Enables return stack */
248 #define PCR0_BTB 0x02 /* Enables branch target buffer */
249 #define PCR0_LOOP 0x04 /* Enables loop */
250 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
251 serialize pipe. */
252 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
253 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
254 #define PCR0_LSSER 0x80 /* Disable reorder */
255
256 /* Device Identification Registers */
257 #define DIR0 0xfe
258 #define DIR1 0xff
259
260 /*
261 * The following four 3-byte registers control the non-cacheable regions.
262 * These registers must be written as three separate bytes.
263 *
264 * NCRx+0: A31-A24 of starting address
265 * NCRx+1: A23-A16 of starting address
266 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
267 *
268 * The non-cacheable region's starting address must be aligned to the
269 * size indicated by the NCR_SIZE_xx field.
270 */
271 #define NCR1 0xc4
272 #define NCR2 0xc7
273 #define NCR3 0xca
274 #define NCR4 0xcd
275
276 #define NCR_SIZE_0K 0
277 #define NCR_SIZE_4K 1
278 #define NCR_SIZE_8K 2
279 #define NCR_SIZE_16K 3
280 #define NCR_SIZE_32K 4
281 #define NCR_SIZE_64K 5
282 #define NCR_SIZE_128K 6
283 #define NCR_SIZE_256K 7
284 #define NCR_SIZE_512K 8
285 #define NCR_SIZE_1M 9
286 #define NCR_SIZE_2M 10
287 #define NCR_SIZE_4M 11
288 #define NCR_SIZE_8M 12
289 #define NCR_SIZE_16M 13
290 #define NCR_SIZE_32M 14
291 #define NCR_SIZE_4G 15
292
293 /*
294 * The address region registers are used to specify the location and
295 * size for the eight address regions.
296 *
297 * ARRx + 0: A31-A24 of start address
298 * ARRx + 1: A23-A16 of start address
299 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
300 */
301 #define ARR0 0xc4
302 #define ARR1 0xc7
303 #define ARR2 0xca
304 #define ARR3 0xcd
305 #define ARR4 0xd0
306 #define ARR5 0xd3
307 #define ARR6 0xd6
308 #define ARR7 0xd9
309
310 #define ARR_SIZE_0K 0
311 #define ARR_SIZE_4K 1
312 #define ARR_SIZE_8K 2
313 #define ARR_SIZE_16K 3
314 #define ARR_SIZE_32K 4
315 #define ARR_SIZE_64K 5
316 #define ARR_SIZE_128K 6
317 #define ARR_SIZE_256K 7
318 #define ARR_SIZE_512K 8
319 #define ARR_SIZE_1M 9
320 #define ARR_SIZE_2M 10
321 #define ARR_SIZE_4M 11
322 #define ARR_SIZE_8M 12
323 #define ARR_SIZE_16M 13
324 #define ARR_SIZE_32M 14
325 #define ARR_SIZE_4G 15
326
327 /*
328 * The region control registers specify the attributes associated with
329 * the ARRx addres regions.
330 */
331 #define RCR0 0xdc
332 #define RCR1 0xdd
333 #define RCR2 0xde
334 #define RCR3 0xdf
335 #define RCR4 0xe0
336 #define RCR5 0xe1
337 #define RCR6 0xe2
338 #define RCR7 0xe3
339
340 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
341 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
342 #define RCR_WWO 0x02 /* Weak write ordering. */
343 #define RCR_WL 0x04 /* Weak locking. */
344 #define RCR_WG 0x08 /* Write gathering. */
345 #define RCR_WT 0x10 /* Write-through. */
346 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
347
348 /* AMD Write Allocate Top-Of-Memory and Control Register */
349 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
350 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
351 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
352
353
354 #ifndef LOCORE
355 static __inline u_char
356 read_cyrix_reg(u_char reg)
357 {
358 outb(0x22, reg);
359 return inb(0x23);
360 }
361
362 static __inline void
363 write_cyrix_reg(u_char reg, u_char data)
364 {
365 outb(0x22, reg);
366 outb(0x23, data);
367 }
368 #endif
369
370 #endif /* !_MACHINE_SPECIALREG_H_ */
Cache object: 903a3650ab5f28e0fe8fc2ee485b6651
|