The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/include/specialreg.h

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    1 /*-
    2  * Copyright (c) 1991 The Regents of the University of California.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 4. Neither the name of the University nor the names of its contributors
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  *      from: @(#)specialreg.h  7.1 (Berkeley) 5/9/91
   30  * $FreeBSD$
   31  */
   32 
   33 #ifndef _MACHINE_SPECIALREG_H_
   34 #define _MACHINE_SPECIALREG_H_
   35 
   36 /*
   37  * Bits in 386 special registers:
   38  */
   39 #define CR0_PE  0x00000001      /* Protected mode Enable */
   40 #define CR0_MP  0x00000002      /* "Math" (fpu) Present */
   41 #define CR0_EM  0x00000004      /* EMulate FPU instructions. (trap ESC only) */
   42 #define CR0_TS  0x00000008      /* Task Switched (if MP, trap ESC and WAIT) */
   43 #define CR0_PG  0x80000000      /* PaGing enable */
   44 
   45 /*
   46  * Bits in 486 special registers:
   47  */
   48 #define CR0_NE  0x00000020      /* Numeric Error enable (EX16 vs IRQ13) */
   49 #define CR0_WP  0x00010000      /* Write Protect (honor page protect in
   50                                                            all modes) */
   51 #define CR0_AM  0x00040000      /* Alignment Mask (set to enable AC flag) */
   52 #define CR0_NW  0x20000000      /* Not Write-through */
   53 #define CR0_CD  0x40000000      /* Cache Disable */
   54 
   55 /*
   56  * Bits in PPro special registers
   57  */
   58 #define CR4_VME 0x00000001      /* Virtual 8086 mode extensions */
   59 #define CR4_PVI 0x00000002      /* Protected-mode virtual interrupts */
   60 #define CR4_TSD 0x00000004      /* Time stamp disable */
   61 #define CR4_DE  0x00000008      /* Debugging extensions */
   62 #define CR4_PSE 0x00000010      /* Page size extensions */
   63 #define CR4_PAE 0x00000020      /* Physical address extension */
   64 #define CR4_MCE 0x00000040      /* Machine check enable */
   65 #define CR4_PGE 0x00000080      /* Page global enable */
   66 #define CR4_PCE 0x00000100      /* Performance monitoring counter enable */
   67 #define CR4_FXSR 0x00000200     /* Fast FPU save/restore used by OS */
   68 #define CR4_XMM 0x00000400      /* enable SIMD/MMX2 to use except 16 */
   69 
   70 /*
   71  * Bits in AMD64 special registers.  EFER is 64 bits wide.
   72  */
   73 #define EFER_NXE 0x000000800    /* PTE No-Execute bit enable (R/W) */
   74 
   75 /*
   76  * CPUID instruction features register
   77  */
   78 #define CPUID_FPU       0x00000001
   79 #define CPUID_VME       0x00000002
   80 #define CPUID_DE        0x00000004
   81 #define CPUID_PSE       0x00000008
   82 #define CPUID_TSC       0x00000010
   83 #define CPUID_MSR       0x00000020
   84 #define CPUID_PAE       0x00000040
   85 #define CPUID_MCE       0x00000080
   86 #define CPUID_CX8       0x00000100
   87 #define CPUID_APIC      0x00000200
   88 #define CPUID_B10       0x00000400
   89 #define CPUID_SEP       0x00000800
   90 #define CPUID_MTRR      0x00001000
   91 #define CPUID_PGE       0x00002000
   92 #define CPUID_MCA       0x00004000
   93 #define CPUID_CMOV      0x00008000
   94 #define CPUID_PAT       0x00010000
   95 #define CPUID_PSE36     0x00020000
   96 #define CPUID_PSN       0x00040000
   97 #define CPUID_CLFSH     0x00080000
   98 #define CPUID_B20       0x00100000
   99 #define CPUID_DS        0x00200000
  100 #define CPUID_ACPI      0x00400000
  101 #define CPUID_MMX       0x00800000
  102 #define CPUID_FXSR      0x01000000
  103 #define CPUID_SSE       0x02000000
  104 #define CPUID_XMM       0x02000000
  105 #define CPUID_SSE2      0x04000000
  106 #define CPUID_SS        0x08000000
  107 #define CPUID_HTT       0x10000000
  108 #define CPUID_TM        0x20000000
  109 #define CPUID_IA64      0x40000000
  110 #define CPUID_PBE       0x80000000
  111 
  112 #define CPUID2_SSE3     0x00000001
  113 #define CPUID2_DTES64   0x00000004
  114 #define CPUID2_MON      0x00000008
  115 #define CPUID2_DS_CPL   0x00000010
  116 #define CPUID2_VMX      0x00000020
  117 #define CPUID2_SMX      0x00000040
  118 #define CPUID2_EST      0x00000080
  119 #define CPUID2_TM2      0x00000100
  120 #define CPUID2_SSSE3    0x00000200
  121 #define CPUID2_CNXTID   0x00000400
  122 #define CPUID2_CX16     0x00002000
  123 #define CPUID2_XTPR     0x00004000
  124 #define CPUID2_PDCM     0x00008000
  125 #define CPUID2_DCA      0x00040000
  126 #define CPUID2_SSE41    0x00080000
  127 #define CPUID2_SSE42    0x00100000
  128 #define CPUID2_X2APIC   0x00200000
  129 #define CPUID2_POPCNT   0x00800000
  130 
  131 /*
  132  * Important bits in the AMD extended cpuid flags
  133  */
  134 #define AMDID_SYSCALL   0x00000800
  135 #define AMDID_MP        0x00080000
  136 #define AMDID_NX        0x00100000
  137 #define AMDID_EXT_MMX   0x00400000
  138 #define AMDID_FFXSR     0x01000000
  139 #define AMDID_PAGE1GB   0x04000000
  140 #define AMDID_RDTSCP    0x08000000
  141 #define AMDID_LM        0x20000000
  142 #define AMDID_EXT_3DNOW 0x40000000
  143 #define AMDID_3DNOW     0x80000000
  144 
  145 #define AMDID2_LAHF     0x00000001
  146 #define AMDID2_CMP      0x00000002
  147 #define AMDID2_SVM      0x00000004
  148 #define AMDID2_EXT_APIC 0x00000008
  149 #define AMDID2_CR8      0x00000010
  150 #define AMDID2_PREFETCH 0x00000100
  151 
  152 /*
  153  * CPUID instruction 1 eax info
  154  */
  155 #define CPUID_STEPPING          0x0000000f
  156 #define CPUID_MODEL             0x000000f0
  157 #define CPUID_FAMILY            0x00000f00
  158 #define CPUID_EXT_MODEL         0x000f0000
  159 #define CPUID_EXT_FAMILY        0x0ff00000
  160 #define I386_CPU_MODEL(id) \
  161     ((((id) & CPUID_MODEL) >> 4) | \
  162     ((((id) & CPUID_FAMILY) >= 0x600) ? \
  163     (((id) & CPUID_EXT_MODEL) >> 12) : 0))
  164 #define I386_CPU_FAMILY(id) \
  165     ((((id) & CPUID_FAMILY) >> 8) + \
  166     ((((id) & CPUID_FAMILY) == 0xf00) ? \
  167     (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
  168 
  169 /*
  170  * CPUID instruction 1 ebx info
  171  */
  172 #define CPUID_BRAND_INDEX       0x000000ff
  173 #define CPUID_CLFUSH_SIZE       0x0000ff00
  174 #define CPUID_HTT_CORES         0x00ff0000
  175 #define CPUID_LOCAL_APIC_ID     0xff000000
  176 
  177 /*
  178  * AMD extended function 8000_0007h edx info
  179  */
  180 #define AMDPM_TS                0x00000001
  181 #define AMDPM_FID               0x00000002
  182 #define AMDPM_VID               0x00000004
  183 #define AMDPM_TTP               0x00000008
  184 #define AMDPM_TM                0x00000010
  185 #define AMDPM_STC               0x00000020
  186 #define AMDPM_100MHZ_STEPS      0x00000040
  187 #define AMDPM_HW_PSTATE         0x00000080
  188 #define AMDPM_TSC_INVARIANT     0x00000100
  189 
  190 /*
  191  * AMD extended function 8000_0008h ecx info
  192  */
  193 #define AMDID_CMP_CORES         0x000000ff
  194 
  195 /*
  196  * CPUID manufacturers identifiers
  197  */
  198 #define INTEL_VENDOR_ID "GenuineIntel"
  199 #define AMD_VENDOR_ID   "AuthenticAMD"
  200 
  201 /*
  202  * Model-specific registers for the i386 family
  203  */
  204 #define MSR_P5_MC_ADDR          0x000
  205 #define MSR_P5_MC_TYPE          0x001
  206 #define MSR_TSC                 0x010
  207 #define MSR_P5_CESR             0x011
  208 #define MSR_P5_CTR0             0x012
  209 #define MSR_P5_CTR1             0x013
  210 #define MSR_IA32_PLATFORM_ID    0x017
  211 #define MSR_APICBASE            0x01b
  212 #define MSR_EBL_CR_POWERON      0x02a
  213 #define MSR_TEST_CTL            0x033
  214 #define MSR_BIOS_UPDT_TRIG      0x079
  215 #define MSR_BBL_CR_D0           0x088
  216 #define MSR_BBL_CR_D1           0x089
  217 #define MSR_BBL_CR_D2           0x08a
  218 #define MSR_BIOS_SIGN           0x08b
  219 #define MSR_PERFCTR0            0x0c1
  220 #define MSR_PERFCTR1            0x0c2
  221 #define MSR_IA32_EXT_CONFIG     0x0ee   /* Undocumented. Core Solo/Duo only */
  222 #define MSR_MTRRcap             0x0fe
  223 #define MSR_BBL_CR_ADDR         0x116
  224 #define MSR_BBL_CR_DECC         0x118
  225 #define MSR_BBL_CR_CTL          0x119
  226 #define MSR_BBL_CR_TRIG         0x11a
  227 #define MSR_BBL_CR_BUSY         0x11b
  228 #define MSR_BBL_CR_CTL3         0x11e
  229 #define MSR_SYSENTER_CS_MSR     0x174
  230 #define MSR_SYSENTER_ESP_MSR    0x175
  231 #define MSR_SYSENTER_EIP_MSR    0x176
  232 #define MSR_MCG_CAP             0x179
  233 #define MSR_MCG_STATUS          0x17a
  234 #define MSR_MCG_CTL             0x17b
  235 #define MSR_EVNTSEL0            0x186
  236 #define MSR_EVNTSEL1            0x187
  237 #define MSR_THERM_CONTROL       0x19a
  238 #define MSR_THERM_INTERRUPT     0x19b
  239 #define MSR_THERM_STATUS        0x19c
  240 #define MSR_IA32_MISC_ENABLE    0x1a0
  241 #define MSR_DEBUGCTLMSR         0x1d9
  242 #define MSR_LASTBRANCHFROMIP    0x1db
  243 #define MSR_LASTBRANCHTOIP      0x1dc
  244 #define MSR_LASTINTFROMIP       0x1dd
  245 #define MSR_LASTINTTOIP         0x1de
  246 #define MSR_ROB_CR_BKUPTMPDR6   0x1e0
  247 #define MSR_MTRRVarBase         0x200
  248 #define MSR_MTRR64kBase         0x250
  249 #define MSR_MTRR16kBase         0x258
  250 #define MSR_MTRR4kBase          0x268
  251 #define MSR_PAT                 0x277
  252 #define MSR_MTRRdefType         0x2ff
  253 #define MSR_MC0_CTL             0x400
  254 #define MSR_MC0_STATUS          0x401
  255 #define MSR_MC0_ADDR            0x402
  256 #define MSR_MC0_MISC            0x403
  257 #define MSR_MC1_CTL             0x404
  258 #define MSR_MC1_STATUS          0x405
  259 #define MSR_MC1_ADDR            0x406
  260 #define MSR_MC1_MISC            0x407
  261 #define MSR_MC2_CTL             0x408
  262 #define MSR_MC2_STATUS          0x409
  263 #define MSR_MC2_ADDR            0x40a
  264 #define MSR_MC2_MISC            0x40b
  265 #define MSR_MC3_CTL             0x40c
  266 #define MSR_MC3_STATUS          0x40d
  267 #define MSR_MC3_ADDR            0x40e
  268 #define MSR_MC3_MISC            0x40f
  269 #define MSR_MC4_CTL             0x410
  270 #define MSR_MC4_STATUS          0x411
  271 #define MSR_MC4_ADDR            0x412
  272 #define MSR_MC4_MISC            0x413
  273 
  274 /*
  275  * Constants related to MSR's.
  276  */
  277 #define APICBASE_RESERVED       0x000006ff
  278 #define APICBASE_BSP            0x00000100
  279 #define APICBASE_ENABLED        0x00000800
  280 #define APICBASE_ADDRESS        0xfffff000
  281 
  282 /*
  283  * PAT modes.
  284  */
  285 #define PAT_UNCACHEABLE         0x00
  286 #define PAT_WRITE_COMBINING     0x01
  287 #define PAT_WRITE_THROUGH       0x04
  288 #define PAT_WRITE_PROTECTED     0x05
  289 #define PAT_WRITE_BACK          0x06
  290 #define PAT_UNCACHED            0x07
  291 #define PAT_VALUE(i, m)         ((long long)(m) << (8 * (i)))
  292 #define PAT_MASK(i)             PAT_VALUE(i, 0xff)
  293 
  294 /*
  295  * Constants related to MTRRs
  296  */
  297 #define MTRR_UNCACHEABLE        0x00
  298 #define MTRR_WRITE_COMBINING    0x01
  299 #define MTRR_WRITE_THROUGH      0x04
  300 #define MTRR_WRITE_PROTECTED    0x05
  301 #define MTRR_WRITE_BACK         0x06
  302 #define MTRR_N64K               8       /* numbers of fixed-size entries */
  303 #define MTRR_N16K               16
  304 #define MTRR_N4K                64
  305 #define MTRR_CAP_WC             0x0000000000000400ULL
  306 #define MTRR_CAP_FIXED          0x0000000000000100ULL
  307 #define MTRR_CAP_VCNT           0x00000000000000ffULL
  308 #define MTRR_DEF_ENABLE         0x0000000000000800ULL
  309 #define MTRR_DEF_FIXED_ENABLE   0x0000000000000400ULL
  310 #define MTRR_DEF_TYPE           0x00000000000000ffULL
  311 #define MTRR_PHYSBASE_PHYSBASE  0x000ffffffffff000ULL
  312 #define MTRR_PHYSBASE_TYPE      0x00000000000000ffULL
  313 #define MTRR_PHYSMASK_PHYSMASK  0x000ffffffffff000ULL
  314 #define MTRR_PHYSMASK_VALID     0x0000000000000800ULL
  315 
  316 /*
  317  * Cyrix configuration registers, accessible as IO ports.
  318  */
  319 #define CCR0                    0xc0    /* Configuration control register 0 */
  320 #define CCR0_NC0                0x01    /* First 64K of each 1M memory region is
  321                                                                    non-cacheable */
  322 #define CCR0_NC1                0x02    /* 640K-1M region is non-cacheable */
  323 #define CCR0_A20M               0x04    /* Enables A20M# input pin */
  324 #define CCR0_KEN                0x08    /* Enables KEN# input pin */
  325 #define CCR0_FLUSH              0x10    /* Enables FLUSH# input pin */
  326 #define CCR0_BARB               0x20    /* Flushes internal cache when entering hold
  327                                                                    state */
  328 #define CCR0_CO                 0x40    /* Cache org: 1=direct mapped, 0=2x set
  329                                                                    assoc */
  330 #define CCR0_SUSPEND    0x80    /* Enables SUSP# and SUSPA# pins */
  331 
  332 #define CCR1                    0xc1    /* Configuration control register 1 */
  333 #define CCR1_RPL                0x01    /* Enables RPLSET and RPLVAL# pins */
  334 #define CCR1_SMI                0x02    /* Enables SMM pins */
  335 #define CCR1_SMAC               0x04    /* System management memory access */
  336 #define CCR1_MMAC               0x08    /* Main memory access */
  337 #define CCR1_NO_LOCK    0x10    /* Negate LOCK# */
  338 #define CCR1_SM3                0x80    /* SMM address space address region 3 */
  339 
  340 #define CCR2                    0xc2
  341 #define CCR2_WB                 0x02    /* Enables WB cache interface pins */
  342 #define CCR2_SADS               0x02    /* Slow ADS */
  343 #define CCR2_LOCK_NW    0x04    /* LOCK NW Bit */
  344 #define CCR2_SUSP_HLT   0x08    /* Suspend on HALT */
  345 #define CCR2_WT1                0x10    /* WT region 1 */
  346 #define CCR2_WPR1               0x10    /* Write-protect region 1 */
  347 #define CCR2_BARB               0x20    /* Flushes write-back cache when entering
  348                                                                    hold state. */
  349 #define CCR2_BWRT               0x40    /* Enables burst write cycles */
  350 #define CCR2_USE_SUSP   0x80    /* Enables suspend pins */
  351 
  352 #define CCR3                    0xc3
  353 #define CCR3_SMILOCK    0x01    /* SMM register lock */
  354 #define CCR3_NMI                0x02    /* Enables NMI during SMM */
  355 #define CCR3_LINBRST    0x04    /* Linear address burst cycles */
  356 #define CCR3_SMMMODE    0x08    /* SMM Mode */
  357 #define CCR3_MAPEN0             0x10    /* Enables Map0 */
  358 #define CCR3_MAPEN1             0x20    /* Enables Map1 */
  359 #define CCR3_MAPEN2             0x40    /* Enables Map2 */
  360 #define CCR3_MAPEN3             0x80    /* Enables Map3 */
  361 
  362 #define CCR4                    0xe8
  363 #define CCR4_IOMASK             0x07
  364 #define CCR4_MEM                0x08    /* Enables momory bypassing */
  365 #define CCR4_DTE                0x10    /* Enables directory table entry cache */
  366 #define CCR4_FASTFPE    0x20    /* Fast FPU exception */
  367 #define CCR4_CPUID              0x80    /* Enables CPUID instruction */
  368 
  369 #define CCR5                    0xe9
  370 #define CCR5_WT_ALLOC   0x01    /* Write-through allocate */
  371 #define CCR5_SLOP               0x02    /* LOOP instruction slowed down */
  372 #define CCR5_LBR1               0x10    /* Local bus region 1 */
  373 #define CCR5_ARREN              0x20    /* Enables ARR region */
  374 
  375 #define CCR6                    0xea
  376 
  377 #define CCR7                    0xeb
  378 
  379 /* Performance Control Register (5x86 only). */
  380 #define PCR0                    0x20
  381 #define PCR0_RSTK               0x01    /* Enables return stack */
  382 #define PCR0_BTB                0x02    /* Enables branch target buffer */
  383 #define PCR0_LOOP               0x04    /* Enables loop */
  384 #define PCR0_AIS                0x08    /* Enables all instrcutions stalled to
  385                                                                    serialize pipe. */
  386 #define PCR0_MLR                0x10    /* Enables reordering of misaligned loads */
  387 #define PCR0_BTBRT              0x40    /* Enables BTB test register. */
  388 #define PCR0_LSSER              0x80    /* Disable reorder */
  389 
  390 /* Device Identification Registers */
  391 #define DIR0                    0xfe
  392 #define DIR1                    0xff
  393 
  394 /*
  395  * The following four 3-byte registers control the non-cacheable regions.
  396  * These registers must be written as three separate bytes.
  397  *
  398  * NCRx+0: A31-A24 of starting address
  399  * NCRx+1: A23-A16 of starting address
  400  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
  401  *
  402  * The non-cacheable region's starting address must be aligned to the
  403  * size indicated by the NCR_SIZE_xx field.
  404  */
  405 #define NCR1    0xc4
  406 #define NCR2    0xc7
  407 #define NCR3    0xca
  408 #define NCR4    0xcd
  409 
  410 #define NCR_SIZE_0K     0
  411 #define NCR_SIZE_4K     1
  412 #define NCR_SIZE_8K     2
  413 #define NCR_SIZE_16K    3
  414 #define NCR_SIZE_32K    4
  415 #define NCR_SIZE_64K    5
  416 #define NCR_SIZE_128K   6
  417 #define NCR_SIZE_256K   7
  418 #define NCR_SIZE_512K   8
  419 #define NCR_SIZE_1M     9
  420 #define NCR_SIZE_2M     10
  421 #define NCR_SIZE_4M     11
  422 #define NCR_SIZE_8M     12
  423 #define NCR_SIZE_16M    13
  424 #define NCR_SIZE_32M    14
  425 #define NCR_SIZE_4G     15
  426 
  427 /*
  428  * The address region registers are used to specify the location and
  429  * size for the eight address regions.
  430  *
  431  * ARRx + 0: A31-A24 of start address
  432  * ARRx + 1: A23-A16 of start address
  433  * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
  434  */
  435 #define ARR0    0xc4
  436 #define ARR1    0xc7
  437 #define ARR2    0xca
  438 #define ARR3    0xcd
  439 #define ARR4    0xd0
  440 #define ARR5    0xd3
  441 #define ARR6    0xd6
  442 #define ARR7    0xd9
  443 
  444 #define ARR_SIZE_0K             0
  445 #define ARR_SIZE_4K             1
  446 #define ARR_SIZE_8K             2
  447 #define ARR_SIZE_16K    3
  448 #define ARR_SIZE_32K    4
  449 #define ARR_SIZE_64K    5
  450 #define ARR_SIZE_128K   6
  451 #define ARR_SIZE_256K   7
  452 #define ARR_SIZE_512K   8
  453 #define ARR_SIZE_1M             9
  454 #define ARR_SIZE_2M             10
  455 #define ARR_SIZE_4M             11
  456 #define ARR_SIZE_8M             12
  457 #define ARR_SIZE_16M    13
  458 #define ARR_SIZE_32M    14
  459 #define ARR_SIZE_4G             15
  460 
  461 /*
  462  * The region control registers specify the attributes associated with
  463  * the ARRx addres regions.
  464  */
  465 #define RCR0    0xdc
  466 #define RCR1    0xdd
  467 #define RCR2    0xde
  468 #define RCR3    0xdf
  469 #define RCR4    0xe0
  470 #define RCR5    0xe1
  471 #define RCR6    0xe2
  472 #define RCR7    0xe3
  473 
  474 #define RCR_RCD 0x01    /* Disables caching for ARRx (x = 0-6). */
  475 #define RCR_RCE 0x01    /* Enables caching for ARR7. */
  476 #define RCR_WWO 0x02    /* Weak write ordering. */
  477 #define RCR_WL  0x04    /* Weak locking. */
  478 #define RCR_WG  0x08    /* Write gathering. */
  479 #define RCR_WT  0x10    /* Write-through. */
  480 #define RCR_NLB 0x20    /* LBA# pin is not asserted. */
  481 
  482 /* AMD Write Allocate Top-Of-Memory and Control Register */
  483 #define AMD_WT_ALLOC_TME        0x40000 /* top-of-memory enable */
  484 #define AMD_WT_ALLOC_PRE        0x20000 /* programmable range enable */
  485 #define AMD_WT_ALLOC_FRE        0x10000 /* fixed (A0000-FFFFF) range enable */
  486 
  487 /* AMD64 MSR's */
  488 #define MSR_EFER        0xc0000080      /* extended features */
  489 #define MSR_K8_UCODE_UPDATE     0xc0010020      /* update microcode */
  490 
  491 /* VIA ACE crypto featureset: for via_feature_rng */
  492 #define VIA_HAS_RNG             1       /* cpu has RNG */
  493 
  494 /* VIA ACE crypto featureset: for via_feature_xcrypt */
  495 #define VIA_HAS_AES             1       /* cpu has AES */
  496 #define VIA_HAS_SHA             2       /* cpu has SHA1 & SHA256 */
  497 #define VIA_HAS_MM              4       /* cpu has RSA instructions */
  498 #define VIA_HAS_AESCTR          8       /* cpu has AES-CTR instructions */
  499 
  500 /* Centaur Extended Feature flags */
  501 #define VIA_CPUID_HAS_RNG       0x000004
  502 #define VIA_CPUID_DO_RNG        0x000008
  503 #define VIA_CPUID_HAS_ACE       0x000040
  504 #define VIA_CPUID_DO_ACE        0x000080
  505 #define VIA_CPUID_HAS_ACE2      0x000100
  506 #define VIA_CPUID_DO_ACE2       0x000200
  507 #define VIA_CPUID_HAS_PHE       0x000400
  508 #define VIA_CPUID_DO_PHE        0x000800
  509 #define VIA_CPUID_HAS_PMM       0x001000
  510 #define VIA_CPUID_DO_PMM        0x002000
  511 
  512 /* VIA ACE xcrypt-* instruction context control options */
  513 #define VIA_CRYPT_CWLO_ROUND_M          0x0000000f
  514 #define VIA_CRYPT_CWLO_ALG_M            0x00000070
  515 #define VIA_CRYPT_CWLO_ALG_AES          0x00000000
  516 #define VIA_CRYPT_CWLO_KEYGEN_M         0x00000080
  517 #define VIA_CRYPT_CWLO_KEYGEN_HW        0x00000000
  518 #define VIA_CRYPT_CWLO_KEYGEN_SW        0x00000080
  519 #define VIA_CRYPT_CWLO_NORMAL           0x00000000
  520 #define VIA_CRYPT_CWLO_INTERMEDIATE     0x00000100
  521 #define VIA_CRYPT_CWLO_ENCRYPT          0x00000000
  522 #define VIA_CRYPT_CWLO_DECRYPT          0x00000200
  523 #define VIA_CRYPT_CWLO_KEY128           0x0000000a      /* 128bit, 10 rds */
  524 #define VIA_CRYPT_CWLO_KEY192           0x0000040c      /* 192bit, 12 rds */
  525 #define VIA_CRYPT_CWLO_KEY256           0x0000080e      /* 256bit, 15 rds */
  526 
  527 #ifndef LOCORE
  528 static __inline u_char
  529 read_cyrix_reg(u_char reg)
  530 {
  531         outb(0x22, reg);
  532         return inb(0x23);
  533 }
  534 
  535 static __inline void
  536 write_cyrix_reg(u_char reg, u_char data)
  537 {
  538         outb(0x22, reg);
  539         outb(0x23, data);
  540 }
  541 #endif
  542 
  543 #endif /* !_MACHINE_SPECIALREG_H_ */

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