1 /*-
2 * Copyright (c) 1991 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 4. Neither the name of the University nor the names of its contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 *
29 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
30 * $FreeBSD: releng/8.1/sys/i386/include/specialreg.h 207955 2010-05-12 09:34:10Z kib $
31 */
32
33 #ifndef _MACHINE_SPECIALREG_H_
34 #define _MACHINE_SPECIALREG_H_
35
36 /*
37 * Bits in 386 special registers:
38 */
39 #define CR0_PE 0x00000001 /* Protected mode Enable */
40 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
41 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
42 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
43 #define CR0_PG 0x80000000 /* PaGing enable */
44
45 /*
46 * Bits in 486 special registers:
47 */
48 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in
50 all modes) */
51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52 #define CR0_NW 0x20000000 /* Not Write-through */
53 #define CR0_CD 0x40000000 /* Cache Disable */
54
55 /*
56 * Bits in PPro special registers
57 */
58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
60 #define CR4_TSD 0x00000004 /* Time stamp disable */
61 #define CR4_DE 0x00000008 /* Debugging extensions */
62 #define CR4_PSE 0x00000010 /* Page size extensions */
63 #define CR4_PAE 0x00000020 /* Physical address extension */
64 #define CR4_MCE 0x00000040 /* Machine check enable */
65 #define CR4_PGE 0x00000080 /* Page global enable */
66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
68 #define CR4_XMM 0x00000400 /* enable SIMD/MMX2 to use except 16 */
69
70 /*
71 * Bits in AMD64 special registers. EFER is 64 bits wide.
72 */
73 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
74
75 /*
76 * CPUID instruction features register
77 */
78 #define CPUID_FPU 0x00000001
79 #define CPUID_VME 0x00000002
80 #define CPUID_DE 0x00000004
81 #define CPUID_PSE 0x00000008
82 #define CPUID_TSC 0x00000010
83 #define CPUID_MSR 0x00000020
84 #define CPUID_PAE 0x00000040
85 #define CPUID_MCE 0x00000080
86 #define CPUID_CX8 0x00000100
87 #define CPUID_APIC 0x00000200
88 #define CPUID_B10 0x00000400
89 #define CPUID_SEP 0x00000800
90 #define CPUID_MTRR 0x00001000
91 #define CPUID_PGE 0x00002000
92 #define CPUID_MCA 0x00004000
93 #define CPUID_CMOV 0x00008000
94 #define CPUID_PAT 0x00010000
95 #define CPUID_PSE36 0x00020000
96 #define CPUID_PSN 0x00040000
97 #define CPUID_CLFSH 0x00080000
98 #define CPUID_B20 0x00100000
99 #define CPUID_DS 0x00200000
100 #define CPUID_ACPI 0x00400000
101 #define CPUID_MMX 0x00800000
102 #define CPUID_FXSR 0x01000000
103 #define CPUID_SSE 0x02000000
104 #define CPUID_XMM 0x02000000
105 #define CPUID_SSE2 0x04000000
106 #define CPUID_SS 0x08000000
107 #define CPUID_HTT 0x10000000
108 #define CPUID_TM 0x20000000
109 #define CPUID_IA64 0x40000000
110 #define CPUID_PBE 0x80000000
111
112 #define CPUID2_SSE3 0x00000001
113 #define CPUID2_PCLMULQDQ 0x00000002
114 #define CPUID2_DTES64 0x00000004
115 #define CPUID2_MON 0x00000008
116 #define CPUID2_DS_CPL 0x00000010
117 #define CPUID2_VMX 0x00000020
118 #define CPUID2_SMX 0x00000040
119 #define CPUID2_EST 0x00000080
120 #define CPUID2_TM2 0x00000100
121 #define CPUID2_SSSE3 0x00000200
122 #define CPUID2_CNXTID 0x00000400
123 #define CPUID2_CX16 0x00002000
124 #define CPUID2_XTPR 0x00004000
125 #define CPUID2_PDCM 0x00008000
126 #define CPUID2_DCA 0x00040000
127 #define CPUID2_SSE41 0x00080000
128 #define CPUID2_SSE42 0x00100000
129 #define CPUID2_X2APIC 0x00200000
130 #define CPUID2_MOVBE 0x00400000
131 #define CPUID2_POPCNT 0x00800000
132 #define CPUID2_AESNI 0x02000000
133
134 /*
135 * Important bits in the AMD extended cpuid flags
136 */
137 #define AMDID_SYSCALL 0x00000800
138 #define AMDID_MP 0x00080000
139 #define AMDID_NX 0x00100000
140 #define AMDID_EXT_MMX 0x00400000
141 #define AMDID_FFXSR 0x01000000
142 #define AMDID_PAGE1GB 0x04000000
143 #define AMDID_RDTSCP 0x08000000
144 #define AMDID_LM 0x20000000
145 #define AMDID_EXT_3DNOW 0x40000000
146 #define AMDID_3DNOW 0x80000000
147
148 #define AMDID2_LAHF 0x00000001
149 #define AMDID2_CMP 0x00000002
150 #define AMDID2_SVM 0x00000004
151 #define AMDID2_EXT_APIC 0x00000008
152 #define AMDID2_CR8 0x00000010
153 #define AMDID2_ABM 0x00000020
154 #define AMDID2_SSE4A 0x00000040
155 #define AMDID2_MAS 0x00000080
156 #define AMDID2_PREFETCH 0x00000100
157 #define AMDID2_OSVW 0x00000200
158 #define AMDID2_IBS 0x00000400
159 #define AMDID2_SSE5 0x00000800
160 #define AMDID2_SKINIT 0x00001000
161 #define AMDID2_WDT 0x00002000
162
163 /*
164 * CPUID instruction 1 eax info
165 */
166 #define CPUID_STEPPING 0x0000000f
167 #define CPUID_MODEL 0x000000f0
168 #define CPUID_FAMILY 0x00000f00
169 #define CPUID_EXT_MODEL 0x000f0000
170 #define CPUID_EXT_FAMILY 0x0ff00000
171 #define CPUID_TO_MODEL(id) \
172 ((((id) & CPUID_MODEL) >> 4) | \
173 ((((id) & CPUID_FAMILY) >= 0x600) ? \
174 (((id) & CPUID_EXT_MODEL) >> 12) : 0))
175 #define CPUID_TO_FAMILY(id) \
176 ((((id) & CPUID_FAMILY) >> 8) + \
177 ((((id) & CPUID_FAMILY) == 0xf00) ? \
178 (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
179
180 /*
181 * CPUID instruction 1 ebx info
182 */
183 #define CPUID_BRAND_INDEX 0x000000ff
184 #define CPUID_CLFUSH_SIZE 0x0000ff00
185 #define CPUID_HTT_CORES 0x00ff0000
186 #define CPUID_LOCAL_APIC_ID 0xff000000
187
188 /*
189 * CPUID instruction 0xb ebx info.
190 */
191 #define CPUID_TYPE_INVAL 0
192 #define CPUID_TYPE_SMT 1
193 #define CPUID_TYPE_CORE 2
194
195 /*
196 * AMD extended function 8000_0007h edx info
197 */
198 #define AMDPM_TS 0x00000001
199 #define AMDPM_FID 0x00000002
200 #define AMDPM_VID 0x00000004
201 #define AMDPM_TTP 0x00000008
202 #define AMDPM_TM 0x00000010
203 #define AMDPM_STC 0x00000020
204 #define AMDPM_100MHZ_STEPS 0x00000040
205 #define AMDPM_HW_PSTATE 0x00000080
206 #define AMDPM_TSC_INVARIANT 0x00000100
207
208 /*
209 * AMD extended function 8000_0008h ecx info
210 */
211 #define AMDID_CMP_CORES 0x000000ff
212
213 /*
214 * CPUID manufacturers identifiers
215 */
216 #define AMD_VENDOR_ID "AuthenticAMD"
217 #define CENTAUR_VENDOR_ID "CentaurHauls"
218 #define CYRIX_VENDOR_ID "CyrixInstead"
219 #define INTEL_VENDOR_ID "GenuineIntel"
220 #define NEXGEN_VENDOR_ID "NexGenDriven"
221 #define NSC_VENDOR_ID "Geode by NSC"
222 #define RISE_VENDOR_ID "RiseRiseRise"
223 #define SIS_VENDOR_ID "SiS SiS SiS "
224 #define TRANSMETA_VENDOR_ID "GenuineTMx86"
225 #define UMC_VENDOR_ID "UMC UMC UMC "
226
227 /*
228 * Model-specific registers for the i386 family
229 */
230 #define MSR_P5_MC_ADDR 0x000
231 #define MSR_P5_MC_TYPE 0x001
232 #define MSR_TSC 0x010
233 #define MSR_P5_CESR 0x011
234 #define MSR_P5_CTR0 0x012
235 #define MSR_P5_CTR1 0x013
236 #define MSR_IA32_PLATFORM_ID 0x017
237 #define MSR_APICBASE 0x01b
238 #define MSR_EBL_CR_POWERON 0x02a
239 #define MSR_TEST_CTL 0x033
240 #define MSR_BIOS_UPDT_TRIG 0x079
241 #define MSR_BBL_CR_D0 0x088
242 #define MSR_BBL_CR_D1 0x089
243 #define MSR_BBL_CR_D2 0x08a
244 #define MSR_BIOS_SIGN 0x08b
245 #define MSR_PERFCTR0 0x0c1
246 #define MSR_PERFCTR1 0x0c2
247 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
248 #define MSR_MTRRcap 0x0fe
249 #define MSR_BBL_CR_ADDR 0x116
250 #define MSR_BBL_CR_DECC 0x118
251 #define MSR_BBL_CR_CTL 0x119
252 #define MSR_BBL_CR_TRIG 0x11a
253 #define MSR_BBL_CR_BUSY 0x11b
254 #define MSR_BBL_CR_CTL3 0x11e
255 #define MSR_SYSENTER_CS_MSR 0x174
256 #define MSR_SYSENTER_ESP_MSR 0x175
257 #define MSR_SYSENTER_EIP_MSR 0x176
258 #define MSR_MCG_CAP 0x179
259 #define MSR_MCG_STATUS 0x17a
260 #define MSR_MCG_CTL 0x17b
261 #define MSR_EVNTSEL0 0x186
262 #define MSR_EVNTSEL1 0x187
263 #define MSR_THERM_CONTROL 0x19a
264 #define MSR_THERM_INTERRUPT 0x19b
265 #define MSR_THERM_STATUS 0x19c
266 #define MSR_IA32_MISC_ENABLE 0x1a0
267 #define MSR_DEBUGCTLMSR 0x1d9
268 #define MSR_LASTBRANCHFROMIP 0x1db
269 #define MSR_LASTBRANCHTOIP 0x1dc
270 #define MSR_LASTINTFROMIP 0x1dd
271 #define MSR_LASTINTTOIP 0x1de
272 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
273 #define MSR_MTRRVarBase 0x200
274 #define MSR_MTRR64kBase 0x250
275 #define MSR_MTRR16kBase 0x258
276 #define MSR_MTRR4kBase 0x268
277 #define MSR_PAT 0x277
278 #define MSR_MC0_CTL2 0x280
279 #define MSR_MTRRdefType 0x2ff
280 #define MSR_MC0_CTL 0x400
281 #define MSR_MC0_STATUS 0x401
282 #define MSR_MC0_ADDR 0x402
283 #define MSR_MC0_MISC 0x403
284 #define MSR_MC1_CTL 0x404
285 #define MSR_MC1_STATUS 0x405
286 #define MSR_MC1_ADDR 0x406
287 #define MSR_MC1_MISC 0x407
288 #define MSR_MC2_CTL 0x408
289 #define MSR_MC2_STATUS 0x409
290 #define MSR_MC2_ADDR 0x40a
291 #define MSR_MC2_MISC 0x40b
292 #define MSR_MC3_CTL 0x40c
293 #define MSR_MC3_STATUS 0x40d
294 #define MSR_MC3_ADDR 0x40e
295 #define MSR_MC3_MISC 0x40f
296 #define MSR_MC4_CTL 0x410
297 #define MSR_MC4_STATUS 0x411
298 #define MSR_MC4_ADDR 0x412
299 #define MSR_MC4_MISC 0x413
300
301 /*
302 * Constants related to MSR's.
303 */
304 #define APICBASE_RESERVED 0x000006ff
305 #define APICBASE_BSP 0x00000100
306 #define APICBASE_ENABLED 0x00000800
307 #define APICBASE_ADDRESS 0xfffff000
308
309 /*
310 * PAT modes.
311 */
312 #define PAT_UNCACHEABLE 0x00
313 #define PAT_WRITE_COMBINING 0x01
314 #define PAT_WRITE_THROUGH 0x04
315 #define PAT_WRITE_PROTECTED 0x05
316 #define PAT_WRITE_BACK 0x06
317 #define PAT_UNCACHED 0x07
318 #define PAT_VALUE(i, m) ((long long)(m) << (8 * (i)))
319 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
320
321 /*
322 * Constants related to MTRRs
323 */
324 #define MTRR_UNCACHEABLE 0x00
325 #define MTRR_WRITE_COMBINING 0x01
326 #define MTRR_WRITE_THROUGH 0x04
327 #define MTRR_WRITE_PROTECTED 0x05
328 #define MTRR_WRITE_BACK 0x06
329 #define MTRR_N64K 8 /* numbers of fixed-size entries */
330 #define MTRR_N16K 16
331 #define MTRR_N4K 64
332 #define MTRR_CAP_WC 0x0000000000000400
333 #define MTRR_CAP_FIXED 0x0000000000000100
334 #define MTRR_CAP_VCNT 0x00000000000000ff
335 #define MTRR_DEF_ENABLE 0x0000000000000800
336 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400
337 #define MTRR_DEF_TYPE 0x00000000000000ff
338 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000
339 #define MTRR_PHYSBASE_TYPE 0x00000000000000ff
340 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000
341 #define MTRR_PHYSMASK_VALID 0x0000000000000800
342
343 /*
344 * Cyrix configuration registers, accessible as IO ports.
345 */
346 #define CCR0 0xc0 /* Configuration control register 0 */
347 #define CCR0_NC0 0x01 /* First 64K of each 1M memory region is
348 non-cacheable */
349 #define CCR0_NC1 0x02 /* 640K-1M region is non-cacheable */
350 #define CCR0_A20M 0x04 /* Enables A20M# input pin */
351 #define CCR0_KEN 0x08 /* Enables KEN# input pin */
352 #define CCR0_FLUSH 0x10 /* Enables FLUSH# input pin */
353 #define CCR0_BARB 0x20 /* Flushes internal cache when entering hold
354 state */
355 #define CCR0_CO 0x40 /* Cache org: 1=direct mapped, 0=2x set
356 assoc */
357 #define CCR0_SUSPEND 0x80 /* Enables SUSP# and SUSPA# pins */
358
359 #define CCR1 0xc1 /* Configuration control register 1 */
360 #define CCR1_RPL 0x01 /* Enables RPLSET and RPLVAL# pins */
361 #define CCR1_SMI 0x02 /* Enables SMM pins */
362 #define CCR1_SMAC 0x04 /* System management memory access */
363 #define CCR1_MMAC 0x08 /* Main memory access */
364 #define CCR1_NO_LOCK 0x10 /* Negate LOCK# */
365 #define CCR1_SM3 0x80 /* SMM address space address region 3 */
366
367 #define CCR2 0xc2
368 #define CCR2_WB 0x02 /* Enables WB cache interface pins */
369 #define CCR2_SADS 0x02 /* Slow ADS */
370 #define CCR2_LOCK_NW 0x04 /* LOCK NW Bit */
371 #define CCR2_SUSP_HLT 0x08 /* Suspend on HALT */
372 #define CCR2_WT1 0x10 /* WT region 1 */
373 #define CCR2_WPR1 0x10 /* Write-protect region 1 */
374 #define CCR2_BARB 0x20 /* Flushes write-back cache when entering
375 hold state. */
376 #define CCR2_BWRT 0x40 /* Enables burst write cycles */
377 #define CCR2_USE_SUSP 0x80 /* Enables suspend pins */
378
379 #define CCR3 0xc3
380 #define CCR3_SMILOCK 0x01 /* SMM register lock */
381 #define CCR3_NMI 0x02 /* Enables NMI during SMM */
382 #define CCR3_LINBRST 0x04 /* Linear address burst cycles */
383 #define CCR3_SMMMODE 0x08 /* SMM Mode */
384 #define CCR3_MAPEN0 0x10 /* Enables Map0 */
385 #define CCR3_MAPEN1 0x20 /* Enables Map1 */
386 #define CCR3_MAPEN2 0x40 /* Enables Map2 */
387 #define CCR3_MAPEN3 0x80 /* Enables Map3 */
388
389 #define CCR4 0xe8
390 #define CCR4_IOMASK 0x07
391 #define CCR4_MEM 0x08 /* Enables momory bypassing */
392 #define CCR4_DTE 0x10 /* Enables directory table entry cache */
393 #define CCR4_FASTFPE 0x20 /* Fast FPU exception */
394 #define CCR4_CPUID 0x80 /* Enables CPUID instruction */
395
396 #define CCR5 0xe9
397 #define CCR5_WT_ALLOC 0x01 /* Write-through allocate */
398 #define CCR5_SLOP 0x02 /* LOOP instruction slowed down */
399 #define CCR5_LBR1 0x10 /* Local bus region 1 */
400 #define CCR5_ARREN 0x20 /* Enables ARR region */
401
402 #define CCR6 0xea
403
404 #define CCR7 0xeb
405
406 /* Performance Control Register (5x86 only). */
407 #define PCR0 0x20
408 #define PCR0_RSTK 0x01 /* Enables return stack */
409 #define PCR0_BTB 0x02 /* Enables branch target buffer */
410 #define PCR0_LOOP 0x04 /* Enables loop */
411 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
412 serialize pipe. */
413 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
414 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
415 #define PCR0_LSSER 0x80 /* Disable reorder */
416
417 /* Device Identification Registers */
418 #define DIR0 0xfe
419 #define DIR1 0xff
420
421 /*
422 * Machine Check register constants.
423 */
424 #define MCG_CAP_COUNT 0x000000ff
425 #define MCG_CAP_CTL_P 0x00000100
426 #define MCG_CAP_EXT_P 0x00000200
427 #define MCG_CAP_CMCI_P 0x00000400
428 #define MCG_CAP_TES_P 0x00000800
429 #define MCG_CAP_EXT_CNT 0x00ff0000
430 #define MCG_CAP_SER_P 0x01000000
431 #define MCG_STATUS_RIPV 0x00000001
432 #define MCG_STATUS_EIPV 0x00000002
433 #define MCG_STATUS_MCIP 0x00000004
434 #define MCG_CTL_ENABLE 0xffffffffffffffff
435 #define MCG_CTL_DISABLE 0x0000000000000000
436 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
437 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
438 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
439 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
440 #define MSR_MC_CTL2(x) (MSR_MC0_CTL2 + (x)) /* If MCG_CAP_CMCI_P */
441 #define MC_STATUS_MCA_ERROR 0x000000000000ffff
442 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000
443 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000
444 #define MC_STATUS_COR_COUNT 0x001fffc000000000 /* If MCG_CAP_TES_P */
445 #define MC_STATUS_TES_STATUS 0x0060000000000000 /* If MCG_CAP_TES_P */
446 #define MC_STATUS_AR 0x0080000000000000 /* If MCG_CAP_CMCI_P */
447 #define MC_STATUS_S 0x0100000000000000 /* If MCG_CAP_CMCI_P */
448 #define MC_STATUS_PCC 0x0200000000000000
449 #define MC_STATUS_ADDRV 0x0400000000000000
450 #define MC_STATUS_MISCV 0x0800000000000000
451 #define MC_STATUS_EN 0x1000000000000000
452 #define MC_STATUS_UC 0x2000000000000000
453 #define MC_STATUS_OVER 0x4000000000000000
454 #define MC_STATUS_VAL 0x8000000000000000
455 #define MC_MISC_RA_LSB 0x000000000000003f /* If MCG_CAP_SER_P */
456 #define MC_MISC_ADDRESS_MODE 0x00000000000001c0 /* If MCG_CAP_SER_P */
457 #define MC_CTL2_THRESHOLD 0x0000000000003fff
458 #define MC_CTL2_CMCI_EN 0x0000000040000000
459
460 /*
461 * The following four 3-byte registers control the non-cacheable regions.
462 * These registers must be written as three separate bytes.
463 *
464 * NCRx+0: A31-A24 of starting address
465 * NCRx+1: A23-A16 of starting address
466 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
467 *
468 * The non-cacheable region's starting address must be aligned to the
469 * size indicated by the NCR_SIZE_xx field.
470 */
471 #define NCR1 0xc4
472 #define NCR2 0xc7
473 #define NCR3 0xca
474 #define NCR4 0xcd
475
476 #define NCR_SIZE_0K 0
477 #define NCR_SIZE_4K 1
478 #define NCR_SIZE_8K 2
479 #define NCR_SIZE_16K 3
480 #define NCR_SIZE_32K 4
481 #define NCR_SIZE_64K 5
482 #define NCR_SIZE_128K 6
483 #define NCR_SIZE_256K 7
484 #define NCR_SIZE_512K 8
485 #define NCR_SIZE_1M 9
486 #define NCR_SIZE_2M 10
487 #define NCR_SIZE_4M 11
488 #define NCR_SIZE_8M 12
489 #define NCR_SIZE_16M 13
490 #define NCR_SIZE_32M 14
491 #define NCR_SIZE_4G 15
492
493 /*
494 * The address region registers are used to specify the location and
495 * size for the eight address regions.
496 *
497 * ARRx + 0: A31-A24 of start address
498 * ARRx + 1: A23-A16 of start address
499 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
500 */
501 #define ARR0 0xc4
502 #define ARR1 0xc7
503 #define ARR2 0xca
504 #define ARR3 0xcd
505 #define ARR4 0xd0
506 #define ARR5 0xd3
507 #define ARR6 0xd6
508 #define ARR7 0xd9
509
510 #define ARR_SIZE_0K 0
511 #define ARR_SIZE_4K 1
512 #define ARR_SIZE_8K 2
513 #define ARR_SIZE_16K 3
514 #define ARR_SIZE_32K 4
515 #define ARR_SIZE_64K 5
516 #define ARR_SIZE_128K 6
517 #define ARR_SIZE_256K 7
518 #define ARR_SIZE_512K 8
519 #define ARR_SIZE_1M 9
520 #define ARR_SIZE_2M 10
521 #define ARR_SIZE_4M 11
522 #define ARR_SIZE_8M 12
523 #define ARR_SIZE_16M 13
524 #define ARR_SIZE_32M 14
525 #define ARR_SIZE_4G 15
526
527 /*
528 * The region control registers specify the attributes associated with
529 * the ARRx addres regions.
530 */
531 #define RCR0 0xdc
532 #define RCR1 0xdd
533 #define RCR2 0xde
534 #define RCR3 0xdf
535 #define RCR4 0xe0
536 #define RCR5 0xe1
537 #define RCR6 0xe2
538 #define RCR7 0xe3
539
540 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
541 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
542 #define RCR_WWO 0x02 /* Weak write ordering. */
543 #define RCR_WL 0x04 /* Weak locking. */
544 #define RCR_WG 0x08 /* Write gathering. */
545 #define RCR_WT 0x10 /* Write-through. */
546 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
547
548 /* AMD Write Allocate Top-Of-Memory and Control Register */
549 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
550 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
551 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
552
553 /* AMD64 MSR's */
554 #define MSR_EFER 0xc0000080 /* extended features */
555 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
556 #define MSR_MC0_CTL_MASK 0xc0010044
557
558 /* VIA ACE crypto featureset: for via_feature_rng */
559 #define VIA_HAS_RNG 1 /* cpu has RNG */
560
561 /* VIA ACE crypto featureset: for via_feature_xcrypt */
562 #define VIA_HAS_AES 1 /* cpu has AES */
563 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
564 #define VIA_HAS_MM 4 /* cpu has RSA instructions */
565 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
566
567 /* Centaur Extended Feature flags */
568 #define VIA_CPUID_HAS_RNG 0x000004
569 #define VIA_CPUID_DO_RNG 0x000008
570 #define VIA_CPUID_HAS_ACE 0x000040
571 #define VIA_CPUID_DO_ACE 0x000080
572 #define VIA_CPUID_HAS_ACE2 0x000100
573 #define VIA_CPUID_DO_ACE2 0x000200
574 #define VIA_CPUID_HAS_PHE 0x000400
575 #define VIA_CPUID_DO_PHE 0x000800
576 #define VIA_CPUID_HAS_PMM 0x001000
577 #define VIA_CPUID_DO_PMM 0x002000
578
579 /* VIA ACE xcrypt-* instruction context control options */
580 #define VIA_CRYPT_CWLO_ROUND_M 0x0000000f
581 #define VIA_CRYPT_CWLO_ALG_M 0x00000070
582 #define VIA_CRYPT_CWLO_ALG_AES 0x00000000
583 #define VIA_CRYPT_CWLO_KEYGEN_M 0x00000080
584 #define VIA_CRYPT_CWLO_KEYGEN_HW 0x00000000
585 #define VIA_CRYPT_CWLO_KEYGEN_SW 0x00000080
586 #define VIA_CRYPT_CWLO_NORMAL 0x00000000
587 #define VIA_CRYPT_CWLO_INTERMEDIATE 0x00000100
588 #define VIA_CRYPT_CWLO_ENCRYPT 0x00000000
589 #define VIA_CRYPT_CWLO_DECRYPT 0x00000200
590 #define VIA_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
591 #define VIA_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
592 #define VIA_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
593
594 #endif /* !_MACHINE_SPECIALREG_H_ */
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