The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/include/specialreg.h

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    1 /*-
    2  * Copyright (c) 1991 The Regents of the University of California.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 4. Neither the name of the University nor the names of its contributors
   14  *    may be used to endorse or promote products derived from this software
   15  *    without specific prior written permission.
   16  *
   17  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   27  * SUCH DAMAGE.
   28  *
   29  *      from: @(#)specialreg.h  7.1 (Berkeley) 5/9/91
   30  * $FreeBSD: releng/9.0/sys/i386/include/specialreg.h 222043 2011-05-17 22:36:16Z jkim $
   31  */
   32 
   33 #ifndef _MACHINE_SPECIALREG_H_
   34 #define _MACHINE_SPECIALREG_H_
   35 
   36 /*
   37  * Bits in 386 special registers:
   38  */
   39 #define CR0_PE  0x00000001      /* Protected mode Enable */
   40 #define CR0_MP  0x00000002      /* "Math" (fpu) Present */
   41 #define CR0_EM  0x00000004      /* EMulate FPU instructions. (trap ESC only) */
   42 #define CR0_TS  0x00000008      /* Task Switched (if MP, trap ESC and WAIT) */
   43 #define CR0_PG  0x80000000      /* PaGing enable */
   44 
   45 /*
   46  * Bits in 486 special registers:
   47  */
   48 #define CR0_NE  0x00000020      /* Numeric Error enable (EX16 vs IRQ13) */
   49 #define CR0_WP  0x00010000      /* Write Protect (honor page protect in
   50                                                            all modes) */
   51 #define CR0_AM  0x00040000      /* Alignment Mask (set to enable AC flag) */
   52 #define CR0_NW  0x20000000      /* Not Write-through */
   53 #define CR0_CD  0x40000000      /* Cache Disable */
   54 
   55 /*
   56  * Bits in PPro special registers
   57  */
   58 #define CR4_VME 0x00000001      /* Virtual 8086 mode extensions */
   59 #define CR4_PVI 0x00000002      /* Protected-mode virtual interrupts */
   60 #define CR4_TSD 0x00000004      /* Time stamp disable */
   61 #define CR4_DE  0x00000008      /* Debugging extensions */
   62 #define CR4_PSE 0x00000010      /* Page size extensions */
   63 #define CR4_PAE 0x00000020      /* Physical address extension */
   64 #define CR4_MCE 0x00000040      /* Machine check enable */
   65 #define CR4_PGE 0x00000080      /* Page global enable */
   66 #define CR4_PCE 0x00000100      /* Performance monitoring counter enable */
   67 #define CR4_FXSR 0x00000200     /* Fast FPU save/restore used by OS */
   68 #define CR4_XMM 0x00000400      /* enable SIMD/MMX2 to use except 16 */
   69 
   70 /*
   71  * Bits in AMD64 special registers.  EFER is 64 bits wide.
   72  */
   73 #define EFER_NXE 0x000000800    /* PTE No-Execute bit enable (R/W) */
   74 
   75 /*
   76  * CPUID instruction features register
   77  */
   78 #define CPUID_FPU       0x00000001
   79 #define CPUID_VME       0x00000002
   80 #define CPUID_DE        0x00000004
   81 #define CPUID_PSE       0x00000008
   82 #define CPUID_TSC       0x00000010
   83 #define CPUID_MSR       0x00000020
   84 #define CPUID_PAE       0x00000040
   85 #define CPUID_MCE       0x00000080
   86 #define CPUID_CX8       0x00000100
   87 #define CPUID_APIC      0x00000200
   88 #define CPUID_B10       0x00000400
   89 #define CPUID_SEP       0x00000800
   90 #define CPUID_MTRR      0x00001000
   91 #define CPUID_PGE       0x00002000
   92 #define CPUID_MCA       0x00004000
   93 #define CPUID_CMOV      0x00008000
   94 #define CPUID_PAT       0x00010000
   95 #define CPUID_PSE36     0x00020000
   96 #define CPUID_PSN       0x00040000
   97 #define CPUID_CLFSH     0x00080000
   98 #define CPUID_B20       0x00100000
   99 #define CPUID_DS        0x00200000
  100 #define CPUID_ACPI      0x00400000
  101 #define CPUID_MMX       0x00800000
  102 #define CPUID_FXSR      0x01000000
  103 #define CPUID_SSE       0x02000000
  104 #define CPUID_XMM       0x02000000
  105 #define CPUID_SSE2      0x04000000
  106 #define CPUID_SS        0x08000000
  107 #define CPUID_HTT       0x10000000
  108 #define CPUID_TM        0x20000000
  109 #define CPUID_IA64      0x40000000
  110 #define CPUID_PBE       0x80000000
  111 
  112 #define CPUID2_SSE3     0x00000001
  113 #define CPUID2_PCLMULQDQ 0x00000002
  114 #define CPUID2_DTES64   0x00000004
  115 #define CPUID2_MON      0x00000008
  116 #define CPUID2_DS_CPL   0x00000010
  117 #define CPUID2_VMX      0x00000020
  118 #define CPUID2_SMX      0x00000040
  119 #define CPUID2_EST      0x00000080
  120 #define CPUID2_TM2      0x00000100
  121 #define CPUID2_SSSE3    0x00000200
  122 #define CPUID2_CNXTID   0x00000400
  123 #define CPUID2_FMA      0x00001000
  124 #define CPUID2_CX16     0x00002000
  125 #define CPUID2_XTPR     0x00004000
  126 #define CPUID2_PDCM     0x00008000
  127 #define CPUID2_PCID     0x00020000
  128 #define CPUID2_DCA      0x00040000
  129 #define CPUID2_SSE41    0x00080000
  130 #define CPUID2_SSE42    0x00100000
  131 #define CPUID2_X2APIC   0x00200000
  132 #define CPUID2_MOVBE    0x00400000
  133 #define CPUID2_POPCNT   0x00800000
  134 #define CPUID2_TSCDLT   0x01000000
  135 #define CPUID2_AESNI    0x02000000
  136 #define CPUID2_XSAVE    0x04000000
  137 #define CPUID2_OSXSAVE  0x08000000
  138 #define CPUID2_AVX      0x10000000
  139 #define CPUID2_F16C     0x20000000
  140 #define CPUID2_HV       0x80000000
  141 
  142 /*
  143  * Important bits in the Thermal and Power Management flags
  144  * CPUID.6 EAX and ECX.
  145  */
  146 #define CPUTPM1_SENSOR  0x00000001
  147 #define CPUTPM1_TURBO   0x00000002
  148 #define CPUTPM1_ARAT    0x00000004
  149 #define CPUTPM2_EFFREQ  0x00000001
  150 
  151 /*
  152  * Important bits in the AMD extended cpuid flags
  153  */
  154 #define AMDID_SYSCALL   0x00000800
  155 #define AMDID_MP        0x00080000
  156 #define AMDID_NX        0x00100000
  157 #define AMDID_EXT_MMX   0x00400000
  158 #define AMDID_FFXSR     0x01000000
  159 #define AMDID_PAGE1GB   0x04000000
  160 #define AMDID_RDTSCP    0x08000000
  161 #define AMDID_LM        0x20000000
  162 #define AMDID_EXT_3DNOW 0x40000000
  163 #define AMDID_3DNOW     0x80000000
  164 
  165 #define AMDID2_LAHF     0x00000001
  166 #define AMDID2_CMP      0x00000002
  167 #define AMDID2_SVM      0x00000004
  168 #define AMDID2_EXT_APIC 0x00000008
  169 #define AMDID2_CR8      0x00000010
  170 #define AMDID2_ABM      0x00000020
  171 #define AMDID2_SSE4A    0x00000040
  172 #define AMDID2_MAS      0x00000080
  173 #define AMDID2_PREFETCH 0x00000100
  174 #define AMDID2_OSVW     0x00000200
  175 #define AMDID2_IBS      0x00000400
  176 #define AMDID2_XOP      0x00000800
  177 #define AMDID2_SKINIT   0x00001000
  178 #define AMDID2_WDT      0x00002000
  179 #define AMDID2_LWP      0x00008000
  180 #define AMDID2_FMA4     0x00010000
  181 #define AMDID2_NODE_ID  0x00080000
  182 #define AMDID2_TBM      0x00200000
  183 #define AMDID2_TOPOLOGY 0x00400000
  184 
  185 /*
  186  * CPUID instruction 1 eax info
  187  */
  188 #define CPUID_STEPPING          0x0000000f
  189 #define CPUID_MODEL             0x000000f0
  190 #define CPUID_FAMILY            0x00000f00
  191 #define CPUID_EXT_MODEL         0x000f0000
  192 #define CPUID_EXT_FAMILY        0x0ff00000
  193 #define CPUID_TO_MODEL(id) \
  194     ((((id) & CPUID_MODEL) >> 4) | \
  195     ((((id) & CPUID_FAMILY) >= 0x600) ? \
  196     (((id) & CPUID_EXT_MODEL) >> 12) : 0))
  197 #define CPUID_TO_FAMILY(id) \
  198     ((((id) & CPUID_FAMILY) >> 8) + \
  199     ((((id) & CPUID_FAMILY) == 0xf00) ? \
  200     (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
  201 
  202 /*
  203  * CPUID instruction 1 ebx info
  204  */
  205 #define CPUID_BRAND_INDEX       0x000000ff
  206 #define CPUID_CLFUSH_SIZE       0x0000ff00
  207 #define CPUID_HTT_CORES         0x00ff0000
  208 #define CPUID_LOCAL_APIC_ID     0xff000000
  209 
  210 /*
  211  * CPUID instruction 6 ecx info
  212  */
  213 #define CPUID_PERF_STAT         0x00000001
  214 #define CPUID_PERF_BIAS         0x00000008
  215 
  216 /* 
  217  * CPUID instruction 0xb ebx info.
  218  */
  219 #define CPUID_TYPE_INVAL        0
  220 #define CPUID_TYPE_SMT          1
  221 #define CPUID_TYPE_CORE         2
  222 
  223 /*
  224  * AMD extended function 8000_0007h edx info
  225  */
  226 #define AMDPM_TS                0x00000001
  227 #define AMDPM_FID               0x00000002
  228 #define AMDPM_VID               0x00000004
  229 #define AMDPM_TTP               0x00000008
  230 #define AMDPM_TM                0x00000010
  231 #define AMDPM_STC               0x00000020
  232 #define AMDPM_100MHZ_STEPS      0x00000040
  233 #define AMDPM_HW_PSTATE         0x00000080
  234 #define AMDPM_TSC_INVARIANT     0x00000100
  235 #define AMDPM_CPB               0x00000200
  236 
  237 /*
  238  * AMD extended function 8000_0008h ecx info
  239  */
  240 #define AMDID_CMP_CORES         0x000000ff
  241 #define AMDID_COREID_SIZE       0x0000f000
  242 #define AMDID_COREID_SIZE_SHIFT 12
  243 
  244 /*
  245  * CPUID manufacturers identifiers
  246  */
  247 #define AMD_VENDOR_ID           "AuthenticAMD"
  248 #define CENTAUR_VENDOR_ID       "CentaurHauls"
  249 #define CYRIX_VENDOR_ID         "CyrixInstead"
  250 #define INTEL_VENDOR_ID         "GenuineIntel"
  251 #define NEXGEN_VENDOR_ID        "NexGenDriven"
  252 #define NSC_VENDOR_ID           "Geode by NSC"
  253 #define RISE_VENDOR_ID          "RiseRiseRise"
  254 #define SIS_VENDOR_ID           "SiS SiS SiS "
  255 #define TRANSMETA_VENDOR_ID     "GenuineTMx86"
  256 #define UMC_VENDOR_ID           "UMC UMC UMC "
  257 
  258 /*
  259  * Model-specific registers for the i386 family
  260  */
  261 #define MSR_P5_MC_ADDR          0x000
  262 #define MSR_P5_MC_TYPE          0x001
  263 #define MSR_TSC                 0x010
  264 #define MSR_P5_CESR             0x011
  265 #define MSR_P5_CTR0             0x012
  266 #define MSR_P5_CTR1             0x013
  267 #define MSR_IA32_PLATFORM_ID    0x017
  268 #define MSR_APICBASE            0x01b
  269 #define MSR_EBL_CR_POWERON      0x02a
  270 #define MSR_TEST_CTL            0x033
  271 #define MSR_BIOS_UPDT_TRIG      0x079
  272 #define MSR_BBL_CR_D0           0x088
  273 #define MSR_BBL_CR_D1           0x089
  274 #define MSR_BBL_CR_D2           0x08a
  275 #define MSR_BIOS_SIGN           0x08b
  276 #define MSR_PERFCTR0            0x0c1
  277 #define MSR_PERFCTR1            0x0c2
  278 #define MSR_MPERF               0x0e7
  279 #define MSR_APERF               0x0e8
  280 #define MSR_IA32_EXT_CONFIG     0x0ee   /* Undocumented. Core Solo/Duo only */
  281 #define MSR_MTRRcap             0x0fe
  282 #define MSR_BBL_CR_ADDR         0x116
  283 #define MSR_BBL_CR_DECC         0x118
  284 #define MSR_BBL_CR_CTL          0x119
  285 #define MSR_BBL_CR_TRIG         0x11a
  286 #define MSR_BBL_CR_BUSY         0x11b
  287 #define MSR_BBL_CR_CTL3         0x11e
  288 #define MSR_SYSENTER_CS_MSR     0x174
  289 #define MSR_SYSENTER_ESP_MSR    0x175
  290 #define MSR_SYSENTER_EIP_MSR    0x176
  291 #define MSR_MCG_CAP             0x179
  292 #define MSR_MCG_STATUS          0x17a
  293 #define MSR_MCG_CTL             0x17b
  294 #define MSR_EVNTSEL0            0x186
  295 #define MSR_EVNTSEL1            0x187
  296 #define MSR_THERM_CONTROL       0x19a
  297 #define MSR_THERM_INTERRUPT     0x19b
  298 #define MSR_THERM_STATUS        0x19c
  299 #define MSR_IA32_MISC_ENABLE    0x1a0
  300 #define MSR_IA32_TEMPERATURE_TARGET     0x1a2
  301 #define MSR_DEBUGCTLMSR         0x1d9
  302 #define MSR_LASTBRANCHFROMIP    0x1db
  303 #define MSR_LASTBRANCHTOIP      0x1dc
  304 #define MSR_LASTINTFROMIP       0x1dd
  305 #define MSR_LASTINTTOIP         0x1de
  306 #define MSR_ROB_CR_BKUPTMPDR6   0x1e0
  307 #define MSR_MTRRVarBase         0x200
  308 #define MSR_MTRR64kBase         0x250
  309 #define MSR_MTRR16kBase         0x258
  310 #define MSR_MTRR4kBase          0x268
  311 #define MSR_PAT                 0x277
  312 #define MSR_MC0_CTL2            0x280
  313 #define MSR_MTRRdefType         0x2ff
  314 #define MSR_MC0_CTL             0x400
  315 #define MSR_MC0_STATUS          0x401
  316 #define MSR_MC0_ADDR            0x402
  317 #define MSR_MC0_MISC            0x403
  318 #define MSR_MC1_CTL             0x404
  319 #define MSR_MC1_STATUS          0x405
  320 #define MSR_MC1_ADDR            0x406
  321 #define MSR_MC1_MISC            0x407
  322 #define MSR_MC2_CTL             0x408
  323 #define MSR_MC2_STATUS          0x409
  324 #define MSR_MC2_ADDR            0x40a
  325 #define MSR_MC2_MISC            0x40b
  326 #define MSR_MC3_CTL             0x40c
  327 #define MSR_MC3_STATUS          0x40d
  328 #define MSR_MC3_ADDR            0x40e
  329 #define MSR_MC3_MISC            0x40f
  330 #define MSR_MC4_CTL             0x410
  331 #define MSR_MC4_STATUS          0x411
  332 #define MSR_MC4_ADDR            0x412
  333 #define MSR_MC4_MISC            0x413
  334 
  335 /*
  336  * Constants related to MSR's.
  337  */
  338 #define APICBASE_RESERVED       0x000006ff
  339 #define APICBASE_BSP            0x00000100
  340 #define APICBASE_ENABLED        0x00000800
  341 #define APICBASE_ADDRESS        0xfffff000
  342 
  343 /*
  344  * PAT modes.
  345  */
  346 #define PAT_UNCACHEABLE         0x00
  347 #define PAT_WRITE_COMBINING     0x01
  348 #define PAT_WRITE_THROUGH       0x04
  349 #define PAT_WRITE_PROTECTED     0x05
  350 #define PAT_WRITE_BACK          0x06
  351 #define PAT_UNCACHED            0x07
  352 #define PAT_VALUE(i, m)         ((long long)(m) << (8 * (i)))
  353 #define PAT_MASK(i)             PAT_VALUE(i, 0xff)
  354 
  355 /*
  356  * Constants related to MTRRs
  357  */
  358 #define MTRR_UNCACHEABLE        0x00
  359 #define MTRR_WRITE_COMBINING    0x01
  360 #define MTRR_WRITE_THROUGH      0x04
  361 #define MTRR_WRITE_PROTECTED    0x05
  362 #define MTRR_WRITE_BACK         0x06
  363 #define MTRR_N64K               8       /* numbers of fixed-size entries */
  364 #define MTRR_N16K               16
  365 #define MTRR_N4K                64
  366 #define MTRR_CAP_WC             0x0000000000000400
  367 #define MTRR_CAP_FIXED          0x0000000000000100
  368 #define MTRR_CAP_VCNT           0x00000000000000ff
  369 #define MTRR_DEF_ENABLE         0x0000000000000800
  370 #define MTRR_DEF_FIXED_ENABLE   0x0000000000000400
  371 #define MTRR_DEF_TYPE           0x00000000000000ff
  372 #define MTRR_PHYSBASE_PHYSBASE  0x000ffffffffff000
  373 #define MTRR_PHYSBASE_TYPE      0x00000000000000ff
  374 #define MTRR_PHYSMASK_PHYSMASK  0x000ffffffffff000
  375 #define MTRR_PHYSMASK_VALID     0x0000000000000800
  376 
  377 /*
  378  * Cyrix configuration registers, accessible as IO ports.
  379  */
  380 #define CCR0                    0xc0    /* Configuration control register 0 */
  381 #define CCR0_NC0                0x01    /* First 64K of each 1M memory region is
  382                                                                    non-cacheable */
  383 #define CCR0_NC1                0x02    /* 640K-1M region is non-cacheable */
  384 #define CCR0_A20M               0x04    /* Enables A20M# input pin */
  385 #define CCR0_KEN                0x08    /* Enables KEN# input pin */
  386 #define CCR0_FLUSH              0x10    /* Enables FLUSH# input pin */
  387 #define CCR0_BARB               0x20    /* Flushes internal cache when entering hold
  388                                                                    state */
  389 #define CCR0_CO                 0x40    /* Cache org: 1=direct mapped, 0=2x set
  390                                                                    assoc */
  391 #define CCR0_SUSPEND    0x80    /* Enables SUSP# and SUSPA# pins */
  392 
  393 #define CCR1                    0xc1    /* Configuration control register 1 */
  394 #define CCR1_RPL                0x01    /* Enables RPLSET and RPLVAL# pins */
  395 #define CCR1_SMI                0x02    /* Enables SMM pins */
  396 #define CCR1_SMAC               0x04    /* System management memory access */
  397 #define CCR1_MMAC               0x08    /* Main memory access */
  398 #define CCR1_NO_LOCK    0x10    /* Negate LOCK# */
  399 #define CCR1_SM3                0x80    /* SMM address space address region 3 */
  400 
  401 #define CCR2                    0xc2
  402 #define CCR2_WB                 0x02    /* Enables WB cache interface pins */
  403 #define CCR2_SADS               0x02    /* Slow ADS */
  404 #define CCR2_LOCK_NW    0x04    /* LOCK NW Bit */
  405 #define CCR2_SUSP_HLT   0x08    /* Suspend on HALT */
  406 #define CCR2_WT1                0x10    /* WT region 1 */
  407 #define CCR2_WPR1               0x10    /* Write-protect region 1 */
  408 #define CCR2_BARB               0x20    /* Flushes write-back cache when entering
  409                                                                    hold state. */
  410 #define CCR2_BWRT               0x40    /* Enables burst write cycles */
  411 #define CCR2_USE_SUSP   0x80    /* Enables suspend pins */
  412 
  413 #define CCR3                    0xc3
  414 #define CCR3_SMILOCK    0x01    /* SMM register lock */
  415 #define CCR3_NMI                0x02    /* Enables NMI during SMM */
  416 #define CCR3_LINBRST    0x04    /* Linear address burst cycles */
  417 #define CCR3_SMMMODE    0x08    /* SMM Mode */
  418 #define CCR3_MAPEN0             0x10    /* Enables Map0 */
  419 #define CCR3_MAPEN1             0x20    /* Enables Map1 */
  420 #define CCR3_MAPEN2             0x40    /* Enables Map2 */
  421 #define CCR3_MAPEN3             0x80    /* Enables Map3 */
  422 
  423 #define CCR4                    0xe8
  424 #define CCR4_IOMASK             0x07
  425 #define CCR4_MEM                0x08    /* Enables momory bypassing */
  426 #define CCR4_DTE                0x10    /* Enables directory table entry cache */
  427 #define CCR4_FASTFPE    0x20    /* Fast FPU exception */
  428 #define CCR4_CPUID              0x80    /* Enables CPUID instruction */
  429 
  430 #define CCR5                    0xe9
  431 #define CCR5_WT_ALLOC   0x01    /* Write-through allocate */
  432 #define CCR5_SLOP               0x02    /* LOOP instruction slowed down */
  433 #define CCR5_LBR1               0x10    /* Local bus region 1 */
  434 #define CCR5_ARREN              0x20    /* Enables ARR region */
  435 
  436 #define CCR6                    0xea
  437 
  438 #define CCR7                    0xeb
  439 
  440 /* Performance Control Register (5x86 only). */
  441 #define PCR0                    0x20
  442 #define PCR0_RSTK               0x01    /* Enables return stack */
  443 #define PCR0_BTB                0x02    /* Enables branch target buffer */
  444 #define PCR0_LOOP               0x04    /* Enables loop */
  445 #define PCR0_AIS                0x08    /* Enables all instrcutions stalled to
  446                                                                    serialize pipe. */
  447 #define PCR0_MLR                0x10    /* Enables reordering of misaligned loads */
  448 #define PCR0_BTBRT              0x40    /* Enables BTB test register. */
  449 #define PCR0_LSSER              0x80    /* Disable reorder */
  450 
  451 /* Device Identification Registers */
  452 #define DIR0                    0xfe
  453 #define DIR1                    0xff
  454 
  455 /*
  456  * Machine Check register constants.
  457  */
  458 #define MCG_CAP_COUNT           0x000000ff
  459 #define MCG_CAP_CTL_P           0x00000100
  460 #define MCG_CAP_EXT_P           0x00000200
  461 #define MCG_CAP_CMCI_P          0x00000400
  462 #define MCG_CAP_TES_P           0x00000800
  463 #define MCG_CAP_EXT_CNT         0x00ff0000
  464 #define MCG_CAP_SER_P           0x01000000
  465 #define MCG_STATUS_RIPV         0x00000001
  466 #define MCG_STATUS_EIPV         0x00000002
  467 #define MCG_STATUS_MCIP         0x00000004
  468 #define MCG_CTL_ENABLE          0xffffffffffffffff
  469 #define MCG_CTL_DISABLE         0x0000000000000000
  470 #define MSR_MC_CTL(x)           (MSR_MC0_CTL + (x) * 4)
  471 #define MSR_MC_STATUS(x)        (MSR_MC0_STATUS + (x) * 4)
  472 #define MSR_MC_ADDR(x)          (MSR_MC0_ADDR + (x) * 4)
  473 #define MSR_MC_MISC(x)          (MSR_MC0_MISC + (x) * 4)
  474 #define MSR_MC_CTL2(x)          (MSR_MC0_CTL2 + (x))    /* If MCG_CAP_CMCI_P */
  475 #define MC_STATUS_MCA_ERROR     0x000000000000ffff
  476 #define MC_STATUS_MODEL_ERROR   0x00000000ffff0000
  477 #define MC_STATUS_OTHER_INFO    0x01ffffff00000000
  478 #define MC_STATUS_COR_COUNT     0x001fffc000000000      /* If MCG_CAP_CMCI_P */
  479 #define MC_STATUS_TES_STATUS    0x0060000000000000      /* If MCG_CAP_TES_P */
  480 #define MC_STATUS_AR            0x0080000000000000      /* If MCG_CAP_TES_P */
  481 #define MC_STATUS_S             0x0100000000000000      /* If MCG_CAP_TES_P */
  482 #define MC_STATUS_PCC           0x0200000000000000
  483 #define MC_STATUS_ADDRV         0x0400000000000000
  484 #define MC_STATUS_MISCV         0x0800000000000000
  485 #define MC_STATUS_EN            0x1000000000000000
  486 #define MC_STATUS_UC            0x2000000000000000
  487 #define MC_STATUS_OVER          0x4000000000000000
  488 #define MC_STATUS_VAL           0x8000000000000000
  489 #define MC_MISC_RA_LSB          0x000000000000003f      /* If MCG_CAP_SER_P */
  490 #define MC_MISC_ADDRESS_MODE    0x00000000000001c0      /* If MCG_CAP_SER_P */
  491 #define MC_CTL2_THRESHOLD       0x0000000000007fff
  492 #define MC_CTL2_CMCI_EN         0x0000000040000000
  493 
  494 /*
  495  * The following four 3-byte registers control the non-cacheable regions.
  496  * These registers must be written as three separate bytes.
  497  *
  498  * NCRx+0: A31-A24 of starting address
  499  * NCRx+1: A23-A16 of starting address
  500  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
  501  *
  502  * The non-cacheable region's starting address must be aligned to the
  503  * size indicated by the NCR_SIZE_xx field.
  504  */
  505 #define NCR1    0xc4
  506 #define NCR2    0xc7
  507 #define NCR3    0xca
  508 #define NCR4    0xcd
  509 
  510 #define NCR_SIZE_0K     0
  511 #define NCR_SIZE_4K     1
  512 #define NCR_SIZE_8K     2
  513 #define NCR_SIZE_16K    3
  514 #define NCR_SIZE_32K    4
  515 #define NCR_SIZE_64K    5
  516 #define NCR_SIZE_128K   6
  517 #define NCR_SIZE_256K   7
  518 #define NCR_SIZE_512K   8
  519 #define NCR_SIZE_1M     9
  520 #define NCR_SIZE_2M     10
  521 #define NCR_SIZE_4M     11
  522 #define NCR_SIZE_8M     12
  523 #define NCR_SIZE_16M    13
  524 #define NCR_SIZE_32M    14
  525 #define NCR_SIZE_4G     15
  526 
  527 /*
  528  * The address region registers are used to specify the location and
  529  * size for the eight address regions.
  530  *
  531  * ARRx + 0: A31-A24 of start address
  532  * ARRx + 1: A23-A16 of start address
  533  * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
  534  */
  535 #define ARR0    0xc4
  536 #define ARR1    0xc7
  537 #define ARR2    0xca
  538 #define ARR3    0xcd
  539 #define ARR4    0xd0
  540 #define ARR5    0xd3
  541 #define ARR6    0xd6
  542 #define ARR7    0xd9
  543 
  544 #define ARR_SIZE_0K             0
  545 #define ARR_SIZE_4K             1
  546 #define ARR_SIZE_8K             2
  547 #define ARR_SIZE_16K    3
  548 #define ARR_SIZE_32K    4
  549 #define ARR_SIZE_64K    5
  550 #define ARR_SIZE_128K   6
  551 #define ARR_SIZE_256K   7
  552 #define ARR_SIZE_512K   8
  553 #define ARR_SIZE_1M             9
  554 #define ARR_SIZE_2M             10
  555 #define ARR_SIZE_4M             11
  556 #define ARR_SIZE_8M             12
  557 #define ARR_SIZE_16M    13
  558 #define ARR_SIZE_32M    14
  559 #define ARR_SIZE_4G             15
  560 
  561 /*
  562  * The region control registers specify the attributes associated with
  563  * the ARRx addres regions.
  564  */
  565 #define RCR0    0xdc
  566 #define RCR1    0xdd
  567 #define RCR2    0xde
  568 #define RCR3    0xdf
  569 #define RCR4    0xe0
  570 #define RCR5    0xe1
  571 #define RCR6    0xe2
  572 #define RCR7    0xe3
  573 
  574 #define RCR_RCD 0x01    /* Disables caching for ARRx (x = 0-6). */
  575 #define RCR_RCE 0x01    /* Enables caching for ARR7. */
  576 #define RCR_WWO 0x02    /* Weak write ordering. */
  577 #define RCR_WL  0x04    /* Weak locking. */
  578 #define RCR_WG  0x08    /* Write gathering. */
  579 #define RCR_WT  0x10    /* Write-through. */
  580 #define RCR_NLB 0x20    /* LBA# pin is not asserted. */
  581 
  582 /* AMD Write Allocate Top-Of-Memory and Control Register */
  583 #define AMD_WT_ALLOC_TME        0x40000 /* top-of-memory enable */
  584 #define AMD_WT_ALLOC_PRE        0x20000 /* programmable range enable */
  585 #define AMD_WT_ALLOC_FRE        0x10000 /* fixed (A0000-FFFFF) range enable */
  586 
  587 /* AMD64 MSR's */
  588 #define MSR_EFER                0xc0000080      /* extended features */
  589 #define MSR_HWCR                0xc0010015
  590 #define MSR_K8_UCODE_UPDATE     0xc0010020      /* update microcode */
  591 #define MSR_MC0_CTL_MASK        0xc0010044
  592 
  593 /* VIA ACE crypto featureset: for via_feature_rng */
  594 #define VIA_HAS_RNG             1       /* cpu has RNG */
  595 
  596 /* VIA ACE crypto featureset: for via_feature_xcrypt */
  597 #define VIA_HAS_AES             1       /* cpu has AES */
  598 #define VIA_HAS_SHA             2       /* cpu has SHA1 & SHA256 */
  599 #define VIA_HAS_MM              4       /* cpu has RSA instructions */
  600 #define VIA_HAS_AESCTR          8       /* cpu has AES-CTR instructions */
  601 
  602 /* Centaur Extended Feature flags */
  603 #define VIA_CPUID_HAS_RNG       0x000004
  604 #define VIA_CPUID_DO_RNG        0x000008
  605 #define VIA_CPUID_HAS_ACE       0x000040
  606 #define VIA_CPUID_DO_ACE        0x000080
  607 #define VIA_CPUID_HAS_ACE2      0x000100
  608 #define VIA_CPUID_DO_ACE2       0x000200
  609 #define VIA_CPUID_HAS_PHE       0x000400
  610 #define VIA_CPUID_DO_PHE        0x000800
  611 #define VIA_CPUID_HAS_PMM       0x001000
  612 #define VIA_CPUID_DO_PMM        0x002000
  613 
  614 /* VIA ACE xcrypt-* instruction context control options */
  615 #define VIA_CRYPT_CWLO_ROUND_M          0x0000000f
  616 #define VIA_CRYPT_CWLO_ALG_M            0x00000070
  617 #define VIA_CRYPT_CWLO_ALG_AES          0x00000000
  618 #define VIA_CRYPT_CWLO_KEYGEN_M         0x00000080
  619 #define VIA_CRYPT_CWLO_KEYGEN_HW        0x00000000
  620 #define VIA_CRYPT_CWLO_KEYGEN_SW        0x00000080
  621 #define VIA_CRYPT_CWLO_NORMAL           0x00000000
  622 #define VIA_CRYPT_CWLO_INTERMEDIATE     0x00000100
  623 #define VIA_CRYPT_CWLO_ENCRYPT          0x00000000
  624 #define VIA_CRYPT_CWLO_DECRYPT          0x00000200
  625 #define VIA_CRYPT_CWLO_KEY128           0x0000000a      /* 128bit, 10 rds */
  626 #define VIA_CRYPT_CWLO_KEY192           0x0000040c      /* 192bit, 12 rds */
  627 #define VIA_CRYPT_CWLO_KEY256           0x0000080e      /* 256bit, 15 rds */
  628 
  629 #endif /* !_MACHINE_SPECIALREG_H_ */

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