The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/include/specialreg.h

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    1 /*-
    2  * Copyright (c) 1991 The Regents of the University of California.
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. Redistributions in binary form must reproduce the above copyright
   11  *    notice, this list of conditions and the following disclaimer in the
   12  *    documentation and/or other materials provided with the distribution.
   13  * 3. All advertising materials mentioning features or use of this software
   14  *    must display the following acknowledgement:
   15  *      This product includes software developed by the University of
   16  *      California, Berkeley and its contributors.
   17  * 4. Neither the name of the University nor the names of its contributors
   18  *    may be used to endorse or promote products derived from this software
   19  *    without specific prior written permission.
   20  *
   21  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   24  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   25  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   26  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   27  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   28  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   29  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   30  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   31  * SUCH DAMAGE.
   32  *
   33  *      from: @(#)specialreg.h  7.1 (Berkeley) 5/9/91
   34  * $FreeBSD: src/sys/i386/include/specialreg.h,v 1.9.2.4 1999/09/05 08:12:05 peter Exp $
   35  */
   36 
   37 #ifndef _MACHINE_SPECIALREG_H_
   38 #define _MACHINE_SPECIALREG_H_
   39 
   40 /*
   41  * Bits in 386 special registers:
   42  */
   43 #define CR0_PE  0x00000001      /* Protected mode Enable */
   44 #define CR0_MP  0x00000002      /* "Math" Present (NPX or NPX emulator) */
   45 #ifdef notused
   46 #define CR0_EM  0x00000004      /* EMulate non-NPX coproc. (trap ESC only) */
   47 #endif
   48 #define CR0_TS  0x00000008      /* Task Switched (if MP, trap ESC and WAIT) */
   49 #ifdef notused
   50 #define CR0_ET  0x00000010      /* Extension Type (387 (if set) vs 287) */
   51 #endif
   52 #define CR0_PG  0x80000000      /* PaGing enable */
   53 
   54 /*
   55  * Bits in 486 special registers:
   56  */
   57 #define CR0_NE  0x00000020      /* Numeric Error enable (EX16 vs IRQ13) */
   58 #define CR0_WP  0x00010000      /* Write Protect (honor page protect in
   59                                                            all modes) */
   60 #define CR0_AM  0x00040000      /* Alignment Mask (set to enable AC flag) */
   61 #define CR0_NW  0x20000000      /* Not Write-through */
   62 #define CR0_CD  0x40000000      /* Cache Disable */
   63 
   64 /*
   65  * Bits in PPro special registers
   66  */
   67 #define CR4_VME 0x00000001      /* Virtual 8086 mode extensions */
   68 #define CR4_PVI 0x00000002      /* Protected-mode virtual interrupts */
   69 #define CR4_TSD 0x00000004      /* Time stamp disable */
   70 #define CR4_DE  0x00000008      /* Debugging extensions */
   71 #define CR4_PSE 0x00000010      /* Page size extensions */
   72 #define CR4_PAE 0x00000020      /* Physical address extension */
   73 #define CR4_MCE 0x00000040      /* Machine check enable */
   74 #define CR4_PGE 0x00000080      /* Page global enable */
   75 #define CR4_PCE 0x00000100      /* Performance monitoring counter enable */
   76 
   77 /*
   78  * CPUID instruction features register
   79  */
   80 #define CPUID_FPU       0x0001
   81 #define CPUID_VME       0x0002
   82 #define CPUID_DE        0x0004
   83 #define CPUID_PSE       0x0008
   84 #define CPUID_TSC       0x0010
   85 #define CPUID_MSR       0x0020
   86 #define CPUID_PAE       0x0040
   87 #define CPUID_MCE       0x0080
   88 #define CPUID_CX8       0x0100
   89 #define CPUID_APIC      0x0200
   90 #define CPUID_B10       0x0400
   91 #define CPUID_B11       0x0800
   92 #define CPUID_MTRR      0x1000
   93 #define CPUID_PGE       0x2000
   94 #define CPUID_MCA       0x4000
   95 #define CPUID_CMOV      0x8000
   96 
   97 /*
   98  * Cyrix configuration registers, accessible as IO ports.
   99  */
  100 #define CCR0                    0xc0    /* Configuration control register 0 */
  101 #define CCR0_NC0                0x01    /* First 64K of each 1M memory region is
  102                                                                    non-cacheable */
  103 #define CCR0_NC1                0x02    /* 640K-1M region is non-cacheable */
  104 #define CCR0_A20M               0x04    /* Enables A20M# input pin */
  105 #define CCR0_KEN                0x08    /* Enables KEN# input pin */
  106 #define CCR0_FLUSH              0x10    /* Enables FLUSH# input pin */
  107 #define CCR0_BARB               0x20    /* Flushes internal cache when entering hold
  108                                                                    state */
  109 #define CCR0_CO                 0x40    /* Cache org: 1=direct mapped, 0=2x set
  110                                                                    assoc */
  111 #define CCR0_SUSPEND    0x80    /* Enables SUSP# and SUSPA# pins */
  112 
  113 #define CCR1                    0xc1    /* Configuration control register 1 */
  114 #define CCR1_RPL                0x01    /* Enables RPLSET and RPLVAL# pins */
  115 #define CCR1_SMI                0x02    /* Enables SMM pins */
  116 #define CCR1_SMAC               0x04    /* System management memory access */
  117 #define CCR1_MMAC               0x08    /* Main memory access */
  118 #define CCR1_NO_LOCK    0x10    /* Negate LOCK# */
  119 #define CCR1_SM3                0x80    /* SMM address space address region 3 */
  120 
  121 #define CCR2                    0xc2
  122 #define CCR2_WB                 0x02    /* Enables WB cache interface pins */
  123 #define CCR2_SADS               0x02    /* Slow ADS */
  124 #define CCR2_LOCK_NW    0x04    /* LOCK NW Bit */
  125 #define CCR2_SUSP_HLT   0x08    /* Suspend on HALT */
  126 #define CCR2_WT1                0x10    /* WT region 1 */
  127 #define CCR2_WPR1               0x10    /* Write-protect region 1 */
  128 #define CCR2_BARB               0x20    /* Flushes write-back cache when entering
  129                                                                    hold state. */
  130 #define CCR2_BWRT               0x40    /* Enables burst write cycles */
  131 #define CCR2_USE_SUSP   0x80    /* Enables suspend pins */
  132 
  133 #define CCR3                    0xc3
  134 #define CCR3_SMILOCK    0x01    /* SMM register lock */
  135 #define CCR3_NMI                0x02    /* Enables NMI during SMM */
  136 #define CCR3_LINBRST    0x04    /* Linear address burst cycles */
  137 #define CCR3_SMMMODE    0x08    /* SMM Mode */
  138 #define CCR3_MAPEN0             0x10    /* Enables Map0 */
  139 #define CCR3_MAPEN1             0x20    /* Enables Map1 */
  140 #define CCR3_MAPEN2             0x40    /* Enables Map2 */
  141 #define CCR3_MAPEN3             0x80    /* Enables Map3 */
  142 
  143 #define CCR4                    0xe8
  144 #define CCR4_IOMASK             0x07
  145 #define CCR4_MEM                0x08    /* Enables momory bypassing */
  146 #define CCR4_DTE                0x10    /* Enables directory table entry cache */
  147 #define CCR4_FASTFPE    0x20    /* Fast FPU exception */
  148 #define CCR4_CPUID              0x80    /* Enables CPUID instruction */
  149 
  150 #define CCR5                    0xe9
  151 #define CCR5_WT_ALLOC   0x01    /* Write-through allocate */
  152 #define CCR5_SLOP               0x02    /* LOOP instruction slowed down */
  153 #define CCR5_LBR1               0x10    /* Local bus region 1 */
  154 #define CCR5_ARREN              0x20    /* Enables ARR region */
  155 
  156 #define CCR6                    0xea
  157 
  158 #define CCR7                    0xeb
  159 
  160 /* Performance Control Register (5x86 only). */
  161 #define PCR0                    0x20
  162 #define PCR0_RSTK               0x01    /* Enables return stack */
  163 #define PCR0_BTB                0x02    /* Enables branch target buffer */
  164 #define PCR0_LOOP               0x04    /* Enables loop */
  165 #define PCR0_AIS                0x08    /* Enables all instrcutions stalled to
  166                                                                    serialize pipe. */
  167 #define PCR0_MLR                0x10    /* Enables reordering of misaligned loads */
  168 #define PCR0_BTBRT              0x40    /* Enables BTB test register. */
  169 #define PCR0_LSSER              0x80    /* Disable reorder */
  170 
  171 /* Device Identification Registers */
  172 #define DIR0                    0xfe
  173 #define DIR1                    0xff
  174 
  175 /*
  176  * The following four 3-byte registers control the non-cacheable regions.
  177  * These registers must be written as three separate bytes.
  178  *
  179  * NCRx+0: A31-A24 of starting address
  180  * NCRx+1: A23-A16 of starting address
  181  * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
  182  *
  183  * The non-cacheable region's starting address must be aligned to the
  184  * size indicated by the NCR_SIZE_xx field.
  185  */
  186 #define NCR1    0xc4
  187 #define NCR2    0xc7
  188 #define NCR3    0xca
  189 #define NCR4    0xcd
  190 
  191 #define NCR_SIZE_0K     0
  192 #define NCR_SIZE_4K     1
  193 #define NCR_SIZE_8K     2
  194 #define NCR_SIZE_16K    3
  195 #define NCR_SIZE_32K    4
  196 #define NCR_SIZE_64K    5
  197 #define NCR_SIZE_128K   6
  198 #define NCR_SIZE_256K   7
  199 #define NCR_SIZE_512K   8
  200 #define NCR_SIZE_1M     9
  201 #define NCR_SIZE_2M     10
  202 #define NCR_SIZE_4M     11
  203 #define NCR_SIZE_8M     12
  204 #define NCR_SIZE_16M    13
  205 #define NCR_SIZE_32M    14
  206 #define NCR_SIZE_4G     15
  207 
  208 /*
  209  * The address region registers are used to specify the location and
  210  * size for the eight address regions.
  211  *
  212  * ARRx + 0: A31-A24 of start address
  213  * ARRx + 1: A23-A16 of start address
  214  * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
  215  */
  216 #define ARR0    0xc4
  217 #define ARR1    0xc7
  218 #define ARR2    0xca
  219 #define ARR3    0xcd
  220 #define ARR4    0xd0
  221 #define ARR5    0xd3
  222 #define ARR6    0xd6
  223 #define ARR7    0xd9
  224 
  225 #define ARR_SIZE_0K             0
  226 #define ARR_SIZE_4K             1
  227 #define ARR_SIZE_8K             2
  228 #define ARR_SIZE_16K    3
  229 #define ARR_SIZE_32K    4
  230 #define ARR_SIZE_64K    5
  231 #define ARR_SIZE_128K   6
  232 #define ARR_SIZE_256K   7
  233 #define ARR_SIZE_512K   8
  234 #define ARR_SIZE_1M             9
  235 #define ARR_SIZE_2M             10
  236 #define ARR_SIZE_4M             11
  237 #define ARR_SIZE_8M             12
  238 #define ARR_SIZE_16M    13
  239 #define ARR_SIZE_32M    14
  240 #define ARR_SIZE_4G             15
  241 
  242 /*
  243  * The region control registers specify the attributes associated with
  244  * the ARRx addres regions.
  245  */
  246 #define RCR0    0xdc
  247 #define RCR1    0xdd
  248 #define RCR2    0xde
  249 #define RCR3    0xdf
  250 #define RCR4    0xe0
  251 #define RCR5    0xe1
  252 #define RCR6    0xe2
  253 #define RCR7    0xe3
  254 
  255 #define RCR_RCD 0x01    /* Disables caching for ARRx (x = 0-6). */
  256 #define RCR_RCE 0x01    /* Enables caching for ARR7. */
  257 #define RCR_WWO 0x02    /* Weak write ordering. */
  258 #define RCR_WL  0x04    /* Weak locking. */
  259 #define RCR_WG  0x08    /* Write gathering. */
  260 #define RCR_WT  0x10    /* Write-through. */
  261 #define RCR_NLB 0x20    /* LBA# pin is not asserted. */
  262 
  263 
  264 #ifndef LOCORE
  265 static __inline u_char
  266 read_cyrix_reg(u_char reg)
  267 {
  268         outb(0x22, reg);
  269         return inb(0x23);
  270 }
  271 
  272 static __inline void
  273 write_cyrix_reg(u_char reg, u_char data)
  274 {
  275         outb(0x22, reg);
  276         outb(0x23, data);
  277 }
  278 #endif
  279 
  280 #endif /* !_MACHINE_SPECIALREG_H_ */

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