FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/aic_98.h
1 /*
2 * Copyright (c) KATO Takenori, 1996. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer as
9 * the first lines of this file unmodified.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. The name of the author may not be used to endorse or promote products
14 * derived from this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #ifndef __PC98_PC98_AIC_98_H__
29 #define __PC98_PC98_AIC_98_H__
30
31
32
33 /* generic card */
34 static int aicport_generic[32] = {
35 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
36 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
37 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
38 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f
39 };
40
41 /* PC-9801-100 */
42 static int aicport_100[32] = {
43 0x00, 0x02, 0x04, 0x06, 0x08, 0x0a, 0x0c, 0x0e,
44 0x10, 0x12, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x1e,
45 0x20, 0x22, 0x24, 0x26, 0x28, 0x2a, 0x2c, 0x2e,
46 0x30, 0x32, 0x34, 0x36, 0x38, 0x3a, 0x3c, 0x3e
47 };
48
49 #define AIC98_GENERIC 0x00
50 #define AIC98_100 0x01
51
52 #define AIC_TYPE98(x) ((x >> 16) & 0xff)
53
54 #define SCSISEQ (iobase + aic->aicport[0x00]) /* SCSI sequence control */
55 #define SXFRCTL0 (iobase + aic->aicport[0x01]) /* SCSI transfer control 0 */
56 #define SXFRCTL1 (iobase + aic->aicport[0x02]) /* SCSI transfer control 1 */
57 #define SCSISIGI (iobase + aic->aicport[0x03]) /* SCSI signal in */
58 #define SCSISIGO (iobase + aic->aicport[0x03]) /* SCSI signal out */
59 #define SCSIRATE (iobase + aic->aicport[0x04]) /* SCSI rate control */
60 #define SCSIID (iobase + aic->aicport[0x05]) /* SCSI ID */
61 #define SELID (iobase + aic->aicport[0x05]) /* Selection/Reselection ID */
62 #define SCSIDAT (iobase + aic->aicport[0x06]) /* SCSI Latched Data */
63 #define SCSIBUS (iobase + aic->aicport[0x07]) /* SCSI Data Bus*/
64 #define STCNT0 (iobase + aic->aicport[0x08]) /* SCSI transfer count */
65 #define STCNT1 (iobase + aic->aicport[0x09])
66 #define STCNT2 (iobase + aic->aicport[0x0a])
67 #define CLRSINT0 (iobase + aic->aicport[0x0b]) /* Clear SCSI interrupts 0 */
68 #define SSTAT0 (iobase + aic->aicport[0x0b]) /* SCSI interrupt status 0 */
69 #define CLRSINT1 (iobase + aic->aicport[0x0c]) /* Clear SCSI interrupts 1 */
70 #define SSTAT1 (iobase + aic->aicport[0x0c]) /* SCSI status 1 */
71 #define SSTAT2 (iobase + aic->aicport[0x0d]) /* SCSI status 2 */
72 #define SCSITEST (iobase + aic->aicport[0x0e]) /* SCSI test control */
73 #define SSTAT3 (iobase + aic->aicport[0x0e]) /* SCSI status 3 */
74 #define CLRSERR (iobase + aic->aicport[0x0f]) /* Clear SCSI errors */
75 #define SSTAT4 (iobase + aic->aicport[0x0f]) /* SCSI status 4 */
76 #define SIMODE0 (iobase + aic->aicport[0x10]) /* SCSI interrupt mode 0 */
77 #define SIMODE1 (iobase + aic->aicport[0x11]) /* SCSI interrupt mode 1 */
78 #define DMACNTRL0 (iobase + aic->aicport[0x12]) /* DMA control 0 */
79 #define DMACNTRL1 (iobase + aic->aicport[0x13]) /* DMA control 1 */
80 #define DMASTAT (iobase + aic->aicport[0x14]) /* DMA status */
81 #define FIFOSTAT (iobase + aic->aicport[0x15]) /* FIFO status */
82 #define DMADATA (iobase + aic->aicport[0x16]) /* DMA data */
83 #define DMADATAL (iobase + aic->aicport[0x16]) /* DMA data low byte */
84 #define DMADATAH (iobase + aic->aicport[0x17]) /* DMA data high byte */
85 #define BRSTCNTRL (iobase + aic->aicport[0x18]) /* Burst Control */
86 #define DMADATALONG (iobase + aic->aicport[0x18])
87 #define PORTA (iobase + aic->aicport[0x1a]) /* Port A */
88 #define PORTB (iobase + aic->aicport[0x1b]) /* Port B */
89 #define REV (iobase + aic->aicport[0x1c]) /* Revision (001 for 6360) */
90 #define STACK (iobase + aic->aicport[0x1d]) /* Stack */
91 #define TEST (iobase + aic->aicport[0x1e]) /* Test register */
92 #define ID (iobase + aic->aicport[0x1f]) /* ID register */
93 #endif
Cache object: 93509f89805defa8e4ab23e83cb90106
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