The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/apic_ipl.s

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    1 /*-
    2  * Copyright (c) 1997, by Steve Passe
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. The name of the developer may NOT be used to endorse or promote products
   11  *    derived from this software without specific prior written permission.
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   23  * SUCH DAMAGE.
   24  *
   25  * $FreeBSD: releng/5.1/sys/i386/isa/apic_ipl.s 88322 2001-12-20 23:48:31Z jhb $
   26  */
   27 
   28         .data
   29         ALIGN_DATA
   30 
   31 /*
   32  * Note:
   33  *      This is the UP equivilant of _imen.
   34  *      It is OPAQUE, and must NOT be accessed directly.
   35  *      It MUST be accessed along with the IO APIC as a 'critical region'.
   36  *      Accessed by:
   37  *              INTREN()
   38  *              INTRDIS()
   39  *              imen_dump()
   40  */
   41         .p2align 2                              /* MUST be 32bit aligned */
   42         .globl apic_imen
   43 apic_imen:
   44         .long   HWI_MASK
   45 
   46         .text
   47         SUPERALIGN_TEXT
   48 
   49 /******************************************************************************
   50  * XXX FIXME: figure out where these belong.
   51  */
   52 
   53 /* this nonsense is to verify that masks ALWAYS have 1 and only 1 bit set */
   54 #define QUALIFY_MASKS_NOT
   55 
   56 #ifdef QUALIFY_MASKS
   57 #define QUALIFY_MASK            \
   58         btrl    %ecx, %eax ;    \
   59         andl    %eax, %eax ;    \
   60         jz      1f ;            \
   61         pushl   $bad_mask ;     \
   62         call    panic ;         \
   63 1:
   64 
   65 bad_mask:       .asciz  "bad mask"
   66 #else
   67 #define QUALIFY_MASK
   68 #endif
   69 
   70 /*
   71  * MP-safe function to clear ONE INT mask bit.
   72  * The passed arg is a 32bit u_int MASK.
   73  * It sets the associated bit in _apic_imen.
   74  * It sets the mask bit of the associated IO APIC register.
   75  */
   76 ENTRY(INTREN)
   77         movl    4(%esp), %eax           /* mask into %eax */
   78         bsfl    %eax, %ecx              /* get pin index */
   79         btrl    %ecx, apic_imen         /* update apic_imen */
   80 
   81         QUALIFY_MASK
   82 
   83         shll    $4, %ecx
   84         movl    CNAME(int_to_apicintpin) + 8(%ecx), %edx
   85         movl    CNAME(int_to_apicintpin) + 12(%ecx), %ecx
   86         testl   %edx, %edx
   87         jz      1f
   88 
   89         movl    %ecx, (%edx)            /* write the target register index */
   90         movl    IOAPIC_WINDOW(%edx), %eax /* read the target register data */
   91         andl    $~IOART_INTMASK, %eax   /* clear mask bit */
   92         movl    %eax, IOAPIC_WINDOW(%edx) /* write the APIC register data */
   93 1:      
   94         ret
   95 
   96 /*
   97  * MP-safe function to set ONE INT mask bit.
   98  * The passed arg is a 32bit u_int MASK.
   99  * It clears the associated bit in _apic_imen.
  100  * It clears the mask bit of the associated IO APIC register.
  101  */
  102 ENTRY(INTRDIS)
  103         movl    4(%esp), %eax           /* mask into %eax */
  104         bsfl    %eax, %ecx              /* get pin index */
  105         btsl    %ecx, apic_imen         /* update apic_imen */
  106 
  107         QUALIFY_MASK
  108 
  109         shll    $4, %ecx
  110         movl    CNAME(int_to_apicintpin) + 8(%ecx), %edx
  111         movl    CNAME(int_to_apicintpin) + 12(%ecx), %ecx
  112         testl   %edx, %edx
  113         jz      1f
  114 
  115         movl    %ecx, (%edx)            /* write the target register index */
  116         movl    IOAPIC_WINDOW(%edx), %eax /* read the target register data */
  117         orl     $IOART_INTMASK, %eax    /* set mask bit */
  118         movl    %eax, IOAPIC_WINDOW(%edx) /* write the APIC register data */
  119 1:      
  120         ret

Cache object: f3793d75eb37a0d9601da95c00bc8490


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