The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/atapi.h

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    1 /*
    2  * Device-independent level for ATAPI drivers.
    3  *
    4  * Copyright (C) 1995 Cronyx Ltd.
    5  * Author Serge Vakulenko, <vak@cronyx.ru>
    6  *
    7  * This software is distributed with NO WARRANTIES, not even the implied
    8  * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    9  *
   10  * Authors grant any other persons or organizations permission to use
   11  * or modify this software as long as this message is kept with the software,
   12  * all derivative works or modified versions.
   13  *
   14  * Version 1.9, Thu Oct 12 15:53:50 MSK 1995
   15  * $FreeBSD$
   16  */
   17 
   18 #define atapi_attach wdc_atapi_attach
   19 #define acdattach wdc_acdattach
   20 
   21 /*
   22  * Disk Controller ATAPI register definitions.
   23  */
   24 #ifdef PC98
   25 #define AR_DATA         0x0             /* RW - data register (16 bits) */
   26 #define AR_ERROR        0x2             /*  R - error register */
   27 #define AR_FEATURES     0x2             /*  W - features */
   28 #define AR_IREASON      0x4             /* RW - interrupt reason */
   29 #define AR_TAG          0x6             /*    - reserved for SAM TAG byte */
   30 #define AR_CNTLO        0x8             /* RW - byte count, low byte */
   31 #define AR_CNTHI        0xa             /* RW - byte count, high byte */
   32 #define AR_DRIVE        0xc             /* RW - drive select */
   33 #define AR_COMMAND      0xe             /*  W - command register */
   34 #define AR_STATUS       0xe             /*  R - immediate status */
   35 #else
   36 #define AR_DATA         0x0             /* RW - data register (16 bits) */
   37 #define AR_ERROR        0x1             /*  R - error register */
   38 #define AR_FEATURES     0x1             /*  W - features */
   39 #define AR_IREASON      0x2             /* RW - interrupt reason */
   40 #define AR_TAG          0x3             /*    - reserved for SAM TAG byte */
   41 #define AR_CNTLO        0x4             /* RW - byte count, low byte */
   42 #define AR_CNTHI        0x5             /* RW - byte count, high byte */
   43 #define AR_DRIVE        0x6             /* RW - drive select */
   44 #define AR_COMMAND      0x7             /*  W - command register */
   45 #define AR_STATUS       0x7             /*  R - immediate status */
   46 #endif
   47 
   48 /*
   49  * Status register bits
   50  */
   51 #define ARS_CHECK       0x01            /* error occured, see sense key/code */
   52                                         /* bit 0x02 reserved */
   53 #define ARS_CORR        0x04            /* correctable error occured */
   54 #define ARS_DRQ         0x08            /* data request / ireason valid */
   55 #define ARS_DSC         0x10            /* immediate operation completed */
   56 #define ARS_DF          0x20            /* drive fault */
   57 #define ARS_DRDY        0x40            /* ready to get command */
   58 #define ARS_BSY         0x80            /* registers busy */
   59                                         /* for overlap mode only: */
   60 #define ARS_SERVICE     0x10            /* service is requested */
   61 #define ARS_DMARDY      0x20            /* ready to start a DMA transfer */
   62 #define ARS_BITS        "\2\010busy\7ready\6fault\5opdone\4drq\3corr\1check"
   63 
   64 /*
   65  * Error register bits
   66  */
   67 #define AER_ILI         0x01            /* illegal length indication */
   68 #define AER_EOM         0x02            /* end of media detected */
   69 #define AER_ABRT        0x04            /* command aborted */
   70 #define AER_MCR         0x08            /* media change requested */
   71 #define AER_SKEY        0xf0            /* sense key mask */
   72 #define AER_SK_NO_SENSE         0x00    /* no specific sense key info */
   73 #define AER_SK_RECOVERED_ERROR  0x10    /* command succeeded, data recovered */
   74 #define AER_SK_NOT_READY        0x20    /* no access to drive */
   75 #define AER_SK_MEDIUM_ERROR     0x30    /* non-recovered data error */
   76 #define AER_SK_HARDWARE_ERROR   0x40    /* non-recoverable hardware failure */
   77 #define AER_SK_ILLEGAL_REQUEST  0x50    /* invalid command parameter(s) */
   78 #define AER_SK_UNIT_ATTENTION   0x60    /* media changed */
   79 #define AER_SK_DATA_PROTECT     0x70    /* reading read-protected sector */
   80 #define AER_SK_BLANK_CHECK      0x80    /* blank check */
   81 #define AER_SK_VENDOR_SPECIFIC  0x90    /* vendor specific skey */
   82 #define AER_SK_COPY_ABORTED     0xa0    /* copy aborted */
   83 #define AER_SK_ABORTED_COMMAND  0xb0    /* command aborted, try again */
   84 #define AER_SK_EQUAL            0xc0    /* equal */
   85 #define AER_SK_VOLUME_OVERFLOW  0xd0    /* volume overflow */
   86 #define AER_SK_MISCOMPARE       0xe0    /* data did not match the medium */
   87 #define AER_SK_RESERVED         0xf0
   88 #define AER_BITS        "\2\4mchg\3abort\2eom\1ili"
   89 
   90 /*
   91  * Feature register bits
   92  */
   93 #define ARF_DMA         0x01            /* transfer data via DMA */
   94 #define ARF_OVERLAP     0x02            /* release the bus until completion */
   95 
   96 /*
   97  * Interrupt reason register bits
   98  */
   99 #define ARI_CMD         0x01            /* command(1) or data(0) */
  100 #define ARI_IN          0x02            /* transfer to(1) or from(0) the host */
  101 #define ARI_RELEASE     0x04            /* bus released until completion */
  102 
  103 /*
  104  * Drive register values
  105  */
  106 #define ARD_DRIVE0      0xa0            /* drive 0 selected */
  107 #define ARD_DRIVE1      0xb0            /* drive 1 selected */
  108 
  109 /*
  110  * ATA commands
  111  */
  112 #define ATAPIC_IDENTIFY         0xa1    /* get drive parameters */
  113 #define ATAPIC_PACKET           0xa0    /* execute packet command */
  114 
  115 /*
  116  * Mandatory packet commands
  117  */
  118 #define ATAPI_TEST_UNIT_READY   0x00    /* check if the device is ready */
  119 #define ATAPI_REZERO_UNIT       0x01    /* reinit device */
  120 #define ATAPI_REQUEST_SENSE     0x03    /* get sense data */
  121 #define ATAPI_START_STOP        0x1b    /* start/stop the media */
  122 #define ATAPI_PREVENT_ALLOW     0x1e    /* prevent/allow media removal */
  123 #define ATAPI_READ_CAPACITY     0x25    /* get volume capacity */
  124 #define ATAPI_READ_BIG          0x28    /* read data */
  125 #define ATAPI_WRITE_BIG         0x2a    /* write data */
  126 #define ATAPI_SYNCHRONIZE_CACHE 0x35    /* flush write buf, close write chan */
  127 #define ATAPI_READ_SUBCHANNEL   0x42    /* get subchannel info */
  128 #define ATAPI_READ_TOC          0x43    /* get table of contents */
  129 #define ATAPI_READ_TRACK_INFO   0x52    /* get track information structure */
  130 #define ATAPI_MODE_SELECT       0x55    /* set device parameters */
  131 #define ATAPI_MODE_SENSE        0x5a    /* get device parameters */
  132 #define ATAPI_CLOSE_TRACK       0x5b    /* close track/session */
  133 #define ATAPI_LOAD_UNLOAD       0xa6    /* changer control command */
  134 #define ATAPI_PLAY_CD           0xb4    /* universal play command */
  135 #define ATAPI_MECH_STATUS       0xbd    /* get changer mechanism status */
  136 #define ATAPI_READ_CD           0xbe    /* read data */
  137 /*
  138  * Optional packet commands
  139  */
  140 #define ATAPI_PLAY_MSF          0x47    /* play by MSF address */
  141 #define ATAPI_PAUSE             0x4b    /* stop/start audio operation */
  142 
  143 /*
  144  * Nonstandard packet commands
  145  */
  146 #define ATAPI_PLAY_TRACK        0x48    /* play by track number */
  147 #define ATAPI_PLAY_BIG          0xa5    /* play by logical block address */
  148 
  149 #define DSC_POLL_INTERVAL       10
  150 
  151 /*
  152  * Drive parameter information
  153  */
  154 struct atapi_params {
  155         unsigned        cmdsz : 2;      /* packet command size */
  156 #define AT_PSIZE_12     0               /* 12 bytes */
  157 #define AT_PSIZE_16     1               /* 16 bytes */
  158         unsigned : 3;
  159         unsigned        drqtype : 2;    /* DRQ type */
  160 #define AT_DRQT_MPROC   0               /* microprocessor DRQ - 3 msec delay */
  161 #define AT_DRQT_INTR    1               /* interrupt DRQ - 10 msec delay */
  162 #define AT_DRQT_ACCEL   2               /* accelerated DRQ - 50 usec delay */
  163         unsigned        removable : 1;  /* device is removable */
  164         unsigned        devtype : 5;    /* device type */
  165 #define AT_TYPE_DIRECT  0               /* direct-access (magnetic disk) */
  166 #define AT_TYPE_TAPE    1               /* streaming tape (QIC-121 model) */
  167 #define AT_TYPE_CDROM   5               /* CD-ROM device */
  168 #define AT_TYPE_OPTICAL 7               /* optical disk */
  169         unsigned : 1;
  170         unsigned        proto : 2;      /* command protocol */
  171 #define AT_PROTO_ATAPI  2
  172         short reserved1[9];
  173         char            serial[20];     /* serial number - optional */
  174         short reserved2[3];
  175         char            revision[8];    /* firmware revision */
  176         char            model[40];      /* model name */
  177         short reserved3[2];
  178         u_char          vendor_cap;     /* vendor unique capabilities */
  179         unsigned        dmaflag : 1;    /* DMA supported */
  180         unsigned        lbaflag : 1;    /* LBA supported - always 1 */
  181         unsigned        iordydis : 1;   /* IORDY can be disabled */
  182         unsigned        iordyflag : 1;  /* IORDY supported */
  183         unsigned : 1;
  184         unsigned        ovlapflag : 1;  /* overlap operation supported */
  185         unsigned : 1;
  186         unsigned        idmaflag : 1;   /* interleaved DMA supported */
  187         short reserved4;
  188         u_short         pio_timing;     /* PIO cycle timing */
  189         u_short         dma_timing;     /* DMA cycle timing */
  190         u_short         flags;
  191 #define AT_FLAG_54_58   1               /* words 54-58 valid */
  192 #define AT_FLAG_64_70   2               /* words 64-70 valid */
  193         short reserved5[8];
  194         u_char          swdma_flag;     /* singleword DMA mode supported */
  195         u_char          swdma_active;   /* singleword DMA mode active */
  196         u_char          mwdma_flag;     /* multiword DMA mode supported */
  197         u_char          mwdma_active;   /* multiword DMA mode active */
  198         u_char          apio_flag;      /* advanced PIO mode supported */
  199         u_char reserved6;
  200         u_short         mwdma_min;      /* min. M/W DMA time per word (ns) */
  201         u_short         mwdma_dflt;     /* recommended M/W DMA time (ns) - optional */
  202         u_short         pio_nfctl_min;  /* min. PIO cycle time w/o flow ctl - optional */
  203         u_short         pio_iordy_min;  /* min. PIO c/t with IORDY flow ctl - optional */
  204         short reserved7[2];
  205         u_short         rls_ovlap;      /* release time (us) for overlap cmd - optional */
  206         u_short         rls_service;    /* release time (us) for service cmd - optional */
  207 };
  208 
  209 /*
  210  * ATAPI operation result structure
  211  */
  212 struct atapires {
  213         u_char code;                    /* result code */
  214 #define RES_OK          0               /* i/o done */
  215 #define RES_ERR         1               /* i/o finished with error */
  216 #define RES_NOTRDY      2               /* controller not ready */
  217 #define RES_NODRQ       3               /* no data request */
  218 #define RES_INVDIR      4               /* invalid bus phase direction */
  219 #define RES_OVERRUN     5               /* data overrun */
  220 #define RES_UNDERRUN    6               /* data underrun */
  221         u_char status;                  /* status register contents */
  222         u_char error;                   /* error register contents */
  223 };
  224 
  225 struct atapidrv {                       /* delayed attach info */
  226         int ctlr;                       /* IDE controller, 0/1 */
  227         int unit;                       /* drive unit, 0/1 */
  228         int port;                       /* controller base port */
  229         int attached;                   /* the drive is attached */
  230 };
  231 
  232 struct buf;
  233 struct dmy;
  234 typedef void atapi_callback_t(struct dmy *, struct buf *, int, struct atapires);
  235 
  236 struct atapicmd {                       /* ATAPI command block */
  237         struct atapicmd *next;          /* next command in queue */
  238         int              busy;          /* busy flag */
  239         u_char           cmd[16];       /* command and args */
  240         int              unit;          /* drive unit number */
  241         int              count;         /* byte count, >0 - read, <0 - write */
  242         char            *addr;          /* data to transfer */
  243         atapi_callback_t *callback;     /* call when done */
  244         void            *cbarg1;        /* callback arg 1 */
  245         void            *cbarg2;        /* callback arg 1 */
  246         struct atapires  result;        /* resulting error code */
  247 };
  248 
  249 struct atapi {                          /* ATAPI controller data */
  250         u_short          port;          /* i/o port base */
  251         u_char           ctrlr;         /* physical controller number */
  252         u_char           debug : 1;     /* trace enable flag */
  253         u_char           cmd16 : 1;     /* 16-byte command flag */
  254         u_char           intrcmd : 1;   /* interrupt before cmd flag */
  255         u_char           slow : 1;      /* slow reaction device */
  256         u_char           accel : 1;     /* accelerated reaction device */
  257         u_char           use_dsc : 1;   /* use DSC completition handeling */
  258         u_char           wait_for_dsc : 1;
  259         u_int            dsc_timeout;
  260         u_char           attached[2];   /* units are attached to subdrivers */
  261         struct atapi_params *params[2]; /* params for units 0,1 */
  262         struct atapicmd *queue;         /* queue of commands to perform */
  263         struct atapicmd *tail;          /* tail of queue */
  264         struct atapicmd *free;          /* queue of free command blocks */
  265         struct atapicmd  cmdrq[16];     /* pool of command requests */
  266 };
  267 
  268 #ifdef _KERNEL
  269 struct atapi;
  270 
  271 extern struct atapidrv atapi_drvtab[4]; /* delayed attach info */
  272 extern int atapi_ndrv;                  /* the number of potential drives */
  273 extern struct atapi *atapi_tab;         /* the table of atapi controllers */
  274 
  275 int atapi_attach (int ctlr, int unit, int port);
  276 int atapi_strt (int ctrlr);
  277 int atapi_intr (int ctrlr);
  278 void atapi_debug (struct atapi *ata, int on);
  279 struct atapires atapi_request_wait (struct atapi *ata, int unit,
  280         u_char cmd, u_char a1, u_char a2, u_char a3, u_char a4,
  281         u_char a5, u_char a6, u_char a7, u_char a8, u_char a9,
  282         u_char a10, u_char a11, u_char a12, u_char a13, u_char a14, u_char a15,
  283         char *addr, int count);
  284 void atapi_request_callback (struct atapi *ata, int unit,
  285         u_char cmd, u_char a1, u_char a2, u_char a3, u_char a4,
  286         u_char a5, u_char a6, u_char a7, u_char a8, u_char a9,
  287         u_char a10, u_char a11, u_char a12, u_char a13, u_char a14, u_char a15,
  288         char *addr, int count, atapi_callback_t *done, void *x, void *y);
  289 struct atapires atapi_request_immediate (struct atapi *ata, int unit,
  290         u_char cmd, u_char a1, u_char a2, u_char a3, u_char a4,
  291         u_char a5, u_char a6, u_char a7, u_char a8, u_char a9,
  292         u_char a10, u_char a11, u_char a12, u_char a13, u_char a14, u_char a15,
  293         char *addr, int count);
  294 #endif

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