Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/bs/bshw.h
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1 /* $NecBSD: bshw.h,v 1.2 1997/10/31 17:43:38 honda Exp $ */ 2 /* $NetBSD$ */ 3 /* 4 * [NetBSD for NEC PC98 series] 5 * Copyright (c) 1994, 1995, 1996 NetBSD/pc98 porting staff. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. The name of the author may not be used to endorse or promote products 17 * derived from this software without specific prior written permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * $FreeBSD: releng/5.2/sys/i386/isa/bs/bshw.h 92765 2002-03-20 07:51:46Z alfred $ 32 */ 33 /* 34 * Copyright (c) 1994, 1995, 1996 Naofumi HONDA. All rights reserved. 35 */ 36 37 /* NEC port offsets */ 38 #define BSHW_DEFAULT_PORT 0xcc0 39 #define BSHW_IOSZ 5 40 41 #define addr_port 0 42 #define stat_port 0 43 #define ctrl_port 2 44 #define cmd_port 4 45 46 #define BSHW_MAX_OFFSET 12 47 #define BSHW_SEL_TIMEOUT 0x80 48 49 #define BSHW_READ BSR_IOR 50 #define BSHW_WRITE 0x0 51 52 #define BSHW_SMITFIFO_OFFSET 0x1000 53 54 #define BSHW_CMD_CHECK(CCB, CAT) (bshw_cmd[(CCB)->cmd[0]] & (CAT)) 55 /********************************************************* 56 * static inline declare. 57 *********************************************************/ 58 static BS_INLINE void write_wd33c93(struct bs_softc *, u_int, u_int8_t); 59 static BS_INLINE u_int8_t read_wd33c93(struct bs_softc *, u_int); 60 static BS_INLINE u_int8_t bshw_get_auxstat(struct bs_softc *); 61 static BS_INLINE u_int8_t bshw_get_busstat(struct bs_softc *); 62 static BS_INLINE u_int8_t bshw_get_status_insat(struct bs_softc *); 63 static BS_INLINE u_int8_t bshw_read_data(struct bs_softc *); 64 static BS_INLINE void bshw_write_data(struct bs_softc *, u_int8_t); 65 static BS_INLINE void bshw_set_count(struct bs_softc *, u_int); 66 static BS_INLINE u_int bshw_get_count(struct bs_softc *); 67 static BS_INLINE void bshw_set_dst_id(struct bs_softc *, u_int, u_int); 68 static BS_INLINE void bshw_set_lun(struct bs_softc *, u_int); 69 static BS_INLINE u_int bshw_get_src_id(struct bs_softc *); 70 static BS_INLINE void bshw_negate_ack(struct bs_softc *); 71 static BS_INLINE void bshw_assert_atn(struct bs_softc *); 72 static BS_INLINE void bshw_assert_select(struct bs_softc *); 73 static BS_INLINE void bshw_start_xfer(struct bs_softc *); 74 static BS_INLINE void bshw_start_sxfer(struct bs_softc *); 75 static BS_INLINE void bshw_cmd_pass(struct bs_softc *, u_int); 76 static BS_INLINE void bshw_start_sat(struct bs_softc *, u_int); 77 static BS_INLINE void bshw_abort_cmd(struct bs_softc *); 78 static BS_INLINE void bshw_set_sync_reg(struct bs_softc *, u_int); 79 static BS_INLINE void bshw_set_poll_trans(struct bs_softc *, u_int); 80 static BS_INLINE void bshw_set_dma_trans(struct bs_softc *, u_int); 81 82 /********************************************************* 83 * global declare 84 *********************************************************/ 85 void bs_dma_xfer(struct targ_info *, u_int); 86 void bs_dma_xfer_end(struct targ_info *); 87 void bshw_dmaabort(struct bs_softc *, struct targ_info *); 88 89 void bshw_adj_syncdata(struct syncdata *); 90 void bshw_set_synchronous(struct bs_softc *, struct targ_info *); 91 92 void bs_smit_xfer_end(struct targ_info *); 93 void bshw_smitabort(struct bs_softc *); 94 95 void bshw_setup_ctrl_reg(struct bs_softc *, u_int); 96 int bshw_chip_reset(struct bs_softc *); 97 void bshw_bus_reset(struct bs_softc *); 98 int bshw_board_probe(struct bs_softc *, u_int *, u_int *); 99 void bshw_lock(struct bs_softc *); 100 void bshw_unlock(struct bs_softc *); 101 void bshw_get_syncreg(struct bs_softc *); 102 void bshw_issue_satcmd(struct bs_softc *, struct bsccb *, int); 103 void bshw_print_port(struct bs_softc *); 104 105 void bs_lc_smit_xfer(struct targ_info *, u_int); 106 107 extern struct dvcfg_hwsel bshw_hwsel; 108 extern u_int8_t bshw_cmd[]; 109 110 /********************************************************* 111 * hw 112 *********************************************************/ 113 struct bshw { 114 #define BSHW_SYNC_RELOAD 0x01 115 #define BSHW_SMFIFO 0x02 116 #define BSHW_DOUBLE_DMACHAN 0x04 117 u_int hw_flags; 118 119 u_int sregaddr; 120 121 int ((*dma_init)(struct bs_softc *)); 122 void ((*dma_start)(struct bs_softc *)); 123 void ((*dma_stop)(struct bs_softc *)); 124 }; 125 126 /********************************************************* 127 * inline funcs. 128 *********************************************************/ 129 /* 130 * XXX: If your board does not work well, Please try BS_NEEDS_WEIGHT. 131 */ 132 static BS_INLINE void 133 write_wd33c93(bsc, addr, data) 134 struct bs_softc *bsc; 135 u_int addr; 136 u_int8_t data; 137 { 138 139 BUS_IOW(addr_port, addr); 140 BUS_IOW(ctrl_port, data); 141 } 142 143 static BS_INLINE u_int8_t 144 read_wd33c93(bsc, addr) 145 struct bs_softc *bsc; 146 u_int addr; 147 { 148 149 BUS_IOW(addr_port, addr); 150 return BUS_IOR(ctrl_port); 151 } 152 153 /* status */ 154 static BS_INLINE u_int8_t 155 bshw_get_auxstat(bsc) 156 struct bs_softc *bsc; 157 { 158 159 return BUS_IOR(stat_port); 160 } 161 162 static BS_INLINE u_int8_t 163 bshw_get_busstat(bsc) 164 struct bs_softc *bsc; 165 { 166 167 return read_wd33c93(bsc, wd3s_stat); 168 } 169 170 static BS_INLINE u_int8_t 171 bshw_get_status_insat(bsc) 172 struct bs_softc *bsc; 173 { 174 175 return read_wd33c93(bsc, wd3s_lun); 176 } 177 178 /* data */ 179 static BS_INLINE u_int8_t 180 bshw_read_data(bsc) 181 struct bs_softc *bsc; 182 { 183 184 return read_wd33c93(bsc, wd3s_data); 185 } 186 187 static BS_INLINE void 188 bshw_write_data(bsc, data) 189 struct bs_softc *bsc; 190 u_int8_t data; 191 { 192 193 write_wd33c93(bsc, wd3s_data, data); 194 } 195 196 /* counter */ 197 static BS_INLINE void 198 bshw_set_count(bsc, count) 199 struct bs_softc *bsc; 200 u_int count; 201 { 202 203 BUS_IOW(addr_port, wd3s_cnt); 204 BUS_IOW(ctrl_port, count >> 16); 205 BUS_IOW(ctrl_port, count >> 8); 206 BUS_IOW(ctrl_port, count); 207 } 208 209 static BS_INLINE u_int 210 bshw_get_count(bsc) 211 struct bs_softc *bsc; 212 { 213 u_int count; 214 215 BUS_IOW(addr_port, wd3s_cnt); 216 count = (((u_int) BUS_IOR(ctrl_port)) << 16); 217 count += (((u_int) BUS_IOR(ctrl_port)) << 8); 218 count += ((u_int) BUS_IOR(ctrl_port)); 219 return count; 220 } 221 222 /* ID */ 223 static BS_INLINE void 224 bshw_set_lun(bsc, lun) 225 struct bs_softc *bsc; 226 u_int lun; 227 { 228 229 write_wd33c93(bsc, wd3s_lun, lun); 230 } 231 232 static BS_INLINE void 233 bshw_set_dst_id(bsc, target, lun) 234 struct bs_softc *bsc; 235 u_int target, lun; 236 { 237 238 write_wd33c93(bsc, wd3s_did, target); 239 write_wd33c93(bsc, wd3s_lun, lun); 240 } 241 242 static BS_INLINE u_int 243 bshw_get_src_id(bsc) 244 struct bs_softc *bsc; 245 { 246 247 return (read_wd33c93(bsc, wd3s_sid) & SIDR_IDM); 248 } 249 250 /* phase */ 251 static BS_INLINE void 252 bshw_negate_ack(bsc) 253 struct bs_softc *bsc; 254 { 255 256 write_wd33c93(bsc, wd3s_cmd, WD3S_NEGATE_ACK); 257 } 258 259 static BS_INLINE void 260 bshw_assert_atn(bsc) 261 struct bs_softc *bsc; 262 { 263 264 write_wd33c93(bsc, wd3s_cmd, WD3S_ASSERT_ATN); 265 } 266 267 static BS_INLINE void 268 bshw_assert_select(bsc) 269 struct bs_softc *bsc; 270 { 271 272 write_wd33c93(bsc, wd3s_cmd, WD3S_SELECT_ATN); 273 } 274 275 static BS_INLINE void 276 bshw_start_xfer(bsc) 277 struct bs_softc *bsc; 278 { 279 280 write_wd33c93(bsc, wd3s_cmd, WD3S_TFR_INFO); 281 } 282 283 static BS_INLINE void 284 bshw_start_sxfer(bsc) 285 struct bs_softc *bsc; 286 { 287 288 write_wd33c93(bsc, wd3s_cmd, WD3S_SBT | WD3S_TFR_INFO); 289 } 290 291 static BS_INLINE void 292 bshw_cmd_pass(bsc, ph) 293 struct bs_softc *bsc; 294 u_int ph; 295 { 296 297 write_wd33c93(bsc, wd3s_cph, ph); 298 } 299 300 static BS_INLINE void 301 bshw_start_sat(bsc, flag) 302 struct bs_softc *bsc; 303 u_int flag; 304 { 305 306 write_wd33c93(bsc, wd3s_cmd, 307 (flag ? WD3S_SELECT_ATN_TFR : WD3S_SELECT_NO_ATN_TFR)); 308 } 309 310 311 static BS_INLINE void 312 bshw_abort_cmd(bsc) 313 struct bs_softc *bsc; 314 { 315 316 write_wd33c93(bsc, wd3s_cmd, WD3S_ABORT); 317 } 318 319 /* transfer mode */ 320 static BS_INLINE void 321 bshw_set_sync_reg(bsc, val) 322 struct bs_softc *bsc; 323 u_int val; 324 { 325 326 write_wd33c93(bsc, wd3s_synch, val); 327 } 328 329 static BS_INLINE void 330 bshw_set_poll_trans(bsc, flags) 331 struct bs_softc *bsc; 332 u_int flags; 333 { 334 335 if (bsc->sc_flags & BSDMATRANSFER) 336 { 337 bsc->sc_flags &= ~BSDMATRANSFER; 338 bshw_setup_ctrl_reg(bsc, flags); 339 } 340 } 341 342 static BS_INLINE void 343 bshw_set_dma_trans(bsc, flags) 344 struct bs_softc *bsc; 345 u_int flags; 346 { 347 348 if ((bsc->sc_flags & BSDMATRANSFER) == 0) 349 { 350 bsc->sc_flags |= BSDMATRANSFER; 351 bshw_setup_ctrl_reg(bsc, flags); 352 } 353 }
Cache object: ba3a97513696c98180f4fac11adf62fe
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