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sys/i386/isa/clock.c
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1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * All rights reserved. 4 * 5 * This code is derived from software contributed to Berkeley by 6 * William Jolitz and Don Ahn. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by the University of 19 * California, Berkeley and its contributors. 20 * 4. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91 37 * $FreeBSD$ 38 */ 39 40 /* 41 * Routines to handle clock hardware. 42 */ 43 44 /* 45 * inittodr, settodr and support routines written 46 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at> 47 * 48 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94 49 */ 50 51 #include "opt_clock.h" 52 #include "apm.h" 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/time.h> 57 #include <sys/kernel.h> 58 #ifndef SMP 59 #include <sys/lock.h> 60 #endif 61 #include <sys/sysctl.h> 62 63 #include <machine/clock.h> 64 #ifdef CLK_CALIBRATION_LOOP 65 #include <machine/cons.h> 66 #endif 67 #include <machine/cputypes.h> 68 #include <machine/frame.h> 69 #include <machine/ipl.h> 70 #include <machine/limits.h> 71 #include <machine/md_var.h> 72 #if NAPM > 0 73 #include <machine/apm_bios.h> 74 #include <i386/apm/apm_setup.h> 75 #endif 76 #ifdef APIC_IO 77 #include <machine/segments.h> 78 #endif 79 #if defined(SMP) || defined(APIC_IO) 80 #include <machine/smp.h> 81 #endif /* SMP || APIC_IO */ 82 #include <machine/specialreg.h> 83 84 #include <i386/isa/icu.h> 85 #include <i386/isa/isa.h> 86 #include <i386/isa/rtc.h> 87 #include <i386/isa/timerreg.h> 88 89 #include <sys/interrupt.h> 90 91 #ifdef SMP 92 #define disable_intr() CLOCK_DISABLE_INTR() 93 #define enable_intr() CLOCK_ENABLE_INTR() 94 95 #ifdef APIC_IO 96 #include <i386/isa/intr_machdep.h> 97 /* The interrupt triggered by the 8254 (timer) chip */ 98 int apic_8254_intr; 99 static u_long read_intr_count __P((int vec)); 100 static void setup_8254_mixed_mode __P((void)); 101 #endif 102 #endif /* SMP */ 103 104 /* 105 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we 106 * can use a simple formula for leap years. 107 */ 108 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0) 109 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31) 110 111 #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x)) 112 113 /* 114 * Time in timer cycles that it takes for microtime() to disable interrupts 115 * and latch the count. microtime() currently uses "cli; outb ..." so it 116 * normally takes less than 2 timer cycles. Add a few for cache misses. 117 * Add a few more to allow for latency in bogus calls to microtime() with 118 * interrupts already disabled. 119 */ 120 #define TIMER0_LATCH_COUNT 20 121 122 /* 123 * Maximum frequency that we are willing to allow for timer0. Must be 124 * low enough to guarantee that the timer interrupt handler returns 125 * before the next timer interrupt. 126 */ 127 #define TIMER0_MAX_FREQ 20000 128 129 int adjkerntz; /* local offset from GMT in seconds */ 130 int disable_rtc_set; /* disable resettodr() if != 0 */ 131 volatile u_int idelayed; 132 int statclock_disable; 133 u_int stat_imask = SWI_CLOCK_MASK; 134 #ifndef TIMER_FREQ 135 #define TIMER_FREQ 1193182 136 #endif 137 u_int timer_freq = TIMER_FREQ; 138 int timer0_max_count; 139 u_int tsc_freq; 140 int tsc_is_broken; 141 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */ 142 143 static int beeping = 0; 144 static u_int clk_imask = HWI_MASK | SWI_MASK; 145 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31}; 146 static u_int hardclock_max_count; 147 static u_int32_t i8254_lastcount; 148 static u_int32_t i8254_offset; 149 static int i8254_ticked; 150 /* 151 * XXX new_function and timer_func should not handle clockframes, but 152 * timer_func currently needs to hold hardclock to handle the 153 * timer0_state == 0 case. We should use register_intr()/unregister_intr() 154 * to switch between clkintr() and a slightly different timerintr(). 155 */ 156 static void (*new_function) __P((struct clockframe *frame)); 157 static u_int new_rate; 158 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 159 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR; 160 static u_int timer0_prescaler_count; 161 162 /* Values for timerX_state: */ 163 #define RELEASED 0 164 #define RELEASE_PENDING 1 165 #define ACQUIRED 2 166 #define ACQUIRE_PENDING 3 167 168 static u_char timer0_state; 169 static u_char timer2_state; 170 static void (*timer_func) __P((struct clockframe *frame)) = hardclock; 171 static u_int tsc_present; 172 173 static unsigned i8254_get_timecount __P((struct timecounter *tc)); 174 static unsigned tsc_get_timecount __P((struct timecounter *tc)); 175 static void set_timer_freq(u_int freq, int intr_freq); 176 177 static struct timecounter tsc_timecounter = { 178 tsc_get_timecount, /* get_timecount */ 179 0, /* no poll_pps */ 180 ~0u, /* counter_mask */ 181 0, /* frequency */ 182 "TSC" /* name */ 183 }; 184 185 SYSCTL_OPAQUE(_debug, OID_AUTO, tsc_timecounter, CTLFLAG_RD, 186 &tsc_timecounter, sizeof(tsc_timecounter), "S,timecounter", ""); 187 188 static struct timecounter i8254_timecounter = { 189 i8254_get_timecount, /* get_timecount */ 190 0, /* no poll_pps */ 191 ~0u, /* counter_mask */ 192 0, /* frequency */ 193 "i8254" /* name */ 194 }; 195 196 SYSCTL_OPAQUE(_debug, OID_AUTO, i8254_timecounter, CTLFLAG_RD, 197 &i8254_timecounter, sizeof(i8254_timecounter), "S,timecounter", ""); 198 199 static void 200 clkintr(struct clockframe frame) 201 { 202 if (timecounter->tc_get_timecount == i8254_get_timecount) { 203 /* 204 * Maintain i8254_offset and related variables. Optimize 205 * the usual case where i8254 counter rollover has not been 206 * detected in i8254_get_timecount() by pretending that we 207 * read the counter when it rolled over. Otherwise, call 208 * i8254_get_timecount() to do most of the work. The 209 * hardware counter must be read to ensure monotonicity 210 * despite multiple rollovers and misbehaving hardware. 211 */ 212 (disable_intr)(); /* XXX avoid clock locking */ 213 if (i8254_ticked) { 214 i8254_get_timecount(NULL); 215 i8254_ticked = 0; 216 } else { 217 i8254_offset += timer0_max_count; 218 i8254_lastcount = 0; 219 } 220 (enable_intr)(); /* XXX avoid clock locking */ 221 } 222 timer_func(&frame); 223 switch (timer0_state) { 224 225 case RELEASED: 226 setdelayed(); 227 break; 228 229 case ACQUIRED: 230 if ((timer0_prescaler_count += timer0_max_count) 231 >= hardclock_max_count) { 232 timer0_prescaler_count -= hardclock_max_count; 233 hardclock(&frame); 234 setdelayed(); 235 } 236 break; 237 238 case ACQUIRE_PENDING: 239 setdelayed(); 240 timer0_max_count = TIMER_DIV(new_rate); 241 disable_intr(); 242 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 243 outb(TIMER_CNTR0, timer0_max_count & 0xff); 244 outb(TIMER_CNTR0, timer0_max_count >> 8); 245 enable_intr(); 246 timer0_prescaler_count = 0; 247 timer_func = new_function; 248 timer0_state = ACQUIRED; 249 break; 250 251 case RELEASE_PENDING: 252 if ((timer0_prescaler_count += timer0_max_count) 253 >= hardclock_max_count) { 254 timer0_prescaler_count -= hardclock_max_count; 255 #ifdef FIXME 256 /* 257 * XXX: This magic doesn't work, but It shouldn't be 258 * needed now anyway since we will not be able to 259 * aquire the i8254 if it is used for timecounting. 260 */ 261 /* 262 * See microtime.s for this magic. 263 */ 264 time.tv_usec += (27465 * timer0_prescaler_count) >> 15; 265 if (time.tv_usec >= 1000000) 266 time.tv_usec -= 1000000; 267 #endif 268 hardclock(&frame); 269 setdelayed(); 270 timer0_max_count = hardclock_max_count; 271 disable_intr(); 272 outb(TIMER_MODE, 273 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 274 outb(TIMER_CNTR0, timer0_max_count & 0xff); 275 outb(TIMER_CNTR0, timer0_max_count >> 8); 276 enable_intr(); 277 timer0_prescaler_count = 0; 278 timer_func = hardclock; 279 timer0_state = RELEASED; 280 } 281 break; 282 } 283 } 284 285 /* 286 * The acquire and release functions must be called at ipl >= splclock(). 287 */ 288 int 289 acquire_timer0(int rate, void (*function) __P((struct clockframe *frame))) 290 { 291 static int old_rate; 292 293 if (rate <= 0 || rate > TIMER0_MAX_FREQ) 294 return (-1); 295 if (strcmp(timecounter->tc_name, "i8254") == 0) 296 return (-1); 297 switch (timer0_state) { 298 299 case RELEASED: 300 timer0_state = ACQUIRE_PENDING; 301 break; 302 303 case RELEASE_PENDING: 304 if (rate != old_rate) 305 return (-1); 306 /* 307 * The timer has been released recently, but is being 308 * re-acquired before the release completed. In this 309 * case, we simply reclaim it as if it had not been 310 * released at all. 311 */ 312 timer0_state = ACQUIRED; 313 break; 314 315 default: 316 return (-1); /* busy */ 317 } 318 new_function = function; 319 old_rate = new_rate = rate; 320 return (0); 321 } 322 323 int 324 acquire_timer2(int mode) 325 { 326 327 if (timer2_state != RELEASED) 328 return (-1); 329 timer2_state = ACQUIRED; 330 331 /* 332 * This access to the timer registers is as atomic as possible 333 * because it is a single instruction. We could do better if we 334 * knew the rate. Use of splclock() limits glitches to 10-100us, 335 * and this is probably good enough for timer2, so we aren't as 336 * careful with it as with timer0. 337 */ 338 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f)); 339 340 return (0); 341 } 342 343 int 344 release_timer0() 345 { 346 switch (timer0_state) { 347 348 case ACQUIRED: 349 timer0_state = RELEASE_PENDING; 350 break; 351 352 case ACQUIRE_PENDING: 353 /* Nothing happened yet, release quickly. */ 354 timer0_state = RELEASED; 355 break; 356 357 default: 358 return (-1); 359 } 360 return (0); 361 } 362 363 int 364 release_timer2() 365 { 366 367 if (timer2_state != ACQUIRED) 368 return (-1); 369 timer2_state = RELEASED; 370 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT); 371 return (0); 372 } 373 374 /* 375 * This routine receives statistical clock interrupts from the RTC. 376 * As explained above, these occur at 128 interrupts per second. 377 * When profiling, we receive interrupts at a rate of 1024 Hz. 378 * 379 * This does not actually add as much overhead as it sounds, because 380 * when the statistical clock is active, the hardclock driver no longer 381 * needs to keep (inaccurate) statistics on its own. This decouples 382 * statistics gathering from scheduling interrupts. 383 * 384 * The RTC chip requires that we read status register C (RTC_INTR) 385 * to acknowledge an interrupt, before it will generate the next one. 386 * Under high interrupt load, rtcintr() can be indefinitely delayed and 387 * the clock can tick immediately after the read from RTC_INTR. In this 388 * case, the mc146818A interrupt signal will not drop for long enough 389 * to register with the 8259 PIC. If an interrupt is missed, the stat 390 * clock will halt, considerably degrading system performance. This is 391 * why we use 'while' rather than a more straightforward 'if' below. 392 * Stat clock ticks can still be lost, causing minor loss of accuracy 393 * in the statistics, but the stat clock will no longer stop. 394 */ 395 static void 396 rtcintr(struct clockframe frame) 397 { 398 while (rtcin(RTC_INTR) & RTCIR_PERIOD) 399 statclock(&frame); 400 } 401 402 #include "opt_ddb.h" 403 #ifdef DDB 404 #include <ddb/ddb.h> 405 406 DB_SHOW_COMMAND(rtc, rtc) 407 { 408 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n", 409 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY), 410 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC), 411 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR)); 412 } 413 #endif /* DDB */ 414 415 static int 416 getit(void) 417 { 418 u_long ef; 419 int high, low; 420 421 ef = read_eflags(); 422 disable_intr(); 423 424 /* Select timer0 and latch counter value. */ 425 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 426 427 low = inb(TIMER_CNTR0); 428 high = inb(TIMER_CNTR0); 429 430 CLOCK_UNLOCK(); 431 write_eflags(ef); 432 return ((high << 8) | low); 433 } 434 435 /* 436 * Wait "n" microseconds. 437 * Relies on timer 1 counting down from (timer_freq / hz) 438 * Note: timer had better have been programmed before this is first used! 439 */ 440 void 441 DELAY(int n) 442 { 443 int delta, prev_tick, tick, ticks_left; 444 445 #ifdef DELAYDEBUG 446 int getit_calls = 1; 447 int n1; 448 static int state = 0; 449 450 if (state == 0) { 451 state = 1; 452 for (n1 = 1; n1 <= 10000000; n1 *= 10) 453 DELAY(n1); 454 state = 2; 455 } 456 if (state == 1) 457 printf("DELAY(%d)...", n); 458 #endif 459 /* 460 * Guard against the timer being uninitialized if we are called 461 * early for console i/o. 462 */ 463 if (timer0_max_count == 0) 464 set_timer_freq(timer_freq, hz); 465 466 /* 467 * Read the counter first, so that the rest of the setup overhead is 468 * counted. Guess the initial overhead is 20 usec (on most systems it 469 * takes about 1.5 usec for each of the i/o's in getit(). The loop 470 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The 471 * multiplications and divisions to scale the count take a while). 472 */ 473 prev_tick = getit(); 474 n -= 0; /* XXX actually guess no initial overhead */ 475 /* 476 * Calculate (n * (timer_freq / 1e6)) without using floating point 477 * and without any avoidable overflows. 478 */ 479 if (n <= 0) 480 ticks_left = 0; 481 else if (n < 256) 482 /* 483 * Use fixed point to avoid a slow division by 1000000. 484 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest. 485 * 2^15 is the first power of 2 that gives exact results 486 * for n between 0 and 256. 487 */ 488 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15; 489 else 490 /* 491 * Don't bother using fixed point, although gcc-2.7.2 492 * generates particularly poor code for the long long 493 * division, since even the slow way will complete long 494 * before the delay is up (unless we're interrupted). 495 */ 496 ticks_left = ((u_int)n * (long long)timer_freq + 999999) 497 / 1000000; 498 499 while (ticks_left > 0) { 500 tick = getit(); 501 #ifdef DELAYDEBUG 502 ++getit_calls; 503 #endif 504 delta = prev_tick - tick; 505 prev_tick = tick; 506 if (delta < 0) { 507 delta += timer0_max_count; 508 /* 509 * Guard against timer0_max_count being wrong. 510 * This shouldn't happen in normal operation, 511 * but it may happen if set_timer_freq() is 512 * traced. 513 */ 514 if (delta < 0) 515 delta = 0; 516 } 517 ticks_left -= delta; 518 } 519 #ifdef DELAYDEBUG 520 if (state == 1) 521 printf(" %d calls to getit() at %d usec each\n", 522 getit_calls, (n + 5) / getit_calls); 523 #endif 524 } 525 526 static void 527 sysbeepstop(void *chan) 528 { 529 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */ 530 release_timer2(); 531 beeping = 0; 532 } 533 534 int 535 sysbeep(int pitch, int period) 536 { 537 int x = splclock(); 538 539 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT)) 540 if (!beeping) { 541 /* Something else owns it. */ 542 splx(x); 543 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */ 544 } 545 disable_intr(); 546 outb(TIMER_CNTR2, pitch); 547 outb(TIMER_CNTR2, (pitch>>8)); 548 enable_intr(); 549 if (!beeping) { 550 /* enable counter2 output to speaker */ 551 outb(IO_PPI, inb(IO_PPI) | 3); 552 beeping = period; 553 timeout(sysbeepstop, (void *)NULL, period); 554 } 555 splx(x); 556 return (0); 557 } 558 559 /* 560 * RTC support routines 561 */ 562 563 int 564 rtcin(reg) 565 int reg; 566 { 567 u_char val; 568 569 outb(IO_RTC, reg); 570 inb(0x84); 571 val = inb(IO_RTC + 1); 572 inb(0x84); 573 return (val); 574 } 575 576 static __inline void 577 writertc(u_char reg, u_char val) 578 { 579 inb(0x84); 580 outb(IO_RTC, reg); 581 inb(0x84); 582 outb(IO_RTC + 1, val); 583 inb(0x84); /* XXX work around wrong order in rtcin() */ 584 } 585 586 static __inline int 587 readrtc(int port) 588 { 589 return(bcd2bin(rtcin(port))); 590 } 591 592 static u_int 593 calibrate_clocks(void) 594 { 595 u_int64_t old_tsc; 596 u_int count, prev_count, tot_count; 597 int sec, start_sec, timeout; 598 599 if (bootverbose) 600 printf("Calibrating clock(s) ... "); 601 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 602 goto fail; 603 timeout = 100000000; 604 605 /* Read the mc146818A seconds counter. */ 606 for (;;) { 607 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 608 sec = rtcin(RTC_SEC); 609 break; 610 } 611 if (--timeout == 0) 612 goto fail; 613 } 614 615 /* Wait for the mC146818A seconds counter to change. */ 616 start_sec = sec; 617 for (;;) { 618 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) { 619 sec = rtcin(RTC_SEC); 620 if (sec != start_sec) 621 break; 622 } 623 if (--timeout == 0) 624 goto fail; 625 } 626 627 /* Start keeping track of the i8254 counter. */ 628 prev_count = getit(); 629 if (prev_count == 0 || prev_count > timer0_max_count) 630 goto fail; 631 tot_count = 0; 632 633 if (tsc_present) 634 old_tsc = rdtsc(); 635 636 /* 637 * Wait for the mc146818A seconds counter to change. Read the i8254 638 * counter for each iteration since this is convenient and only 639 * costs a few usec of inaccuracy. The timing of the final reads 640 * of the counters almost matches the timing of the initial reads, 641 * so the main cause of inaccuracy is the varying latency from 642 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the 643 * rtcin(RTC_SEC) that returns a changed seconds count. The 644 * maximum inaccuracy from this cause is < 10 usec on 486's. 645 */ 646 start_sec = sec; 647 for (;;) { 648 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) 649 sec = rtcin(RTC_SEC); 650 count = getit(); 651 if (count == 0 || count > timer0_max_count) 652 goto fail; 653 if (count > prev_count) 654 tot_count += prev_count - (count - timer0_max_count); 655 else 656 tot_count += prev_count - count; 657 prev_count = count; 658 if (sec != start_sec) 659 break; 660 if (--timeout == 0) 661 goto fail; 662 } 663 664 /* 665 * Read the cpu cycle counter. The timing considerations are 666 * similar to those for the i8254 clock. 667 */ 668 if (tsc_present) 669 tsc_freq = rdtsc() - old_tsc; 670 671 if (bootverbose) { 672 if (tsc_present) 673 printf("TSC clock: %u Hz, ", tsc_freq); 674 printf("i8254 clock: %u Hz\n", tot_count); 675 } 676 return (tot_count); 677 678 fail: 679 if (bootverbose) 680 printf("failed, using default i8254 clock of %u Hz\n", 681 timer_freq); 682 return (timer_freq); 683 } 684 685 static void 686 set_timer_freq(u_int freq, int intr_freq) 687 { 688 u_long ef; 689 int new_timer0_max_count; 690 691 ef = read_eflags(); 692 disable_intr(); 693 timer_freq = freq; 694 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq); 695 if (new_timer0_max_count != timer0_max_count) { 696 timer0_max_count = new_timer0_max_count; 697 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 698 outb(TIMER_CNTR0, timer0_max_count & 0xff); 699 outb(TIMER_CNTR0, timer0_max_count >> 8); 700 } 701 CLOCK_UNLOCK(); 702 write_eflags(ef); 703 } 704 705 /* 706 * i8254_restore is called from apm_default_resume() to reload 707 * the countdown register. 708 * this should not be necessary but there are broken laptops that 709 * do not restore the countdown register on resume. 710 * when it happnes, it messes up the hardclock interval and system clock, 711 * which leads to the infamous "calcru: negative time" problem. 712 */ 713 void 714 i8254_restore(void) 715 { 716 u_long ef; 717 718 ef = read_eflags(); 719 disable_intr(); 720 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT); 721 outb(TIMER_CNTR0, timer0_max_count & 0xff); 722 outb(TIMER_CNTR0, timer0_max_count >> 8); 723 CLOCK_UNLOCK(); 724 write_eflags(ef); 725 } 726 727 /* 728 * Initialize 8254 timer 0 early so that it can be used in DELAY(). 729 * XXX initialization of other timers is unintentionally left blank. 730 */ 731 void 732 startrtclock() 733 { 734 u_int delta, freq; 735 736 if (cpu_feature & CPUID_TSC) 737 tsc_present = 1; 738 else 739 tsc_present = 0; 740 741 writertc(RTC_STATUSA, rtc_statusa); 742 writertc(RTC_STATUSB, RTCSB_24HR); 743 744 set_timer_freq(timer_freq, hz); 745 freq = calibrate_clocks(); 746 #ifdef CLK_CALIBRATION_LOOP 747 if (bootverbose) { 748 printf( 749 "Press a key on the console to abort clock calibration\n"); 750 while (cncheckc() == -1) 751 calibrate_clocks(); 752 } 753 #endif 754 755 /* 756 * Use the calibrated i8254 frequency if it seems reasonable. 757 * Otherwise use the default, and don't use the calibrated i586 758 * frequency. 759 */ 760 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq; 761 if (delta < timer_freq / 100) { 762 #ifndef CLK_USE_I8254_CALIBRATION 763 if (bootverbose) 764 printf( 765 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n"); 766 freq = timer_freq; 767 #endif 768 timer_freq = freq; 769 } else { 770 if (bootverbose) 771 printf( 772 "%d Hz differs from default of %d Hz by more than 1%%\n", 773 freq, timer_freq); 774 tsc_freq = 0; 775 } 776 777 set_timer_freq(timer_freq, hz); 778 i8254_timecounter.tc_frequency = timer_freq; 779 init_timecounter(&i8254_timecounter); 780 781 #ifndef CLK_USE_TSC_CALIBRATION 782 if (tsc_freq != 0) { 783 if (bootverbose) 784 printf( 785 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n"); 786 tsc_freq = 0; 787 } 788 #endif 789 if (tsc_present && tsc_freq == 0) { 790 /* 791 * Calibration of the i586 clock relative to the mc146818A 792 * clock failed. Do a less accurate calibration relative 793 * to the i8254 clock. 794 */ 795 u_int64_t old_tsc = rdtsc(); 796 797 DELAY(1000000); 798 tsc_freq = rdtsc() - old_tsc; 799 #ifdef CLK_USE_TSC_CALIBRATION 800 if (bootverbose) 801 printf("TSC clock: %u Hz (Method B)\n", tsc_freq); 802 #endif 803 } 804 805 #if !defined(SMP) 806 /* 807 * We can not use the TSC in SMP mode, until we figure out a 808 * cheap (impossible), reliable and precise (yeah right!) way 809 * to synchronize the TSCs of all the CPUs. 810 * Curse Intel for leaving the counter out of the I/O APIC. 811 */ 812 813 #if NAPM > 0 814 /* 815 * We can not use the TSC if we found an APM bios. Too many 816 * of them lie about their ability&intention to fiddle the CPU 817 * clock for us to rely on this. Precise timekeeping on an 818 * APM'ed machine is at best a fools pursuit anyway, since 819 * any and all of the time spent in various SMM code can't 820 * be reliably accounted for. Reading the RTC is your only 821 * source of reliable time info. The i8254 looses too of course 822 * but we need to have some kind of time... 823 */ 824 if (apm_version != APMINI_CANTFIND) 825 return; 826 #endif /* NAPM > 0 */ 827 828 if (tsc_present && tsc_freq != 0 && !tsc_is_broken) { 829 tsc_timecounter.tc_frequency = tsc_freq; 830 init_timecounter(&tsc_timecounter); 831 } 832 833 #endif /* !defined(SMP) */ 834 } 835 836 /* 837 * Initialize the time of day register, based on the time base which is, e.g. 838 * from a filesystem. 839 */ 840 void 841 inittodr(time_t base) 842 { 843 unsigned long sec, days; 844 int yd; 845 int year, month; 846 int y, m, s; 847 struct timespec ts; 848 849 if (base) { 850 s = splclock(); 851 ts.tv_sec = base; 852 ts.tv_nsec = 0; 853 set_timecounter(&ts); 854 splx(s); 855 } 856 857 /* Look if we have a RTC present and the time is valid */ 858 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) 859 goto wrong_time; 860 861 /* wait for time update to complete */ 862 /* If RTCSA_TUP is zero, we have at least 244us before next update */ 863 while (rtcin(RTC_STATUSA) & RTCSA_TUP); 864 865 days = 0; 866 #ifdef USE_RTC_CENTURY 867 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100; 868 #else 869 year = readrtc(RTC_YEAR) + 1900; 870 if (year < 1970) 871 year += 100; 872 #endif 873 if (year < 1970) 874 goto wrong_time; 875 month = readrtc(RTC_MONTH); 876 for (m = 1; m < month; m++) 877 days += daysinmonth[m-1]; 878 if ((month > 2) && LEAPYEAR(year)) 879 days ++; 880 days += readrtc(RTC_DAY) - 1; 881 yd = days; 882 for (y = 1970; y < year; y++) 883 days += DAYSPERYEAR + LEAPYEAR(y); 884 sec = ((( days * 24 + 885 readrtc(RTC_HRS)) * 60 + 886 readrtc(RTC_MIN)) * 60 + 887 readrtc(RTC_SEC)); 888 /* sec now contains the number of seconds, since Jan 1 1970, 889 in the local time zone */ 890 891 sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 892 893 y = time_second - sec; 894 if (y <= -2 || y >= 2) { 895 /* badly off, adjust it */ 896 s = splclock(); 897 ts.tv_sec = sec; 898 ts.tv_nsec = 0; 899 set_timecounter(&ts); 900 splx(s); 901 } 902 return; 903 904 wrong_time: 905 printf("Invalid time in real time clock.\n"); 906 printf("Check and reset the date immediately!\n"); 907 } 908 909 /* 910 * Write system time back to RTC 911 */ 912 void 913 resettodr() 914 { 915 unsigned long tm; 916 int y, m, s; 917 918 if (disable_rtc_set) 919 return; 920 921 s = splclock(); 922 tm = time_second; 923 splx(s); 924 925 /* Disable RTC updates and interrupts. */ 926 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR); 927 928 /* Calculate local time to put in RTC */ 929 930 tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0); 931 932 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */ 933 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */ 934 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */ 935 936 /* We have now the days since 01-01-1970 in tm */ 937 writertc(RTC_WDAY, (tm+4)%7); /* Write back Weekday */ 938 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y); 939 tm >= m; 940 y++, m = DAYSPERYEAR + LEAPYEAR(y)) 941 tm -= m; 942 943 /* Now we have the years in y and the day-of-the-year in tm */ 944 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */ 945 #ifdef USE_RTC_CENTURY 946 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */ 947 #endif 948 for (m = 0; ; m++) { 949 int ml; 950 951 ml = daysinmonth[m]; 952 if (m == 1 && LEAPYEAR(y)) 953 ml++; 954 if (tm < ml) 955 break; 956 tm -= ml; 957 } 958 959 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */ 960 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */ 961 962 /* Reenable RTC updates and interrupts. */ 963 writertc(RTC_STATUSB, rtc_statusb); 964 } 965 966 967 /* 968 * Start both clocks running. 969 */ 970 void 971 cpu_initclocks() 972 { 973 int diag; 974 #ifdef APIC_IO 975 int apic_8254_trial; 976 #endif /* APIC_IO */ 977 978 if (statclock_disable) { 979 /* 980 * The stat interrupt mask is different without the 981 * statistics clock. Also, don't set the interrupt 982 * flag which would normally cause the RTC to generate 983 * interrupts. 984 */ 985 stat_imask = HWI_MASK | SWI_MASK; 986 rtc_statusb = RTCSB_24HR; 987 } else { 988 /* Setting stathz to nonzero early helps avoid races. */ 989 stathz = RTC_NOPROFRATE; 990 profhz = RTC_PROFRATE; 991 } 992 993 /* Finish initializing 8253 timer 0. */ 994 #ifdef APIC_IO 995 996 apic_8254_intr = isa_apic_irq(0); 997 apic_8254_trial = 0; 998 if (apic_8254_intr >= 0 ) { 999 if (apic_int_type(0, 0) == 3) 1000 apic_8254_trial = 1; 1001 } else { 1002 /* look for ExtInt on pin 0 */ 1003 if (apic_int_type(0, 0) == 3) { 1004 apic_8254_intr = 0; 1005 setup_8254_mixed_mode(); 1006 } else 1007 panic("APIC_IO: Cannot route 8254 interrupt to CPU"); 1008 } 1009 1010 register_intr(/* irq */ apic_8254_intr, /* XXX id */ 0, /* flags */ 0, 1011 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1012 /* unit */ 0); 1013 INTREN(1 << apic_8254_intr); 1014 1015 #else /* APIC_IO */ 1016 1017 register_intr(/* irq */ 0, /* XXX id */ 0, /* flags */ 0, 1018 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1019 /* unit */ 0); 1020 INTREN(IRQ0); 1021 1022 #endif /* APIC_IO */ 1023 1024 /* Initialize RTC. */ 1025 writertc(RTC_STATUSA, rtc_statusa); 1026 writertc(RTC_STATUSB, RTCSB_24HR); 1027 1028 /* Don't bother enabling the statistics clock. */ 1029 if (statclock_disable) 1030 return; 1031 diag = rtcin(RTC_DIAG); 1032 if (diag != 0) 1033 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS); 1034 1035 #ifdef APIC_IO 1036 if (isa_apic_irq(8) != 8) 1037 panic("APIC RTC != 8"); 1038 #endif /* APIC_IO */ 1039 1040 register_intr(/* irq */ 8, /* XXX id */ 1, /* flags */ 0, 1041 /* XXX */ (inthand2_t *)rtcintr, &stat_imask, 1042 /* unit */ 0); 1043 1044 #ifdef APIC_IO 1045 INTREN(APIC_IRQ8); 1046 #else 1047 INTREN(IRQ8); 1048 #endif /* APIC_IO */ 1049 1050 writertc(RTC_STATUSB, rtc_statusb); 1051 1052 #ifdef APIC_IO 1053 if (apic_8254_trial) { 1054 1055 printf("APIC_IO: Testing 8254 interrupt delivery\n"); 1056 while (read_intr_count(8) < 6) 1057 ; /* nothing */ 1058 if (read_intr_count(apic_8254_intr) < 3) { 1059 /* 1060 * The MP table is broken. 1061 * The 8254 was not connected to the specified pin 1062 * on the IO APIC. 1063 * Workaround: Limited variant of mixed mode. 1064 */ 1065 INTRDIS(1 << apic_8254_intr); 1066 unregister_intr(apic_8254_intr, 1067 /* XXX */ (inthand2_t *) clkintr); 1068 printf("APIC_IO: Broken MP table detected: " 1069 "8254 is not connected to IO APIC int pin %d\n", 1070 apic_8254_intr); 1071 1072 apic_8254_intr = 0; 1073 setup_8254_mixed_mode(); 1074 register_intr(/* irq */ apic_8254_intr, /* XXX id */ 0, /* flags */ 0, 1075 /* XXX */ (inthand2_t *)clkintr, &clk_imask, 1076 /* unit */ 0); 1077 INTREN(1 << apic_8254_intr); 1078 } 1079 1080 } 1081 if (apic_8254_intr) 1082 printf("APIC_IO: routing 8254 via pin %d\n",apic_8254_intr); 1083 else 1084 printf("APIC_IO: routing 8254 via 8259 on pin 0\n"); 1085 #endif 1086 1087 } 1088 1089 #ifdef APIC_IO 1090 static u_long 1091 read_intr_count(int vec) 1092 { 1093 u_long *up; 1094 up = intr_countp[vec]; 1095 if (up) 1096 return *up; 1097 return 0UL; 1098 } 1099 1100 static void 1101 setup_8254_mixed_mode() 1102 { 1103 /* 1104 * Allow 8254 timer to INTerrupt 8259: 1105 * re-initialize master 8259: 1106 * reset; prog 4 bytes, single ICU, edge triggered 1107 */ 1108 outb(IO_ICU1, 0x13); 1109 outb(IO_ICU1 + 1, NRSVIDT); /* start vector (unused) */ 1110 outb(IO_ICU1 + 1, 0x00); /* ignore slave */ 1111 outb(IO_ICU1 + 1, 0x03); /* auto EOI, 8086 */ 1112 outb(IO_ICU1 + 1, 0xfe); /* unmask INT0 */ 1113 1114 /* program IO APIC for type 3 INT on INT0 */ 1115 if (ext_int_setup(0, 0) < 0) 1116 panic("8254 redirect via APIC pin0 impossible!"); 1117 } 1118 #endif 1119 1120 void 1121 setstatclockrate(int newhz) 1122 { 1123 if (newhz == RTC_PROFRATE) 1124 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF; 1125 else 1126 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF; 1127 writertc(RTC_STATUSA, rtc_statusa); 1128 } 1129 1130 static int 1131 sysctl_machdep_i8254_freq SYSCTL_HANDLER_ARGS 1132 { 1133 int error; 1134 u_int freq; 1135 1136 /* 1137 * Use `i8254' instead of `timer' in external names because `timer' 1138 * is is too generic. Should use it everywhere. 1139 */ 1140 freq = timer_freq; 1141 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1142 if (error == 0 && req->newptr != NULL) { 1143 if (timer0_state != RELEASED) 1144 return (EBUSY); /* too much trouble to handle */ 1145 set_timer_freq(freq, hz); 1146 i8254_timecounter.tc_frequency = freq; 1147 update_timecounter(&i8254_timecounter); 1148 } 1149 return (error); 1150 } 1151 1152 SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW, 1153 0, sizeof(u_int), sysctl_machdep_i8254_freq, "I", ""); 1154 1155 static int 1156 sysctl_machdep_tsc_freq SYSCTL_HANDLER_ARGS 1157 { 1158 int error; 1159 u_int freq; 1160 1161 if (tsc_timecounter.tc_frequency == 0) 1162 return (EOPNOTSUPP); 1163 freq = tsc_freq; 1164 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req); 1165 if (error == 0 && req->newptr != NULL) { 1166 tsc_freq = freq; 1167 tsc_timecounter.tc_frequency = tsc_freq; 1168 update_timecounter(&tsc_timecounter); 1169 } 1170 return (error); 1171 } 1172 1173 SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW, 1174 0, sizeof(u_int), sysctl_machdep_tsc_freq, "I", ""); 1175 1176 static unsigned 1177 i8254_get_timecount(struct timecounter *tc) 1178 { 1179 u_int count; 1180 u_long ef; 1181 u_int high, low; 1182 1183 ef = read_eflags(); 1184 disable_intr(); 1185 1186 /* Select timer0 and latch counter value. */ 1187 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH); 1188 1189 low = inb(TIMER_CNTR0); 1190 high = inb(TIMER_CNTR0); 1191 1192 count = hardclock_max_count - ((high << 8) | low); 1193 if (count < i8254_lastcount) { 1194 i8254_ticked = 1; 1195 i8254_offset += hardclock_max_count; 1196 } 1197 1198 i8254_lastcount = count; 1199 count += i8254_offset; 1200 CLOCK_UNLOCK(); 1201 write_eflags(ef); 1202 return (count); 1203 } 1204 1205 static unsigned 1206 tsc_get_timecount(struct timecounter *tc) 1207 { 1208 return (rdtsc()); 1209 }
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