The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/clock.c

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    1 /*-
    2  * Copyright (c) 1990 The Regents of the University of California.
    3  * All rights reserved.
    4  *
    5  * This code is derived from software contributed to Berkeley by
    6  * William Jolitz and Don Ahn.
    7  *
    8  * Redistribution and use in source and binary forms, with or without
    9  * modification, are permitted provided that the following conditions
   10  * are met:
   11  * 1. Redistributions of source code must retain the above copyright
   12  *    notice, this list of conditions and the following disclaimer.
   13  * 2. Redistributions in binary form must reproduce the above copyright
   14  *    notice, this list of conditions and the following disclaimer in the
   15  *    documentation and/or other materials provided with the distribution.
   16  * 3. All advertising materials mentioning features or use of this software
   17  *    must display the following acknowledgement:
   18  *      This product includes software developed by the University of
   19  *      California, Berkeley and its contributors.
   20  * 4. Neither the name of the University nor the names of its contributors
   21  *    may be used to endorse or promote products derived from this software
   22  *    without specific prior written permission.
   23  *
   24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
   25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
   28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   34  * SUCH DAMAGE.
   35  *
   36  *      from: @(#)clock.c       7.2 (Berkeley) 5/12/91
   37  * $FreeBSD: releng/5.0/sys/i386/isa/clock.c 107576 2002-12-04 13:46:49Z phk $
   38  */
   39 
   40 /*
   41  * Routines to handle clock hardware.
   42  */
   43 
   44 /*
   45  * inittodr, settodr and support routines written
   46  * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
   47  *
   48  * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
   49  */
   50 
   51 #include "opt_clock.h"
   52 #include "opt_isa.h"
   53 #include "opt_mca.h"
   54 
   55 #include <sys/param.h>
   56 #include <sys/systm.h>
   57 #include <sys/bus.h>
   58 #include <sys/lock.h>
   59 #include <sys/mutex.h>
   60 #include <sys/proc.h>
   61 #include <sys/time.h>
   62 #include <sys/timetc.h>
   63 #include <sys/kernel.h>
   64 #include <sys/sysctl.h>
   65 #include <sys/cons.h>
   66 #include <sys/power.h>
   67 
   68 #include <machine/clock.h>
   69 #include <machine/cputypes.h>
   70 #include <machine/frame.h>
   71 #include <machine/limits.h>
   72 #include <machine/md_var.h>
   73 #include <machine/psl.h>
   74 #ifdef APIC_IO
   75 #include <machine/segments.h>
   76 #endif
   77 #if defined(SMP) || defined(APIC_IO)
   78 #include <machine/smp.h>
   79 #endif /* SMP || APIC_IO */
   80 #include <machine/specialreg.h>
   81 
   82 #include <i386/isa/icu.h>
   83 #include <i386/isa/isa.h>
   84 #include <isa/rtc.h>
   85 #ifdef DEV_ISA
   86 #include <isa/isavar.h>
   87 #endif
   88 #include <i386/isa/timerreg.h>
   89 
   90 #include <i386/isa/intr_machdep.h>
   91 
   92 #ifdef DEV_MCA
   93 #include <i386/isa/mca_machdep.h>
   94 #endif
   95 
   96 #ifdef APIC_IO
   97 #include <i386/isa/intr_machdep.h>
   98 /* The interrupt triggered by the 8254 (timer) chip */
   99 int apic_8254_intr;
  100 static u_long read_intr_count(int vec);
  101 static void setup_8254_mixed_mode(void);
  102 #endif
  103 
  104 /*
  105  * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
  106  * can use a simple formula for leap years.
  107  */
  108 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
  109 #define DAYSPERYEAR   (31+28+31+30+31+30+31+31+30+31+30+31)
  110 
  111 #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
  112 
  113 /*
  114  * Time in timer cycles that it takes for microtime() to disable interrupts
  115  * and latch the count.  microtime() currently uses "cli; outb ..." so it
  116  * normally takes less than 2 timer cycles.  Add a few for cache misses.
  117  * Add a few more to allow for latency in bogus calls to microtime() with
  118  * interrupts already disabled.
  119  */
  120 #define TIMER0_LATCH_COUNT      20
  121 
  122 /*
  123  * Maximum frequency that we are willing to allow for timer0.  Must be
  124  * low enough to guarantee that the timer interrupt handler returns
  125  * before the next timer interrupt.
  126  */
  127 #define TIMER0_MAX_FREQ         20000
  128 
  129 int     adjkerntz;              /* local offset from GMT in seconds */
  130 int     clkintr_pending;
  131 int     disable_rtc_set;        /* disable resettodr() if != 0 */
  132 int     statclock_disable;
  133 #ifndef TIMER_FREQ
  134 #define TIMER_FREQ   1193182
  135 #endif
  136 u_int   timer_freq = TIMER_FREQ;
  137 int     timer0_max_count;
  138 u_int   tsc_freq;
  139 int     tsc_is_broken;
  140 u_int   tsc_present;
  141 int     wall_cmos_clock;        /* wall CMOS clock assumed if != 0 */
  142 struct mtx clock_lock;
  143 
  144 static  int     beeping = 0;
  145 static  const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
  146 static  u_int   hardclock_max_count;
  147 static  u_int32_t i8254_lastcount;
  148 static  u_int32_t i8254_offset;
  149 static  int     i8254_ticked;
  150 /*
  151  * XXX new_function and timer_func should not handle clockframes, but
  152  * timer_func currently needs to hold hardclock to handle the
  153  * timer0_state == 0 case.  We should use inthand_add()/inthand_remove()
  154  * to switch between clkintr() and a slightly different timerintr().
  155  */
  156 static  void    (*new_function)(struct clockframe *frame);
  157 static  u_int   new_rate;
  158 static  u_char  rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
  159 static  u_char  rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
  160 static  u_int   timer0_prescaler_count;
  161 
  162 /* Values for timerX_state: */
  163 #define RELEASED        0
  164 #define RELEASE_PENDING 1
  165 #define ACQUIRED        2
  166 #define ACQUIRE_PENDING 3
  167 
  168 static  u_char  timer0_state;
  169 static  u_char  timer2_state;
  170 static  void    (*timer_func)(struct clockframe *frame) = hardclock;
  171 
  172 static  unsigned i8254_get_timecount(struct timecounter *tc);
  173 static  unsigned tsc_get_timecount(struct timecounter *tc);
  174 static  void    set_timer_freq(u_int freq, int intr_freq);
  175 
  176 static struct timecounter tsc_timecounter = {
  177         tsc_get_timecount,      /* get_timecount */
  178         0,                      /* no poll_pps */
  179         ~0u,                    /* counter_mask */
  180         0,                      /* frequency */
  181          "TSC"                  /* name */
  182 };
  183 
  184 static struct timecounter i8254_timecounter = {
  185         i8254_get_timecount,    /* get_timecount */
  186         0,                      /* no poll_pps */
  187         ~0u,                    /* counter_mask */
  188         0,                      /* frequency */
  189         "i8254"                 /* name */
  190 };
  191 
  192 static void
  193 clkintr(struct clockframe frame)
  194 {
  195 
  196         if (timecounter->tc_get_timecount == i8254_get_timecount) {
  197                 mtx_lock_spin(&clock_lock);
  198                 if (i8254_ticked)
  199                         i8254_ticked = 0;
  200                 else {
  201                         i8254_offset += timer0_max_count;
  202                         i8254_lastcount = 0;
  203                 }
  204                 clkintr_pending = 0;
  205                 mtx_unlock_spin(&clock_lock);
  206         }
  207         timer_func(&frame);
  208 #ifdef SMP
  209         if (timer_func == hardclock)
  210                 forward_hardclock();
  211 #endif
  212         switch (timer0_state) {
  213 
  214         case RELEASED:
  215                 break;
  216 
  217         case ACQUIRED:
  218                 if ((timer0_prescaler_count += timer0_max_count)
  219                     >= hardclock_max_count) {
  220                         timer0_prescaler_count -= hardclock_max_count;
  221                         hardclock(&frame);
  222 #ifdef SMP
  223                         forward_hardclock();
  224 #endif
  225                 }
  226                 break;
  227 
  228         case ACQUIRE_PENDING:
  229                 mtx_lock_spin(&clock_lock);
  230                 i8254_offset = i8254_get_timecount(NULL);
  231                 i8254_lastcount = 0;
  232                 timer0_max_count = TIMER_DIV(new_rate);
  233                 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
  234                 outb(TIMER_CNTR0, timer0_max_count & 0xff);
  235                 outb(TIMER_CNTR0, timer0_max_count >> 8);
  236                 mtx_unlock_spin(&clock_lock);
  237                 timer_func = new_function;
  238                 timer0_state = ACQUIRED;
  239                 break;
  240 
  241         case RELEASE_PENDING:
  242                 if ((timer0_prescaler_count += timer0_max_count)
  243                     >= hardclock_max_count) {
  244                         mtx_lock_spin(&clock_lock);
  245                         i8254_offset = i8254_get_timecount(NULL);
  246                         i8254_lastcount = 0;
  247                         timer0_max_count = hardclock_max_count;
  248                         outb(TIMER_MODE,
  249                              TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
  250                         outb(TIMER_CNTR0, timer0_max_count & 0xff);
  251                         outb(TIMER_CNTR0, timer0_max_count >> 8);
  252                         mtx_unlock_spin(&clock_lock);
  253                         timer0_prescaler_count = 0;
  254                         timer_func = hardclock;
  255                         timer0_state = RELEASED;
  256                         hardclock(&frame);
  257 #ifdef SMP
  258                         forward_hardclock();
  259 #endif
  260                 }
  261                 break;
  262         }
  263 #ifdef DEV_MCA
  264         /* Reset clock interrupt by asserting bit 7 of port 0x61 */
  265         if (MCA_system)
  266                 outb(0x61, inb(0x61) | 0x80);
  267 #endif
  268 }
  269 
  270 /*
  271  * The acquire and release functions must be called at ipl >= splclock().
  272  */
  273 int
  274 acquire_timer0(int rate, void (*function)(struct clockframe *frame))
  275 {
  276         static int old_rate;
  277 
  278         if (rate <= 0 || rate > TIMER0_MAX_FREQ)
  279                 return (-1);
  280         switch (timer0_state) {
  281 
  282         case RELEASED:
  283                 timer0_state = ACQUIRE_PENDING;
  284                 break;
  285 
  286         case RELEASE_PENDING:
  287                 if (rate != old_rate)
  288                         return (-1);
  289                 /*
  290                  * The timer has been released recently, but is being
  291                  * re-acquired before the release completed.  In this
  292                  * case, we simply reclaim it as if it had not been
  293                  * released at all.
  294                  */
  295                 timer0_state = ACQUIRED;
  296                 break;
  297 
  298         default:
  299                 return (-1);    /* busy */
  300         }
  301         new_function = function;
  302         old_rate = new_rate = rate;
  303         return (0);
  304 }
  305 
  306 int
  307 acquire_timer2(int mode)
  308 {
  309 
  310         if (timer2_state != RELEASED)
  311                 return (-1);
  312         timer2_state = ACQUIRED;
  313 
  314         /*
  315          * This access to the timer registers is as atomic as possible
  316          * because it is a single instruction.  We could do better if we
  317          * knew the rate.  Use of splclock() limits glitches to 10-100us,
  318          * and this is probably good enough for timer2, so we aren't as
  319          * careful with it as with timer0.
  320          */
  321         outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
  322 
  323         return (0);
  324 }
  325 
  326 int
  327 release_timer0()
  328 {
  329         switch (timer0_state) {
  330 
  331         case ACQUIRED:
  332                 timer0_state = RELEASE_PENDING;
  333                 break;
  334 
  335         case ACQUIRE_PENDING:
  336                 /* Nothing happened yet, release quickly. */
  337                 timer0_state = RELEASED;
  338                 break;
  339 
  340         default:
  341                 return (-1);
  342         }
  343         return (0);
  344 }
  345 
  346 int
  347 release_timer2()
  348 {
  349 
  350         if (timer2_state != ACQUIRED)
  351                 return (-1);
  352         timer2_state = RELEASED;
  353         outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
  354         return (0);
  355 }
  356 
  357 /*
  358  * This routine receives statistical clock interrupts from the RTC.
  359  * As explained above, these occur at 128 interrupts per second.
  360  * When profiling, we receive interrupts at a rate of 1024 Hz.
  361  *
  362  * This does not actually add as much overhead as it sounds, because
  363  * when the statistical clock is active, the hardclock driver no longer
  364  * needs to keep (inaccurate) statistics on its own.  This decouples
  365  * statistics gathering from scheduling interrupts.
  366  *
  367  * The RTC chip requires that we read status register C (RTC_INTR)
  368  * to acknowledge an interrupt, before it will generate the next one.
  369  * Under high interrupt load, rtcintr() can be indefinitely delayed and
  370  * the clock can tick immediately after the read from RTC_INTR.  In this
  371  * case, the mc146818A interrupt signal will not drop for long enough
  372  * to register with the 8259 PIC.  If an interrupt is missed, the stat
  373  * clock will halt, considerably degrading system performance.  This is
  374  * why we use 'while' rather than a more straightforward 'if' below.
  375  * Stat clock ticks can still be lost, causing minor loss of accuracy
  376  * in the statistics, but the stat clock will no longer stop.
  377  */
  378 static void
  379 rtcintr(struct clockframe frame)
  380 {
  381         while (rtcin(RTC_INTR) & RTCIR_PERIOD) {
  382                 statclock(&frame);
  383 #ifdef SMP
  384                 forward_statclock();
  385 #endif
  386         }
  387 }
  388 
  389 #include "opt_ddb.h"
  390 #ifdef DDB
  391 #include <ddb/ddb.h>
  392 
  393 DB_SHOW_COMMAND(rtc, rtc)
  394 {
  395         printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
  396                rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
  397                rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
  398                rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
  399 }
  400 #endif /* DDB */
  401 
  402 static int
  403 getit(void)
  404 {
  405         int high, low;
  406 
  407         mtx_lock_spin(&clock_lock);
  408 
  409         /* Select timer0 and latch counter value. */
  410         outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
  411 
  412         low = inb(TIMER_CNTR0);
  413         high = inb(TIMER_CNTR0);
  414 
  415         mtx_unlock_spin(&clock_lock);
  416         return ((high << 8) | low);
  417 }
  418 
  419 /*
  420  * Wait "n" microseconds.
  421  * Relies on timer 1 counting down from (timer_freq / hz)
  422  * Note: timer had better have been programmed before this is first used!
  423  */
  424 void
  425 DELAY(int n)
  426 {
  427         int delta, prev_tick, tick, ticks_left;
  428 
  429 #ifdef DELAYDEBUG
  430         int getit_calls = 1;
  431         int n1;
  432         static int state = 0;
  433 
  434         if (state == 0) {
  435                 state = 1;
  436                 for (n1 = 1; n1 <= 10000000; n1 *= 10)
  437                         DELAY(n1);
  438                 state = 2;
  439         }
  440         if (state == 1)
  441                 printf("DELAY(%d)...", n);
  442 #endif
  443         /*
  444          * Guard against the timer being uninitialized if we are called
  445          * early for console i/o.
  446          */
  447         if (timer0_max_count == 0)
  448                 set_timer_freq(timer_freq, hz);
  449 
  450         /*
  451          * Read the counter first, so that the rest of the setup overhead is
  452          * counted.  Guess the initial overhead is 20 usec (on most systems it
  453          * takes about 1.5 usec for each of the i/o's in getit().  The loop
  454          * takes about 6 usec on a 486/33 and 13 usec on a 386/20.  The
  455          * multiplications and divisions to scale the count take a while).
  456          */
  457         prev_tick = getit();
  458         n -= 0;                 /* XXX actually guess no initial overhead */
  459         /*
  460          * Calculate (n * (timer_freq / 1e6)) without using floating point
  461          * and without any avoidable overflows.
  462          */
  463         if (n <= 0)
  464                 ticks_left = 0;
  465         else if (n < 256)
  466                 /*
  467                  * Use fixed point to avoid a slow division by 1000000.
  468                  * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
  469                  * 2^15 is the first power of 2 that gives exact results
  470                  * for n between 0 and 256.
  471                  */
  472                 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
  473         else
  474                 /*
  475                  * Don't bother using fixed point, although gcc-2.7.2
  476                  * generates particularly poor code for the long long
  477                  * division, since even the slow way will complete long
  478                  * before the delay is up (unless we're interrupted).
  479                  */
  480                 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
  481                              / 1000000;
  482 
  483         while (ticks_left > 0) {
  484                 tick = getit();
  485 #ifdef DELAYDEBUG
  486                 ++getit_calls;
  487 #endif
  488                 delta = prev_tick - tick;
  489                 prev_tick = tick;
  490                 if (delta < 0) {
  491                         delta += timer0_max_count;
  492                         /*
  493                          * Guard against timer0_max_count being wrong.
  494                          * This shouldn't happen in normal operation,
  495                          * but it may happen if set_timer_freq() is
  496                          * traced.
  497                          */
  498                         if (delta < 0)
  499                                 delta = 0;
  500                 }
  501                 ticks_left -= delta;
  502         }
  503 #ifdef DELAYDEBUG
  504         if (state == 1)
  505                 printf(" %d calls to getit() at %d usec each\n",
  506                        getit_calls, (n + 5) / getit_calls);
  507 #endif
  508 }
  509 
  510 static void
  511 sysbeepstop(void *chan)
  512 {
  513         outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
  514         release_timer2();
  515         beeping = 0;
  516 }
  517 
  518 int
  519 sysbeep(int pitch, int period)
  520 {
  521         int x = splclock();
  522 
  523         if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
  524                 if (!beeping) {
  525                         /* Something else owns it. */
  526                         splx(x);
  527                         return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
  528                 }
  529         mtx_lock_spin(&clock_lock);
  530         outb(TIMER_CNTR2, pitch);
  531         outb(TIMER_CNTR2, (pitch>>8));
  532         mtx_unlock_spin(&clock_lock);
  533         if (!beeping) {
  534                 /* enable counter2 output to speaker */
  535                 outb(IO_PPI, inb(IO_PPI) | 3);
  536                 beeping = period;
  537                 timeout(sysbeepstop, (void *)NULL, period);
  538         }
  539         splx(x);
  540         return (0);
  541 }
  542 
  543 /*
  544  * RTC support routines
  545  */
  546 
  547 int
  548 rtcin(reg)
  549         int reg;
  550 {
  551         int s;
  552         u_char val;
  553 
  554         s = splhigh();
  555         outb(IO_RTC, reg);
  556         inb(0x84);
  557         val = inb(IO_RTC + 1);
  558         inb(0x84);
  559         splx(s);
  560         return (val);
  561 }
  562 
  563 static __inline void
  564 writertc(u_char reg, u_char val)
  565 {
  566         int s;
  567 
  568         s = splhigh();
  569         inb(0x84);
  570         outb(IO_RTC, reg);
  571         inb(0x84);
  572         outb(IO_RTC + 1, val);
  573         inb(0x84);              /* XXX work around wrong order in rtcin() */
  574         splx(s);
  575 }
  576 
  577 static __inline int
  578 readrtc(int port)
  579 {
  580         return(bcd2bin(rtcin(port)));
  581 }
  582 
  583 static u_int
  584 calibrate_clocks(void)
  585 {
  586         u_int64_t old_tsc;
  587         u_int count, prev_count, tot_count;
  588         int sec, start_sec, timeout;
  589 
  590         if (bootverbose)
  591                 printf("Calibrating clock(s) ... ");
  592         if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
  593                 goto fail;
  594         timeout = 100000000;
  595 
  596         /* Read the mc146818A seconds counter. */
  597         for (;;) {
  598                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
  599                         sec = rtcin(RTC_SEC);
  600                         break;
  601                 }
  602                 if (--timeout == 0)
  603                         goto fail;
  604         }
  605 
  606         /* Wait for the mC146818A seconds counter to change. */
  607         start_sec = sec;
  608         for (;;) {
  609                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
  610                         sec = rtcin(RTC_SEC);
  611                         if (sec != start_sec)
  612                                 break;
  613                 }
  614                 if (--timeout == 0)
  615                         goto fail;
  616         }
  617 
  618         /* Start keeping track of the i8254 counter. */
  619         prev_count = getit();
  620         if (prev_count == 0 || prev_count > timer0_max_count)
  621                 goto fail;
  622         tot_count = 0;
  623 
  624         if (tsc_present) 
  625                 old_tsc = rdtsc();
  626         else
  627                 old_tsc = 0;            /* shut up gcc */
  628 
  629         /*
  630          * Wait for the mc146818A seconds counter to change.  Read the i8254
  631          * counter for each iteration since this is convenient and only
  632          * costs a few usec of inaccuracy. The timing of the final reads
  633          * of the counters almost matches the timing of the initial reads,
  634          * so the main cause of inaccuracy is the varying latency from 
  635          * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
  636          * rtcin(RTC_SEC) that returns a changed seconds count.  The
  637          * maximum inaccuracy from this cause is < 10 usec on 486's.
  638          */
  639         start_sec = sec;
  640         for (;;) {
  641                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
  642                         sec = rtcin(RTC_SEC);
  643                 count = getit();
  644                 if (count == 0 || count > timer0_max_count)
  645                         goto fail;
  646                 if (count > prev_count)
  647                         tot_count += prev_count - (count - timer0_max_count);
  648                 else
  649                         tot_count += prev_count - count;
  650                 prev_count = count;
  651                 if (sec != start_sec)
  652                         break;
  653                 if (--timeout == 0)
  654                         goto fail;
  655         }
  656 
  657         /*
  658          * Read the cpu cycle counter.  The timing considerations are
  659          * similar to those for the i8254 clock.
  660          */
  661         if (tsc_present) 
  662                 tsc_freq = rdtsc() - old_tsc;
  663 
  664         if (bootverbose) {
  665                 if (tsc_present)
  666                         printf("TSC clock: %u Hz, ", tsc_freq);
  667                 printf("i8254 clock: %u Hz\n", tot_count);
  668         }
  669         return (tot_count);
  670 
  671 fail:
  672         if (bootverbose)
  673                 printf("failed, using default i8254 clock of %u Hz\n",
  674                        timer_freq);
  675         return (timer_freq);
  676 }
  677 
  678 static void
  679 set_timer_freq(u_int freq, int intr_freq)
  680 {
  681         int new_timer0_max_count;
  682 
  683         mtx_lock_spin(&clock_lock);
  684         timer_freq = freq;
  685         new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
  686         if (new_timer0_max_count != timer0_max_count) {
  687                 timer0_max_count = new_timer0_max_count;
  688                 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
  689                 outb(TIMER_CNTR0, timer0_max_count & 0xff);
  690                 outb(TIMER_CNTR0, timer0_max_count >> 8);
  691         }
  692         mtx_unlock_spin(&clock_lock);
  693 }
  694 
  695 static void
  696 i8254_restore(void)
  697 {
  698 
  699         mtx_lock_spin(&clock_lock);
  700         outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
  701         outb(TIMER_CNTR0, timer0_max_count & 0xff);
  702         outb(TIMER_CNTR0, timer0_max_count >> 8);
  703         mtx_unlock_spin(&clock_lock);
  704 }
  705 
  706 static void
  707 rtc_restore(void)
  708 {
  709 
  710         /* Restore all of the RTC's "status" (actually, control) registers. */
  711         /* XXX locking is needed for RTC access. */
  712         writertc(RTC_STATUSB, RTCSB_24HR);
  713         writertc(RTC_STATUSA, rtc_statusa);
  714         writertc(RTC_STATUSB, rtc_statusb);
  715 }
  716 
  717 /*
  718  * Restore all the timers non-atomically (XXX: should be atomically).
  719  *
  720  * This function is called from pmtimer_resume() to restore all the timers.
  721  * This should not be necessary, but there are broken laptops that do not
  722  * restore all the timers on resume.
  723  */
  724 void
  725 timer_restore(void)
  726 {
  727 
  728         i8254_restore();                /* restore timer_freq and hz */
  729         rtc_restore();                  /* reenable RTC interrupts */
  730 }
  731 
  732 /*
  733  * Initialize 8254 timer 0 early so that it can be used in DELAY().
  734  * XXX initialization of other timers is unintentionally left blank.
  735  */
  736 void
  737 startrtclock()
  738 {
  739         u_int delta, freq;
  740 
  741         if (cpu_feature & CPUID_TSC)
  742                 tsc_present = 1;
  743         else
  744                 tsc_present = 0;
  745 
  746         writertc(RTC_STATUSA, rtc_statusa);
  747         writertc(RTC_STATUSB, RTCSB_24HR);
  748 
  749         set_timer_freq(timer_freq, hz);
  750         freq = calibrate_clocks();
  751 #ifdef CLK_CALIBRATION_LOOP
  752         if (bootverbose) {
  753                 printf(
  754                 "Press a key on the console to abort clock calibration\n");
  755                 while (cncheckc() == -1)
  756                         calibrate_clocks();
  757         }
  758 #endif
  759 
  760         /*
  761          * Use the calibrated i8254 frequency if it seems reasonable.
  762          * Otherwise use the default, and don't use the calibrated i586
  763          * frequency.
  764          */
  765         delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
  766         if (delta < timer_freq / 100) {
  767 #ifndef CLK_USE_I8254_CALIBRATION
  768                 if (bootverbose)
  769                         printf(
  770 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
  771                 freq = timer_freq;
  772 #endif
  773                 timer_freq = freq;
  774         } else {
  775                 if (bootverbose)
  776                         printf(
  777                     "%d Hz differs from default of %d Hz by more than 1%%\n",
  778                                freq, timer_freq);
  779                 tsc_freq = 0;
  780         }
  781 
  782         set_timer_freq(timer_freq, hz);
  783         i8254_timecounter.tc_frequency = timer_freq;
  784         tc_init(&i8254_timecounter);
  785 
  786 #ifndef CLK_USE_TSC_CALIBRATION
  787         if (tsc_freq != 0) {
  788                 if (bootverbose)
  789                         printf(
  790 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
  791                 tsc_freq = 0;
  792         }
  793 #endif
  794         if (tsc_present && tsc_freq == 0) {
  795                 /*
  796                  * Calibration of the i586 clock relative to the mc146818A
  797                  * clock failed.  Do a less accurate calibration relative
  798                  * to the i8254 clock.
  799                  */
  800                 u_int64_t old_tsc = rdtsc();
  801 
  802                 DELAY(1000000);
  803                 tsc_freq = rdtsc() - old_tsc;
  804 #ifdef CLK_USE_TSC_CALIBRATION
  805                 if (bootverbose)
  806                         printf("TSC clock: %u Hz (Method B)\n", tsc_freq);
  807 #endif
  808         }
  809 
  810 #if !defined(SMP)
  811         /*
  812          * We can not use the TSC in SMP mode, until we figure out a
  813          * cheap (impossible), reliable and precise (yeah right!)  way
  814          * to synchronize the TSCs of all the CPUs.
  815          * Curse Intel for leaving the counter out of the I/O APIC.
  816          */
  817 
  818         /*
  819          * We can not use the TSC if we support APM. Precise timekeeping
  820          * on an APM'ed machine is at best a fools pursuit, since 
  821          * any and all of the time spent in various SMM code can't 
  822          * be reliably accounted for.  Reading the RTC is your only
  823          * source of reliable time info.  The i8254 looses too of course
  824          * but we need to have some kind of time...
  825          * We don't know at this point whether APM is going to be used
  826          * or not, nor when it might be activated.  Play it safe.
  827          */
  828         if (power_pm_get_type() == POWER_PM_TYPE_APM) {
  829                 if (bootverbose)
  830                         printf("TSC initialization skipped: APM enabled.\n");
  831                 return;
  832         }
  833 
  834         if (tsc_present && tsc_freq != 0 && !tsc_is_broken) {
  835                 tsc_timecounter.tc_frequency = tsc_freq;
  836                 tc_init(&tsc_timecounter);
  837         }
  838 
  839 #endif /* !defined(SMP) */
  840 }
  841 
  842 /*
  843  * Initialize the time of day register, based on the time base which is, e.g.
  844  * from a filesystem.
  845  */
  846 void
  847 inittodr(time_t base)
  848 {
  849         unsigned long   sec, days;
  850         int             year, month;
  851         int             y, m, s;
  852         struct timespec ts;
  853 
  854         if (base) {
  855                 s = splclock();
  856                 ts.tv_sec = base;
  857                 ts.tv_nsec = 0;
  858                 tc_setclock(&ts);
  859                 splx(s);
  860         }
  861 
  862         /* Look if we have a RTC present and the time is valid */
  863         if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
  864                 goto wrong_time;
  865 
  866         /* wait for time update to complete */
  867         /* If RTCSA_TUP is zero, we have at least 244us before next update */
  868         s = splhigh();
  869         while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
  870                 splx(s);
  871                 s = splhigh();
  872         }
  873 
  874         days = 0;
  875 #ifdef USE_RTC_CENTURY
  876         year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
  877 #else
  878         year = readrtc(RTC_YEAR) + 1900;
  879         if (year < 1970)
  880                 year += 100;
  881 #endif
  882         if (year < 1970) {
  883                 splx(s);
  884                 goto wrong_time;
  885         }
  886         month = readrtc(RTC_MONTH);
  887         for (m = 1; m < month; m++)
  888                 days += daysinmonth[m-1];
  889         if ((month > 2) && LEAPYEAR(year))
  890                 days ++;
  891         days += readrtc(RTC_DAY) - 1;
  892         for (y = 1970; y < year; y++)
  893                 days += DAYSPERYEAR + LEAPYEAR(y);
  894         sec = ((( days * 24 +
  895                   readrtc(RTC_HRS)) * 60 +
  896                   readrtc(RTC_MIN)) * 60 +
  897                   readrtc(RTC_SEC));
  898         /* sec now contains the number of seconds, since Jan 1 1970,
  899            in the local time zone */
  900 
  901         sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
  902 
  903         y = time_second - sec;
  904         if (y <= -2 || y >= 2) {
  905                 /* badly off, adjust it */
  906                 ts.tv_sec = sec;
  907                 ts.tv_nsec = 0;
  908                 tc_setclock(&ts);
  909         }
  910         splx(s);
  911         return;
  912 
  913 wrong_time:
  914         printf("Invalid time in real time clock.\n");
  915         printf("Check and reset the date immediately!\n");
  916 }
  917 
  918 /*
  919  * Write system time back to RTC
  920  */
  921 void
  922 resettodr()
  923 {
  924         unsigned long   tm;
  925         int             y, m, s;
  926 
  927         if (disable_rtc_set)
  928                 return;
  929 
  930         s = splclock();
  931         tm = time_second;
  932         splx(s);
  933 
  934         /* Disable RTC updates and interrupts. */
  935         writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
  936 
  937         /* Calculate local time to put in RTC */
  938 
  939         tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
  940 
  941         writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60;    /* Write back Seconds */
  942         writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60;    /* Write back Minutes */
  943         writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24;    /* Write back Hours   */
  944 
  945         /* We have now the days since 01-01-1970 in tm */
  946         writertc(RTC_WDAY, (tm + 4) % 7 + 1);           /* Write back Weekday */
  947         for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
  948              tm >= m;
  949              y++,      m = DAYSPERYEAR + LEAPYEAR(y))
  950              tm -= m;
  951 
  952         /* Now we have the years in y and the day-of-the-year in tm */
  953         writertc(RTC_YEAR, bin2bcd(y%100));             /* Write back Year    */
  954 #ifdef USE_RTC_CENTURY
  955         writertc(RTC_CENTURY, bin2bcd(y/100));          /* ... and Century    */
  956 #endif
  957         for (m = 0; ; m++) {
  958                 int ml;
  959 
  960                 ml = daysinmonth[m];
  961                 if (m == 1 && LEAPYEAR(y))
  962                         ml++;
  963                 if (tm < ml)
  964                         break;
  965                 tm -= ml;
  966         }
  967 
  968         writertc(RTC_MONTH, bin2bcd(m + 1));            /* Write back Month   */
  969         writertc(RTC_DAY, bin2bcd(tm + 1));             /* Write back Month Day */
  970 
  971         /* Reenable RTC updates and interrupts. */
  972         writertc(RTC_STATUSB, rtc_statusb);
  973 }
  974 
  975 
  976 /*
  977  * Start both clocks running.
  978  */
  979 void
  980 cpu_initclocks()
  981 {
  982         int diag;
  983 #ifdef APIC_IO
  984         int apic_8254_trial;
  985         void *clkdesc;
  986 #endif /* APIC_IO */
  987         register_t crit;
  988 
  989         if (statclock_disable) {
  990                 /*
  991                  * The stat interrupt mask is different without the
  992                  * statistics clock.  Also, don't set the interrupt
  993                  * flag which would normally cause the RTC to generate
  994                  * interrupts.
  995                  */
  996                 rtc_statusb = RTCSB_24HR;
  997         } else {
  998                 /* Setting stathz to nonzero early helps avoid races. */
  999                 stathz = RTC_NOPROFRATE;
 1000                 profhz = RTC_PROFRATE;
 1001         }
 1002 
 1003         /* Finish initializing 8253 timer 0. */
 1004 #ifdef APIC_IO
 1005 
 1006         apic_8254_intr = isa_apic_irq(0);
 1007         apic_8254_trial = 0;
 1008         if (apic_8254_intr >= 0 ) {
 1009                 if (apic_int_type(0, 0) == 3)
 1010                         apic_8254_trial = 1;
 1011         } else {
 1012                 /* look for ExtInt on pin 0 */
 1013                 if (apic_int_type(0, 0) == 3) {
 1014                         apic_8254_intr = apic_irq(0, 0);
 1015                         setup_8254_mixed_mode();
 1016                 } else 
 1017                         panic("APIC_IO: Cannot route 8254 interrupt to CPU");
 1018         }
 1019 
 1020         inthand_add("clk", apic_8254_intr, (driver_intr_t *)clkintr, NULL,
 1021             INTR_TYPE_CLK | INTR_FAST, &clkdesc);
 1022         crit = intr_disable();
 1023         mtx_lock_spin(&icu_lock);
 1024         INTREN(1 << apic_8254_intr);
 1025         mtx_unlock_spin(&icu_lock);
 1026         intr_restore(crit);
 1027 
 1028 #else /* APIC_IO */
 1029 
 1030         /*
 1031          * XXX Check the priority of this interrupt handler.  I
 1032          * couldn't find anything suitable in the BSD/OS code (grog,
 1033          * 19 July 2000).
 1034          */
 1035         inthand_add("clk", 0, (driver_intr_t *)clkintr, NULL,
 1036             INTR_TYPE_CLK | INTR_FAST, NULL);
 1037         crit = intr_disable();
 1038         mtx_lock_spin(&icu_lock);
 1039         INTREN(IRQ0);
 1040         mtx_unlock_spin(&icu_lock);
 1041         intr_restore(crit);
 1042 
 1043 #endif /* APIC_IO */
 1044 
 1045         /* Initialize RTC. */
 1046         writertc(RTC_STATUSA, rtc_statusa);
 1047         writertc(RTC_STATUSB, RTCSB_24HR);
 1048 
 1049         /* Don't bother enabling the statistics clock. */
 1050         if (statclock_disable)
 1051                 return;
 1052         diag = rtcin(RTC_DIAG);
 1053         if (diag != 0)
 1054                 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
 1055 
 1056 #ifdef APIC_IO
 1057         if (isa_apic_irq(8) != 8)
 1058                 panic("APIC RTC != 8");
 1059 #endif /* APIC_IO */
 1060 
 1061         inthand_add("rtc", 8, (driver_intr_t *)rtcintr, NULL,
 1062             INTR_TYPE_CLK | INTR_FAST, NULL);
 1063 
 1064         crit = intr_disable();
 1065         mtx_lock_spin(&icu_lock);
 1066 #ifdef APIC_IO
 1067         INTREN(APIC_IRQ8);
 1068 #else
 1069         INTREN(IRQ8);
 1070 #endif /* APIC_IO */
 1071         mtx_unlock_spin(&icu_lock);
 1072         intr_restore(crit);
 1073 
 1074         writertc(RTC_STATUSB, rtc_statusb);
 1075 
 1076 #ifdef APIC_IO
 1077         if (apic_8254_trial) {
 1078 
 1079                 printf("APIC_IO: Testing 8254 interrupt delivery\n");
 1080                 while (read_intr_count(8) < 6)
 1081                         ;       /* nothing */
 1082                 if (read_intr_count(apic_8254_intr) < 3) {
 1083                         /* 
 1084                          * The MP table is broken.
 1085                          * The 8254 was not connected to the specified pin
 1086                          * on the IO APIC.
 1087                          * Workaround: Limited variant of mixed mode.
 1088                          */
 1089 
 1090                         crit = intr_disable();
 1091                         mtx_lock_spin(&icu_lock);
 1092                         INTRDIS(1 << apic_8254_intr);
 1093                         mtx_unlock_spin(&icu_lock);
 1094                         intr_restore(crit);
 1095                         inthand_remove(clkdesc);
 1096                         printf("APIC_IO: Broken MP table detected: "
 1097                                "8254 is not connected to "
 1098                                "IOAPIC #%d intpin %d\n",
 1099                                int_to_apicintpin[apic_8254_intr].ioapic,
 1100                                int_to_apicintpin[apic_8254_intr].int_pin);
 1101                         /* 
 1102                          * Revoke current ISA IRQ 0 assignment and 
 1103                          * configure a fallback interrupt routing from
 1104                          * the 8254 Timer via the 8259 PIC to the
 1105                          * an ExtInt interrupt line on IOAPIC #0 intpin 0.
 1106                          * We reuse the low level interrupt handler number.
 1107                          */
 1108                         if (apic_irq(0, 0) < 0) {
 1109                                 revoke_apic_irq(apic_8254_intr);
 1110                                 assign_apic_irq(0, 0, apic_8254_intr);
 1111                         }
 1112                         apic_8254_intr = apic_irq(0, 0);
 1113                         setup_8254_mixed_mode();
 1114                         inthand_add("clk", apic_8254_intr,
 1115                                     (driver_intr_t *)clkintr, NULL,
 1116                                     INTR_TYPE_CLK | INTR_FAST, NULL);
 1117                         crit = intr_disable();
 1118                         mtx_lock_spin(&icu_lock);
 1119                         INTREN(1 << apic_8254_intr);
 1120                         mtx_unlock_spin(&icu_lock);
 1121                         intr_restore(crit);
 1122                 }
 1123                 
 1124         }
 1125         if (apic_int_type(0, 0) != 3 ||
 1126             int_to_apicintpin[apic_8254_intr].ioapic != 0 ||
 1127             int_to_apicintpin[apic_8254_intr].int_pin != 0)
 1128                 printf("APIC_IO: routing 8254 via IOAPIC #%d intpin %d\n",
 1129                        int_to_apicintpin[apic_8254_intr].ioapic,
 1130                        int_to_apicintpin[apic_8254_intr].int_pin);
 1131         else
 1132                 printf("APIC_IO: "
 1133                        "routing 8254 via 8259 and IOAPIC #0 intpin 0\n");
 1134 #endif
 1135         
 1136 }
 1137 
 1138 #ifdef APIC_IO
 1139 static u_long
 1140 read_intr_count(int vec)
 1141 {
 1142         u_long *up;
 1143         up = intr_countp[vec];
 1144         if (up)
 1145                 return *up;
 1146         return 0UL;
 1147 }
 1148 
 1149 static void 
 1150 setup_8254_mixed_mode()
 1151 {
 1152         /*
 1153          * Allow 8254 timer to INTerrupt 8259:
 1154          *  re-initialize master 8259:
 1155          *   reset; prog 4 bytes, single ICU, edge triggered
 1156          */
 1157         outb(IO_ICU1, 0x13);
 1158         outb(IO_ICU1 + 1, NRSVIDT);     /* start vector (unused) */
 1159         outb(IO_ICU1 + 1, 0x00);        /* ignore slave */
 1160         outb(IO_ICU1 + 1, 0x03);        /* auto EOI, 8086 */
 1161         outb(IO_ICU1 + 1, 0xfe);        /* unmask INT0 */
 1162         
 1163         /* program IO APIC for type 3 INT on INT0 */
 1164         if (ext_int_setup(0, 0) < 0)
 1165                 panic("8254 redirect via APIC pin0 impossible!");
 1166 }
 1167 #endif
 1168 
 1169 void
 1170 setstatclockrate(int newhz)
 1171 {
 1172         if (newhz == RTC_PROFRATE)
 1173                 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
 1174         else
 1175                 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
 1176         writertc(RTC_STATUSA, rtc_statusa);
 1177 }
 1178 
 1179 static int
 1180 sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
 1181 {
 1182         int error;
 1183         u_int freq;
 1184 
 1185         /*
 1186          * Use `i8254' instead of `timer' in external names because `timer'
 1187          * is is too generic.  Should use it everywhere.
 1188          */
 1189         freq = timer_freq;
 1190         error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
 1191         if (error == 0 && req->newptr != NULL) {
 1192                 if (timer0_state != RELEASED)
 1193                         return (EBUSY); /* too much trouble to handle */
 1194                 set_timer_freq(freq, hz);
 1195                 i8254_timecounter.tc_frequency = freq;
 1196         }
 1197         return (error);
 1198 }
 1199 
 1200 SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
 1201     0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", "");
 1202 
 1203 static int
 1204 sysctl_machdep_tsc_freq(SYSCTL_HANDLER_ARGS)
 1205 {
 1206         int error;
 1207         u_int freq;
 1208 
 1209         if (tsc_timecounter.tc_frequency == 0)
 1210                 return (EOPNOTSUPP);
 1211         freq = tsc_freq;
 1212         error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
 1213         if (error == 0 && req->newptr != NULL) {
 1214                 tsc_freq = freq;
 1215                 tsc_timecounter.tc_frequency = tsc_freq;
 1216         }
 1217         return (error);
 1218 }
 1219 
 1220 SYSCTL_PROC(_machdep, OID_AUTO, tsc_freq, CTLTYPE_INT | CTLFLAG_RW,
 1221     0, sizeof(u_int), sysctl_machdep_tsc_freq, "IU", "");
 1222 
 1223 static unsigned
 1224 i8254_get_timecount(struct timecounter *tc)
 1225 {
 1226         u_int count;
 1227         u_int high, low;
 1228         u_int eflags;
 1229 
 1230         eflags = read_eflags();
 1231         mtx_lock_spin(&clock_lock);
 1232 
 1233         /* Select timer0 and latch counter value. */
 1234         outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
 1235 
 1236         low = inb(TIMER_CNTR0);
 1237         high = inb(TIMER_CNTR0);
 1238         count = timer0_max_count - ((high << 8) | low);
 1239         if (count < i8254_lastcount ||
 1240             (!i8254_ticked && (clkintr_pending ||
 1241             ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) &&
 1242 #ifdef APIC_IO
 1243 #define lapic_irr1      ((volatile u_int *)&lapic)[0x210 / 4]   /* XXX XXX */
 1244             /* XXX this assumes that apic_8254_intr is < 24. */
 1245             (lapic_irr1 & (1 << apic_8254_intr))))
 1246 #else
 1247             (inb(IO_ICU1) & 1)))
 1248 #endif
 1249             )) {
 1250                 i8254_ticked = 1;
 1251                 i8254_offset += timer0_max_count;
 1252         }
 1253         i8254_lastcount = count;
 1254         count += i8254_offset;
 1255         mtx_unlock_spin(&clock_lock);
 1256         return (count);
 1257 }
 1258 
 1259 static unsigned
 1260 tsc_get_timecount(struct timecounter *tc)
 1261 {
 1262         return (rdtsc());
 1263 }
 1264 
 1265 #ifdef DEV_ISA
 1266 /*
 1267  * Attach to the ISA PnP descriptors for the timer and realtime clock.
 1268  */
 1269 static struct isa_pnp_id attimer_ids[] = {
 1270         { 0x0001d041 /* PNP0100 */, "AT timer" },
 1271         { 0x000bd041 /* PNP0B00 */, "AT realtime clock" },
 1272         { 0 }
 1273 };
 1274 
 1275 static int
 1276 attimer_probe(device_t dev)
 1277 {
 1278         int result;
 1279         
 1280         if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0)
 1281                 device_quiet(dev);
 1282         return(result);
 1283 }
 1284 
 1285 static int
 1286 attimer_attach(device_t dev)
 1287 {
 1288         return(0);
 1289 }
 1290 
 1291 static device_method_t attimer_methods[] = {
 1292         /* Device interface */
 1293         DEVMETHOD(device_probe,         attimer_probe),
 1294         DEVMETHOD(device_attach,        attimer_attach),
 1295         DEVMETHOD(device_detach,        bus_generic_detach),
 1296         DEVMETHOD(device_shutdown,      bus_generic_shutdown),
 1297         DEVMETHOD(device_suspend,       bus_generic_suspend),   /* XXX stop statclock? */
 1298         DEVMETHOD(device_resume,        bus_generic_resume),    /* XXX restart statclock? */
 1299         { 0, 0 }
 1300 };
 1301 
 1302 static driver_t attimer_driver = {
 1303         "attimer",
 1304         attimer_methods,
 1305         1,              /* no softc */
 1306 };
 1307 
 1308 static devclass_t attimer_devclass;
 1309 
 1310 DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0);
 1311 DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0);
 1312 #endif /* DEV_ISA */

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