FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/clock.c
1 /*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 4. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
33 */
34
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD: src/sys/i386/isa/clock.c,v 1.213.2.2 2005/05/11 20:02:16 mdodd Exp $");
37
38 /*
39 * Routines to handle clock hardware.
40 */
41
42 /*
43 * inittodr, settodr and support routines written
44 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
45 *
46 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
47 */
48
49 #include "opt_clock.h"
50 #include "opt_isa.h"
51 #include "opt_mca.h"
52
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/bus.h>
56 #include <sys/lock.h>
57 #include <sys/kdb.h>
58 #include <sys/mutex.h>
59 #include <sys/proc.h>
60 #include <sys/time.h>
61 #include <sys/timetc.h>
62 #include <sys/kernel.h>
63 #include <sys/limits.h>
64 #include <sys/module.h>
65 #include <sys/sysctl.h>
66 #include <sys/cons.h>
67 #include <sys/power.h>
68
69 #include <machine/clock.h>
70 #include <machine/cputypes.h>
71 #include <machine/frame.h>
72 #include <machine/intr_machdep.h>
73 #include <machine/md_var.h>
74 #include <machine/psl.h>
75 #if defined(SMP)
76 #include <machine/smp.h>
77 #endif
78 #include <machine/specialreg.h>
79
80 #include <i386/isa/isa.h>
81 #include <isa/rtc.h>
82 #ifdef DEV_ISA
83 #include <isa/isavar.h>
84 #endif
85 #include <i386/isa/timerreg.h>
86
87 #ifdef DEV_MCA
88 #include <i386/bios/mca_machdep.h>
89 #endif
90
91 /*
92 * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
93 * can use a simple formula for leap years.
94 */
95 #define LEAPYEAR(y) (((u_int)(y) % 4 == 0) ? 1 : 0)
96 #define DAYSPERYEAR (31+28+31+30+31+30+31+31+30+31+30+31)
97
98 #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
99
100 #ifndef BURN_BRIDGES
101 /*
102 * Time in timer cycles that it takes for microtime() to disable interrupts
103 * and latch the count. microtime() currently uses "cli; outb ..." so it
104 * normally takes less than 2 timer cycles. Add a few for cache misses.
105 * Add a few more to allow for latency in bogus calls to microtime() with
106 * interrupts already disabled.
107 */
108 #define TIMER0_LATCH_COUNT 20
109
110 /*
111 * Maximum frequency that we are willing to allow for timer0. Must be
112 * low enough to guarantee that the timer interrupt handler returns
113 * before the next timer interrupt.
114 */
115 #define TIMER0_MAX_FREQ 20000
116 #endif
117
118 int adjkerntz; /* local offset from GMT in seconds */
119 int clkintr_pending;
120 int disable_rtc_set; /* disable resettodr() if != 0 */
121 int pscnt = 1;
122 int psdiv = 1;
123 int statclock_disable;
124 #ifndef TIMER_FREQ
125 #define TIMER_FREQ 1193182
126 #endif
127 u_int timer_freq = TIMER_FREQ;
128 int timer0_max_count;
129 int wall_cmos_clock; /* wall CMOS clock assumed if != 0 */
130 struct mtx clock_lock;
131 #define RTC_LOCK mtx_lock_spin(&clock_lock)
132 #define RTC_UNLOCK mtx_unlock_spin(&clock_lock)
133
134 static int beeping = 0;
135 static const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
136 static u_int hardclock_max_count;
137 static struct intsrc *i8254_intsrc;
138 static u_int32_t i8254_lastcount;
139 static u_int32_t i8254_offset;
140 static int (*i8254_pending)(struct intsrc *);
141 static int i8254_ticked;
142 #ifndef BURN_BRIDGES
143 /*
144 * XXX new_function and timer_func should not handle clockframes, but
145 * timer_func currently needs to hold hardclock to handle the
146 * timer0_state == 0 case. We should use inthand_add()/inthand_remove()
147 * to switch between clkintr() and a slightly different timerintr().
148 */
149 static void (*new_function)(struct clockframe *frame);
150 static u_int new_rate;
151 static u_int timer0_prescaler_count;
152 static u_char timer0_state;
153 #endif
154 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
155 static u_char rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
156
157 /* Values for timerX_state: */
158 #define RELEASED 0
159 #define RELEASE_PENDING 1
160 #define ACQUIRED 2
161 #define ACQUIRE_PENDING 3
162
163 static u_char timer2_state;
164 static void (*timer_func)(struct clockframe *frame) = hardclock;
165
166 static unsigned i8254_get_timecount(struct timecounter *tc);
167 static void set_timer_freq(u_int freq, int intr_freq);
168
169 static struct timecounter i8254_timecounter = {
170 i8254_get_timecount, /* get_timecount */
171 0, /* no poll_pps */
172 ~0u, /* counter_mask */
173 0, /* frequency */
174 "i8254", /* name */
175 0 /* quality */
176 };
177
178 static void
179 clkintr(struct clockframe *frame)
180 {
181
182 if (timecounter->tc_get_timecount == i8254_get_timecount) {
183 mtx_lock_spin(&clock_lock);
184 if (i8254_ticked)
185 i8254_ticked = 0;
186 else {
187 i8254_offset += timer0_max_count;
188 i8254_lastcount = 0;
189 }
190 clkintr_pending = 0;
191 mtx_unlock_spin(&clock_lock);
192 }
193 timer_func(frame);
194 #ifdef SMP
195 if (timer_func == hardclock)
196 forward_hardclock();
197 #endif
198 #ifndef BURN_BRIDGES
199 switch (timer0_state) {
200
201 case RELEASED:
202 break;
203
204 case ACQUIRED:
205 if ((timer0_prescaler_count += timer0_max_count)
206 >= hardclock_max_count) {
207 timer0_prescaler_count -= hardclock_max_count;
208 hardclock(frame);
209 #ifdef SMP
210 forward_hardclock();
211 #endif
212 }
213 break;
214
215 case ACQUIRE_PENDING:
216 mtx_lock_spin(&clock_lock);
217 i8254_offset = i8254_get_timecount(NULL);
218 i8254_lastcount = 0;
219 timer0_max_count = TIMER_DIV(new_rate);
220 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
221 outb(TIMER_CNTR0, timer0_max_count & 0xff);
222 outb(TIMER_CNTR0, timer0_max_count >> 8);
223 mtx_unlock_spin(&clock_lock);
224 timer_func = new_function;
225 timer0_state = ACQUIRED;
226 break;
227
228 case RELEASE_PENDING:
229 if ((timer0_prescaler_count += timer0_max_count)
230 >= hardclock_max_count) {
231 mtx_lock_spin(&clock_lock);
232 i8254_offset = i8254_get_timecount(NULL);
233 i8254_lastcount = 0;
234 timer0_max_count = hardclock_max_count;
235 outb(TIMER_MODE,
236 TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
237 outb(TIMER_CNTR0, timer0_max_count & 0xff);
238 outb(TIMER_CNTR0, timer0_max_count >> 8);
239 mtx_unlock_spin(&clock_lock);
240 timer0_prescaler_count = 0;
241 timer_func = hardclock;
242 timer0_state = RELEASED;
243 hardclock(frame);
244 #ifdef SMP
245 forward_hardclock();
246 #endif
247 }
248 break;
249 }
250 #endif
251 #ifdef DEV_MCA
252 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
253 if (MCA_system)
254 outb(0x61, inb(0x61) | 0x80);
255 #endif
256 }
257
258 #ifndef BURN_BRIDGES
259 /*
260 * The acquire and release functions must be called at ipl >= splclock().
261 */
262 int
263 acquire_timer0(int rate, void (*function)(struct clockframe *frame))
264 {
265 static int old_rate;
266
267 if (rate <= 0 || rate > TIMER0_MAX_FREQ)
268 return (-1);
269 switch (timer0_state) {
270
271 case RELEASED:
272 timer0_state = ACQUIRE_PENDING;
273 break;
274
275 case RELEASE_PENDING:
276 if (rate != old_rate)
277 return (-1);
278 /*
279 * The timer has been released recently, but is being
280 * re-acquired before the release completed. In this
281 * case, we simply reclaim it as if it had not been
282 * released at all.
283 */
284 timer0_state = ACQUIRED;
285 break;
286
287 default:
288 return (-1); /* busy */
289 }
290 new_function = function;
291 old_rate = new_rate = rate;
292 return (0);
293 }
294 #endif
295
296 int
297 acquire_timer2(int mode)
298 {
299
300 if (timer2_state != RELEASED)
301 return (-1);
302 timer2_state = ACQUIRED;
303
304 /*
305 * This access to the timer registers is as atomic as possible
306 * because it is a single instruction. We could do better if we
307 * knew the rate. Use of splclock() limits glitches to 10-100us,
308 * and this is probably good enough for timer2, so we aren't as
309 * careful with it as with timer0.
310 */
311 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
312
313 return (0);
314 }
315
316 #ifndef BURN_BRIDGES
317 int
318 release_timer0()
319 {
320 switch (timer0_state) {
321
322 case ACQUIRED:
323 timer0_state = RELEASE_PENDING;
324 break;
325
326 case ACQUIRE_PENDING:
327 /* Nothing happened yet, release quickly. */
328 timer0_state = RELEASED;
329 break;
330
331 default:
332 return (-1);
333 }
334 return (0);
335 }
336 #endif
337
338 int
339 release_timer2()
340 {
341
342 if (timer2_state != ACQUIRED)
343 return (-1);
344 timer2_state = RELEASED;
345 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
346 return (0);
347 }
348
349 /*
350 * This routine receives statistical clock interrupts from the RTC.
351 * As explained above, these occur at 128 interrupts per second.
352 * When profiling, we receive interrupts at a rate of 1024 Hz.
353 *
354 * This does not actually add as much overhead as it sounds, because
355 * when the statistical clock is active, the hardclock driver no longer
356 * needs to keep (inaccurate) statistics on its own. This decouples
357 * statistics gathering from scheduling interrupts.
358 *
359 * The RTC chip requires that we read status register C (RTC_INTR)
360 * to acknowledge an interrupt, before it will generate the next one.
361 * Under high interrupt load, rtcintr() can be indefinitely delayed and
362 * the clock can tick immediately after the read from RTC_INTR. In this
363 * case, the mc146818A interrupt signal will not drop for long enough
364 * to register with the 8259 PIC. If an interrupt is missed, the stat
365 * clock will halt, considerably degrading system performance. This is
366 * why we use 'while' rather than a more straightforward 'if' below.
367 * Stat clock ticks can still be lost, causing minor loss of accuracy
368 * in the statistics, but the stat clock will no longer stop.
369 */
370 static void
371 rtcintr(struct clockframe *frame)
372 {
373
374 while (rtcin(RTC_INTR) & RTCIR_PERIOD) {
375 if (profprocs != 0) {
376 if (--pscnt == 0)
377 pscnt = psdiv;
378 profclock(frame);
379 }
380 if (pscnt == psdiv)
381 statclock(frame);
382 #ifdef SMP
383 forward_statclock();
384 #endif
385 }
386 }
387
388 #include "opt_ddb.h"
389 #ifdef DDB
390 #include <ddb/ddb.h>
391
392 DB_SHOW_COMMAND(rtc, rtc)
393 {
394 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
395 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
396 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
397 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
398 }
399 #endif /* DDB */
400
401 static int
402 getit(void)
403 {
404 int high, low;
405
406 mtx_lock_spin(&clock_lock);
407
408 /* Select timer0 and latch counter value. */
409 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
410
411 low = inb(TIMER_CNTR0);
412 high = inb(TIMER_CNTR0);
413
414 mtx_unlock_spin(&clock_lock);
415 return ((high << 8) | low);
416 }
417
418 /*
419 * Wait "n" microseconds.
420 * Relies on timer 1 counting down from (timer_freq / hz)
421 * Note: timer had better have been programmed before this is first used!
422 */
423 void
424 DELAY(int n)
425 {
426 int delta, prev_tick, tick, ticks_left;
427
428 #ifdef DELAYDEBUG
429 int getit_calls = 1;
430 int n1;
431 static int state = 0;
432
433 if (state == 0) {
434 state = 1;
435 for (n1 = 1; n1 <= 10000000; n1 *= 10)
436 DELAY(n1);
437 state = 2;
438 }
439 if (state == 1)
440 printf("DELAY(%d)...", n);
441 #endif
442 /*
443 * Guard against the timer being uninitialized if we are called
444 * early for console i/o.
445 */
446 if (timer0_max_count == 0)
447 set_timer_freq(timer_freq, hz);
448
449 /*
450 * Read the counter first, so that the rest of the setup overhead is
451 * counted. Guess the initial overhead is 20 usec (on most systems it
452 * takes about 1.5 usec for each of the i/o's in getit(). The loop
453 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
454 * multiplications and divisions to scale the count take a while).
455 *
456 * However, if ddb is active then use a fake counter since reading
457 * the i8254 counter involves acquiring a lock. ddb must not do
458 * locking for many reasons, but it calls here for at least atkbd
459 * input.
460 */
461 #ifdef KDB
462 if (kdb_active)
463 prev_tick = 1;
464 else
465 #endif
466 prev_tick = getit();
467 n -= 0; /* XXX actually guess no initial overhead */
468 /*
469 * Calculate (n * (timer_freq / 1e6)) without using floating point
470 * and without any avoidable overflows.
471 */
472 if (n <= 0)
473 ticks_left = 0;
474 else if (n < 256)
475 /*
476 * Use fixed point to avoid a slow division by 1000000.
477 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
478 * 2^15 is the first power of 2 that gives exact results
479 * for n between 0 and 256.
480 */
481 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
482 else
483 /*
484 * Don't bother using fixed point, although gcc-2.7.2
485 * generates particularly poor code for the long long
486 * division, since even the slow way will complete long
487 * before the delay is up (unless we're interrupted).
488 */
489 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
490 / 1000000;
491
492 while (ticks_left > 0) {
493 #ifdef KDB
494 if (kdb_active) {
495 inb(0x84);
496 tick = prev_tick - 1;
497 if (tick <= 0)
498 tick = timer0_max_count;
499 } else
500 #endif
501 tick = getit();
502 #ifdef DELAYDEBUG
503 ++getit_calls;
504 #endif
505 delta = prev_tick - tick;
506 prev_tick = tick;
507 if (delta < 0) {
508 delta += timer0_max_count;
509 /*
510 * Guard against timer0_max_count being wrong.
511 * This shouldn't happen in normal operation,
512 * but it may happen if set_timer_freq() is
513 * traced.
514 */
515 if (delta < 0)
516 delta = 0;
517 }
518 ticks_left -= delta;
519 }
520 #ifdef DELAYDEBUG
521 if (state == 1)
522 printf(" %d calls to getit() at %d usec each\n",
523 getit_calls, (n + 5) / getit_calls);
524 #endif
525 }
526
527 static void
528 sysbeepstop(void *chan)
529 {
530 outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
531 release_timer2();
532 beeping = 0;
533 }
534
535 int
536 sysbeep(int pitch, int period)
537 {
538 int x = splclock();
539
540 if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
541 if (!beeping) {
542 /* Something else owns it. */
543 splx(x);
544 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
545 }
546 mtx_lock_spin(&clock_lock);
547 outb(TIMER_CNTR2, pitch);
548 outb(TIMER_CNTR2, (pitch>>8));
549 mtx_unlock_spin(&clock_lock);
550 if (!beeping) {
551 /* enable counter2 output to speaker */
552 outb(IO_PPI, inb(IO_PPI) | 3);
553 beeping = period;
554 timeout(sysbeepstop, (void *)NULL, period);
555 }
556 splx(x);
557 return (0);
558 }
559
560 /*
561 * RTC support routines
562 */
563
564 int
565 rtcin(reg)
566 int reg;
567 {
568 u_char val;
569
570 RTC_LOCK;
571 outb(IO_RTC, reg);
572 inb(0x84);
573 val = inb(IO_RTC + 1);
574 inb(0x84);
575 RTC_UNLOCK;
576 return (val);
577 }
578
579 static __inline void
580 writertc(u_char reg, u_char val)
581 {
582
583 RTC_LOCK;
584 inb(0x84);
585 outb(IO_RTC, reg);
586 inb(0x84);
587 outb(IO_RTC + 1, val);
588 inb(0x84); /* XXX work around wrong order in rtcin() */
589 RTC_UNLOCK;
590 }
591
592 static __inline int
593 readrtc(int port)
594 {
595 return(bcd2bin(rtcin(port)));
596 }
597
598 static u_int
599 calibrate_clocks(void)
600 {
601 u_int count, prev_count, tot_count;
602 int sec, start_sec, timeout;
603
604 if (bootverbose)
605 printf("Calibrating clock(s) ... ");
606 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
607 goto fail;
608 timeout = 100000000;
609
610 /* Read the mc146818A seconds counter. */
611 for (;;) {
612 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
613 sec = rtcin(RTC_SEC);
614 break;
615 }
616 if (--timeout == 0)
617 goto fail;
618 }
619
620 /* Wait for the mC146818A seconds counter to change. */
621 start_sec = sec;
622 for (;;) {
623 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
624 sec = rtcin(RTC_SEC);
625 if (sec != start_sec)
626 break;
627 }
628 if (--timeout == 0)
629 goto fail;
630 }
631
632 /* Start keeping track of the i8254 counter. */
633 prev_count = getit();
634 if (prev_count == 0 || prev_count > timer0_max_count)
635 goto fail;
636 tot_count = 0;
637
638 /*
639 * Wait for the mc146818A seconds counter to change. Read the i8254
640 * counter for each iteration since this is convenient and only
641 * costs a few usec of inaccuracy. The timing of the final reads
642 * of the counters almost matches the timing of the initial reads,
643 * so the main cause of inaccuracy is the varying latency from
644 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
645 * rtcin(RTC_SEC) that returns a changed seconds count. The
646 * maximum inaccuracy from this cause is < 10 usec on 486's.
647 */
648 start_sec = sec;
649 for (;;) {
650 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
651 sec = rtcin(RTC_SEC);
652 count = getit();
653 if (count == 0 || count > timer0_max_count)
654 goto fail;
655 if (count > prev_count)
656 tot_count += prev_count - (count - timer0_max_count);
657 else
658 tot_count += prev_count - count;
659 prev_count = count;
660 if (sec != start_sec)
661 break;
662 if (--timeout == 0)
663 goto fail;
664 }
665
666 if (bootverbose) {
667 printf("i8254 clock: %u Hz\n", tot_count);
668 }
669 return (tot_count);
670
671 fail:
672 if (bootverbose)
673 printf("failed, using default i8254 clock of %u Hz\n",
674 timer_freq);
675 return (timer_freq);
676 }
677
678 static void
679 set_timer_freq(u_int freq, int intr_freq)
680 {
681 int new_timer0_max_count;
682
683 mtx_lock_spin(&clock_lock);
684 timer_freq = freq;
685 new_timer0_max_count = hardclock_max_count = TIMER_DIV(intr_freq);
686 if (new_timer0_max_count != timer0_max_count) {
687 timer0_max_count = new_timer0_max_count;
688 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
689 outb(TIMER_CNTR0, timer0_max_count & 0xff);
690 outb(TIMER_CNTR0, timer0_max_count >> 8);
691 }
692 mtx_unlock_spin(&clock_lock);
693 }
694
695 static void
696 i8254_restore(void)
697 {
698
699 mtx_lock_spin(&clock_lock);
700 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
701 outb(TIMER_CNTR0, timer0_max_count & 0xff);
702 outb(TIMER_CNTR0, timer0_max_count >> 8);
703 mtx_unlock_spin(&clock_lock);
704 }
705
706 static void
707 rtc_restore(void)
708 {
709
710 /* Restore all of the RTC's "status" (actually, control) registers. */
711 /* XXX locking is needed for RTC access. */
712 writertc(RTC_STATUSB, RTCSB_24HR);
713 writertc(RTC_STATUSA, rtc_statusa);
714 writertc(RTC_STATUSB, rtc_statusb);
715 rtcin(RTC_INTR);
716 }
717
718 /*
719 * Restore all the timers non-atomically (XXX: should be atomically).
720 *
721 * This function is called from pmtimer_resume() to restore all the timers.
722 * This should not be necessary, but there are broken laptops that do not
723 * restore all the timers on resume.
724 */
725 void
726 timer_restore(void)
727 {
728
729 i8254_restore(); /* restore timer_freq and hz */
730 rtc_restore(); /* reenable RTC interrupts */
731 }
732
733 /*
734 * Initialize 8254 timer 0 early so that it can be used in DELAY().
735 * XXX initialization of other timers is unintentionally left blank.
736 */
737 void
738 startrtclock()
739 {
740 u_int delta, freq;
741
742 writertc(RTC_STATUSA, rtc_statusa);
743 writertc(RTC_STATUSB, RTCSB_24HR);
744
745 set_timer_freq(timer_freq, hz);
746 freq = calibrate_clocks();
747 #ifdef CLK_CALIBRATION_LOOP
748 if (bootverbose) {
749 printf(
750 "Press a key on the console to abort clock calibration\n");
751 while (cncheckc() == -1)
752 calibrate_clocks();
753 }
754 #endif
755
756 /*
757 * Use the calibrated i8254 frequency if it seems reasonable.
758 * Otherwise use the default, and don't use the calibrated i586
759 * frequency.
760 */
761 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
762 if (delta < timer_freq / 100) {
763 #ifndef CLK_USE_I8254_CALIBRATION
764 if (bootverbose)
765 printf(
766 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
767 freq = timer_freq;
768 #endif
769 timer_freq = freq;
770 } else {
771 if (bootverbose)
772 printf(
773 "%d Hz differs from default of %d Hz by more than 1%%\n",
774 freq, timer_freq);
775 }
776
777 set_timer_freq(timer_freq, hz);
778 i8254_timecounter.tc_frequency = timer_freq;
779 tc_init(&i8254_timecounter);
780
781 init_TSC();
782 }
783
784 /*
785 * Initialize the time of day register, based on the time base which is, e.g.
786 * from a filesystem.
787 */
788 void
789 inittodr(time_t base)
790 {
791 unsigned long sec, days;
792 int year, month;
793 int y, m, s;
794 struct timespec ts;
795
796 if (base) {
797 s = splclock();
798 ts.tv_sec = base;
799 ts.tv_nsec = 0;
800 tc_setclock(&ts);
801 splx(s);
802 }
803
804 /* Look if we have a RTC present and the time is valid */
805 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
806 goto wrong_time;
807
808 /* wait for time update to complete */
809 /* If RTCSA_TUP is zero, we have at least 244us before next update */
810 s = splhigh();
811 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
812 splx(s);
813 s = splhigh();
814 }
815
816 days = 0;
817 #ifdef USE_RTC_CENTURY
818 year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
819 #else
820 year = readrtc(RTC_YEAR) + 1900;
821 if (year < 1970)
822 year += 100;
823 #endif
824 if (year < 1970) {
825 splx(s);
826 goto wrong_time;
827 }
828 month = readrtc(RTC_MONTH);
829 for (m = 1; m < month; m++)
830 days += daysinmonth[m-1];
831 if ((month > 2) && LEAPYEAR(year))
832 days ++;
833 days += readrtc(RTC_DAY) - 1;
834 for (y = 1970; y < year; y++)
835 days += DAYSPERYEAR + LEAPYEAR(y);
836 sec = ((( days * 24 +
837 readrtc(RTC_HRS)) * 60 +
838 readrtc(RTC_MIN)) * 60 +
839 readrtc(RTC_SEC));
840 /* sec now contains the number of seconds, since Jan 1 1970,
841 in the local time zone */
842
843 sec += tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
844
845 y = time_second - sec;
846 if (y <= -2 || y >= 2) {
847 /* badly off, adjust it */
848 ts.tv_sec = sec;
849 ts.tv_nsec = 0;
850 tc_setclock(&ts);
851 }
852 splx(s);
853 return;
854
855 wrong_time:
856 printf("Invalid time in real time clock.\n");
857 printf("Check and reset the date immediately!\n");
858 }
859
860 /*
861 * Write system time back to RTC
862 */
863 void
864 resettodr()
865 {
866 unsigned long tm;
867 int y, m, s;
868
869 if (disable_rtc_set)
870 return;
871
872 s = splclock();
873 tm = time_second;
874 splx(s);
875
876 /* Disable RTC updates and interrupts. */
877 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
878
879 /* Calculate local time to put in RTC */
880
881 tm -= tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
882
883 writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60; /* Write back Seconds */
884 writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60; /* Write back Minutes */
885 writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24; /* Write back Hours */
886
887 /* We have now the days since 01-01-1970 in tm */
888 writertc(RTC_WDAY, (tm + 4) % 7 + 1); /* Write back Weekday */
889 for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
890 tm >= m;
891 y++, m = DAYSPERYEAR + LEAPYEAR(y))
892 tm -= m;
893
894 /* Now we have the years in y and the day-of-the-year in tm */
895 writertc(RTC_YEAR, bin2bcd(y%100)); /* Write back Year */
896 #ifdef USE_RTC_CENTURY
897 writertc(RTC_CENTURY, bin2bcd(y/100)); /* ... and Century */
898 #endif
899 for (m = 0; ; m++) {
900 int ml;
901
902 ml = daysinmonth[m];
903 if (m == 1 && LEAPYEAR(y))
904 ml++;
905 if (tm < ml)
906 break;
907 tm -= ml;
908 }
909
910 writertc(RTC_MONTH, bin2bcd(m + 1)); /* Write back Month */
911 writertc(RTC_DAY, bin2bcd(tm + 1)); /* Write back Month Day */
912
913 /* Reenable RTC updates and interrupts. */
914 writertc(RTC_STATUSB, rtc_statusb);
915 rtcin(RTC_INTR);
916 }
917
918
919 /*
920 * Start both clocks running.
921 */
922 void
923 cpu_initclocks()
924 {
925 int diag;
926
927 if (statclock_disable) {
928 /*
929 * The stat interrupt mask is different without the
930 * statistics clock. Also, don't set the interrupt
931 * flag which would normally cause the RTC to generate
932 * interrupts.
933 */
934 rtc_statusb = RTCSB_24HR;
935 } else {
936 /* Setting stathz to nonzero early helps avoid races. */
937 stathz = RTC_NOPROFRATE;
938 profhz = RTC_PROFRATE;
939 }
940
941 /* Finish initializing 8254 timer 0. */
942 intr_add_handler("clk", 0, (driver_intr_t *)clkintr, NULL,
943 INTR_TYPE_CLK | INTR_FAST, NULL);
944 i8254_intsrc = intr_lookup_source(0);
945 if (i8254_intsrc != NULL)
946 i8254_pending = i8254_intsrc->is_pic->pic_source_pending;
947
948 /* Initialize RTC. */
949 writertc(RTC_STATUSA, rtc_statusa);
950 writertc(RTC_STATUSB, RTCSB_24HR);
951
952 /* Don't bother enabling the statistics clock. */
953 if (!statclock_disable) {
954 diag = rtcin(RTC_DIAG);
955 if (diag != 0)
956 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
957
958 intr_add_handler("rtc", 8, (driver_intr_t *)rtcintr, NULL,
959 INTR_TYPE_CLK | INTR_FAST, NULL);
960
961 writertc(RTC_STATUSB, rtc_statusb);
962 rtcin(RTC_INTR);
963 }
964
965 init_TSC_tc();
966 }
967
968 void
969 cpu_startprofclock(void)
970 {
971
972 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
973 writertc(RTC_STATUSA, rtc_statusa);
974 psdiv = pscnt = psratio;
975 }
976
977 void
978 cpu_stopprofclock(void)
979 {
980
981 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
982 writertc(RTC_STATUSA, rtc_statusa);
983 psdiv = pscnt = 1;
984 }
985
986 static int
987 sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
988 {
989 int error;
990 u_int freq;
991
992 /*
993 * Use `i8254' instead of `timer' in external names because `timer'
994 * is is too generic. Should use it everywhere.
995 */
996 freq = timer_freq;
997 error = sysctl_handle_int(oidp, &freq, sizeof(freq), req);
998 if (error == 0 && req->newptr != NULL) {
999 #ifndef BURN_BRIDGES
1000 if (timer0_state != RELEASED)
1001 return (EBUSY); /* too much trouble to handle */
1002 #endif
1003 set_timer_freq(freq, hz);
1004 i8254_timecounter.tc_frequency = freq;
1005 }
1006 return (error);
1007 }
1008
1009 SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
1010 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", "");
1011
1012 static unsigned
1013 i8254_get_timecount(struct timecounter *tc)
1014 {
1015 u_int count;
1016 u_int high, low;
1017 u_int eflags;
1018
1019 eflags = read_eflags();
1020 mtx_lock_spin(&clock_lock);
1021
1022 /* Select timer0 and latch counter value. */
1023 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
1024
1025 low = inb(TIMER_CNTR0);
1026 high = inb(TIMER_CNTR0);
1027 count = timer0_max_count - ((high << 8) | low);
1028 if (count < i8254_lastcount ||
1029 (!i8254_ticked && (clkintr_pending ||
1030 ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) &&
1031 i8254_pending != NULL && i8254_pending(i8254_intsrc))))) {
1032 i8254_ticked = 1;
1033 i8254_offset += timer0_max_count;
1034 }
1035 i8254_lastcount = count;
1036 count += i8254_offset;
1037 mtx_unlock_spin(&clock_lock);
1038 return (count);
1039 }
1040
1041 #ifdef DEV_ISA
1042 /*
1043 * Attach to the ISA PnP descriptors for the timer and realtime clock.
1044 */
1045 static struct isa_pnp_id attimer_ids[] = {
1046 { 0x0001d041 /* PNP0100 */, "AT timer" },
1047 { 0x000bd041 /* PNP0B00 */, "AT realtime clock" },
1048 { 0 }
1049 };
1050
1051 static int
1052 attimer_probe(device_t dev)
1053 {
1054 int result;
1055
1056 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0)
1057 device_quiet(dev);
1058 return(result);
1059 }
1060
1061 static int
1062 attimer_attach(device_t dev)
1063 {
1064 return(0);
1065 }
1066
1067 static device_method_t attimer_methods[] = {
1068 /* Device interface */
1069 DEVMETHOD(device_probe, attimer_probe),
1070 DEVMETHOD(device_attach, attimer_attach),
1071 DEVMETHOD(device_detach, bus_generic_detach),
1072 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1073 DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */
1074 DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */
1075 { 0, 0 }
1076 };
1077
1078 static driver_t attimer_driver = {
1079 "attimer",
1080 attimer_methods,
1081 1, /* no softc */
1082 };
1083
1084 static devclass_t attimer_devclass;
1085
1086 DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0);
1087 DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0);
1088 #endif /* DEV_ISA */
Cache object: dd8c8f1f24f514efde8b0827cdd773b6
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