FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/clock.c
1 /*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz and Don Ahn.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 4. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * from: @(#)clock.c 7.2 (Berkeley) 5/12/91
33 */
34
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
37
38 /*
39 * Routines to handle clock hardware.
40 */
41
42 /*
43 * inittodr, settodr and support routines written
44 * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
45 *
46 * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
47 */
48
49 #include "opt_apic.h"
50 #include "opt_clock.h"
51 #include "opt_isa.h"
52 #include "opt_mca.h"
53 #include "opt_xbox.h"
54
55 #include <sys/param.h>
56 #include <sys/systm.h>
57 #include <sys/bus.h>
58 #include <sys/clock.h>
59 #include <sys/conf.h>
60 #include <sys/fcntl.h>
61 #include <sys/lock.h>
62 #include <sys/kdb.h>
63 #include <sys/mutex.h>
64 #include <sys/proc.h>
65 #include <sys/time.h>
66 #include <sys/timetc.h>
67 #include <sys/uio.h>
68 #include <sys/kernel.h>
69 #include <sys/limits.h>
70 #include <sys/module.h>
71 #include <sys/sched.h>
72 #include <sys/sysctl.h>
73 #include <sys/cons.h>
74 #include <sys/power.h>
75
76 #include <machine/clock.h>
77 #include <machine/cpu.h>
78 #include <machine/cputypes.h>
79 #include <machine/frame.h>
80 #include <machine/intr_machdep.h>
81 #include <machine/md_var.h>
82 #include <machine/psl.h>
83 #ifdef DEV_APIC
84 #include <machine/apicvar.h>
85 #endif
86 #include <machine/specialreg.h>
87 #include <machine/ppireg.h>
88 #include <machine/timerreg.h>
89
90 #include <isa/rtc.h>
91 #ifdef DEV_ISA
92 #include <isa/isareg.h>
93 #include <isa/isavar.h>
94 #endif
95
96 #ifdef DEV_MCA
97 #include <i386/bios/mca_machdep.h>
98 #endif
99
100 #define TIMER_DIV(x) ((timer_freq + (x) / 2) / (x))
101
102 int clkintr_pending;
103 int pscnt = 1;
104 int psdiv = 1;
105 int statclock_disable;
106 #ifndef TIMER_FREQ
107 #define TIMER_FREQ 1193182
108 #endif
109 u_int timer_freq = TIMER_FREQ;
110 int timer0_max_count;
111 int timer0_real_max_count;
112 #define RTC_LOCK mtx_lock_spin(&clock_lock)
113 #define RTC_UNLOCK mtx_unlock_spin(&clock_lock)
114
115 static int beeping = 0;
116 static struct mtx clock_lock;
117 static struct intsrc *i8254_intsrc;
118 static u_int32_t i8254_lastcount;
119 static u_int32_t i8254_offset;
120 static int (*i8254_pending)(struct intsrc *);
121 static int i8254_ticked;
122 static int using_lapic_timer;
123 static int rtc_reg = -1;
124 static u_char rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
125 static u_char rtc_statusb = RTCSB_24HR;
126
127 /* Values for timerX_state: */
128 #define RELEASED 0
129 #define RELEASE_PENDING 1
130 #define ACQUIRED 2
131 #define ACQUIRE_PENDING 3
132
133 static u_char timer2_state;
134
135 static unsigned i8254_get_timecount(struct timecounter *tc);
136 static unsigned i8254_simple_get_timecount(struct timecounter *tc);
137 static void set_timer_freq(u_int freq, int intr_freq);
138
139 static struct timecounter i8254_timecounter = {
140 i8254_get_timecount, /* get_timecount */
141 0, /* no poll_pps */
142 ~0u, /* counter_mask */
143 0, /* frequency */
144 "i8254", /* name */
145 0 /* quality */
146 };
147
148 static int
149 clkintr(struct trapframe *frame)
150 {
151
152 if (timecounter->tc_get_timecount == i8254_get_timecount) {
153 mtx_lock_spin(&clock_lock);
154 if (i8254_ticked)
155 i8254_ticked = 0;
156 else {
157 i8254_offset += timer0_max_count;
158 i8254_lastcount = 0;
159 }
160 clkintr_pending = 0;
161 mtx_unlock_spin(&clock_lock);
162 }
163 KASSERT(!using_lapic_timer, ("clk interrupt enabled with lapic timer"));
164 hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
165 #ifdef DEV_MCA
166 /* Reset clock interrupt by asserting bit 7 of port 0x61 */
167 if (MCA_system)
168 outb(0x61, inb(0x61) | 0x80);
169 #endif
170 return (FILTER_HANDLED);
171 }
172
173 int
174 acquire_timer2(int mode)
175 {
176
177 if (timer2_state != RELEASED)
178 return (-1);
179 timer2_state = ACQUIRED;
180
181 /*
182 * This access to the timer registers is as atomic as possible
183 * because it is a single instruction. We could do better if we
184 * knew the rate. Use of splclock() limits glitches to 10-100us,
185 * and this is probably good enough for timer2, so we aren't as
186 * careful with it as with timer0.
187 */
188 outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
189
190 return (0);
191 }
192
193 int
194 release_timer2()
195 {
196
197 if (timer2_state != ACQUIRED)
198 return (-1);
199 timer2_state = RELEASED;
200 outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
201 return (0);
202 }
203
204 /*
205 * This routine receives statistical clock interrupts from the RTC.
206 * As explained above, these occur at 128 interrupts per second.
207 * When profiling, we receive interrupts at a rate of 1024 Hz.
208 *
209 * This does not actually add as much overhead as it sounds, because
210 * when the statistical clock is active, the hardclock driver no longer
211 * needs to keep (inaccurate) statistics on its own. This decouples
212 * statistics gathering from scheduling interrupts.
213 *
214 * The RTC chip requires that we read status register C (RTC_INTR)
215 * to acknowledge an interrupt, before it will generate the next one.
216 * Under high interrupt load, rtcintr() can be indefinitely delayed and
217 * the clock can tick immediately after the read from RTC_INTR. In this
218 * case, the mc146818A interrupt signal will not drop for long enough
219 * to register with the 8259 PIC. If an interrupt is missed, the stat
220 * clock will halt, considerably degrading system performance. This is
221 * why we use 'while' rather than a more straightforward 'if' below.
222 * Stat clock ticks can still be lost, causing minor loss of accuracy
223 * in the statistics, but the stat clock will no longer stop.
224 */
225 static int
226 rtcintr(struct trapframe *frame)
227 {
228
229 while (rtcin(RTC_INTR) & RTCIR_PERIOD) {
230 if (profprocs != 0) {
231 if (--pscnt == 0)
232 pscnt = psdiv;
233 profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame));
234 }
235 if (pscnt == psdiv)
236 statclock(TRAPF_USERMODE(frame));
237 }
238 return (FILTER_HANDLED);
239 }
240
241 #include "opt_ddb.h"
242 #ifdef DDB
243 #include <ddb/ddb.h>
244
245 DB_SHOW_COMMAND(rtc, rtc)
246 {
247 printf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
248 rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
249 rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
250 rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
251 }
252 #endif /* DDB */
253
254 static int
255 getit(void)
256 {
257 int high, low;
258
259 mtx_lock_spin(&clock_lock);
260
261 /* Select timer0 and latch counter value. */
262 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
263
264 low = inb(TIMER_CNTR0);
265 high = inb(TIMER_CNTR0);
266
267 mtx_unlock_spin(&clock_lock);
268 return ((high << 8) | low);
269 }
270
271 /*
272 * Wait "n" microseconds.
273 * Relies on timer 1 counting down from (timer_freq / hz)
274 * Note: timer had better have been programmed before this is first used!
275 */
276 void
277 DELAY(int n)
278 {
279 int delta, prev_tick, tick, ticks_left;
280
281 #ifdef DELAYDEBUG
282 int getit_calls = 1;
283 int n1;
284 static int state = 0;
285 #endif
286
287 if (tsc_freq != 0 && !tsc_is_broken) {
288 uint64_t start, end, now;
289
290 sched_pin();
291 start = rdtsc();
292 end = start + (tsc_freq * n) / 1000000;
293 do {
294 cpu_spinwait();
295 now = rdtsc();
296 } while (now < end || (now > start && end < start));
297 sched_unpin();
298 return;
299 }
300 #ifdef DELAYDEBUG
301 if (state == 0) {
302 state = 1;
303 for (n1 = 1; n1 <= 10000000; n1 *= 10)
304 DELAY(n1);
305 state = 2;
306 }
307 if (state == 1)
308 printf("DELAY(%d)...", n);
309 #endif
310 /*
311 * Read the counter first, so that the rest of the setup overhead is
312 * counted. Guess the initial overhead is 20 usec (on most systems it
313 * takes about 1.5 usec for each of the i/o's in getit(). The loop
314 * takes about 6 usec on a 486/33 and 13 usec on a 386/20. The
315 * multiplications and divisions to scale the count take a while).
316 *
317 * However, if ddb is active then use a fake counter since reading
318 * the i8254 counter involves acquiring a lock. ddb must not do
319 * locking for many reasons, but it calls here for at least atkbd
320 * input.
321 */
322 #ifdef KDB
323 if (kdb_active)
324 prev_tick = 1;
325 else
326 #endif
327 prev_tick = getit();
328 n -= 0; /* XXX actually guess no initial overhead */
329 /*
330 * Calculate (n * (timer_freq / 1e6)) without using floating point
331 * and without any avoidable overflows.
332 */
333 if (n <= 0)
334 ticks_left = 0;
335 else if (n < 256)
336 /*
337 * Use fixed point to avoid a slow division by 1000000.
338 * 39099 = 1193182 * 2^15 / 10^6 rounded to nearest.
339 * 2^15 is the first power of 2 that gives exact results
340 * for n between 0 and 256.
341 */
342 ticks_left = ((u_int)n * 39099 + (1 << 15) - 1) >> 15;
343 else
344 /*
345 * Don't bother using fixed point, although gcc-2.7.2
346 * generates particularly poor code for the long long
347 * division, since even the slow way will complete long
348 * before the delay is up (unless we're interrupted).
349 */
350 ticks_left = ((u_int)n * (long long)timer_freq + 999999)
351 / 1000000;
352
353 while (ticks_left > 0) {
354 #ifdef KDB
355 if (kdb_active) {
356 inb(0x84);
357 tick = prev_tick - 1;
358 if (tick <= 0)
359 tick = timer0_max_count;
360 } else
361 #endif
362 tick = getit();
363 #ifdef DELAYDEBUG
364 ++getit_calls;
365 #endif
366 delta = prev_tick - tick;
367 prev_tick = tick;
368 if (delta < 0) {
369 delta += timer0_max_count;
370 /*
371 * Guard against timer0_max_count being wrong.
372 * This shouldn't happen in normal operation,
373 * but it may happen if set_timer_freq() is
374 * traced.
375 */
376 if (delta < 0)
377 delta = 0;
378 }
379 ticks_left -= delta;
380 }
381 #ifdef DELAYDEBUG
382 if (state == 1)
383 printf(" %d calls to getit() at %d usec each\n",
384 getit_calls, (n + 5) / getit_calls);
385 #endif
386 }
387
388 static void
389 sysbeepstop(void *chan)
390 {
391 ppi_spkr_off(); /* disable counter2 output to speaker */
392 timer_spkr_release();
393 beeping = 0;
394 }
395
396 int
397 sysbeep(int pitch, int period)
398 {
399 int x = splclock();
400
401 if (timer_spkr_acquire())
402 if (!beeping) {
403 /* Something else owns it. */
404 splx(x);
405 return (-1); /* XXX Should be EBUSY, but nobody cares anyway. */
406 }
407 mtx_lock_spin(&clock_lock);
408 spkr_set_pitch(pitch);
409 mtx_unlock_spin(&clock_lock);
410 if (!beeping) {
411 /* enable counter2 output to speaker */
412 ppi_spkr_on();
413 beeping = period;
414 timeout(sysbeepstop, (void *)NULL, period);
415 }
416 splx(x);
417 return (0);
418 }
419
420 /*
421 * RTC support routines
422 */
423
424 int
425 rtcin(reg)
426 int reg;
427 {
428 u_char val;
429
430 RTC_LOCK;
431 if (rtc_reg != reg) {
432 inb(0x84);
433 outb(IO_RTC, reg);
434 rtc_reg = reg;
435 inb(0x84);
436 }
437 val = inb(IO_RTC + 1);
438 RTC_UNLOCK;
439 return (val);
440 }
441
442 void
443 writertc(int reg, u_char val)
444 {
445
446 RTC_LOCK;
447 if (rtc_reg != reg) {
448 inb(0x84);
449 outb(IO_RTC, reg);
450 rtc_reg = reg;
451 inb(0x84);
452 }
453 outb(IO_RTC + 1, val);
454 inb(0x84);
455 RTC_UNLOCK;
456 }
457
458 static __inline int
459 readrtc(int port)
460 {
461 return(bcd2bin(rtcin(port)));
462 }
463
464 static u_int
465 calibrate_clocks(void)
466 {
467 u_int count, prev_count, tot_count;
468 int sec, start_sec, timeout;
469
470 if (bootverbose)
471 printf("Calibrating clock(s) ... ");
472 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
473 goto fail;
474 timeout = 100000000;
475
476 /* Read the mc146818A seconds counter. */
477 for (;;) {
478 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
479 sec = rtcin(RTC_SEC);
480 break;
481 }
482 if (--timeout == 0)
483 goto fail;
484 }
485
486 /* Wait for the mC146818A seconds counter to change. */
487 start_sec = sec;
488 for (;;) {
489 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
490 sec = rtcin(RTC_SEC);
491 if (sec != start_sec)
492 break;
493 }
494 if (--timeout == 0)
495 goto fail;
496 }
497
498 /* Start keeping track of the i8254 counter. */
499 prev_count = getit();
500 if (prev_count == 0 || prev_count > timer0_max_count)
501 goto fail;
502 tot_count = 0;
503
504 /*
505 * Wait for the mc146818A seconds counter to change. Read the i8254
506 * counter for each iteration since this is convenient and only
507 * costs a few usec of inaccuracy. The timing of the final reads
508 * of the counters almost matches the timing of the initial reads,
509 * so the main cause of inaccuracy is the varying latency from
510 * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
511 * rtcin(RTC_SEC) that returns a changed seconds count. The
512 * maximum inaccuracy from this cause is < 10 usec on 486's.
513 */
514 start_sec = sec;
515 for (;;) {
516 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
517 sec = rtcin(RTC_SEC);
518 count = getit();
519 if (count == 0 || count > timer0_max_count)
520 goto fail;
521 if (count > prev_count)
522 tot_count += prev_count - (count - timer0_max_count);
523 else
524 tot_count += prev_count - count;
525 prev_count = count;
526 if (sec != start_sec)
527 break;
528 if (--timeout == 0)
529 goto fail;
530 }
531
532 if (bootverbose) {
533 printf("i8254 clock: %u Hz\n", tot_count);
534 }
535 return (tot_count);
536
537 fail:
538 if (bootverbose)
539 printf("failed, using default i8254 clock of %u Hz\n",
540 timer_freq);
541 return (timer_freq);
542 }
543
544 static void
545 set_timer_freq(u_int freq, int intr_freq)
546 {
547 int new_timer0_real_max_count;
548
549 i8254_timecounter.tc_frequency = freq;
550 mtx_lock_spin(&clock_lock);
551 timer_freq = freq;
552 if (using_lapic_timer)
553 new_timer0_real_max_count = 0x10000;
554 else
555 new_timer0_real_max_count = TIMER_DIV(intr_freq);
556 if (new_timer0_real_max_count != timer0_real_max_count) {
557 timer0_real_max_count = new_timer0_real_max_count;
558 if (timer0_real_max_count == 0x10000)
559 timer0_max_count = 0xffff;
560 else
561 timer0_max_count = timer0_real_max_count;
562 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
563 outb(TIMER_CNTR0, timer0_real_max_count & 0xff);
564 outb(TIMER_CNTR0, timer0_real_max_count >> 8);
565 }
566 mtx_unlock_spin(&clock_lock);
567 }
568
569 static void
570 i8254_restore(void)
571 {
572
573 mtx_lock_spin(&clock_lock);
574 outb(TIMER_MODE, TIMER_SEL0 | TIMER_RATEGEN | TIMER_16BIT);
575 outb(TIMER_CNTR0, timer0_real_max_count & 0xff);
576 outb(TIMER_CNTR0, timer0_real_max_count >> 8);
577 mtx_unlock_spin(&clock_lock);
578 }
579
580 static void
581 rtc_restore(void)
582 {
583
584 /* Restore all of the RTC's "status" (actually, control) registers. */
585 /* XXX locking is needed for RTC access. */
586 rtc_reg = -1;
587 writertc(RTC_STATUSB, RTCSB_24HR);
588 writertc(RTC_STATUSA, rtc_statusa);
589 writertc(RTC_STATUSB, rtc_statusb);
590 rtcin(RTC_INTR);
591 }
592
593 /*
594 * Restore all the timers non-atomically (XXX: should be atomically).
595 *
596 * This function is called from pmtimer_resume() to restore all the timers.
597 * This should not be necessary, but there are broken laptops that do not
598 * restore all the timers on resume.
599 */
600 void
601 timer_restore(void)
602 {
603
604 i8254_restore(); /* restore timer_freq and hz */
605 rtc_restore(); /* reenable RTC interrupts */
606 }
607
608 /* This is separate from startrtclock() so that it can be called early. */
609 void
610 i8254_init(void)
611 {
612
613 mtx_init(&clock_lock, "clk", NULL, MTX_SPIN | MTX_NOPROFILE);
614 set_timer_freq(timer_freq, hz);
615 }
616
617 void
618 startrtclock()
619 {
620 u_int delta, freq;
621
622 writertc(RTC_STATUSA, rtc_statusa);
623 writertc(RTC_STATUSB, RTCSB_24HR);
624
625 freq = calibrate_clocks();
626 #ifdef CLK_CALIBRATION_LOOP
627 if (bootverbose) {
628 printf(
629 "Press a key on the console to abort clock calibration\n");
630 while (cncheckc() == -1)
631 calibrate_clocks();
632 }
633 #endif
634
635 /*
636 * Use the calibrated i8254 frequency if it seems reasonable.
637 * Otherwise use the default, and don't use the calibrated i586
638 * frequency.
639 */
640 delta = freq > timer_freq ? freq - timer_freq : timer_freq - freq;
641 if (delta < timer_freq / 100) {
642 #ifndef CLK_USE_I8254_CALIBRATION
643 if (bootverbose)
644 printf(
645 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
646 freq = timer_freq;
647 #endif
648 timer_freq = freq;
649 } else {
650 if (bootverbose)
651 printf(
652 "%d Hz differs from default of %d Hz by more than 1%%\n",
653 freq, timer_freq);
654 }
655
656 set_timer_freq(timer_freq, hz);
657 tc_init(&i8254_timecounter);
658
659 init_TSC();
660 }
661
662 /*
663 * Initialize the time of day register, based on the time base which is, e.g.
664 * from a filesystem.
665 */
666 void
667 inittodr(time_t base)
668 {
669 int s;
670 struct timespec ts;
671 struct clocktime ct;
672
673 if (base) {
674 s = splclock();
675 ts.tv_sec = base;
676 ts.tv_nsec = 0;
677 tc_setclock(&ts);
678 splx(s);
679 }
680
681 /* Look if we have a RTC present and the time is valid */
682 if (!(rtcin(RTC_STATUSD) & RTCSD_PWR)) {
683 printf("Invalid time in clock: check and reset the date!\n");
684 return;
685 }
686
687 /* wait for time update to complete */
688 /* If RTCSA_TUP is zero, we have at least 244us before next update */
689 s = splhigh();
690 while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
691 splx(s);
692 s = splhigh();
693 }
694 ct.nsec = 0;
695 ct.sec = readrtc(RTC_SEC);
696 ct.min = readrtc(RTC_MIN);
697 ct.hour = readrtc(RTC_HRS);
698 ct.day = readrtc(RTC_DAY);
699 ct.dow = readrtc(RTC_WDAY) - 1;
700 ct.mon = readrtc(RTC_MONTH);
701 ct.year = readrtc(RTC_YEAR);
702 #ifdef USE_RTC_CENTURY
703 ct.year += readrtc(RTC_CENTURY) * 100;
704 #else
705 ct.year += 2000;
706 #endif
707 /* Set dow = -1 because some clocks don't set it correctly. */
708 ct.dow = -1;
709 if (clock_ct_to_ts(&ct, &ts)) {
710 printf("Invalid time in clock: check and reset the date!\n");
711 return;
712 }
713 ts.tv_sec += utc_offset();
714 tc_setclock(&ts);
715 }
716
717 /*
718 * Write system time back to RTC
719 */
720 void
721 resettodr()
722 {
723 struct timespec ts;
724 struct clocktime ct;
725
726 if (disable_rtc_set)
727 return;
728
729 getnanotime(&ts);
730 ts.tv_sec -= utc_offset();
731 clock_ts_to_ct(&ts, &ct);
732
733 /* Disable RTC updates and interrupts. */
734 writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
735
736 writertc(RTC_SEC, bin2bcd(ct.sec)); /* Write back Seconds */
737 writertc(RTC_MIN, bin2bcd(ct.min)); /* Write back Minutes */
738 writertc(RTC_HRS, bin2bcd(ct.hour)); /* Write back Hours */
739
740 writertc(RTC_WDAY, ct.dow + 1); /* Write back Weekday */
741 writertc(RTC_DAY, bin2bcd(ct.day)); /* Write back Day */
742 writertc(RTC_MONTH, bin2bcd(ct.mon)); /* Write back Month */
743 writertc(RTC_YEAR, bin2bcd(ct.year % 100)); /* Write back Year */
744 #ifdef USE_RTC_CENTURY
745 writertc(RTC_CENTURY, bin2bcd(ct.year / 100)); /* ... and Century */
746 #endif
747
748 /* Reenable RTC updates and interrupts. */
749 writertc(RTC_STATUSB, rtc_statusb);
750 rtcin(RTC_INTR);
751 }
752
753
754 /*
755 * Start both clocks running.
756 */
757 void
758 cpu_initclocks()
759 {
760 int diag;
761
762 #ifdef DEV_APIC
763 using_lapic_timer = lapic_setup_clock();
764 #endif
765 /*
766 * If we aren't using the local APIC timer to drive the kernel
767 * clocks, setup the interrupt handler for the 8254 timer 0 so
768 * that it can drive hardclock(). Otherwise, change the 8254
769 * timecounter to user a simpler algorithm.
770 */
771 if (!using_lapic_timer) {
772 intr_add_handler("clk", 0, (driver_filter_t *)clkintr, NULL,
773 NULL, INTR_TYPE_CLK, NULL);
774 i8254_intsrc = intr_lookup_source(0);
775 if (i8254_intsrc != NULL)
776 i8254_pending =
777 i8254_intsrc->is_pic->pic_source_pending;
778 } else {
779 i8254_timecounter.tc_get_timecount =
780 i8254_simple_get_timecount;
781 i8254_timecounter.tc_counter_mask = 0xffff;
782 set_timer_freq(timer_freq, hz);
783 }
784
785 /* Initialize RTC. */
786 writertc(RTC_STATUSA, rtc_statusa);
787 writertc(RTC_STATUSB, RTCSB_24HR);
788
789 /*
790 * If the separate statistics clock hasn't been explicility disabled
791 * and we aren't already using the local APIC timer to drive the
792 * kernel clocks, then setup the RTC to periodically interrupt to
793 * drive statclock() and profclock().
794 */
795 if (!statclock_disable && !using_lapic_timer) {
796 diag = rtcin(RTC_DIAG);
797 if (diag != 0)
798 printf("RTC BIOS diagnostic error %b\n", diag, RTCDG_BITS);
799
800 /* Setting stathz to nonzero early helps avoid races. */
801 stathz = RTC_NOPROFRATE;
802 profhz = RTC_PROFRATE;
803
804 /* Enable periodic interrupts from the RTC. */
805 rtc_statusb |= RTCSB_PINTR;
806 intr_add_handler("rtc", 8, (driver_filter_t *)rtcintr, NULL, NULL,
807 INTR_TYPE_CLK, NULL);
808
809 writertc(RTC_STATUSB, rtc_statusb);
810 rtcin(RTC_INTR);
811 }
812
813 init_TSC_tc();
814 }
815
816 void
817 cpu_startprofclock(void)
818 {
819
820 if (using_lapic_timer)
821 return;
822 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
823 writertc(RTC_STATUSA, rtc_statusa);
824 psdiv = pscnt = psratio;
825 }
826
827 void
828 cpu_stopprofclock(void)
829 {
830
831 if (using_lapic_timer)
832 return;
833 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
834 writertc(RTC_STATUSA, rtc_statusa);
835 psdiv = pscnt = 1;
836 }
837
838 static int
839 sysctl_machdep_i8254_freq(SYSCTL_HANDLER_ARGS)
840 {
841 int error;
842 u_int freq;
843
844 /*
845 * Use `i8254' instead of `timer' in external names because `timer'
846 * is is too generic. Should use it everywhere.
847 */
848 freq = timer_freq;
849 error = sysctl_handle_int(oidp, &freq, 0, req);
850 if (error == 0 && req->newptr != NULL)
851 set_timer_freq(freq, hz);
852 return (error);
853 }
854
855 SYSCTL_PROC(_machdep, OID_AUTO, i8254_freq, CTLTYPE_INT | CTLFLAG_RW,
856 0, sizeof(u_int), sysctl_machdep_i8254_freq, "IU", "");
857
858 static unsigned
859 i8254_simple_get_timecount(struct timecounter *tc)
860 {
861
862 return (timer0_max_count - getit());
863 }
864
865 static unsigned
866 i8254_get_timecount(struct timecounter *tc)
867 {
868 u_int count;
869 u_int high, low;
870 u_int eflags;
871
872 eflags = read_eflags();
873 mtx_lock_spin(&clock_lock);
874
875 /* Select timer0 and latch counter value. */
876 outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);
877
878 low = inb(TIMER_CNTR0);
879 high = inb(TIMER_CNTR0);
880 count = timer0_max_count - ((high << 8) | low);
881 if (count < i8254_lastcount ||
882 (!i8254_ticked && (clkintr_pending ||
883 ((count < 20 || (!(eflags & PSL_I) && count < timer0_max_count / 2u)) &&
884 i8254_pending != NULL && i8254_pending(i8254_intsrc))))) {
885 i8254_ticked = 1;
886 i8254_offset += timer0_max_count;
887 }
888 i8254_lastcount = count;
889 count += i8254_offset;
890 mtx_unlock_spin(&clock_lock);
891 return (count);
892 }
893
894 #ifdef DEV_ISA
895 /*
896 * Attach to the ISA PnP descriptors for the timer and realtime clock.
897 */
898 static struct isa_pnp_id attimer_ids[] = {
899 { 0x0001d041 /* PNP0100 */, "AT timer" },
900 { 0x000bd041 /* PNP0B00 */, "AT realtime clock" },
901 { 0 }
902 };
903
904 static int
905 attimer_probe(device_t dev)
906 {
907 int result;
908
909 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, attimer_ids)) <= 0)
910 device_quiet(dev);
911 return(result);
912 }
913
914 static int
915 attimer_attach(device_t dev)
916 {
917 return(0);
918 }
919
920 static device_method_t attimer_methods[] = {
921 /* Device interface */
922 DEVMETHOD(device_probe, attimer_probe),
923 DEVMETHOD(device_attach, attimer_attach),
924 DEVMETHOD(device_detach, bus_generic_detach),
925 DEVMETHOD(device_shutdown, bus_generic_shutdown),
926 DEVMETHOD(device_suspend, bus_generic_suspend), /* XXX stop statclock? */
927 DEVMETHOD(device_resume, bus_generic_resume), /* XXX restart statclock? */
928 { 0, 0 }
929 };
930
931 static driver_t attimer_driver = {
932 "attimer",
933 attimer_methods,
934 1, /* no softc */
935 };
936
937 static devclass_t attimer_devclass;
938
939 DRIVER_MODULE(attimer, isa, attimer_driver, attimer_devclass, 0, 0);
940 DRIVER_MODULE(attimer, acpi, attimer_driver, attimer_devclass, 0, 0);
941
942 #endif /* DEV_ISA */
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