The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/cxreg.h

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    1 /*
    2  * Defines for Cronyx-Sigma adapter, based on Cirrus Logic multiprotocol
    3  * controller RISC processor CL-CD2400/2401.
    4  *
    5  * Copyright (C) 1994 Cronyx Ltd.
    6  * Author: Serge Vakulenko, <vak@zebub.msk.su>
    7  *
    8  * This software is distributed with NO WARRANTIES, not even the implied
    9  * warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
   10  *
   11  * Authors grant any other persons or organizations permission to use
   12  * or modify this software as long as this message is kept with the software,
   13  * all derivative works or modified versions.
   14  *
   15  * Version 1.0, Fri Oct  7 19:34:06 MSD 1994
   16  * $FreeBSD: releng/5.0/sys/i386/isa/cxreg.h 59874 2000-05-01 20:32:07Z peter $
   17  */
   18 #define NBRD      3             /* the maximum number of installed boards */
   19 #define NPORT     16            /* the number of i/o ports per board */
   20 
   21 #define REVCL_MIN 7             /* CD2400 min. revision number G */
   22 #define REVCL_MAX 11            /* CD2400 max. revision number K */
   23 
   24 #define BRD_INTR_LEVEL 0x5a     /* interrupt level (arbitrary PILR value) */
   25 
   26 #define CS0(p)  ((p) | 0x8000)  /* chip select 0 */
   27 #define CS1(p)  ((p) | 0xc000)  /* chip select 1 */
   28 #define BSR(p)  (p)             /* board status register, read only */
   29 #define BCR0(p) (p)             /* board command register 0, write only */
   30 #define BCR1(p) ((p) | 0x2000)  /* board command register 1, write only */
   31 
   32 /*
   33  * Chip register address, B is chip base port, R is chip register number.
   34  */
   35 #define R(b,r) ((b) | (((r)<<6 & 0x3c00) | ((r) & 0xf)))
   36 
   37 /*
   38  * Interrupt acknowledge register, P is board port, L is interrupt level,
   39  * as programmed in PILR.
   40  */
   41 #define IACK(p,l)   (R(p,l) | 0x4000)
   42 
   43 /*
   44  * Global registers.
   45  */
   46 #define GFRCR(b)    R(b,0x82)   /* global firmware revision code register */
   47 #define CAR(b)      R(b,0xec)   /* channel access register */
   48 
   49 /*
   50  * Option registers.
   51  */
   52 #define CMR(b)      R(b,0x18)   /* channel mode register */
   53 #define COR1(b)     R(b,0x13)   /* channel option register 1 */
   54 #define COR2(b)     R(b,0x14)   /* channel option register 2 */
   55 #define COR3(b)     R(b,0x15)   /* channel option register 3 */
   56 #define COR4(b)     R(b,0x16)   /* channel option register 4 */
   57 #define COR5(b)     R(b,0x17)   /* channel option register 5 */
   58 #define COR6(b)     R(b,0x1b)   /* channel option register 6 */
   59 #define COR7(b)     R(b,0x04)   /* channel option register 7 */
   60 #define SCHR1(b)    R(b,0x1c)   /* special character register 1 */
   61 #define SCHR2(b)    R(b,0x1d)   /* special character register 2 */
   62 #define SCHR3(b)    R(b,0x1e)   /* special character register 3 */
   63 #define SCHR4(b)    R(b,0x1f)   /* special character register 4 */
   64 #define SCRL(b)     R(b,0x20)   /* special character range low */
   65 #define SCRH(b)     R(b,0x21)   /* special character range high */
   66 #define LNXT(b)     R(b,0x2d)   /* LNext character */
   67 #define RFAR1(b)    R(b,0x1c)   /* receive frame address register 1 */
   68 #define RFAR2(b)    R(b,0x1d)   /* receive frame address register 2 */
   69 #define RFAR3(b)    R(b,0x1e)   /* receive frame address register 3 */
   70 #define RFAR4(b)    R(b,0x1f)   /* receive frame address register 4 */
   71 #define CPSR(b)     R(b,0xd4)   /* CRC polynomial select register */
   72 
   73 /*
   74  * Bit rate and clock option registers.
   75  */
   76 #define RBPR(b)     R(b,0xc9)   /* receive baud rate period register */
   77 #define RCOR(b)     R(b,0xca)   /* receive clock option register */
   78 #define TBPR(b)     R(b,0xc1)   /* transmit baud rate period register */
   79 #define TCOR(b)     R(b,0xc2)   /* receive clock option register */
   80 
   81 /*
   82  * Channel command and status registers.
   83  */
   84 #define CCR(b)      R(b,0x10)   /* channel command register */
   85 #define STCR(b)     R(b,0x11)   /* special transmit command register */
   86 #define CSR(b)      R(b,0x19)   /* channel status register */
   87 #define MSVR(b)     R(b,0xdc)   /* modem signal value register */
   88 #define MSVR_RTS(b) R(b,0xdc)   /* modem RTS setup register */
   89 #define MSVR_DTR(b) R(b,0xdd)   /* modem DTR setup register */
   90 
   91 /*
   92  * Interrupt registers.
   93  */
   94 #define LIVR(b)     R(b,0x0a)   /* local interrupt vector register */
   95 #define IER(b)      R(b,0x12)   /* interrupt enable register */
   96 #define LICR(b)     R(b,0x25)   /* local interrupting channel register */
   97 #define STK(b)      R(b,0xe0)   /* stack register */
   98 
   99 /*
  100  * Receive interrupt registers.
  101  */
  102 #define RPILR(b)    R(b,0xe3)   /* receive priority interrupt level register */
  103 #define RIR(b)      R(b,0xef)   /* receive interrupt register */
  104 #define RISR(b)     R(b,0x8a)   /* receive interrupt status register */
  105 #define RISRL(b)    R(b,0x8a)   /* receive interrupt status register low */
  106 #define RISRH(b)    R(b,0x8b)   /* receive interrupt status register high */
  107 #define RFOC(b)     R(b,0x33)   /* receive FIFO output count */
  108 #define RDR(b)      R(b,0xf8)   /* receive data register */
  109 #define REOIR(b)    R(b,0x87)   /* receive end of interrupt register */
  110 
  111 /*
  112  * Transmit interrupt registers.
  113  */
  114 #define TPILR(b)    R(b,0xe2)   /* transmit priority interrupt level reg */
  115 #define TIR(b)      R(b,0xee)   /* transmit interrupt register */
  116 #define TISR(b)     R(b,0x89)   /* transmit interrupt status register */
  117 #define TFTC(b)     R(b,0x83)   /* transmit FIFO transfer count */
  118 #define TDR(b)      R(b,0xf8)   /* transmit data register */
  119 #define TEOIR(b)    R(b,0x86)   /* transmit end of interrupt register */
  120 
  121 /*
  122  * Modem interrupt registers.
  123  */
  124 #define MPILR(b)    R(b,0xe1)   /* modem priority interrupt level register */
  125 #define MIR(b)      R(b,0xed)   /* modem interrupt register */
  126 #define MISR(b)     R(b,0x88)   /* modem/timer interrupt status register */
  127 #define MEOIR(b)    R(b,0x85)   /* modem end of interrupt register */
  128 
  129 /*
  130  * DMA registers.
  131  */
  132 #define DMR(b)      R(b,0xf4)   /* DMA mode register */
  133 #define BERCNT(b)   R(b,0x8d)   /* bus error retry count */
  134 #define DMABSTS(b)  R(b,0x1a)   /* DMA buffer status */
  135 
  136 /*
  137  * DMA receive registers.
  138  */
  139 #define ARBADRL(b)  R(b,0x40)   /* A receive buffer address lower */
  140 #define ARBADRU(b)  R(b,0x42)   /* A receive buffer address upper */
  141 #define BRBADRL(b)  R(b,0x44)   /* B receive buffer address lower */
  142 #define BRBADRU(b)  R(b,0x46)   /* B receive buffer address upper */
  143 #define ARBCNT(b)   R(b,0x48)   /* A receive buffer byte count */
  144 #define BRBCNT(b)   R(b,0x4a)   /* B receive buffer byte count */
  145 #define ARBSTS(b)   R(b,0x4c)   /* A receive buffer status */
  146 #define BRBSTS(b)   R(b,0x4d)   /* B receive buffer status */
  147 #define RCBADRL(b)  R(b,0x3c)   /* receive current buffer address lower */
  148 #define RCBADRU(b)  R(b,0x3e)   /* receive current buffer address upper */
  149 
  150 /*
  151  * DMA transmit registers.
  152  */
  153 #define ATBADRL(b)  R(b,0x50)   /* A transmit buffer address lower */
  154 #define ATBADRU(b)  R(b,0x52)   /* A transmit buffer address upper */
  155 #define BTBADRL(b)  R(b,0x54)   /* B transmit buffer address lower */
  156 #define BTBADRU(b)  R(b,0x56)   /* B transmit buffer address upper */
  157 #define ATBCNT(b)   R(b,0x58)   /* A transmit buffer byte count */
  158 #define BTBCNT(b)   R(b,0x5a)   /* B transmit buffer byte count */
  159 #define ATBSTS(b)   R(b,0x5c)   /* A transmit buffer status */
  160 #define BTBSTS(b)   R(b,0x5d)   /* B transmit buffer status */
  161 #define TCBADRL(b)  R(b,0x38)   /* transmit current buffer address lower */
  162 #define TCBADRU(b)  R(b,0x3a)   /* transmit current buffer address upper */
  163 
  164 /*
  165  * Timer registers.
  166  */
  167 #define TPR(b)      R(b,0xd8)   /* timer period register */
  168 #define RTPR(b)     R(b,0x26)   /* receive timeout period register */
  169 #define RTPRL(b)    R(b,0x26)   /* receive timeout period register low */
  170 #define RTPTH(b)    R(b,0x27)   /* receive timeout period register high */
  171 #define GT1(b)      R(b,0x28)   /* general timer 1 */
  172 #define GT1L(b)     R(b,0x28)   /* general timer 1 low */
  173 #define GT1H(b)     R(b,0x29)   /* general timer 1 high */
  174 #define GT2(b)      R(b,0x2a)   /* general timer 2 */
  175 #define TTR(b)      R(b,0x2a)   /* transmit timer register */
  176 
  177 /*
  178  * Board status register bits.
  179  */
  180 #define BSR_NOINTR     0x01     /* no interrupt pending flag */
  181 
  182 #define BSR_VAR_MASK   0x66     /* adapter variant mask */
  183 
  184 #define BSR_OSC_MASK   0x18     /* oscillator frequency mask */
  185 #define BSR_OSC_20     0x18     /* 20 MHz */
  186 #define BSR_OSC_18432  0x10     /* 18.432 MHz */
  187 
  188 #define BSR_NOCHAIN    0x80     /* no daisy chained board */
  189 
  190 #define BSR_NODSR(n)   (0x100 << (n))   /* DSR from channels 0-3, inverted */
  191 #define BSR_NOCD(n)    (0x1000 << (n))  /* CD from channels 0-3, inverted */
  192 
  193 /*
  194  * Board revision mask.
  195  */
  196 #define BSR_REV_MASK   (BSR_OSC_MASK|BSR_VAR_MASK|BSR_NOCHAIN)
  197 
  198 /*
  199  * Board control register 0 bits.
  200  */
  201 #define BCR0_IRQ_DIS  0x00      /* no interrupt generated */
  202 #define BCR0_IRQ_3    0x01      /* select IRQ number 3 */
  203 #define BCR0_IRQ_5    0x02      /* select IRQ number 5 */
  204 #define BCR0_IRQ_7    0x03      /* select IRQ number 7 */
  205 #define BCR0_IRQ_10   0x04      /* select IRQ number 10 */
  206 #define BCR0_IRQ_11   0x05      /* select IRQ number 11 */
  207 #define BCR0_IRQ_12   0x06      /* select IRQ number 12 */
  208 #define BCR0_IRQ_15   0x07      /* select IRQ number 15 */
  209 
  210 #define BCR0_NORESET  0x08      /* CD2400 reset flag (inverted) */
  211 
  212 #define BCR0_DMA_DIS  0x00      /* no interrupt generated */
  213 #define BCR0_DMA_5    0x10      /* select DMA channel 5 */
  214 #define BCR0_DMA_6    0x20      /* select DMA channel 6 */
  215 #define BCR0_DMA_7    0x30      /* select DMA channel 7 */
  216 
  217 #define BCR0_UM_ASYNC 0x00      /* channel 0 mode - async */
  218 #define BCR0_UM_SYNC  0x80      /* channel 0 mode - sync */
  219 #define BCR0_UI_RS232 0x00      /* channel 0 interface - RS-232 */
  220 #define BCR0_UI_RS449 0x40      /* channel 0 interface - RS-449/V.35 */
  221 #define BCR0_UMASK    0xc0      /* channel 0 interface mask */
  222 
  223 /*
  224  * Board control register 1 bits.
  225  */
  226 #define BCR1_DTR(n)  (0x100 << (n))     /* DTR for channels 0-3 sync */
  227 
  228 /*
  229  * Cronyx board variants.
  230  */
  231 #define CRONYX_100      0x64
  232 #define CRONYX_400      0x62
  233 #define CRONYX_500      0x60
  234 #define CRONYX_410      0x24
  235 #define CRONYX_810      0x20
  236 #define CRONYX_410s     0x04
  237 #define CRONYX_810s     0x00
  238 #define CRONYX_440      0x44
  239 #define CRONYX_840      0x40
  240 #define CRONYX_401      0x26
  241 #define CRONYX_801      0x22
  242 #define CRONYX_401s     0x06
  243 #define CRONYX_801s     0x02
  244 #define CRONYX_404      0x46
  245 #define CRONYX_703      0x42
  246 
  247 /*
  248  * Channel commands (CCR).
  249  */
  250 #define CCR_CLRCH  0x40         /* clear channel */
  251 #define CCR_INITCH 0x20         /* initialize channel */
  252 #define CCR_RSTALL 0x10         /* reset all channels */
  253 #define CCR_ENTX   0x08         /* enable transmitter */
  254 #define CCR_DISTX  0x04         /* disable transmitter */
  255 #define CCR_ENRX   0x02         /* enable receiver */
  256 #define CCR_DISRX  0x01         /* disable receiver */
  257 #define CCR_CLRT1  0xc0         /* clear timer 1 */
  258 #define CCR_CLRT2  0xa0         /* clear timer 2 */
  259 #define CCR_CLRRCV 0x90         /* clear receiver */
  260 
  261 /*
  262  * Interrupt enable register (IER) bits.
  263  */
  264 #define IER_MDM    0x80         /* modem status changed */
  265 #define IER_RET    0x20         /* receive exception timeout */
  266 #define IER_RXD    0x08         /* data received */
  267 #define IER_TIMER  0x04         /* timer expired */
  268 #define IER_TXMPTY 0x02         /* transmitter empty */
  269 #define IER_TXD    0x01         /* data transmitted */
  270 
  271 /*
  272  * Modem signal values register bits (MSVR).
  273  */
  274 #define MSV_DSR    0x80         /* state of Data Set Ready input */
  275 #define MSV_CD     0x40         /* state of Carrier Detect input */
  276 #define MSV_CTS    0x20         /* state of Clear to Send input */
  277 #define MSV_TXCOUT 0x10         /* TXCout/DTR pin output flag */
  278 #define MSV_PORTID 0x04         /* device is CL-CD2401 (not 2400) */
  279 #define MSV_DTR    0x02         /* state of Data Terminal Ready output */
  280 #define MSV_RTS    0x01         /* state of Request to Send output */
  281 #define MSV_BITS "\2\1rts\2dtr\3cd2400\5txcout\6cts\7cd\10dsr"
  282 
  283 /*
  284  * DMA buffer status register bits (DMABSTS).
  285  */
  286 #define DMABSTS_TDALIGN 0x80    /* internal data alignment in transmit FIFO */
  287 #define DMABSTS_RSTAPD  0x40    /* reset append mode */
  288 #define DMABSTS_CRTTBUF 0x20    /* internal current transmit buffer in use */
  289 #define DMABSTS_APPEND  0x10    /* append buffer is in use */
  290 #define DMABSTS_NTBUF   0x08    /* next transmit buffer is B (not A) */
  291 #define DMABSTS_TBUSY   0x04    /* current transmit buffer is in use */
  292 #define DMABSTS_NRBUF   0x02    /* next receive buffer is B (not A) */
  293 #define DMABSTS_RBUSY   0x01    /* current receive buffer is in use */
  294 
  295 /*
  296  * Buffer status register bits ([AB][RT]BSTS).
  297  */
  298 #define BSTS_BUSERR 0x80        /* bus error */
  299 #define BSTS_EOFR   0x40        /* end of frame */
  300 #define BSTS_EOBUF  0x20        /* end of buffer */
  301 #define BSTS_APPEND 0x08        /* append mode */
  302 #define BSTS_INTR   0x02        /* interrupt required */
  303 #define BSTS_OWN24  0x01        /* buffer is (free to be) used by CD2400 */
  304 #define BSTS_BITS "\2\1own24\2intr\4append\6eobuf\7eofr\10buserr"
  305 
  306 /*
  307  * Receive interrupt status register (RISR) bits.
  308  */
  309 #define RIS_OVERRUN   0x0008    /* overrun error */
  310 #define RIS_BB        0x0800    /* buffer B status (not A) */
  311 #define RIS_EOBUF     0x2000    /* end of buffer reached */
  312 #define RIS_EOFR      0x4000    /* frame reception complete */
  313 #define RIS_BUSERR    0x8000    /* bus error */
  314 
  315 #define RISH_CLRDCT   0x0001    /* X.21 clear detect */
  316 #define RISH_RESIND   0x0004    /* residual indication */
  317 #define RISH_CRCERR   0x0010    /* CRC error */
  318 #define RISH_RXABORT  0x0020    /* abort sequence received */
  319 #define RISH_EOFR     0x0040    /* complete frame received */
  320 #define RISH_BITS "\2\1clrdct\3resind\4overrun\5crcerr\6rxabort\7eofr\14bb\16eobuf\17eofr\20buserr"
  321 
  322 #define RISA_BREAK    0x0001    /* break signal detected */
  323 #define RISA_FRERR    0x0002    /* frame error (bad stop bits) */
  324 #define RISA_PARERR   0x0004    /* parity error */
  325 #define RISA_SCMASK   0x0070    /* special character detect mask */
  326 #define RISA_SCHR1    0x0010    /* special character 1 detected */
  327 #define RISA_SCHR2    0x0020    /* special character 2 detected */
  328 #define RISA_SCHR3    0x0030    /* special character 3 detected */
  329 #define RISA_SCHR4    0x0040    /* special character 4 detected */
  330 #define RISA_SCRANGE  0x0070    /* special character in range detected */
  331 #define RISA_TIMEOUT  0x0080    /* receive timeout, no data */
  332 #define RISA_BITS "\2\1break\2frerr\3parerr\4overrun\5schr1\6schr2\7schr4\10timeout\14bb\16eobuf\17eofr\20buserr"
  333 
  334 #define RISB_CRCERR   0x0010    /* CRC error */
  335 #define RISB_RXABORT  0x0020    /* abort sequence received */
  336 #define RISB_EOFR     0x0040    /* complete frame received */
  337 
  338 #define RISX_LEADCHG  0x0001    /* CTS lead change */
  339 #define RISX_PARERR   0x0004    /* parity error */
  340 #define RISX_SCMASK   0x0070    /* special character detect mask */
  341 #define RISX_SCHR1    0x0010    /* special character 1 detected */
  342 #define RISX_SCHR2    0x0020    /* special character 2 detected */
  343 #define RISX_SCHR3    0x0030    /* special character 3 detected */
  344 #define RISX_ALLZERO  0x0040    /* all 0 condition detected */
  345 #define RISX_ALLONE   0x0050    /* all 1 condition detected */
  346 #define RISX_ALTOZ    0x0060    /* alternating 1 0 condition detected */
  347 #define RISX_SYN      0x0070    /* SYN detected */
  348 #define RISX_LEAD     0x0080    /* leading value */
  349 
  350 /*
  351  * Channel mode register (CMR) bits.
  352  */
  353 #define CMR_RXDMA     0x80      /* DMA receive transfer mode */
  354 #define CMR_TXDMA     0x40      /* DMA transmit transfer mode */
  355 #define CMR_HDLC      0x00      /* HDLC protocol mode */
  356 #define CMR_BISYNC    0x01      /* BISYNC protocol mode */
  357 #define CMR_ASYNC     0x02      /* ASYNC protocol mode */
  358 #define CMR_X21       0x03      /* X.21 protocol mode */
  359 
  360 /*
  361  * Modem interrupt status register (MISR) bits.
  362  */
  363 #define MIS_CDSR      0x80      /* DSR changed */
  364 #define MIS_CCD       0x40      /* CD changed */
  365 #define MIS_CCTS      0x20      /* CTS changed */
  366 #define MIS_CGT2      0x02      /* GT2 timer expired */
  367 #define MIS_CGT1      0x01      /* GT1 timer expired */
  368 #define MIS_BITS "\2\1gt1\2gt2\6ccts\7ccd\10cdsr"
  369 
  370 /*
  371  * Transmit interrupt status register (TISR) bits.
  372  */
  373 #define TIS_BUSERR    0x80      /* Bus error */
  374 #define TIS_EOFR      0x40      /* End of frame */
  375 #define TIS_EOBUF     0x20      /* end of transmit buffer reached */
  376 #define TIS_UNDERRUN  0x10      /* transmit underrun */
  377 #define TIS_BB        0x08      /* buffer B status (not A) */
  378 #define TIS_TXEMPTY   0x02      /* transmitter empty */
  379 #define TIS_TXDATA    0x01      /* transmit data below threshold */
  380 #define TIS_BITS "\2\1txdata\2txempty\4bb\5underrun\6eobuf\7eofr\10buserr"
  381 
  382 /*
  383  * Local interrupt vector register (LIVR) bits.
  384  */
  385 #define LIV_EXCEP     0
  386 #define LIV_MODEM     1
  387 #define LIV_TXDATA    2
  388 #define LIV_RXDATA    3
  389 
  390 /*
  391  * Transmit end of interrupt registers (TEOIR) bits.
  392  */
  393 #define TEOI_TERMBUFF  0x80     /* force current buffer to be discarded */
  394 #define TEOI_EOFR      0x40     /* end of frame in interrupt mode */
  395 #define TEOI_SETTM2    0x20     /* set general timer 2 in sync mode */
  396 #define TEOI_SETTM1    0x10     /* set general timer 1 in sync mode */
  397 #define TEOI_NOTRANSF  0x08     /* no transfer of data on this interrupt */
  398 
  399 /*
  400  * Receive end of interrupt registers (REOIR) bits.
  401  */
  402 #define REOI_TERMBUFF  0x80     /* force current buffer to be terminated */
  403 #define REOI_DISCEXC   0x40     /* discard exception character */
  404 #define REOI_SETTM2    0x20     /* set general timer 2 */
  405 #define REOI_SETTM1    0x10     /* set general timer 1 */
  406 #define REOI_NOTRANSF  0x08     /* no transfer of data */
  407 #define REOI_GAP_MASK  0x07     /* optional gap size to leave in buffer */
  408 
  409 /*
  410  * Special transmit command register (STCR) bits.
  411  */
  412 #define STC_ABORTTX   0x40      /* abort transmission (HDLC mode) */
  413 #define STC_APPDCMP   0x20      /* append complete (async DMA mode) */
  414 #define STC_SNDSPC    0x08      /* send special characters (async mode) */
  415 #define STC_SSPC_MASK 0x07      /* special character select */
  416 #define STC_SSPC_1    0x01      /* send special character #1 */
  417 #define STC_SSPC_2    0x02      /* send special character #2 */
  418 #define STC_SSPC_3    0x03      /* send special character #3 */
  419 #define STC_SSPC_4    0x04      /* send special character #4 */
  420 
  421 /*
  422  * Channel status register (CSR) bits, asynchronous mode.
  423  */
  424 #define CSRA_RXEN    0x80       /* receiver enable */
  425 #define CSRA_RXFLOFF 0x40       /* receiver flow off */
  426 #define CSRA_RXFLON  0x20       /* receiver flow on */
  427 #define CSRA_TXEN    0x08       /* transmitter enable */
  428 #define CSRA_TXFLOFF 0x04       /* transmitter flow off */
  429 #define CSRA_TXFLON  0x02       /* transmitter flow on */
  430 #define CSRA_BITS "\2\2txflon\3txfloff\4txen\6rxflon\7rxfloff\10rxen"

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