FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/ic/lemac.h
1 /*
2 * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com)
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software without specific prior written permission
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * $FreeBSD: releng/5.1/sys/i386/isa/ic/lemac.h 97748 2002-06-02 20:05:59Z schweikh $
25 */
26 #ifndef _LEMAC_H_
27 #define _LEMAC_H_
28
29 /*
30 * This is list of registers used on a DEC EtherWORKS III card.
31 * Each board occupies a 32 byte register space. This can be
32 * in either EISA or ISA space. Currently we only support ISA
33 * space.
34 */
35
36 #define LEMAC_REG_CS 0x00 /* Control and Status */
37 #define LEMAC_REG_CTL 0x01 /* Control */
38 #define LEMAC_REG_IC 0x02 /* Interrupt Control */
39 #define LEMAC_REG_TS 0x03 /* Transmit Status */
40 #define LEMAC_REG_RSVD1 0x04 /* Reserved (not used) */
41 #define LEMAC_REG_RSVD2 0x05 /* Reserved (not used) */
42 #define LEMAC_REG_FMQ 0x06 /* Free Memory Queue */
43 #define LEMAC_REG_FMC 0x07 /* Free Memory Queue Count */
44 #define LEMAC_REG_RQ 0x08 /* Receive Queue */
45 #define LEMAC_REG_RQC 0x09 /* Receive Queue Count */
46 #define LEMAC_REG_TQ 0x0A /* Transmit Queue */
47 #define LEMAC_REG_TQC 0x0B /* Transmit Queue Count */
48 #define LEMAC_REG_TDQ 0x0C /* Transmit Done Queue */
49 #define LEMAC_REG_TDC 0x0D /* Transmit Done Queue Count */
50 #define LEMAC_REG_PI1 0x0E /* Page Index #1 */
51 #define LEMAC_REG_PI2 0x0F /* Page Index #2 */
52 #define LEMAC_REG_DAT 0x10 /* Data */
53 #define LEMAC_REG_IOP 0x11 /* I/O Page */
54 #define LEMAC_REG_IOB 0x12 /* I/O Base */
55 #define LEMAC_REG_MPN 0x13 /* Memory Page */
56 #define LEMAC_REG_MBR 0x14 /* Memory Base */
57 #define LEMAC_REG_APD 0x15 /* Address PROM */
58 #define LEMAC_REG_EE1 0x16 /* EEPROM Data #1 */
59 #define LEMAC_REG_EE2 0x17 /* EEPROM Data #2 */
60 #define LEMAC_REG_PA0 0x18 /* Physical Address (Byte 0) */
61 #define LEMAC_REG_PA1 0x19 /* Physical Address (Byte 1) */
62 #define LEMAC_REG_PA2 0x1A /* Physical Address (Byte 2) */
63 #define LEMAC_REG_PA3 0x1B /* Physical Address (Byte 3) */
64 #define LEMAC_REG_PA4 0x1C /* Physical Address (Byte 4) */
65 #define LEMAC_REG_PA5 0x1D /* Physical Address (Byte 5) */
66 #define LEMAC_REG_CNF 0x1E /* Configuration Management */
67 #define LEMAC_IOSPACE 0x20 /* LEMAC uses 32 bytes of IOSPACE */
68
69
70 #define LEMAC_REG_EID0 0x80 /* EISA Identification 0 */
71 #define LEMAC_REG_EID1 0x81 /* EISA Identification 1 */
72 #define LEMAC_REG_EID2 0x82 /* EISA Identification 2 */
73 #define LEMAC_REG_EID3 0x83 /* EISA Identification 3 */
74 #define LEMAC_REG_EIC 0x84 /* EISA Control */
75
76 /* Control Page (Page 0) Definitions */
77
78 #define LEMAC_MCTBL_BITS 9
79 #define LEMAC_MCTBL_OFF 512
80 #define LEMAC_MCTBL_SIZE (1 << (LEMAC_MCTBL_BITS - 3))
81 #define LEMAC_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian) */
82
83 /* EEPROM Definitions */
84
85 #define LEMAC_EEP_CKSUM 0 /* The valid checksum is 0 */
86 #define LEMAC_EEP_SIZE 32 /* EEPROM is 32 bytes */
87 #define LEMAC_EEP_DELAY 2000 /* 2ms = 2000us */
88 #define LEMAC_EEP_PRDNM 8 /* Product Name Offset */
89 #define LEMAC_EEP_PRDNMSZ 8 /* Product Name Size */
90 #define LEMAC_EEP_SWFLAGS 16 /* Software Options Offset */
91 #define LEMAC_EEP_SETUP 23 /* Setup Options Offset */
92
93 #define LEMAC_EEP_SW_SQE 0x10 /* Enable TX_SQE on Transmits */
94 #define LEMAC_EEP_SW_LAB 0x08 /* Enable TX_LAB on Transmits */
95 #define LEMAC_EEP_ST_DRAM 0x02 /* Enable extra DRAM */
96
97 #define LEMAC_ADP_ROMSZ 32 /* Size of Address PROM */
98
99 /* Receive Status Definitions */
100
101 #define LEMAC_RX_PLL 0x01 /* Phase Lock Lost */
102 #define LEMAC_RX_CRC 0x02 /* CRC Error */
103 #define LEMAC_RX_DBE 0x04 /* Dribble Bit Error */
104 #define LEMAC_RX_MCM 0x08 /* Multicast Match */
105 #define LEMAC_RX_IAM 0x10 /* Individual Address Match */
106 #define LEMAC_RX_OK 0x80 /* No Errors */
107
108 /* Transmit Status Definitions (not valid if TXD == 0) */
109
110 #define LEMAC_TS_RTRYMSK 0x0F /* Retries of last TX PDU */
111 #define LEMAC_TS_ECL 0x10 /* Excessive collision of ... */
112 #define LEMAC_TS_LCL 0x20 /* Late collision of ... */
113 #define LEMAC_TS_ID 0x40 /* Initially Deferred ... */
114
115 /* Transmit Control Definitions */
116
117 #define LEMAC_TX_ISA 0x01 /* Insert Source Address (no) */
118 #define LEMAC_TX_IFC 0x02 /* Insert Frame Check (yes) */
119 #define LEMAC_TX_PAD 0x04 /* Zero PAD to mininum length (yes) */
120 #define LEMAC_TX_LAB 0x08 /* Less Agressive Backoff (no) */
121 #define LEMAC_TX_QMD 0x10 /* Q-Mode (yes) */
122 #define LEMAC_TX_STP 0x20 /* Stop on Error (yes) */
123 #define LEMAC_TX_SQE 0x40 /* SQE Enable (yes) */
124
125 #define LEMAC_TX_FLAGS (LEMAC_TX_IFC|LEMAC_TX_PAD|LEMAC_TX_QMD|\
126 LEMAC_TX_STP|LEMAC_TX_SQE)
127 #define LEMAC_TX_HDRSZ 4 /* Size of TX header */
128
129 /* Transmit Done Queue Status Definitions */
130
131 #define LEMAC_TDQ_COL 0x03 /* Collision Mask */
132 #define LEMAC_TDQ_NOCOL 0x00 /* No Collisions */
133 #define LEMAC_TDQ_ONECOL 0x01 /* One Collision */
134 #define LEMAC_TDQ_MULCOL 0x02 /* Multiple Collisions */
135 #define LEMAC_TDQ_EXCCOL 0x03 /* Excesive Collisions */
136 #define LEMAC_TDQ_ID 0x04 /* Initially Deferred */
137 #define LEMAC_TDQ_LCL 0x08 /* Late Collision (will TX_STP) */
138
139 /* Control / Status Definitions */
140
141 #define LEMAC_CS_RXD 0x01 /* Receiver Disabled */
142 #define LEMAC_CS_TXD 0x02 /* Transmitter Disabled */
143 #define LEMAC_CS_RNE 0x04 /* Receive Queue Not Empty */
144 #define LEMAC_CS_TNE 0x08 /* Transmit Done Queue Not Empty */
145 #define LEMAC_CS_MBZ4 0x10 /* MBZ */
146 #define LEMAC_CS_MCE 0x20 /* Multicast Enable */
147 #define LEMAC_CS_PME 0x40 /* Promiscuous Mode Enable */
148 #define LEMAC_CS_RA 0x80 /* Runt Accept */
149
150 /* Control Definitions */
151
152 #define LEMAC_CTL_LED 0x02 /* LED state (inverted) */
153
154 /* Interrupt Control Definitions */
155
156 #define LEMAC_IC_RXD 0x01 /* Enable RXD Interrupt */
157 #define LEMAC_IC_TXD 0x02 /* Enable TXD Interrupt */
158 #define LEMAC_IC_RNE 0x04 /* Enable RNE Interrupt */
159 #define LEMAC_IC_TNE 0x08 /* Enable TNE Interrupt */
160 #define LEMAC_IC_ALL 0x0F /* Enable RXD,TXD,RNE,TNE */
161 #define LEMAC_IC_IRQMSK 0x60 /* Interrupt Select */
162 #define LEMAC_IC_IRQ5 0x00 /* Select IRQ 5 */
163 #define LEMAC_IC_IRQ10 0x20 /* Select IRQ 10 */
164 #define LEMAC_IC_IRQ11 0x40 /* Select IRQ 11 */
165 #define LEMAC_IC_IRQ15 0x60 /* Select IRQ 15 */
166 #define LEMAC_IC_IE 0x80 /* Interrupt Enable */
167
168 /* I/O Page Definitions */
169
170 #define LEMAC_IOP_EEINIT 0xC0 /* Perform a board init/reset */
171 #define LEMAC_IOP_EEREAD 0xE0 /* Start a read from EEPROM */
172
173 /* Configuration / Management Definitions */
174
175 #define LEMAC_CNF_DRAM 0x02 /* Extra on-board DRAM is available */
176
177 #endif /* _LEMAC_H_ */
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