FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/icu.h
1 /*-
2 * Copyright (c) 1990 The Regents of the University of California.
3 * All rights reserved.
4 *
5 * This code is derived from software contributed to Berkeley by
6 * William Jolitz.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by the University of
19 * California, Berkeley and its contributors.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: @(#)icu.h 5.6 (Berkeley) 5/9/91
37 * $FreeBSD: releng/5.2/sys/i386/isa/icu.h 122691 2003-11-14 19:12:25Z jhb $
38 */
39
40 /*
41 * AT/386 Interrupt Control constants
42 * W. Jolitz 8/89
43 */
44
45 #ifndef _I386_ISA_ICU_H_
46 #define _I386_ISA_ICU_H_
47
48 /*
49 * Interrupt enable bits - in normal order of priority (which we change)
50 */
51 #ifdef PC98
52 #define IRQ0 0x0001
53 #define IRQ1 0x0002
54 #define IRQ2 0x0004
55 #define IRQ3 0x0008
56 #define IRQ4 0x0010
57 #define IRQ5 0x0020
58 #define IRQ6 0x0040
59 #define IRQ7 0x0080
60 #define IRQ_SLAVE 0x0080
61 #define IRQ8 0x0100
62 #define IRQ9 0x0200
63 #define IRQ10 0x0400
64 #define IRQ11 0x0800
65 #define IRQ12 0x1000
66 #define IRQ13 0x2000
67 #define IRQ14 0x4000
68 #define IRQ15 0x8000
69 #else
70 #define IRQ0 0x0001 /* highest priority - timer */
71 #define IRQ1 0x0002
72 #define IRQ_SLAVE 0x0004
73 #define IRQ8 0x0100
74 #define IRQ9 0x0200
75 #define IRQ2 IRQ9
76 #define IRQ10 0x0400
77 #define IRQ11 0x0800
78 #define IRQ12 0x1000
79 #define IRQ13 0x2000
80 #define IRQ14 0x4000
81 #define IRQ15 0x8000
82 #define IRQ3 0x0008 /* this is highest after rotation */
83 #define IRQ4 0x0010
84 #define IRQ5 0x0020
85 #define IRQ6 0x0040
86 #define IRQ7 0x0080 /* lowest - parallel printer */
87 #endif
88
89 /* Initialization control word 1. Written to even address. */
90 #define ICW1_IC4 0x01 /* ICW4 present */
91 #define ICW1_SNGL 0x02 /* 1 = single, 0 = cascaded */
92 #define ICW1_ADI 0x04 /* 1 = 4, 0 = 8 byte vectors */
93 #define ICW1_LTIM 0x08 /* 1 = level trigger, 0 = edge */
94 #define ICW1_RESET 0x10 /* must be 1 */
95 /* 0x20 - 0x80 - in 8080/8085 mode only */
96
97 /* Initialization control word 2. Written to the odd address. */
98 /* No definitions, it is the base vector of the IDT for 8086 mode */
99
100 /* Initialization control word 3. Written to the odd address. */
101 /* For a master PIC, bitfield indicating a slave 8259 on given input */
102 /* For slave, lower 3 bits are the slave's ID binary id on master */
103
104 #ifdef PC98
105 /* XXX: missing pc98 bits */
106 #else
107
108 /* Initialization control word 4. Written to the odd address. */
109 #define ICW4_8086 0x01 /* 1 = 8086, 0 = 8080 */
110 #define ICW4_AEOI 0x02 /* 1 = Auto EOI */
111 #define ICW4_MS 0x04 /* 1 = buffered master, 0 = slave */
112 #define ICW4_BUF 0x08 /* 1 = enable buffer mode */
113 #define ICW4_SFNM 0x10 /* 1 = special fully nested mode */
114
115 #endif
116
117 /* Operation control words. Written after initialization. */
118
119 /* Operation control word type 1 */
120 /*
121 * No definitions. Written to the odd address. Bitmask for interrupts.
122 * 1 = disabled.
123 */
124
125 /* Operation control word type 2. Bit 3 (0x08) must be zero. Even address. */
126 #define OCW2_L0 0x01 /* Level */
127 #define OCW2_L1 0x02
128 #define OCW2_L2 0x04
129 /* 0x08 must be 0 to select OCW2 vs OCW3 */
130 /* 0x10 must be 0 to select OCW2 vs ICW1 */
131 #define OCW2_EOI 0x20 /* 1 = EOI */
132 #define OCW2_SL 0x40 /* EOI mode */
133 #define OCW2_R 0x80 /* EOI mode */
134
135 /* Operation control word type 3. Bit 3 (0x08) must be set. Even address. */
136 #define OCW3_RIS 0x01 /* 1 = read IS, 0 = read IR */
137 #define OCW3_RR 0x02 /* register read */
138 #define OCW3_P 0x04 /* poll mode command */
139 /* 0x08 must be 1 to select OCW3 vs OCW2 */
140 #define OCW3_SEL 0x08 /* must be 1 */
141 /* 0x10 must be 0 to select OCW3 vs ICW1 */
142 #define OCW3_SMM 0x20 /* special mode mask */
143 #define OCW3_ESMM 0x40 /* enable SMM */
144
145 /*
146 * Interrupt Control offset into Interrupt descriptor table (IDT)
147 */
148 #define ICU_OFFSET 32 /* 0-31 are processor exceptions */
149 #define ICU_LEN 16 /* 32-47 are ISA interrupts */
150
151 #ifdef PC98
152 #define ICU_IMR_OFFSET 2
153 #define ICU_SLAVEID 7
154 #else
155 #define ICU_IMR_OFFSET 1
156 #define ICU_SLAVEID 2
157 #endif
158
159 #define ICU_EOI (OCW2_EOI) /* non-specific EOI */
160
161 #ifndef LOCORE
162 void atpic_handle_intr(struct intrframe iframe);
163 void atpic_startup(void);
164 #endif
165
166 #endif /* !_I386_ISA_ICU_H_ */
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