1 /*
2 * Copyright (c) 1995 John Hay. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * 3. All advertising materials mentioning features or use of this software
13 * must display the following acknowledgement:
14 * This product includes software developed by [your name]
15 * and [any other names deserving credit ]
16 * 4. Neither the name of the author nor the names of any co-contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY [your name] AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * $FreeBSD$
33 */
34 #ifndef _IF_ARREGS_H_
35 #define _IF_ARREGS_H_
36
37 #define NCHAN 2 /* A HD64570 chip have 2 channels */
38 #define NPORT 4 /* A ArNet board can have 4 ports or */
39 /* channels */
40
41 #define AR_BUF_SIZ 512
42 #define AR_TX_BLOCKS 2
43 #define ARC_IO_SIZ 0x10
44 #define ARC_WIN_SIZ 0x00004000
45 #define ARC_WIN_MSK (ARC_WIN_SIZ - 1)
46 #define ARC_WIN_SHFT 14
47
48 #define AR_ID_5 0x00 /* RO, Card probe '5' */
49 #define AR_ID_7 0x01 /* RO, Card probe '7' */
50 #define AR_ID_0 0x02 /* RO, Card probe '' */
51 #define AR_BMI 0x03 /* RO, Bus, mem and interface type */
52 #define AR_REV 0x04 /* RO, Adapter revision */
53 #define AR_PNUM 0x05 /* RO, Port number */
54 #define AR_HNDSH 0x06 /* RO, Supported handshake */
55 #define AR_ISTAT 0x07 /* RO, DCD and Interrupt status */
56 #define AR_MSCA_EN 0x08 /* WO, Memory and SCA enable */
57 #define AR_TXC_DTR0 0x09 /* WO, Tx Clock and DTR control 0 + 1 */
58 #define AR_SEC_PAL 0x0A /* RW, Security PAL */
59 #define AR_INT_ACK0 0x0B /* RO, Interrupt Acknowledge 0 + 1 */
60 #define AR_INT_SEL 0x0C /* RW, Interrupt Select */
61 #define AR_MEM_SEL 0x0D /* RW, Memory Select */
62 #define AR_INT_ACK2 0x0E /* RO, Interrupt Acknowledge 2 + 3 */
63 #define AR_TXC_DTR2 0x0E /* WO, Tx Clock and DTR control 2 + 3 */
64
65 /* Bus memory and interface type */
66 #define AR_BUS_MSK 0x03
67 #define AR_BUS_ISA 0x00
68 #define AR_BUS_MCA 0x01
69 #define AR_BUS_EISA 0x02
70
71 #define AR_MEM_MSK 0x1C
72 #define AR_MEM_SHFT 0x02
73 #define AR_MEM_64K 0x00
74 #define AR_MEM_128K 0x04
75 #define AR_MEM_256K 0x08
76 #define AR_MEM_512K 0x0C
77
78 /*
79 * EIA-232
80 * V.35/EIA-232
81 * EIA-530
82 * X.21
83 * EIA-530/X.21 Combo
84 */
85 #define AR_IFACE_MSK 0xE0
86 #define AR_IFACE_SHFT 0x05
87 #define AR_IFACE_EIA_232 0x00 /* Only on the 570 card, not 570i */
88 #define AR_IFACE_V_35 0x20 /* Selectable between V.35 and EIA-232 */
89 #define AR_IFACE_EIA_530 0x40
90 #define AR_IFACE_X_21 0x60
91 #define AR_IFACE_COMBO 0xC0 /* X.21 / EIA-530 */
92
93 /* Supported Handshake signals */
94 #define AR_SHSK_DTR 0x01
95 #define AR_SHSK_RTS 0x02
96 #define AR_SHSK_CTS 0x10
97 #define AR_SHSK_DSR 0x20
98 #define AR_SHSK_RI 0x40
99 #define AR_SHSK_DCD 0x80
100
101 /* DCD and Interrupt status */
102 #define AR_BD_INT 0x01
103 #define AR_INT_0 0x20
104 #define AR_INT_1 0x40
105
106 #define AR_DCD_MSK 0x1E
107 #define AR_DCD_SHFT 0x01
108 #define AR_DCD_0 0x02
109 #define AR_DCD_1 0x04
110 #define AR_DCD_2 0x08
111 #define AR_DCD_3 0x10
112
113 /* Memory and SCA enable */
114 #define AR_WIN_MSK 0x1F
115
116 #define AR_SEL_SCA_0 0x00
117 #define AR_SEL_SCA_1 0x20
118 #define AR_ENA_SCA 0x40
119 #define AR_ENA_MEM 0x80
120
121 /* Transmit Clock and DTR and RESET */
122 #define AR_TXC_DTR_TX0 0x01
123 #define AR_TXC_DTR_TX1 0x02
124 #define AR_TXC_DTR_DTR0 0x04
125 #define AR_TXC_DTR_DTR1 0x08
126 #define AR_TXC_DTR_TXCS0 0x10
127 #define AR_TXC_DTR_TXCS1 0x20
128 #define AR_TXC_DTR_NOTRESET 0x40
129 #define AR_TXC_DTR_RESET 0x00
130
131 /* Interrupt select register */
132 #define AR_INTS_CEN 0x01
133 #define AR_INTS_ISEL0 0x02
134 #define AR_INTS_ISEL1 0x04
135 #define AR_INTS_ISEL2 0x08
136 #define AR_INTS_CMA14 0x10
137 #define AR_INTS_CMA15 0x20
138
139 /* Memory select register */
140
141
142 #endif /* _IF_ARREGS_H_ */
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