Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/i386/isa/if_ed.c
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1 /* 2 * Copyright (c) 1995, David Greenman 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 /* 31 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet 32 * adapters. By David Greenman, 29-April-1993 33 * 34 * Currently supports the Western Digital/SMC 8003 and 8013 series, 35 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000, 36 * and a variety of similar clones. 37 * 38 */ 39 40 #include "ed.h" 41 #include "bpfilter.h" 42 #include "pnp.h" 43 44 #ifndef EXTRA_ED 45 # if NPNP > 0 46 # define EXTRA_ED 8 47 # else 48 # define EXTRA_ED 0 49 # endif 50 #endif 51 52 #define NEDTOT (NED + EXTRA_ED) 53 54 #include <sys/param.h> 55 #include <sys/systm.h> 56 #include <sys/sockio.h> 57 #include <sys/malloc.h> 58 #include <sys/mbuf.h> 59 #include <sys/socket.h> 60 #include <sys/syslog.h> 61 62 #include <net/ethernet.h> 63 #include <net/if.h> 64 #include <net/if_arp.h> 65 #include <net/if_dl.h> 66 #include <net/if_mib.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 #include "opt_bdg.h" 72 #ifdef BRIDGE 73 #include <net/bridge.h> 74 #endif 75 76 #include <machine/clock.h> 77 #include <machine/md_var.h> 78 79 #include <i386/isa/isa_device.h> 80 #include <i386/isa/icu.h> 81 #include <i386/isa/if_edreg.h> 82 83 #if NPNP > 0 84 #include <i386/isa/pnp.h> 85 #endif 86 87 /* 88 * ed_softc: per line info and status 89 */ 90 struct ed_softc { 91 struct arpcom arpcom; /* ethernet common */ 92 93 char *type_str; /* pointer to type string */ 94 u_char vendor; /* interface vendor */ 95 u_char type; /* interface type code */ 96 u_char gone; /* HW missing, presumed having a good time */ 97 98 u_short asic_addr; /* ASIC I/O bus address */ 99 u_short nic_addr; /* NIC (DS8390) I/O bus address */ 100 101 /* 102 * The following 'proto' variable is part of a work-around for 8013EBT asics 103 * being write-only. It's sort of a prototype/shadow of the real thing. 104 */ 105 u_char wd_laar_proto; 106 u_char cr_proto; 107 u_char isa16bit; /* width of access to card 0=8 or 1=16 */ 108 int is790; /* set by the probe code if the card is 790 109 * based */ 110 111 /* 112 * HP PC LAN PLUS card support. 113 */ 114 115 u_short hpp_options; /* flags controlling behaviour of the HP card */ 116 u_short hpp_id; /* software revision and other fields */ 117 caddr_t hpp_mem_start; /* Memory-mapped IO register address */ 118 119 caddr_t mem_start; /* NIC memory start address */ 120 caddr_t mem_end; /* NIC memory end address */ 121 u_long mem_size; /* total NIC memory size */ 122 caddr_t mem_ring; /* start of RX ring-buffer (in NIC mem) */ 123 124 u_char mem_shared; /* NIC memory is shared with host */ 125 u_char xmit_busy; /* transmitter is busy */ 126 u_char txb_cnt; /* number of transmit buffers */ 127 u_char txb_inuse; /* number of TX buffers currently in-use */ 128 129 u_char txb_new; /* pointer to where new buffer will be added */ 130 u_char txb_next_tx; /* pointer to next buffer ready to xmit */ 131 u_short txb_len[8]; /* buffered xmit buffer lengths */ 132 u_char tx_page_start; /* first page of TX buffer area */ 133 u_char rec_page_start; /* first page of RX ring-buffer */ 134 u_char rec_page_stop; /* last page of RX ring-buffer */ 135 u_char next_packet; /* pointer to next unread RX packet */ 136 struct ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */ 137 }; 138 139 static struct ed_softc ed_softc[NEDTOT]; 140 141 static int ed_attach __P((struct ed_softc *, int, int)); 142 static int ed_attach_isa __P((struct isa_device *)); 143 144 static void ed_init __P((void *)); 145 static ointhand2_t edintr; 146 static int ed_ioctl __P((struct ifnet *, u_long, caddr_t)); 147 static int ed_probe __P((struct isa_device *)); 148 static void ed_start __P((struct ifnet *)); 149 static void ed_reset __P((struct ifnet *)); 150 static void ed_watchdog __P((struct ifnet *)); 151 152 static void ed_stop __P((struct ed_softc *)); 153 static int ed_probe_generic8390 __P((struct ed_softc *)); 154 static int ed_probe_WD80x3 __P((struct isa_device *)); 155 static int ed_probe_3Com __P((struct isa_device *)); 156 static int ed_probe_Novell __P((struct isa_device *)); 157 static int ed_probe_Novell_generic __P((struct ed_softc *, int, int, int)); 158 static int ed_probe_HP_pclanp __P((struct isa_device *)); 159 160 #include "pci.h" 161 #if NPCI > 0 162 void *ed_attach_NE2000_pci __P((int, int)); 163 #endif 164 165 #include "card.h" 166 #if NCARD > 0 167 static int ed_probe_pccard __P((struct isa_device *, u_char *)); 168 #endif 169 170 static void ds_getmcaf __P((struct ed_softc *, u_long *)); 171 172 static void ed_get_packet __P((struct ed_softc *, char *, /* u_short */ int, int)); 173 174 static __inline void ed_rint __P((struct ed_softc *)); 175 static __inline void ed_xmit __P((struct ed_softc *)); 176 static __inline char * ed_ring_copy __P((struct ed_softc *, char *, char *, 177 /* u_short */ int)); 178 static void ed_hpp_set_physical_link __P((struct ed_softc *)); 179 static void ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *, 180 /* u_short */ int)); 181 static u_short ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *, 182 int)); 183 184 static void ed_pio_readmem __P((struct ed_softc *, int, unsigned char *, 185 /* u_short */ int)); 186 static void ed_pio_writemem __P((struct ed_softc *, char *, 187 /* u_short */ int, /* u_short */ int)); 188 static u_short ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *, 189 int)); 190 void edintr_sc __P((struct ed_softc *)); 191 192 static void ed_setrcr __P((struct ed_softc *)); 193 194 static u_long ds_crc __P((u_char *ep)); 195 196 #if (NCARD > 0) || (NPNP > 0) 197 #include <sys/kernel.h> 198 #endif 199 #if NCARD > 0 200 #include <sys/select.h> 201 #include <sys/module.h> 202 #include <pccard/cardinfo.h> 203 #include <pccard/slot.h> 204 205 /* 206 * PC-Card (PCMCIA) specific code. 207 */ 208 static int edinit __P((struct pccard_devinfo *)); 209 static void edunload __P((struct pccard_devinfo *)); 210 static int card_intr __P((struct pccard_devinfo *)); 211 212 PCCARD_MODULE(ed, edinit, edunload, card_intr, 0, net_imask); 213 214 /* 215 * Initialize the device - called from Slot manager. 216 */ 217 static int 218 edinit(struct pccard_devinfo *devi) 219 { 220 int i; 221 u_char e; 222 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit]; 223 224 /* validate unit number. */ 225 if (devi->isahd.id_unit >= NEDTOT) 226 return(ENODEV); 227 /* 228 * Probe the device. If a value is returned, the 229 * device was found at the location. 230 */ 231 sc->gone = 0; 232 if (ed_probe_pccard(&devi->isahd, devi->misc) == 0) 233 return(ENXIO); 234 e = 0; 235 for (i = 0; i < ETHER_ADDR_LEN; ++i) 236 e |= devi->misc[i]; 237 if (e) 238 for (i = 0; i < ETHER_ADDR_LEN; ++i) 239 sc->arpcom.ac_enaddr[i] = devi->misc[i]; 240 if (ed_attach_isa(&devi->isahd) == 0) 241 return(ENXIO); 242 243 return(0); 244 } 245 246 /* 247 * edunload - unload the driver and clear the table. 248 * XXX TODO: 249 * This is usually called when the card is ejected, but 250 * can be caused by a modunload of a controller driver. 251 * The idea is to reset the driver's view of the device 252 * and ensure that any driver entry points such as 253 * read and write do not hang. 254 */ 255 static void 256 edunload(struct pccard_devinfo *devi) 257 { 258 struct ed_softc *sc = &ed_softc[devi->isahd.id_unit]; 259 struct ifnet *ifp = &sc->arpcom.ac_if; 260 261 if (sc->gone) { 262 printf("ed%d: already unloaded\n", devi->isahd.id_unit); 263 return; 264 } 265 ifp->if_flags &= ~IFF_RUNNING; 266 if_down(ifp); 267 sc->gone = 1; 268 printf("ed%d: unload\n", devi->isahd.id_unit); 269 } 270 271 /* 272 * card_intr - Shared interrupt called from 273 * front end of PC-Card handler. 274 */ 275 static int 276 card_intr(struct pccard_devinfo *devi) 277 { 278 edintr_sc(&ed_softc[devi->isahd.id_unit]); 279 return(1); 280 } 281 #endif /* NCARD > 0 */ 282 283 struct isa_driver eddriver = { 284 ed_probe, 285 ed_attach_isa, 286 "ed", 287 1 /* We are ultra sensitive */ 288 }; 289 290 /* 291 * Interrupt conversion table for WD/SMC ASIC/83C584 292 * (IRQ* are defined in icu.h) 293 */ 294 static unsigned short ed_intr_mask[] = { 295 IRQ9, 296 IRQ3, 297 IRQ5, 298 IRQ7, 299 IRQ10, 300 IRQ11, 301 IRQ15, 302 IRQ4 303 }; 304 305 /* 306 * Interrupt conversion table for 83C790 307 */ 308 static unsigned short ed_790_intr_mask[] = { 309 0, 310 IRQ9, 311 IRQ3, 312 IRQ5, 313 IRQ7, 314 IRQ10, 315 IRQ11, 316 IRQ15 317 }; 318 319 /* 320 * Interrupt conversion table for the HP PC LAN+ 321 */ 322 323 static unsigned short ed_hpp_intr_mask[] = { 324 0, /* 0 */ 325 0, /* 1 */ 326 0, /* 2 */ 327 IRQ3, /* 3 */ 328 IRQ4, /* 4 */ 329 IRQ5, /* 5 */ 330 IRQ6, /* 6 */ 331 IRQ7, /* 7 */ 332 0, /* 8 */ 333 IRQ9, /* 9 */ 334 IRQ10, /* 10 */ 335 IRQ11, /* 11 */ 336 IRQ12, /* 12 */ 337 0, /* 13 */ 338 0, /* 14 */ 339 IRQ15 /* 15 */ 340 }; 341 342 /* 343 * Determine if the device is present 344 * 345 * on entry: 346 * a pointer to an isa_device struct 347 * on exit: 348 * NULL if device not found 349 * or # of i/o addresses used (if found) 350 */ 351 static int 352 ed_probe(isa_dev) 353 struct isa_device *isa_dev; 354 { 355 int nports; 356 357 nports = ed_probe_WD80x3(isa_dev); 358 if (nports) 359 return (nports); 360 361 nports = ed_probe_3Com(isa_dev); 362 if (nports) 363 return (nports); 364 365 nports = ed_probe_Novell(isa_dev); 366 if (nports) 367 return (nports); 368 369 nports = ed_probe_HP_pclanp(isa_dev); 370 if (nports) 371 return (nports); 372 373 return (0); 374 } 375 376 /* 377 * Generic probe routine for testing for the existance of a DS8390. 378 * Must be called after the NIC has just been reset. This routine 379 * works by looking at certain register values that are guaranteed 380 * to be initialized a certain way after power-up or reset. Seems 381 * not to currently work on the 83C690. 382 * 383 * Specifically: 384 * 385 * Register reset bits set bits 386 * Command Register (CR) TXP, STA RD2, STP 387 * Interrupt Status (ISR) RST 388 * Interrupt Mask (IMR) All bits 389 * Data Control (DCR) LAS 390 * Transmit Config. (TCR) LB1, LB0 391 * 392 * We only look at the CR and ISR registers, however, because looking at 393 * the others would require changing register pages (which would be 394 * intrusive if this isn't an 8390). 395 * 396 * Return 1 if 8390 was found, 0 if not. 397 */ 398 399 static int 400 ed_probe_generic8390(sc) 401 struct ed_softc *sc; 402 { 403 if ((inb(sc->nic_addr + ED_P0_CR) & 404 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) != 405 (ED_CR_RD2 | ED_CR_STP)) 406 return (0); 407 if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST) 408 return (0); 409 410 return (1); 411 } 412 413 /* 414 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards 415 */ 416 static int 417 ed_probe_WD80x3(isa_dev) 418 struct isa_device *isa_dev; 419 { 420 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 421 int i; 422 u_int memsize, maddr; 423 u_char iptr, isa16bit, sum; 424 425 sc->asic_addr = isa_dev->id_iobase; 426 sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET; 427 sc->is790 = 0; 428 429 #ifdef TOSH_ETHER 430 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW); 431 DELAY(10000); 432 #endif 433 434 /* 435 * Attempt to do a checksum over the station address PROM. If it 436 * fails, it's probably not a SMC/WD board. There is a problem with 437 * this, though: some clone WD boards don't pass the checksum test. 438 * Danpex boards for one. 439 */ 440 for (sum = 0, i = 0; i < 8; ++i) 441 sum += inb(sc->asic_addr + ED_WD_PROM + i); 442 443 if (sum != ED_WD_ROM_CHECKSUM_TOTAL) { 444 445 /* 446 * Checksum is invalid. This often happens with cheap WD8003E 447 * clones. In this case, the checksum byte (the eighth byte) 448 * seems to always be zero. 449 */ 450 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E || 451 inb(sc->asic_addr + ED_WD_PROM + 7) != 0) 452 return (0); 453 } 454 /* reset card to force it into a known state. */ 455 #ifdef TOSH_ETHER 456 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW); 457 #else 458 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST); 459 #endif 460 DELAY(100); 461 outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST); 462 /* wait in the case this card is reading its EEROM */ 463 DELAY(5000); 464 465 sc->vendor = ED_VENDOR_WD_SMC; 466 sc->type = inb(sc->asic_addr + ED_WD_CARD_ID); 467 468 /* 469 * Set initial values for width/size. 470 */ 471 memsize = 8192; 472 isa16bit = 0; 473 switch (sc->type) { 474 case ED_TYPE_WD8003S: 475 sc->type_str = "WD8003S"; 476 break; 477 case ED_TYPE_WD8003E: 478 sc->type_str = "WD8003E"; 479 break; 480 case ED_TYPE_WD8003EB: 481 sc->type_str = "WD8003EB"; 482 break; 483 case ED_TYPE_WD8003W: 484 sc->type_str = "WD8003W"; 485 break; 486 case ED_TYPE_WD8013EBT: 487 sc->type_str = "WD8013EBT"; 488 memsize = 16384; 489 isa16bit = 1; 490 break; 491 case ED_TYPE_WD8013W: 492 sc->type_str = "WD8013W"; 493 memsize = 16384; 494 isa16bit = 1; 495 break; 496 case ED_TYPE_WD8013EP: /* also WD8003EP */ 497 if (inb(sc->asic_addr + ED_WD_ICR) 498 & ED_WD_ICR_16BIT) { 499 isa16bit = 1; 500 memsize = 16384; 501 sc->type_str = "WD8013EP"; 502 } else { 503 sc->type_str = "WD8003EP"; 504 } 505 break; 506 case ED_TYPE_WD8013WC: 507 sc->type_str = "WD8013WC"; 508 memsize = 16384; 509 isa16bit = 1; 510 break; 511 case ED_TYPE_WD8013EBP: 512 sc->type_str = "WD8013EBP"; 513 memsize = 16384; 514 isa16bit = 1; 515 break; 516 case ED_TYPE_WD8013EPC: 517 sc->type_str = "WD8013EPC"; 518 memsize = 16384; 519 isa16bit = 1; 520 break; 521 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */ 522 case ED_TYPE_SMC8216T: 523 if (sc->type == ED_TYPE_SMC8216C) { 524 sc->type_str = "SMC8216/SMC8216C"; 525 } else { 526 sc->type_str = "SMC8216T"; 527 } 528 529 outb(sc->asic_addr + ED_WD790_HWR, 530 inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH); 531 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) { 532 case ED_WD790_RAR_SZ64: 533 memsize = 65536; 534 break; 535 case ED_WD790_RAR_SZ32: 536 memsize = 32768; 537 break; 538 case ED_WD790_RAR_SZ16: 539 memsize = 16384; 540 break; 541 case ED_WD790_RAR_SZ8: 542 /* 8216 has 16K shared mem -- 8416 has 8K */ 543 if (sc->type == ED_TYPE_SMC8216C) { 544 sc->type_str = "SMC8416C/SMC8416BT"; 545 } else { 546 sc->type_str = "SMC8416T"; 547 } 548 memsize = 8192; 549 break; 550 } 551 outb(sc->asic_addr + ED_WD790_HWR, 552 inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 553 554 isa16bit = 1; 555 sc->is790 = 1; 556 break; 557 #ifdef TOSH_ETHER 558 case ED_TYPE_TOSHIBA1: 559 sc->type_str = "Toshiba1"; 560 memsize = 32768; 561 isa16bit = 1; 562 break; 563 case ED_TYPE_TOSHIBA4: 564 sc->type_str = "Toshiba4"; 565 memsize = 32768; 566 isa16bit = 1; 567 break; 568 #endif 569 default: 570 sc->type_str = ""; 571 break; 572 } 573 574 /* 575 * Make some adjustments to initial values depending on what is found 576 * in the ICR. 577 */ 578 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT) 579 #ifdef TOSH_ETHER 580 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4) 581 #endif 582 && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) { 583 isa16bit = 0; 584 memsize = 8192; 585 } 586 587 #if ED_DEBUG 588 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n", 589 sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize); 590 for (i = 0; i < 8; i++) 591 printf("%x -> %x\n", i, inb(sc->asic_addr + i)); 592 #endif 593 594 /* 595 * Allow the user to override the autoconfiguration 596 */ 597 if (isa_dev->id_msize) 598 memsize = isa_dev->id_msize; 599 600 maddr = (u_int) isa_dev->id_maddr & 0xffffff; 601 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) { 602 printf("ed%d: Invalid ISA memory address range configured: 0x%x - 0x%x\n", 603 isa_dev->id_unit, maddr, maddr + memsize); 604 return 0; 605 } 606 607 /* 608 * (note that if the user specifies both of the following flags that 609 * '8bit' mode intentionally has precedence) 610 */ 611 if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE) 612 isa16bit = 1; 613 if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE) 614 isa16bit = 0; 615 616 /* 617 * If possible, get the assigned interrupt number from the card and 618 * use it. 619 */ 620 if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) { 621 622 /* 623 * Assemble together the encoded interrupt number. 624 */ 625 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) | 626 ((inb(isa_dev->id_iobase + ED_WD_IRR) & 627 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5); 628 629 /* 630 * If no interrupt specified (or "?"), use what the board tells us. 631 */ 632 if (isa_dev->id_irq <= 0) 633 isa_dev->id_irq = ed_intr_mask[iptr]; 634 635 /* 636 * Enable the interrupt. 637 */ 638 outb(isa_dev->id_iobase + ED_WD_IRR, 639 inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN); 640 } 641 if (sc->is790) { 642 outb(isa_dev->id_iobase + ED_WD790_HWR, 643 inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH); 644 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) | 645 (inb(isa_dev->id_iobase + ED_WD790_GCR) & 646 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2); 647 outb(isa_dev->id_iobase + ED_WD790_HWR, 648 inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH); 649 650 /* 651 * If no interrupt specified (or "?"), use what the board tells us. 652 */ 653 if (isa_dev->id_irq <= 0) 654 isa_dev->id_irq = ed_790_intr_mask[iptr]; 655 656 /* 657 * Enable interrupts. 658 */ 659 outb(isa_dev->id_iobase + ED_WD790_ICR, 660 inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL); 661 } 662 if (isa_dev->id_irq <= 0) { 663 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n", 664 isa_dev->id_unit, sc->type_str); 665 return (0); 666 } 667 sc->isa16bit = isa16bit; 668 sc->mem_shared = 1; 669 isa_dev->id_msize = memsize; 670 sc->mem_start = (caddr_t) isa_dev->id_maddr; 671 672 /* 673 * allocate one xmit buffer if < 16k, two buffers otherwise 674 */ 675 if ((memsize < 16384) || 676 (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) { 677 sc->txb_cnt = 1; 678 } else { 679 sc->txb_cnt = 2; 680 } 681 sc->tx_page_start = ED_WD_PAGE_OFFSET; 682 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt; 683 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE; 684 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start); 685 sc->mem_size = memsize; 686 sc->mem_end = sc->mem_start + memsize; 687 688 /* 689 * Get station address from on-board ROM 690 */ 691 for (i = 0; i < ETHER_ADDR_LEN; ++i) 692 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i); 693 694 /* 695 * Set upper address bits and 8/16 bit access to shared memory. 696 */ 697 if (isa16bit) { 698 if (sc->is790) { 699 sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR); 700 } else { 701 sc->wd_laar_proto = ED_WD_LAAR_L16EN | 702 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI); 703 } 704 /* 705 * Enable 16bit access 706 */ 707 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto | 708 ED_WD_LAAR_M16EN); 709 } else { 710 if (((sc->type & ED_WD_SOFTCONFIG) || 711 #ifdef TOSH_ETHER 712 (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) || 713 #endif 714 (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) { 715 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) & 716 ED_WD_LAAR_ADDRHI; 717 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto); 718 } 719 } 720 721 /* 722 * Set address and enable interface shared memory. 723 */ 724 if (!sc->is790) { 725 #ifdef TOSH_ETHER 726 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4); 727 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f)); 728 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW); 729 730 #else 731 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) & 732 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB); 733 #endif 734 sc->cr_proto = ED_CR_RD2; 735 } else { 736 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 737 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH)); 738 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) | 739 ((kvtop(sc->mem_start) >> 11) & 0x40) | 740 (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0)); 741 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH)); 742 sc->cr_proto = 0; 743 } 744 745 #if 0 746 printf("starting memory performance test at 0x%x, size %d...\n", 747 sc->mem_start, memsize*16384); 748 for (i = 0; i < 16384; i++) 749 bzero(sc->mem_start, memsize); 750 printf("***DONE***\n"); 751 #endif 752 753 /* 754 * Now zero memory and verify that it is clear 755 */ 756 bzero(sc->mem_start, memsize); 757 758 for (i = 0; i < memsize; ++i) { 759 if (sc->mem_start[i]) { 760 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 761 isa_dev->id_unit, kvtop(sc->mem_start + i)); 762 763 /* 764 * Disable 16 bit access to shared memory 765 */ 766 if (isa16bit) { 767 if (sc->is790) { 768 outb(sc->asic_addr + ED_WD_MSR, 0x00); 769 } 770 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 771 ~ED_WD_LAAR_M16EN); 772 } 773 return (0); 774 } 775 } 776 777 /* 778 * Disable 16bit access to shared memory - we leave it 779 * disabled so that 1) machines reboot properly when the board 780 * is set 16 bit mode and there are conflicting 8bit 781 * devices/ROMS in the same 128k address space as this boards 782 * shared memory. and 2) so that other 8 bit devices with 783 * shared memory can be used in this 128k region, too. 784 */ 785 if (isa16bit) { 786 if (sc->is790) { 787 outb(sc->asic_addr + ED_WD_MSR, 0x00); 788 } 789 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto & 790 ~ED_WD_LAAR_M16EN); 791 } 792 return (ED_WD_IO_PORTS); 793 } 794 795 /* 796 * Probe and vendor-specific initialization routine for 3Com 3c503 boards 797 */ 798 static int 799 ed_probe_3Com(isa_dev) 800 struct isa_device *isa_dev; 801 { 802 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 803 int i; 804 u_int memsize; 805 u_char isa16bit; 806 807 sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET; 808 sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET; 809 810 /* 811 * Verify that the kernel configured I/O address matches the board 812 * configured address 813 */ 814 switch (inb(sc->asic_addr + ED_3COM_BCFR)) { 815 case ED_3COM_BCFR_300: 816 if (isa_dev->id_iobase != 0x300) 817 return (0); 818 break; 819 case ED_3COM_BCFR_310: 820 if (isa_dev->id_iobase != 0x310) 821 return (0); 822 break; 823 case ED_3COM_BCFR_330: 824 if (isa_dev->id_iobase != 0x330) 825 return (0); 826 break; 827 case ED_3COM_BCFR_350: 828 if (isa_dev->id_iobase != 0x350) 829 return (0); 830 break; 831 case ED_3COM_BCFR_250: 832 if (isa_dev->id_iobase != 0x250) 833 return (0); 834 break; 835 case ED_3COM_BCFR_280: 836 if (isa_dev->id_iobase != 0x280) 837 return (0); 838 break; 839 case ED_3COM_BCFR_2A0: 840 if (isa_dev->id_iobase != 0x2a0) 841 return (0); 842 break; 843 case ED_3COM_BCFR_2E0: 844 if (isa_dev->id_iobase != 0x2e0) 845 return (0); 846 break; 847 default: 848 return (0); 849 } 850 851 /* 852 * Verify that the kernel shared memory address matches the board 853 * configured address. 854 */ 855 switch (inb(sc->asic_addr + ED_3COM_PCFR)) { 856 case ED_3COM_PCFR_DC000: 857 if (kvtop(isa_dev->id_maddr) != 0xdc000) 858 return (0); 859 break; 860 case ED_3COM_PCFR_D8000: 861 if (kvtop(isa_dev->id_maddr) != 0xd8000) 862 return (0); 863 break; 864 case ED_3COM_PCFR_CC000: 865 if (kvtop(isa_dev->id_maddr) != 0xcc000) 866 return (0); 867 break; 868 case ED_3COM_PCFR_C8000: 869 if (kvtop(isa_dev->id_maddr) != 0xc8000) 870 return (0); 871 break; 872 default: 873 return (0); 874 } 875 876 877 /* 878 * Reset NIC and ASIC. Enable on-board transceiver throughout reset 879 * sequence because it'll lock up if the cable isn't connected if we 880 * don't. 881 */ 882 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL); 883 884 /* 885 * Wait for a while, then un-reset it 886 */ 887 DELAY(50); 888 889 /* 890 * The 3Com ASIC defaults to rather strange settings for the CR after 891 * a reset - it's important to set it again after the following outb 892 * (this is done when we map the PROM below). 893 */ 894 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 895 896 /* 897 * Wait a bit for the NIC to recover from the reset 898 */ 899 DELAY(5000); 900 901 sc->vendor = ED_VENDOR_3COM; 902 sc->type_str = "3c503"; 903 sc->mem_shared = 1; 904 sc->cr_proto = ED_CR_RD2; 905 906 /* 907 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window 908 * to it. 909 */ 910 memsize = 8192; 911 912 /* 913 * Get station address from on-board ROM 914 */ 915 916 /* 917 * First, map ethernet address PROM over the top of where the NIC 918 * registers normally appear. 919 */ 920 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL); 921 922 for (i = 0; i < ETHER_ADDR_LEN; ++i) 923 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i); 924 925 /* 926 * Unmap PROM - select NIC registers. The proper setting of the 927 * tranceiver is set in ed_init so that the attach code is given a 928 * chance to set the default based on a compile-time config option 929 */ 930 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 931 932 /* 933 * Determine if this is an 8bit or 16bit board 934 */ 935 936 /* 937 * select page 0 registers 938 */ 939 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 940 941 /* 942 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit 943 * board. 944 */ 945 outb(sc->nic_addr + ED_P0_DCR, 0); 946 947 /* 948 * select page 2 registers 949 */ 950 outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP); 951 952 /* 953 * The 3c503 forces the WTS bit to a one if this is a 16bit board 954 */ 955 if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS) 956 isa16bit = 1; 957 else 958 isa16bit = 0; 959 960 /* 961 * select page 0 registers 962 */ 963 outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP); 964 965 sc->mem_start = (caddr_t) isa_dev->id_maddr; 966 sc->mem_size = memsize; 967 sc->mem_end = sc->mem_start + memsize; 968 969 /* 970 * We have an entire 8k window to put the transmit buffers on the 971 * 16bit boards. But since the 16bit 3c503's shared memory is only 972 * fast enough to overlap the loading of one full-size packet, trying 973 * to load more than 2 buffers can actually leave the transmitter idle 974 * during the load. So 2 seems the best value. (Although a mix of 975 * variable-sized packets might change this assumption. Nonetheless, 976 * we optimize for linear transfers of same-size packets.) 977 */ 978 if (isa16bit) { 979 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 980 sc->txb_cnt = 1; 981 else 982 sc->txb_cnt = 2; 983 984 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT; 985 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT; 986 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 987 ED_3COM_RX_PAGE_OFFSET_16BIT; 988 sc->mem_ring = sc->mem_start; 989 } else { 990 sc->txb_cnt = 1; 991 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT; 992 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT; 993 sc->rec_page_stop = memsize / ED_PAGE_SIZE + 994 ED_3COM_TX_PAGE_OFFSET_8BIT; 995 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE); 996 } 997 998 sc->isa16bit = isa16bit; 999 1000 /* 1001 * Initialize GA page start/stop registers. Probably only needed if 1002 * doing DMA, but what the hell. 1003 */ 1004 outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start); 1005 outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop); 1006 1007 /* 1008 * Set IRQ. 3c503 only allows a choice of irq 2-5. 1009 */ 1010 switch (isa_dev->id_irq) { 1011 case IRQ2: 1012 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2); 1013 break; 1014 case IRQ3: 1015 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3); 1016 break; 1017 case IRQ4: 1018 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4); 1019 break; 1020 case IRQ5: 1021 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5); 1022 break; 1023 default: 1024 printf("ed%d: Invalid irq configuration (%d) must be 3-5,9 for 3c503\n", 1025 isa_dev->id_unit, ffs(isa_dev->id_irq) - 1); 1026 return (0); 1027 } 1028 1029 /* 1030 * Initialize GA configuration register. Set bank and enable shared 1031 * mem. 1032 */ 1033 outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL | 1034 ED_3COM_GACFR_MBS0); 1035 1036 /* 1037 * Initialize "Vector Pointer" registers. These gawd-awful things are 1038 * compared to 20 bits of the address on ISA, and if they match, the 1039 * shared memory is disabled. We set them to 0xffff0...allegedly the 1040 * reset vector. 1041 */ 1042 outb(sc->asic_addr + ED_3COM_VPTR2, 0xff); 1043 outb(sc->asic_addr + ED_3COM_VPTR1, 0xff); 1044 outb(sc->asic_addr + ED_3COM_VPTR0, 0x00); 1045 1046 /* 1047 * Zero memory and verify that it is clear 1048 */ 1049 bzero(sc->mem_start, memsize); 1050 1051 for (i = 0; i < memsize; ++i) 1052 if (sc->mem_start[i]) { 1053 printf("ed%d: failed to clear shared memory at %lx - check configuration\n", 1054 isa_dev->id_unit, kvtop(sc->mem_start + i)); 1055 return (0); 1056 } 1057 isa_dev->id_msize = memsize; 1058 return (ED_3COM_IO_PORTS); 1059 } 1060 1061 /* 1062 * Probe and vendor-specific initialization routine for NE1000/2000 boards 1063 */ 1064 static int 1065 ed_probe_Novell_generic(sc, port, unit, flags) 1066 struct ed_softc *sc; 1067 int port; 1068 int unit; 1069 int flags; 1070 { 1071 u_int memsize, n; 1072 u_char romdata[16], tmp; 1073 static char test_pattern[32] = "THIS is A memory TEST pattern"; 1074 char test_buffer[32]; 1075 1076 sc->asic_addr = port + ED_NOVELL_ASIC_OFFSET; 1077 sc->nic_addr = port + ED_NOVELL_NIC_OFFSET; 1078 1079 /* XXX - do Novell-specific probe here */ 1080 1081 /* Reset the board */ 1082 #ifdef GWETHER 1083 outb(sc->asic_addr + ED_NOVELL_RESET, 0); 1084 DELAY(200); 1085 #endif /* GWETHER */ 1086 tmp = inb(sc->asic_addr + ED_NOVELL_RESET); 1087 1088 /* 1089 * I don't know if this is necessary; probably cruft leftover from 1090 * Clarkson packet driver code. Doesn't do a thing on the boards I've 1091 * tested. -DG [note that a outb(0x84, 0) seems to work here, and is 1092 * non-invasive...but some boards don't seem to reset and I don't have 1093 * complete documentation on what the 'right' thing to do is...so we 1094 * do the invasive thing for now. Yuck.] 1095 */ 1096 outb(sc->asic_addr + ED_NOVELL_RESET, tmp); 1097 DELAY(5000); 1098 1099 /* 1100 * This is needed because some NE clones apparently don't reset the 1101 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX 1102 * - this makes the probe invasive! ...Done against my better 1103 * judgement. -DLG 1104 */ 1105 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP); 1106 1107 DELAY(5000); 1108 1109 /* Make sure that we really have an 8390 based board */ 1110 if (!ed_probe_generic8390(sc)) 1111 return (0); 1112 1113 sc->vendor = ED_VENDOR_NOVELL; 1114 sc->mem_shared = 0; 1115 sc->cr_proto = ED_CR_RD2; 1116 1117 /* 1118 * Test the ability to read and write to the NIC memory. This has the 1119 * side affect of determining if this is an NE1000 or an NE2000. 1120 */ 1121 1122 /* 1123 * This prevents packets from being stored in the NIC memory when the 1124 * readmem routine turns on the start bit in the CR. 1125 */ 1126 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1127 1128 /* Temporarily initialize DCR for byte operations */ 1129 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1130 1131 outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE); 1132 outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE); 1133 1134 sc->isa16bit = 0; 1135 1136 /* 1137 * Write a test pattern in byte mode. If this fails, then there 1138 * probably isn't any memory at 8k - which likely means that the board 1139 * is an NE2000. 1140 */ 1141 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern)); 1142 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern)); 1143 1144 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) { 1145 /* not an NE1000 - try NE2000 */ 1146 1147 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS); 1148 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE); 1149 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE); 1150 1151 sc->isa16bit = 1; 1152 1153 /* 1154 * Write a test pattern in word mode. If this also fails, then 1155 * we don't know what this board is. 1156 */ 1157 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern)); 1158 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern)); 1159 1160 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) 1161 return (0); /* not an NE2000 either */ 1162 1163 sc->type = ED_TYPE_NE2000; 1164 sc->type_str = "NE2000"; 1165 } else { 1166 sc->type = ED_TYPE_NE1000; 1167 sc->type_str = "NE1000"; 1168 } 1169 1170 /* 8k of memory plus an additional 8k if 16bit */ 1171 memsize = 8192 + sc->isa16bit * 8192; 1172 1173 #if 0 /* probably not useful - NE boards only come two ways */ 1174 /* allow kernel config file overrides */ 1175 if (isa_dev->id_msize) 1176 memsize = isa_dev->id_msize; 1177 #endif 1178 1179 sc->mem_size = memsize; 1180 1181 /* NIC memory doesn't start at zero on an NE board */ 1182 /* The start address is tied to the bus width */ 1183 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192; 1184 sc->mem_end = sc->mem_start + memsize; 1185 sc->tx_page_start = memsize / ED_PAGE_SIZE; 1186 1187 #ifdef GWETHER 1188 { 1189 int x, i, mstart = 0, msize = 0; 1190 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE]; 1191 1192 for (i = 0; i < ED_PAGE_SIZE; i++) 1193 pbuf0[i] = 0; 1194 1195 /* Clear all the memory. */ 1196 for (x = 1; x < 256; x++) 1197 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE); 1198 1199 /* Search for the start of RAM. */ 1200 for (x = 1; x < 256; x++) { 1201 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1202 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1203 for (i = 0; i < ED_PAGE_SIZE; i++) 1204 pbuf[i] = 255 - x; 1205 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1206 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1207 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) { 1208 mstart = x * ED_PAGE_SIZE; 1209 msize = ED_PAGE_SIZE; 1210 break; 1211 } 1212 } 1213 } 1214 1215 if (mstart == 0) { 1216 printf("ed%d: Cannot find start of RAM.\n", unit); 1217 return 0; 1218 } 1219 /* Search for the start of RAM. */ 1220 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) { 1221 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1222 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) { 1223 for (i = 0; i < ED_PAGE_SIZE; i++) 1224 pbuf[i] = 255 - x; 1225 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE); 1226 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE); 1227 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) 1228 msize += ED_PAGE_SIZE; 1229 else { 1230 break; 1231 } 1232 } else { 1233 break; 1234 } 1235 } 1236 1237 if (msize == 0) { 1238 printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", unit, mstart, x); 1239 return 0; 1240 } 1241 printf("ed%d: RAM start at %d, size : %d.\n", unit, mstart, msize); 1242 1243 sc->mem_size = msize; 1244 sc->mem_start = (char *) mstart; 1245 sc->mem_end = (char *) (msize + mstart); 1246 sc->tx_page_start = mstart / ED_PAGE_SIZE; 1247 } 1248 #endif /* GWETHER */ 1249 1250 /* 1251 * Use one xmit buffer if < 16k, two buffers otherwise (if not told 1252 * otherwise). 1253 */ 1254 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) 1255 sc->txb_cnt = 1; 1256 else 1257 sc->txb_cnt = 2; 1258 1259 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE; 1260 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE; 1261 1262 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE; 1263 1264 ed_pio_readmem(sc, 0, romdata, 16); 1265 for (n = 0; n < ETHER_ADDR_LEN; n++) 1266 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)]; 1267 1268 #ifdef GWETHER 1269 if (sc->arpcom.ac_enaddr[2] == 0x86) { 1270 sc->type_str = "Gateway AT"; 1271 } 1272 #endif /* GWETHER */ 1273 1274 /* clear any pending interrupts that might have occurred above */ 1275 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1276 1277 return (ED_NOVELL_IO_PORTS); 1278 } 1279 1280 static int 1281 ed_probe_Novell(isa_dev) 1282 struct isa_device *isa_dev; 1283 { 1284 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1285 int nports; 1286 1287 nports = ed_probe_Novell_generic(sc, isa_dev->id_iobase, 1288 isa_dev->id_unit, isa_dev->id_flags); 1289 if (nports) 1290 isa_dev->id_maddr = 0; 1291 1292 return (nports); 1293 } 1294 1295 #if NCARD > 0 1296 /* 1297 * Probe framework for pccards. Replicates the standard framework, 1298 * minus the pccard driver registration and ignores the ether address 1299 * supplied (from the CIS), relying on the probe to find it instead. 1300 */ 1301 static int 1302 ed_probe_pccard(isa_dev, ether) 1303 struct isa_device *isa_dev; 1304 u_char *ether; 1305 { 1306 int nports; 1307 1308 nports = ed_probe_WD80x3(isa_dev); 1309 if (nports) 1310 return (nports); 1311 1312 nports = ed_probe_Novell(isa_dev); 1313 if (nports) 1314 return (nports); 1315 1316 return (0); 1317 } 1318 1319 #endif /* NCARD > 0 */ 1320 1321 #define ED_HPP_TEST_SIZE 16 1322 1323 /* 1324 * Probe and vendor specific initialization for the HP PC Lan+ Cards. 1325 * (HP Part nos: 27247B and 27252A). 1326 * 1327 * The card has an asic wrapper around a DS8390 core. The asic handles 1328 * host accesses and offers both standard register IO and memory mapped 1329 * IO. Memory mapped I/O allows better performance at the expense of greater 1330 * chance of an incompatibility with existing ISA cards. 1331 * 1332 * The card has a few caveats: it isn't tolerant of byte wide accesses, only 1333 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions 1334 * don't allow 32 bit accesses; these are indicated by a bit in the software 1335 * ID register (see if_edreg.h). 1336 * 1337 * Other caveats are: we should read the MAC address only when the card 1338 * is inactive. 1339 * 1340 * For more information; please consult the CRYNWR packet driver. 1341 * 1342 * The AUI port is turned on using the "link2" option on the ifconfig 1343 * command line. 1344 */ 1345 static int 1346 ed_probe_HP_pclanp(isa_dev) 1347 struct isa_device *isa_dev; 1348 { 1349 struct ed_softc *sc = &ed_softc[isa_dev->id_unit]; 1350 int n; /* temp var */ 1351 int memsize; /* mem on board */ 1352 u_char checksum; /* checksum of board address */ 1353 u_char irq; /* board configured IRQ */ 1354 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */ 1355 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */ 1356 1357 1358 /* Fill in basic information */ 1359 sc->asic_addr = isa_dev->id_iobase + ED_HPP_ASIC_OFFSET; 1360 sc->nic_addr = isa_dev->id_iobase + ED_HPP_NIC_OFFSET; 1361 sc->is790 = 0; 1362 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */ 1363 1364 /* 1365 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 1366 */ 1367 1368 if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) || 1369 (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) || 1370 ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) || 1371 (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53)) 1372 return 0; 1373 1374 /* 1375 * Read the MAC address and verify checksum on the address. 1376 */ 1377 1378 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC); 1379 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++) 1380 checksum += (sc->arpcom.ac_enaddr[n] = 1381 inb(sc->asic_addr + ED_HPP_MAC_ADDR + n)); 1382 1383 checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN); 1384 1385 if (checksum != 0xFF) 1386 return 0; 1387 1388 /* 1389 * Verify that the software model number is 0. 1390 */ 1391 1392 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID); 1393 if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) & 1394 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000) 1395 return 0; 1396 1397 /* 1398 * Read in and save the current options configured on card. 1399 */ 1400 1401 sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION); 1402 1403 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 1404 ED_HPP_OPTION_CHIP_RESET | 1405 ED_HPP_OPTION_ENABLE_IRQ); 1406 1407 /* 1408 * Reset the chip. This requires writing to the option register 1409 * so take care to preserve the other bits. 1410 */ 1411 1412 outw(sc->asic_addr + ED_HPP_OPTION, 1413 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 1414 ED_HPP_OPTION_CHIP_RESET))); 1415 1416 DELAY(5000); /* wait for chip reset to complete */ 1417 1418 outw(sc->asic_addr + ED_HPP_OPTION, 1419 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET | 1420 ED_HPP_OPTION_CHIP_RESET | 1421 ED_HPP_OPTION_ENABLE_IRQ))); 1422 1423 DELAY(5000); 1424 1425 if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST)) 1426 return 0; /* reset did not complete */ 1427 1428 /* 1429 * Read out configuration information. 1430 */ 1431 1432 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1433 1434 irq = inb(sc->asic_addr + ED_HPP_HW_IRQ); 1435 1436 /* 1437 * Check for impossible IRQ. 1438 */ 1439 1440 if (irq >= (sizeof(ed_hpp_intr_mask) / sizeof(ed_hpp_intr_mask[0]))) 1441 return 0; 1442 1443 /* 1444 * If the kernel IRQ was specified with a '?' use the cards idea 1445 * of the IRQ. If the kernel IRQ was explicitly specified, it 1446 * should match that of the hardware. 1447 */ 1448 1449 if (isa_dev->id_irq <= 0) 1450 isa_dev->id_irq = ed_hpp_intr_mask[irq]; 1451 else if (isa_dev->id_irq != ed_hpp_intr_mask[irq]) 1452 return 0; 1453 1454 /* 1455 * Fill in softconfig info. 1456 */ 1457 1458 sc->vendor = ED_VENDOR_HP; 1459 sc->type = ED_TYPE_HP_PCLANPLUS; 1460 sc->type_str = "HP-PCLAN+"; 1461 1462 sc->mem_shared = 0; /* we DON'T have dual ported RAM */ 1463 sc->mem_start = 0; /* we use offsets inside the card RAM */ 1464 1465 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */ 1466 1467 /* 1468 * Check if memory mapping of the I/O registers possible. 1469 */ 1470 1471 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE) 1472 { 1473 u_long mem_addr; 1474 1475 /* 1476 * determine the memory address from the board. 1477 */ 1478 1479 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1480 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8); 1481 1482 /* 1483 * Check that the kernel specified start of memory and 1484 * hardware's idea of it match. 1485 */ 1486 1487 if (mem_addr != kvtop(isa_dev->id_maddr)) 1488 return 0; 1489 1490 sc->hpp_mem_start = isa_dev->id_maddr; 1491 } 1492 1493 /* 1494 * The board has 32KB of memory. Is there a way to determine 1495 * this programmatically? 1496 */ 1497 1498 memsize = 32768; 1499 1500 /* 1501 * Fill in the rest of the soft config structure. 1502 */ 1503 1504 /* 1505 * The transmit page index. 1506 */ 1507 1508 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET; 1509 1510 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING) 1511 sc->txb_cnt = 1; 1512 else 1513 sc->txb_cnt = 2; 1514 1515 /* 1516 * Memory description 1517 */ 1518 1519 sc->mem_size = memsize; 1520 sc->mem_ring = sc->mem_start + 1521 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE); 1522 sc->mem_end = sc->mem_start + sc->mem_size; 1523 1524 /* 1525 * Receive area starts after the transmit area and 1526 * continues till the end of memory. 1527 */ 1528 1529 sc->rec_page_start = sc->tx_page_start + 1530 (sc->txb_cnt * ED_TXBUF_SIZE); 1531 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE); 1532 1533 1534 sc->cr_proto = 0; /* value works */ 1535 1536 /* 1537 * Set the wrap registers for string I/O reads. 1538 */ 1539 1540 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW); 1541 outw(sc->asic_addr + ED_HPP_HW_WRAP, 1542 ((sc->rec_page_start / ED_PAGE_SIZE) | 1543 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8))); 1544 1545 /* 1546 * Reset the register page to normal operation. 1547 */ 1548 1549 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1550 1551 /* 1552 * Verify that we can read/write from adapter memory. 1553 * Create test pattern. 1554 */ 1555 1556 for (n = 0; n < ED_HPP_TEST_SIZE; n++) 1557 { 1558 test_pattern[n] = (n*n) ^ ~n; 1559 } 1560 1561 #undef ED_HPP_TEST_SIZE 1562 1563 /* 1564 * Check that the memory is accessible thru the I/O ports. 1565 * Write out the contents of "test_pattern", read back 1566 * into "test_buffer" and compare the two for any 1567 * mismatch. 1568 */ 1569 1570 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) { 1571 1572 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 1573 sizeof(test_pattern)); 1574 ed_pio_readmem(sc, (n * ED_PAGE_SIZE), 1575 test_buffer, sizeof(test_pattern)); 1576 1577 if (bcmp(test_pattern, test_buffer, 1578 sizeof(test_pattern))) 1579 return 0; 1580 } 1581 1582 return (ED_HPP_IO_PORTS); 1583 1584 } 1585 1586 /* 1587 * HP PC Lan+ : Set the physical link to use AUI or TP/TL. 1588 */ 1589 1590 void 1591 ed_hpp_set_physical_link(struct ed_softc *sc) 1592 { 1593 struct ifnet *ifp = &sc->arpcom.ac_if; 1594 int lan_page; 1595 1596 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1597 lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0); 1598 1599 if (ifp->if_flags & IFF_ALTPHYS) { 1600 1601 /* 1602 * Use the AUI port. 1603 */ 1604 1605 lan_page |= ED_HPP_LAN_AUI; 1606 1607 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1608 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1609 1610 1611 } else { 1612 1613 /* 1614 * Use the ThinLan interface 1615 */ 1616 1617 lan_page &= ~ED_HPP_LAN_AUI; 1618 1619 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN); 1620 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page); 1621 1622 } 1623 1624 /* 1625 * Wait for the lan card to re-initialize itself 1626 */ 1627 1628 DELAY(150000); /* wait 150 ms */ 1629 1630 /* 1631 * Restore normal pages. 1632 */ 1633 1634 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF); 1635 1636 } 1637 1638 1639 /* 1640 * Install interface into kernel networking data structures 1641 */ 1642 static int 1643 ed_attach(sc, unit, flags) 1644 struct ed_softc *sc; 1645 int unit; 1646 int flags; 1647 { 1648 struct ifnet *ifp = &sc->arpcom.ac_if; 1649 1650 /* 1651 * Set interface to stopped condition (reset) 1652 */ 1653 ed_stop(sc); 1654 1655 if (!ifp->if_name) { 1656 /* 1657 * Initialize ifnet structure 1658 */ 1659 ifp->if_softc = sc; 1660 ifp->if_unit = unit; 1661 ifp->if_name = "ed"; 1662 ifp->if_output = ether_output; 1663 ifp->if_start = ed_start; 1664 ifp->if_ioctl = ed_ioctl; 1665 ifp->if_watchdog = ed_watchdog; 1666 ifp->if_init = ed_init; 1667 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 1668 ifp->if_linkmib = &sc->mibdata; 1669 ifp->if_linkmiblen = sizeof sc->mibdata; 1670 /* 1671 * XXX - should do a better job. 1672 */ 1673 if (sc->is790) 1674 sc->mibdata.dot3StatsEtherChipSet = 1675 DOT3CHIPSET(dot3VendorWesternDigital, 1676 dot3ChipSetWesternDigital83C790); 1677 else 1678 sc->mibdata.dot3StatsEtherChipSet = 1679 DOT3CHIPSET(dot3VendorNational, 1680 dot3ChipSetNational8390); 1681 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS; 1682 1683 /* 1684 * Set default state for ALTPHYS flag (used to disable the 1685 * tranceiver for AUI operation), based on compile-time 1686 * config option. 1687 */ 1688 if (flags & ED_FLAGS_DISABLE_TRANCEIVER) 1689 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1690 IFF_MULTICAST | IFF_ALTPHYS); 1691 else 1692 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 1693 IFF_MULTICAST); 1694 1695 /* 1696 * Attach the interface 1697 */ 1698 if_attach(ifp); 1699 ether_ifattach(ifp); 1700 } 1701 /* device attach does transition from UNCONFIGURED to IDLE state */ 1702 1703 /* 1704 * Print additional info when attached 1705 */ 1706 printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit, 1707 sc->arpcom.ac_enaddr, ":"); 1708 1709 if (sc->type_str && (*sc->type_str != 0)) 1710 printf("type %s ", sc->type_str); 1711 else 1712 printf("type unknown (0x%x) ", sc->type); 1713 1714 if (sc->vendor == ED_VENDOR_HP) 1715 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ? 1716 "16-bit" : "32-bit", 1717 sc->hpp_mem_start ? "memory mapped" : "regular"); 1718 else 1719 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)"); 1720 1721 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) || 1722 (sc->vendor == ED_VENDOR_HP)) && 1723 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : ""); 1724 1725 /* 1726 * If BPF is in the kernel, call the attach for it 1727 */ 1728 #if NBPFILTER > 0 1729 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 1730 #endif 1731 return 1; 1732 } 1733 1734 static int 1735 ed_attach_isa(isa_dev) 1736 struct isa_device *isa_dev; 1737 { 1738 int unit = isa_dev->id_unit; 1739 struct ed_softc *sc = &ed_softc[unit]; 1740 int flags = isa_dev->id_flags; 1741 1742 isa_dev->id_ointr = edintr; 1743 return ed_attach(sc, unit, flags); 1744 } 1745 1746 #if NPCI > 0 1747 void * 1748 ed_attach_NE2000_pci(unit, port) 1749 int unit; 1750 int port; 1751 { 1752 struct ed_softc *sc = malloc(sizeof *sc, M_DEVBUF, M_NOWAIT); 1753 int isa_flags = 0; 1754 1755 if (!sc) 1756 return sc; 1757 1758 bzero(sc, sizeof *sc); 1759 if (ed_probe_Novell_generic(sc, port, unit, isa_flags) == 0 1760 || ed_attach(sc, unit, isa_flags) == 0) { 1761 free(sc, M_DEVBUF); 1762 return NULL; 1763 } 1764 return sc; 1765 } 1766 #endif 1767 1768 /* 1769 * Reset interface. 1770 */ 1771 static void 1772 ed_reset(ifp) 1773 struct ifnet *ifp; 1774 { 1775 struct ed_softc *sc = ifp->if_softc; 1776 int s; 1777 1778 if (sc->gone) 1779 return; 1780 s = splimp(); 1781 1782 /* 1783 * Stop interface and re-initialize. 1784 */ 1785 ed_stop(sc); 1786 ed_init(sc); 1787 1788 (void) splx(s); 1789 } 1790 1791 /* 1792 * Take interface offline. 1793 */ 1794 static void 1795 ed_stop(sc) 1796 struct ed_softc *sc; 1797 { 1798 int n = 5000; 1799 1800 if (sc->gone) 1801 return; 1802 /* 1803 * Stop everything on the interface, and select page 0 registers. 1804 */ 1805 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1806 1807 /* 1808 * Wait for interface to enter stopped state, but limit # of checks to 1809 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but 1810 * just in case it's an old one. 1811 */ 1812 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n); 1813 } 1814 1815 /* 1816 * Device timeout/watchdog routine. Entered if the device neglects to 1817 * generate an interrupt after a transmit has been started on it. 1818 */ 1819 static void 1820 ed_watchdog(ifp) 1821 struct ifnet *ifp; 1822 { 1823 struct ed_softc *sc = ifp->if_softc; 1824 1825 if (sc->gone) 1826 return; 1827 log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit); 1828 ifp->if_oerrors++; 1829 1830 ed_reset(ifp); 1831 } 1832 1833 /* 1834 * Initialize device. 1835 */ 1836 static void 1837 ed_init(xsc) 1838 void *xsc; 1839 { 1840 struct ed_softc *sc = xsc; 1841 struct ifnet *ifp = &sc->arpcom.ac_if; 1842 int i, s; 1843 1844 if (sc->gone) 1845 return; 1846 1847 /* address not known */ 1848 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */ 1849 return; 1850 1851 /* 1852 * Initialize the NIC in the exact order outlined in the NS manual. 1853 * This init procedure is "mandatory"...don't change what or when 1854 * things happen. 1855 */ 1856 s = splimp(); 1857 1858 /* reset transmitter flags */ 1859 sc->xmit_busy = 0; 1860 ifp->if_timer = 0; 1861 1862 sc->txb_inuse = 0; 1863 sc->txb_new = 0; 1864 sc->txb_next_tx = 0; 1865 1866 /* This variable is used below - don't move this assignment */ 1867 sc->next_packet = sc->rec_page_start + 1; 1868 1869 /* 1870 * Set interface for page 0, Remote DMA complete, Stopped 1871 */ 1872 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 1873 1874 if (sc->isa16bit) { 1875 1876 /* 1877 * Set FIFO threshold to 8, No auto-init Remote DMA, byte 1878 * order=80x86, word-wide DMA xfers, 1879 */ 1880 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS); 1881 } else { 1882 1883 /* 1884 * Same as above, but byte-wide DMA xfers 1885 */ 1886 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS); 1887 } 1888 1889 /* 1890 * Clear Remote Byte Count Registers 1891 */ 1892 outb(sc->nic_addr + ED_P0_RBCR0, 0); 1893 outb(sc->nic_addr + ED_P0_RBCR1, 0); 1894 1895 /* 1896 * For the moment, don't store incoming packets in memory. 1897 */ 1898 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON); 1899 1900 /* 1901 * Place NIC in internal loopback mode 1902 */ 1903 outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0); 1904 1905 /* 1906 * Initialize transmit/receive (ring-buffer) Page Start 1907 */ 1908 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start); 1909 outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start); 1910 /* Set lower bits of byte addressable framing to 0 */ 1911 if (sc->is790) 1912 outb(sc->nic_addr + 0x09, 0); 1913 1914 /* 1915 * Initialize Receiver (ring-buffer) Page Stop and Boundry 1916 */ 1917 outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop); 1918 outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start); 1919 1920 /* 1921 * Clear all interrupts. A '1' in each bit position clears the 1922 * corresponding flag. 1923 */ 1924 outb(sc->nic_addr + ED_P0_ISR, 0xff); 1925 1926 /* 1927 * Enable the following interrupts: receive/transmit complete, 1928 * receive/transmit error, and Receiver OverWrite. 1929 * 1930 * Counter overflow and Remote DMA complete are *not* enabled. 1931 */ 1932 outb(sc->nic_addr + ED_P0_IMR, 1933 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE); 1934 1935 /* 1936 * Program Command Register for page 1 1937 */ 1938 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 1939 1940 /* 1941 * Copy out our station address 1942 */ 1943 for (i = 0; i < ETHER_ADDR_LEN; ++i) 1944 outb(sc->nic_addr + ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]); 1945 1946 /* 1947 * Set Current Page pointer to next_packet (initialized above) 1948 */ 1949 outb(sc->nic_addr + ED_P1_CURR, sc->next_packet); 1950 1951 /* 1952 * Program Receiver Configuration Register and multicast filter. CR is 1953 * set to page 0 on return. 1954 */ 1955 ed_setrcr(sc); 1956 1957 /* 1958 * Take interface out of loopback 1959 */ 1960 outb(sc->nic_addr + ED_P0_TCR, 0); 1961 1962 /* 1963 * If this is a 3Com board, the tranceiver must be software enabled 1964 * (there is no settable hardware default). 1965 */ 1966 if (sc->vendor == ED_VENDOR_3COM) { 1967 if (ifp->if_flags & IFF_ALTPHYS) { 1968 outb(sc->asic_addr + ED_3COM_CR, 0); 1969 } else { 1970 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 1971 } 1972 } 1973 1974 /* 1975 * Set 'running' flag, and clear output active flag. 1976 */ 1977 ifp->if_flags |= IFF_RUNNING; 1978 ifp->if_flags &= ~IFF_OACTIVE; 1979 1980 /* 1981 * ...and attempt to start output 1982 */ 1983 ed_start(ifp); 1984 1985 (void) splx(s); 1986 } 1987 1988 /* 1989 * This routine actually starts the transmission on the interface 1990 */ 1991 static __inline void 1992 ed_xmit(sc) 1993 struct ed_softc *sc; 1994 { 1995 struct ifnet *ifp = (struct ifnet *)sc; 1996 unsigned short len; 1997 1998 if (sc->gone) 1999 return; 2000 len = sc->txb_len[sc->txb_next_tx]; 2001 2002 /* 2003 * Set NIC for page 0 register access 2004 */ 2005 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2006 2007 /* 2008 * Set TX buffer start page 2009 */ 2010 outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start + 2011 sc->txb_next_tx * ED_TXBUF_SIZE); 2012 2013 /* 2014 * Set TX length 2015 */ 2016 outb(sc->nic_addr + ED_P0_TBCR0, len); 2017 outb(sc->nic_addr + ED_P0_TBCR1, len >> 8); 2018 2019 /* 2020 * Set page 0, Remote DMA complete, Transmit Packet, and *Start* 2021 */ 2022 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA); 2023 sc->xmit_busy = 1; 2024 2025 /* 2026 * Point to next transmit buffer slot and wrap if necessary. 2027 */ 2028 sc->txb_next_tx++; 2029 if (sc->txb_next_tx == sc->txb_cnt) 2030 sc->txb_next_tx = 0; 2031 2032 /* 2033 * Set a timer just in case we never hear from the board again 2034 */ 2035 ifp->if_timer = 2; 2036 } 2037 2038 /* 2039 * Start output on interface. 2040 * We make two assumptions here: 2041 * 1) that the current priority is set to splimp _before_ this code 2042 * is called *and* is returned to the appropriate priority after 2043 * return 2044 * 2) that the IFF_OACTIVE flag is checked before this code is called 2045 * (i.e. that the output part of the interface is idle) 2046 */ 2047 static void 2048 ed_start(ifp) 2049 struct ifnet *ifp; 2050 { 2051 struct ed_softc *sc = ifp->if_softc; 2052 struct mbuf *m0, *m; 2053 caddr_t buffer; 2054 int len; 2055 2056 if (sc->gone) { 2057 printf("ed_start(%p) GONE\n",ifp); 2058 return; 2059 } 2060 outloop: 2061 2062 /* 2063 * First, see if there are buffered packets and an idle transmitter - 2064 * should never happen at this point. 2065 */ 2066 if (sc->txb_inuse && (sc->xmit_busy == 0)) { 2067 printf("ed: packets buffered, but transmitter idle\n"); 2068 ed_xmit(sc); 2069 } 2070 2071 /* 2072 * See if there is room to put another packet in the buffer. 2073 */ 2074 if (sc->txb_inuse == sc->txb_cnt) { 2075 2076 /* 2077 * No room. Indicate this to the outside world and exit. 2078 */ 2079 ifp->if_flags |= IFF_OACTIVE; 2080 return; 2081 } 2082 IF_DEQUEUE(&ifp->if_snd, m); 2083 if (m == 0) { 2084 2085 /* 2086 * We are using the !OACTIVE flag to indicate to the outside 2087 * world that we can accept an additional packet rather than 2088 * that the transmitter is _actually_ active. Indeed, the 2089 * transmitter may be active, but if we haven't filled all the 2090 * buffers with data then we still want to accept more. 2091 */ 2092 ifp->if_flags &= ~IFF_OACTIVE; 2093 return; 2094 } 2095 2096 /* 2097 * Copy the mbuf chain into the transmit buffer 2098 */ 2099 2100 m0 = m; 2101 2102 /* txb_new points to next open buffer slot */ 2103 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE); 2104 2105 if (sc->mem_shared) { 2106 2107 /* 2108 * Special case setup for 16 bit boards... 2109 */ 2110 if (sc->isa16bit) { 2111 switch (sc->vendor) { 2112 2113 /* 2114 * For 16bit 3Com boards (which have 16k of 2115 * memory), we have the xmit buffers in a 2116 * different page of memory ('page 0') - so 2117 * change pages. 2118 */ 2119 case ED_VENDOR_3COM: 2120 outb(sc->asic_addr + ED_3COM_GACFR, 2121 ED_3COM_GACFR_RSEL); 2122 break; 2123 2124 /* 2125 * Enable 16bit access to shared memory on 2126 * WD/SMC boards. 2127 */ 2128 case ED_VENDOR_WD_SMC:{ 2129 outb(sc->asic_addr + ED_WD_LAAR, 2130 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2131 if (sc->is790) { 2132 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB); 2133 } 2134 break; 2135 } 2136 } 2137 } 2138 for (len = 0; m != 0; m = m->m_next) { 2139 bcopy(mtod(m, caddr_t), buffer, m->m_len); 2140 buffer += m->m_len; 2141 len += m->m_len; 2142 } 2143 2144 /* 2145 * Restore previous shared memory access 2146 */ 2147 if (sc->isa16bit) { 2148 switch (sc->vendor) { 2149 case ED_VENDOR_3COM: 2150 outb(sc->asic_addr + ED_3COM_GACFR, 2151 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0); 2152 break; 2153 case ED_VENDOR_WD_SMC:{ 2154 if (sc->is790) { 2155 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2156 } 2157 outb(sc->asic_addr + ED_WD_LAAR, 2158 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2159 break; 2160 } 2161 } 2162 } 2163 } else { 2164 len = ed_pio_write_mbufs(sc, m, (int)buffer); 2165 if (len == 0) 2166 goto outloop; 2167 } 2168 2169 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN)); 2170 2171 sc->txb_inuse++; 2172 2173 /* 2174 * Point to next buffer slot and wrap if necessary. 2175 */ 2176 sc->txb_new++; 2177 if (sc->txb_new == sc->txb_cnt) 2178 sc->txb_new = 0; 2179 2180 if (sc->xmit_busy == 0) 2181 ed_xmit(sc); 2182 2183 /* 2184 * Tap off here if there is a bpf listener. 2185 */ 2186 #if NBPFILTER > 0 2187 if (ifp->if_bpf) { 2188 bpf_mtap(ifp, m0); 2189 } 2190 #endif 2191 2192 m_freem(m0); 2193 2194 /* 2195 * Loop back to the top to possibly buffer more packets 2196 */ 2197 goto outloop; 2198 } 2199 2200 /* 2201 * Ethernet interface receiver interrupt. 2202 */ 2203 static __inline void 2204 ed_rint(sc) 2205 struct ed_softc *sc; 2206 { 2207 struct ifnet *ifp = &sc->arpcom.ac_if; 2208 u_char boundry; 2209 u_short len; 2210 struct ed_ring packet_hdr; 2211 char *packet_ptr; 2212 2213 if (sc->gone) 2214 return; 2215 2216 /* 2217 * Set NIC to page 1 registers to get 'current' pointer 2218 */ 2219 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2220 2221 /* 2222 * 'sc->next_packet' is the logical beginning of the ring-buffer - 2223 * i.e. it points to where new data has been buffered. The 'CURR' 2224 * (current) register points to the logical end of the ring-buffer - 2225 * i.e. it points to where additional new data will be added. We loop 2226 * here until the logical beginning equals the logical end (or in 2227 * other words, until the ring-buffer is empty). 2228 */ 2229 while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) { 2230 2231 /* get pointer to this buffer's header structure */ 2232 packet_ptr = sc->mem_ring + 2233 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE; 2234 2235 /* 2236 * The byte count includes a 4 byte header that was added by 2237 * the NIC. 2238 */ 2239 if (sc->mem_shared) 2240 packet_hdr = *(struct ed_ring *) packet_ptr; 2241 else 2242 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr, 2243 sizeof(packet_hdr)); 2244 len = packet_hdr.count; 2245 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) || 2246 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) { 2247 /* 2248 * Length is a wild value. There's a good chance that 2249 * this was caused by the NIC being old and buggy. 2250 * The bug is that the length low byte is duplicated in 2251 * the high byte. Try to recalculate the length based on 2252 * the pointer to the next packet. 2253 */ 2254 /* 2255 * NOTE: sc->next_packet is pointing at the current packet. 2256 */ 2257 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */ 2258 if (packet_hdr.next_packet >= sc->next_packet) { 2259 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE; 2260 } else { 2261 len += ((packet_hdr.next_packet - sc->rec_page_start) + 2262 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE; 2263 } 2264 /* 2265 * because buffers are aligned on 256-byte boundary, 2266 * the length computed above is off by 256 in almost 2267 * all cases. Fix it... 2268 */ 2269 if (len & 0xff) 2270 len -= 256 ; 2271 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 2272 + sizeof(struct ed_ring))) 2273 sc->mibdata.dot3StatsFrameTooLongs++; 2274 } 2275 /* 2276 * Be fairly liberal about what we allow as a "reasonable" length 2277 * so that a [crufty] packet will make it to BPF (and can thus 2278 * be analyzed). Note that all that is really important is that 2279 * we have a length that will fit into one mbuf cluster or less; 2280 * the upper layer protocols can then figure out the length from 2281 * their own length field(s). 2282 */ 2283 if ((len > sizeof(struct ed_ring)) && 2284 (len <= MCLBYTES) && 2285 (packet_hdr.next_packet >= sc->rec_page_start) && 2286 (packet_hdr.next_packet < sc->rec_page_stop)) { 2287 /* 2288 * Go get packet. 2289 */ 2290 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring), 2291 len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY); 2292 ifp->if_ipackets++; 2293 } else { 2294 /* 2295 * Really BAD. The ring pointers are corrupted. 2296 */ 2297 log(LOG_ERR, 2298 "ed%d: NIC memory corrupt - invalid packet length %d\n", 2299 ifp->if_unit, len); 2300 ifp->if_ierrors++; 2301 ed_reset(ifp); 2302 return; 2303 } 2304 2305 /* 2306 * Update next packet pointer 2307 */ 2308 sc->next_packet = packet_hdr.next_packet; 2309 2310 /* 2311 * Update NIC boundry pointer - being careful to keep it one 2312 * buffer behind. (as recommended by NS databook) 2313 */ 2314 boundry = sc->next_packet - 1; 2315 if (boundry < sc->rec_page_start) 2316 boundry = sc->rec_page_stop - 1; 2317 2318 /* 2319 * Set NIC to page 0 registers to update boundry register 2320 */ 2321 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2322 2323 outb(sc->nic_addr + ED_P0_BNRY, boundry); 2324 2325 /* 2326 * Set NIC to page 1 registers before looping to top (prepare 2327 * to get 'CURR' current pointer) 2328 */ 2329 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA); 2330 } 2331 } 2332 2333 /* 2334 * Ethernet interface interrupt processor 2335 */ 2336 void 2337 edintr_sc(sc) 2338 struct ed_softc *sc; 2339 { 2340 struct ifnet *ifp = (struct ifnet *)sc; 2341 u_char isr; 2342 2343 if (sc->gone) 2344 return; 2345 /* 2346 * Set NIC to page 0 registers 2347 */ 2348 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2349 2350 /* 2351 * loop until there are no more new interrupts 2352 */ 2353 while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) { 2354 2355 /* 2356 * reset all the bits that we are 'acknowledging' by writing a 2357 * '1' to each bit position that was set (writing a '1' 2358 * *clears* the bit) 2359 */ 2360 outb(sc->nic_addr + ED_P0_ISR, isr); 2361 2362 /* 2363 * Handle transmitter interrupts. Handle these first because 2364 * the receiver will reset the board under some conditions. 2365 */ 2366 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) { 2367 u_char collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f; 2368 2369 /* 2370 * Check for transmit error. If a TX completed with an 2371 * error, we end up throwing the packet away. Really 2372 * the only error that is possible is excessive 2373 * collisions, and in this case it is best to allow 2374 * the automatic mechanisms of TCP to backoff the 2375 * flow. Of course, with UDP we're screwed, but this 2376 * is expected when a network is heavily loaded. 2377 */ 2378 (void) inb(sc->nic_addr + ED_P0_TSR); 2379 if (isr & ED_ISR_TXE) { 2380 u_char tsr; 2381 2382 /* 2383 * Excessive collisions (16) 2384 */ 2385 tsr = inb(sc->nic_addr + ED_P0_TSR); 2386 if ((tsr & ED_TSR_ABT) 2387 && (collisions == 0)) { 2388 2389 /* 2390 * When collisions total 16, the 2391 * P0_NCR will indicate 0, and the 2392 * TSR_ABT is set. 2393 */ 2394 collisions = 16; 2395 sc->mibdata.dot3StatsExcessiveCollisions++; 2396 sc->mibdata.dot3StatsCollFrequencies[15]++; 2397 } 2398 if (tsr & ED_TSR_OWC) 2399 sc->mibdata.dot3StatsLateCollisions++; 2400 if (tsr & ED_TSR_CDH) 2401 sc->mibdata.dot3StatsSQETestErrors++; 2402 if (tsr & ED_TSR_CRS) 2403 sc->mibdata.dot3StatsCarrierSenseErrors++; 2404 if (tsr & ED_TSR_FU) 2405 sc->mibdata.dot3StatsInternalMacTransmitErrors++; 2406 2407 /* 2408 * update output errors counter 2409 */ 2410 ifp->if_oerrors++; 2411 } else { 2412 2413 /* 2414 * Update total number of successfully 2415 * transmitted packets. 2416 */ 2417 ifp->if_opackets++; 2418 } 2419 2420 /* 2421 * reset tx busy and output active flags 2422 */ 2423 sc->xmit_busy = 0; 2424 ifp->if_flags &= ~IFF_OACTIVE; 2425 2426 /* 2427 * clear watchdog timer 2428 */ 2429 ifp->if_timer = 0; 2430 2431 /* 2432 * Add in total number of collisions on last 2433 * transmission. 2434 */ 2435 ifp->if_collisions += collisions; 2436 switch(collisions) { 2437 case 0: 2438 case 16: 2439 break; 2440 case 1: 2441 sc->mibdata.dot3StatsSingleCollisionFrames++; 2442 sc->mibdata.dot3StatsCollFrequencies[0]++; 2443 break; 2444 default: 2445 sc->mibdata.dot3StatsMultipleCollisionFrames++; 2446 sc->mibdata. 2447 dot3StatsCollFrequencies[collisions-1] 2448 ++; 2449 break; 2450 } 2451 2452 /* 2453 * Decrement buffer in-use count if not zero (can only 2454 * be zero if a transmitter interrupt occured while 2455 * not actually transmitting). If data is ready to 2456 * transmit, start it transmitting, otherwise defer 2457 * until after handling receiver 2458 */ 2459 if (sc->txb_inuse && --sc->txb_inuse) 2460 ed_xmit(sc); 2461 } 2462 2463 /* 2464 * Handle receiver interrupts 2465 */ 2466 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) { 2467 2468 /* 2469 * Overwrite warning. In order to make sure that a 2470 * lockup of the local DMA hasn't occurred, we reset 2471 * and re-init the NIC. The NSC manual suggests only a 2472 * partial reset/re-init is necessary - but some chips 2473 * seem to want more. The DMA lockup has been seen 2474 * only with early rev chips - Methinks this bug was 2475 * fixed in later revs. -DG 2476 */ 2477 if (isr & ED_ISR_OVW) { 2478 ifp->if_ierrors++; 2479 #ifdef DIAGNOSTIC 2480 log(LOG_WARNING, 2481 "ed%d: warning - receiver ring buffer overrun\n", 2482 ifp->if_unit); 2483 #endif 2484 2485 /* 2486 * Stop/reset/re-init NIC 2487 */ 2488 ed_reset(ifp); 2489 } else { 2490 2491 /* 2492 * Receiver Error. One or more of: CRC error, 2493 * frame alignment error FIFO overrun, or 2494 * missed packet. 2495 */ 2496 if (isr & ED_ISR_RXE) { 2497 u_char rsr; 2498 rsr = inb(sc->nic_addr + ED_P0_RSR); 2499 if (rsr & ED_RSR_CRC) 2500 sc->mibdata.dot3StatsFCSErrors++; 2501 if (rsr & ED_RSR_FAE) 2502 sc->mibdata.dot3StatsAlignmentErrors++; 2503 if (rsr & ED_RSR_FO) 2504 sc->mibdata.dot3StatsInternalMacReceiveErrors++; 2505 ifp->if_ierrors++; 2506 #ifdef ED_DEBUG 2507 printf("ed%d: receive error %x\n", ifp->if_unit, 2508 inb(sc->nic_addr + ED_P0_RSR)); 2509 #endif 2510 } 2511 2512 /* 2513 * Go get the packet(s) XXX - Doing this on an 2514 * error is dubious because there shouldn't be 2515 * any data to get (we've configured the 2516 * interface to not accept packets with 2517 * errors). 2518 */ 2519 2520 /* 2521 * Enable 16bit access to shared memory first 2522 * on WD/SMC boards. 2523 */ 2524 if (sc->isa16bit && 2525 (sc->vendor == ED_VENDOR_WD_SMC)) { 2526 2527 outb(sc->asic_addr + ED_WD_LAAR, 2528 sc->wd_laar_proto | ED_WD_LAAR_M16EN); 2529 if (sc->is790) { 2530 outb(sc->asic_addr + ED_WD_MSR, 2531 ED_WD_MSR_MENB); 2532 } 2533 } 2534 ed_rint(sc); 2535 2536 /* disable 16bit access */ 2537 if (sc->isa16bit && 2538 (sc->vendor == ED_VENDOR_WD_SMC)) { 2539 2540 if (sc->is790) { 2541 outb(sc->asic_addr + ED_WD_MSR, 0x00); 2542 } 2543 outb(sc->asic_addr + ED_WD_LAAR, 2544 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN); 2545 } 2546 } 2547 } 2548 2549 /* 2550 * If it looks like the transmitter can take more data, 2551 * attempt to start output on the interface. This is done 2552 * after handling the receiver to give the receiver priority. 2553 */ 2554 if ((ifp->if_flags & IFF_OACTIVE) == 0) 2555 ed_start(ifp); 2556 2557 /* 2558 * return NIC CR to standard state: page 0, remote DMA 2559 * complete, start (toggling the TXP bit off, even if was just 2560 * set in the transmit routine, is *okay* - it is 'edge' 2561 * triggered from low to high) 2562 */ 2563 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 2564 2565 /* 2566 * If the Network Talley Counters overflow, read them to reset 2567 * them. It appears that old 8390's won't clear the ISR flag 2568 * otherwise - resulting in an infinite loop. 2569 */ 2570 if (isr & ED_ISR_CNT) { 2571 (void) inb(sc->nic_addr + ED_P0_CNTR0); 2572 (void) inb(sc->nic_addr + ED_P0_CNTR1); 2573 (void) inb(sc->nic_addr + ED_P0_CNTR2); 2574 } 2575 } 2576 } 2577 2578 static void 2579 edintr(unit) 2580 int unit; 2581 { 2582 edintr_sc (&ed_softc[unit]); 2583 } 2584 2585 /* 2586 * Process an ioctl request. This code needs some work - it looks 2587 * pretty ugly. 2588 */ 2589 static int 2590 ed_ioctl(ifp, command, data) 2591 register struct ifnet *ifp; 2592 u_long command; 2593 caddr_t data; 2594 { 2595 struct ed_softc *sc = ifp->if_softc; 2596 int s, error = 0; 2597 2598 if (sc->gone) { 2599 ifp->if_flags &= ~IFF_RUNNING; 2600 return ENXIO; 2601 } 2602 s = splimp(); 2603 2604 switch (command) { 2605 2606 case SIOCSIFADDR: 2607 case SIOCGIFADDR: 2608 case SIOCSIFMTU: 2609 error = ether_ioctl(ifp, command, data); 2610 break; 2611 2612 case SIOCSIFFLAGS: 2613 2614 /* 2615 * If the interface is marked up and stopped, then start it. 2616 * If it is marked down and running, then stop it. 2617 */ 2618 if (ifp->if_flags & IFF_UP) { 2619 if ((ifp->if_flags & IFF_RUNNING) == 0) 2620 ed_init(sc); 2621 } else { 2622 if (ifp->if_flags & IFF_RUNNING) { 2623 ed_stop(sc); 2624 ifp->if_flags &= ~IFF_RUNNING; 2625 } 2626 } 2627 2628 #if NBPFILTER > 0 2629 2630 /* 2631 * Promiscuous flag may have changed, so reprogram the RCR. 2632 */ 2633 ed_setrcr(sc); 2634 #endif 2635 2636 /* 2637 * An unfortunate hack to provide the (required) software 2638 * control of the tranceiver for 3Com boards. The ALTPHYS flag 2639 * disables the tranceiver if set. 2640 */ 2641 if (sc->vendor == ED_VENDOR_3COM) { 2642 if (ifp->if_flags & IFF_ALTPHYS) { 2643 outb(sc->asic_addr + ED_3COM_CR, 0); 2644 } else { 2645 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL); 2646 } 2647 } else if (sc->vendor == ED_VENDOR_HP) 2648 ed_hpp_set_physical_link(sc); 2649 break; 2650 2651 case SIOCADDMULTI: 2652 case SIOCDELMULTI: 2653 /* 2654 * Multicast list has changed; set the hardware filter 2655 * accordingly. 2656 */ 2657 ed_setrcr(sc); 2658 error = 0; 2659 break; 2660 2661 default: 2662 error = EINVAL; 2663 } 2664 (void) splx(s); 2665 return (error); 2666 } 2667 2668 /* 2669 * Given a source and destination address, copy 'amount' of a packet from 2670 * the ring buffer into a linear destination buffer. Takes into account 2671 * ring-wrap. 2672 */ 2673 static __inline char * 2674 ed_ring_copy(sc, src, dst, amount) 2675 struct ed_softc *sc; 2676 char *src; 2677 char *dst; 2678 u_short amount; 2679 { 2680 u_short tmp_amount; 2681 2682 /* does copy wrap to lower addr in ring buffer? */ 2683 if (src + amount > sc->mem_end) { 2684 tmp_amount = sc->mem_end - src; 2685 2686 /* copy amount up to end of NIC memory */ 2687 if (sc->mem_shared) 2688 bcopy(src, dst, tmp_amount); 2689 else 2690 ed_pio_readmem(sc, (int)src, dst, tmp_amount); 2691 2692 amount -= tmp_amount; 2693 src = sc->mem_ring; 2694 dst += tmp_amount; 2695 } 2696 if (sc->mem_shared) 2697 bcopy(src, dst, amount); 2698 else 2699 ed_pio_readmem(sc, (int)src, dst, amount); 2700 2701 return (src + amount); 2702 } 2703 2704 /* 2705 * Retreive packet from shared memory and send to the next level up via 2706 * ether_input(). If there is a BPF listener, give a copy to BPF, too. 2707 */ 2708 static void 2709 ed_get_packet(sc, buf, len, multicast) 2710 struct ed_softc *sc; 2711 char *buf; 2712 u_short len; 2713 int multicast; 2714 { 2715 struct ether_header *eh; 2716 struct mbuf *m; 2717 2718 /* Allocate a header mbuf */ 2719 MGETHDR(m, M_DONTWAIT, MT_DATA); 2720 if (m == NULL) 2721 return; 2722 m->m_pkthdr.rcvif = &sc->arpcom.ac_if; 2723 m->m_pkthdr.len = m->m_len = len; 2724 2725 /* 2726 * We always put the received packet in a single buffer - 2727 * either with just an mbuf header or in a cluster attached 2728 * to the header. The +2 is to compensate for the alignment 2729 * fixup below. 2730 */ 2731 if ((len + 2) > MHLEN) { 2732 /* Attach an mbuf cluster */ 2733 MCLGET(m, M_DONTWAIT); 2734 2735 /* Insist on getting a cluster */ 2736 if ((m->m_flags & M_EXT) == 0) { 2737 m_freem(m); 2738 return; 2739 } 2740 } 2741 2742 /* 2743 * The +2 is to longword align the start of the real packet. 2744 * This is important for NFS. 2745 */ 2746 m->m_data += 2; 2747 eh = mtod(m, struct ether_header *); 2748 2749 #ifdef BRIDGE 2750 /* 2751 * Get link layer header, invoke brige_in, then 2752 * depending on the outcome of the test fetch the rest of the 2753 * packet and either pass up or call bdg_forward. 2754 */ 2755 if (do_bridge) { 2756 struct ifnet *ifp ; 2757 int need_more = 1 ; /* in case not bpf */ 2758 2759 #if NBPFILTER > 0 2760 if (sc->arpcom.ac_if.if_bpf) { 2761 need_more = 0 ; 2762 ed_ring_copy(sc, buf, (char *)eh, len); 2763 bpf_mtap(&sc->arpcom.ac_if, m); 2764 } else 2765 #endif 2766 ed_ring_copy(sc, buf, (char *)eh, 14); 2767 ifp = bridge_in(m); 2768 if (ifp == BDG_DROP) { 2769 m_freem(m); 2770 return ; 2771 } 2772 /* else fetch rest of pkt and continue */ 2773 if (need_more && len > 14) 2774 ed_ring_copy(sc, buf+14, (char *)(eh+1), len - 14); 2775 if (ifp != BDG_LOCAL ) 2776 bdg_forward(&m, ifp); /* not local, need forwarding */ 2777 if (m == NULL) 2778 return ; /* dropped */ 2779 eh = mtod(m, struct ether_header *); 2780 if (ifp == BDG_LOCAL || ifp == BDG_BCAST || ifp == BDG_MCAST) 2781 goto getit ; 2782 /* not local and not multicast, just drop it */ 2783 if (m) 2784 m_freem(m); 2785 return ; 2786 } 2787 #endif 2788 /* 2789 * Get packet, including link layer address, from interface. 2790 */ 2791 ed_ring_copy(sc, buf, (char *)eh, len); 2792 2793 #if NBPFILTER > 0 2794 2795 /* 2796 * Check if there's a BPF listener on this interface. If so, hand off 2797 * the raw packet to bpf. 2798 */ 2799 if (sc->arpcom.ac_if.if_bpf) 2800 bpf_mtap(&sc->arpcom.ac_if, m); 2801 #endif 2802 /* 2803 * If we are in promiscuous mode, we have to check whether 2804 * this packet is really for us. 2805 */ 2806 if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) && 2807 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 2808 sizeof(eh->ether_dhost)) != 0 && multicast == 0) { 2809 m_freem(m); 2810 return; 2811 } 2812 2813 getit: 2814 /* 2815 * Remove link layer address. 2816 */ 2817 m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header); 2818 m->m_data += sizeof(struct ether_header); 2819 2820 ether_input(&sc->arpcom.ac_if, eh, m); 2821 return; 2822 } 2823 2824 /* 2825 * Supporting routines 2826 */ 2827 2828 /* 2829 * Given a NIC memory source address and a host memory destination 2830 * address, copy 'amount' from NIC to host using Programmed I/O. 2831 * The 'amount' is rounded up to a word - okay as long as mbufs 2832 * are word sized. 2833 * This routine is currently Novell-specific. 2834 */ 2835 static void 2836 ed_pio_readmem(sc, src, dst, amount) 2837 struct ed_softc *sc; 2838 int src; 2839 unsigned char *dst; 2840 unsigned short amount; 2841 { 2842 /* HP cards need special handling */ 2843 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) { 2844 ed_hpp_readmem(sc, src, dst, amount); 2845 return; 2846 } 2847 2848 /* Regular Novell cards */ 2849 /* select page 0 registers */ 2850 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2851 2852 /* round up to a word */ 2853 if (amount & 1) 2854 ++amount; 2855 2856 /* set up DMA byte count */ 2857 outb(sc->nic_addr + ED_P0_RBCR0, amount); 2858 outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8); 2859 2860 /* set up source address in NIC mem */ 2861 outb(sc->nic_addr + ED_P0_RSAR0, src); 2862 outb(sc->nic_addr + ED_P0_RSAR1, src >> 8); 2863 2864 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA); 2865 2866 if (sc->isa16bit) { 2867 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2); 2868 } else 2869 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount); 2870 2871 } 2872 2873 /* 2874 * Stripped down routine for writing a linear buffer to NIC memory. 2875 * Only used in the probe routine to test the memory. 'len' must 2876 * be even. 2877 */ 2878 static void 2879 ed_pio_writemem(sc, src, dst, len) 2880 struct ed_softc *sc; 2881 char *src; 2882 unsigned short dst; 2883 unsigned short len; 2884 { 2885 int maxwait = 200; /* about 240us */ 2886 2887 if (sc->vendor == ED_VENDOR_NOVELL) { 2888 2889 /* select page 0 registers */ 2890 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2891 2892 /* reset remote DMA complete flag */ 2893 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2894 2895 /* set up DMA byte count */ 2896 outb(sc->nic_addr + ED_P0_RBCR0, len); 2897 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8); 2898 2899 /* set up destination address in NIC mem */ 2900 outb(sc->nic_addr + ED_P0_RSAR0, dst); 2901 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 2902 2903 /* set remote DMA write */ 2904 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 2905 2906 if (sc->isa16bit) 2907 outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2); 2908 else 2909 outsb(sc->asic_addr + ED_NOVELL_DATA, src, len); 2910 2911 /* 2912 * Wait for remote DMA complete. This is necessary because on the 2913 * transmit side, data is handled internally by the NIC in bursts and 2914 * we can't start another remote DMA until this one completes. Not 2915 * waiting causes really bad things to happen - like the NIC 2916 * irrecoverably jamming the ISA bus. 2917 */ 2918 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 2919 2920 } else if ((sc->vendor == ED_VENDOR_HP) && 2921 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2922 2923 /* HP PCLAN+ */ 2924 2925 /* reset remote DMA complete flag */ 2926 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 2927 2928 /* program the write address in RAM */ 2929 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 2930 2931 if (sc->hpp_mem_start) { 2932 u_short *s = (u_short *) src; 2933 volatile u_short *d = (u_short *) sc->hpp_mem_start; 2934 u_short *const fence = s + (len >> 1); 2935 2936 /* 2937 * Enable memory mapped access. 2938 */ 2939 2940 outw(sc->asic_addr + ED_HPP_OPTION, 2941 sc->hpp_options & 2942 ~(ED_HPP_OPTION_MEM_DISABLE | 2943 ED_HPP_OPTION_BOOT_ROM_ENB)); 2944 2945 /* 2946 * Copy to NIC memory. 2947 */ 2948 2949 while (s < fence) 2950 *d = *s++; 2951 2952 /* 2953 * Restore Boot ROM access. 2954 */ 2955 2956 outw(sc->asic_addr + ED_HPP_OPTION, 2957 sc->hpp_options); 2958 2959 } else { 2960 /* write data using I/O writes */ 2961 outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2); 2962 } 2963 2964 } 2965 } 2966 2967 /* 2968 * Write an mbuf chain to the destination NIC memory address using 2969 * programmed I/O. 2970 */ 2971 static u_short 2972 ed_pio_write_mbufs(sc, m, dst) 2973 struct ed_softc *sc; 2974 struct mbuf *m; 2975 int dst; 2976 { 2977 struct ifnet *ifp = (struct ifnet *)sc; 2978 unsigned short total_len, dma_len; 2979 struct mbuf *mp; 2980 int maxwait = 200; /* about 240us */ 2981 2982 /* HP PC Lan+ cards need special handling */ 2983 if ((sc->vendor == ED_VENDOR_HP) && 2984 (sc->type == ED_TYPE_HP_PCLANPLUS)) { 2985 return ed_hpp_write_mbufs(sc, m, dst); 2986 } 2987 2988 /* First, count up the total number of bytes to copy */ 2989 for (total_len = 0, mp = m; mp; mp = mp->m_next) 2990 total_len += mp->m_len; 2991 2992 dma_len = total_len; 2993 if (sc->isa16bit && (dma_len & 1)) 2994 dma_len++; 2995 2996 /* select page 0 registers */ 2997 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA); 2998 2999 /* reset remote DMA complete flag */ 3000 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3001 3002 /* set up DMA byte count */ 3003 outb(sc->nic_addr + ED_P0_RBCR0, dma_len); 3004 outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8); 3005 3006 /* set up destination address in NIC mem */ 3007 outb(sc->nic_addr + ED_P0_RSAR0, dst); 3008 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8); 3009 3010 /* set remote DMA write */ 3011 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA); 3012 3013 /* 3014 * Transfer the mbuf chain to the NIC memory. 3015 * 16-bit cards require that data be transferred as words, and only words. 3016 * So that case requires some extra code to patch over odd-length mbufs. 3017 */ 3018 3019 if (!sc->isa16bit) { 3020 /* NE1000s are easy */ 3021 while (m) { 3022 if (m->m_len) { 3023 outsb(sc->asic_addr + ED_NOVELL_DATA, 3024 m->m_data, m->m_len); 3025 } 3026 m = m->m_next; 3027 } 3028 } else { 3029 /* NE2000s are a pain */ 3030 unsigned char *data; 3031 int len, wantbyte; 3032 unsigned char savebyte[2]; 3033 3034 wantbyte = 0; 3035 3036 while (m) { 3037 len = m->m_len; 3038 if (len) { 3039 data = mtod(m, caddr_t); 3040 /* finish the last word */ 3041 if (wantbyte) { 3042 savebyte[1] = *data; 3043 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 3044 data++; 3045 len--; 3046 wantbyte = 0; 3047 } 3048 /* output contiguous words */ 3049 if (len > 1) { 3050 outsw(sc->asic_addr + ED_NOVELL_DATA, 3051 data, len >> 1); 3052 data += len & ~1; 3053 len &= 1; 3054 } 3055 /* save last byte, if necessary */ 3056 if (len == 1) { 3057 savebyte[0] = *data; 3058 wantbyte = 1; 3059 } 3060 } 3061 m = m->m_next; 3062 } 3063 /* spit last byte */ 3064 if (wantbyte) { 3065 outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte); 3066 } 3067 } 3068 3069 /* 3070 * Wait for remote DMA complete. This is necessary because on the 3071 * transmit side, data is handled internally by the NIC in bursts and 3072 * we can't start another remote DMA until this one completes. Not 3073 * waiting causes really bad things to happen - like the NIC 3074 * irrecoverably jamming the ISA bus. 3075 */ 3076 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait); 3077 3078 if (!maxwait) { 3079 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n", 3080 ifp->if_unit); 3081 ed_reset(ifp); 3082 return(0); 3083 } 3084 return (total_len); 3085 } 3086 3087 /* 3088 * Support routines to handle the HP PC Lan+ card. 3089 */ 3090 3091 /* 3092 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped 3093 * IO. 3094 */ 3095 3096 static void 3097 ed_hpp_readmem(sc, src, dst, amount) 3098 struct ed_softc *sc; 3099 unsigned short src; 3100 unsigned char *dst; 3101 unsigned short amount; 3102 { 3103 3104 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3105 3106 3107 /* Program the source address in RAM */ 3108 outw(sc->asic_addr + ED_HPP_PAGE_2, src); 3109 3110 /* 3111 * The HP PC Lan+ card supports word reads as well as 3112 * a memory mapped i/o port that is aliased to every 3113 * even address on the board. 3114 */ 3115 3116 if (sc->hpp_mem_start) { 3117 3118 /* Enable memory mapped access. */ 3119 outw(sc->asic_addr + ED_HPP_OPTION, 3120 sc->hpp_options & 3121 ~(ED_HPP_OPTION_MEM_DISABLE | 3122 ED_HPP_OPTION_BOOT_ROM_ENB)); 3123 3124 if (use_32bit_access && (amount > 3)) { 3125 u_long *dl = (u_long *) dst; 3126 volatile u_long *const sl = 3127 (u_long *) sc->hpp_mem_start; 3128 u_long *const fence = dl + (amount >> 2); 3129 3130 /* Copy out NIC data. We could probably write this 3131 as a `movsl'. The currently generated code is lousy. 3132 */ 3133 3134 while (dl < fence) 3135 *dl++ = *sl; 3136 3137 dst += (amount & ~3); 3138 amount &= 3; 3139 3140 } 3141 3142 /* Finish off any words left, as a series of short reads */ 3143 if (amount > 1) { 3144 u_short *d = (u_short *) dst; 3145 volatile u_short *const s = 3146 (u_short *) sc->hpp_mem_start; 3147 u_short *const fence = d + (amount >> 1); 3148 3149 /* Copy out NIC data. */ 3150 3151 while (d < fence) 3152 *d++ = *s; 3153 3154 dst += (amount & ~1); 3155 amount &= 1; 3156 } 3157 3158 /* 3159 * read in a byte; however we need to always read 16 bits 3160 * at a time or the hardware gets into a funny state 3161 */ 3162 3163 if (amount == 1) { 3164 /* need to read in a short and copy LSB */ 3165 volatile u_short *const s = 3166 (volatile u_short *) sc->hpp_mem_start; 3167 3168 *dst = (*s) & 0xFF; 3169 } 3170 3171 /* Restore Boot ROM access. */ 3172 3173 outw(sc->asic_addr + ED_HPP_OPTION, 3174 sc->hpp_options); 3175 3176 3177 } else { 3178 /* Read in data using the I/O port */ 3179 if (use_32bit_access && (amount > 3)) { 3180 insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2); 3181 dst += (amount & ~3); 3182 amount &= 3; 3183 } 3184 if (amount > 1) { 3185 insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1); 3186 dst += (amount & ~1); 3187 amount &= 1; 3188 } 3189 if (amount == 1) { /* read in a short and keep the LSB */ 3190 *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF; 3191 } 3192 } 3193 } 3194 3195 /* 3196 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using 3197 * outsw() or via the memory mapped interface to the same register. 3198 * Writes have to be in word units; byte accesses won't work and may cause 3199 * the NIC to behave wierdly. Long word accesses are permitted if the ASIC 3200 * allows it. 3201 */ 3202 3203 static u_short 3204 ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst) 3205 { 3206 int len, wantbyte; 3207 unsigned short total_len; 3208 unsigned char savebyte[2]; 3209 volatile u_short * const d = 3210 (volatile u_short *) sc->hpp_mem_start; 3211 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS); 3212 3213 /* select page 0 registers */ 3214 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3215 3216 /* reset remote DMA complete flag */ 3217 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC); 3218 3219 /* program the write address in RAM */ 3220 outw(sc->asic_addr + ED_HPP_PAGE_0, dst); 3221 3222 if (sc->hpp_mem_start) /* enable memory mapped I/O */ 3223 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options & 3224 ~(ED_HPP_OPTION_MEM_DISABLE | 3225 ED_HPP_OPTION_BOOT_ROM_ENB)); 3226 3227 wantbyte = 0; 3228 total_len = 0; 3229 3230 if (sc->hpp_mem_start) { /* Memory mapped I/O port */ 3231 while (m) { 3232 total_len += (len = m->m_len); 3233 if (len) { 3234 caddr_t data = mtod(m, caddr_t); 3235 /* finish the last word of the previous mbuf */ 3236 if (wantbyte) { 3237 savebyte[1] = *data; 3238 *d = *((ushort *) savebyte); 3239 data++; len--; wantbyte = 0; 3240 } 3241 /* output contiguous words */ 3242 if ((len > 3) && (use_32bit_accesses)) { 3243 volatile u_long *const dl = 3244 (volatile u_long *) d; 3245 u_long *sl = (u_long *) data; 3246 u_long *fence = sl + (len >> 2); 3247 3248 while (sl < fence) 3249 *dl = *sl++; 3250 3251 data += (len & ~3); 3252 len &= 3; 3253 } 3254 /* finish off remain 16 bit writes */ 3255 if (len > 1) { 3256 u_short *s = (u_short *) data; 3257 u_short *fence = s + (len >> 1); 3258 3259 while (s < fence) 3260 *d = *s++; 3261 3262 data += (len & ~1); 3263 len &= 1; 3264 } 3265 /* save last byte if needed */ 3266 if (wantbyte = (len == 1)) 3267 savebyte[0] = *data; 3268 } 3269 m = m->m_next; /* to next mbuf */ 3270 } 3271 if (wantbyte) /* write last byte */ 3272 *d = *((u_short *) savebyte); 3273 } else { 3274 /* use programmed I/O */ 3275 while (m) { 3276 total_len += (len = m->m_len); 3277 if (len) { 3278 caddr_t data = mtod(m, caddr_t); 3279 /* finish the last word of the previous mbuf */ 3280 if (wantbyte) { 3281 savebyte[1] = *data; 3282 outw(sc->asic_addr + ED_HPP_PAGE_4, 3283 *((u_short *)savebyte)); 3284 data++; 3285 len--; 3286 wantbyte = 0; 3287 } 3288 /* output contiguous words */ 3289 if ((len > 3) && use_32bit_accesses) { 3290 outsl(sc->asic_addr + ED_HPP_PAGE_4, 3291 data, len >> 2); 3292 data += (len & ~3); 3293 len &= 3; 3294 } 3295 /* finish off remaining 16 bit accesses */ 3296 if (len > 1) { 3297 outsw(sc->asic_addr + ED_HPP_PAGE_4, 3298 data, len >> 1); 3299 data += (len & ~1); 3300 len &= 1; 3301 } 3302 if (wantbyte = (len == 1)) 3303 savebyte[0] = *data; 3304 3305 } /* if len != 0 */ 3306 m = m->m_next; 3307 } 3308 if (wantbyte) /* spit last byte */ 3309 outw(sc->asic_addr + ED_HPP_PAGE_4, 3310 *(u_short *)savebyte); 3311 3312 } 3313 3314 if (sc->hpp_mem_start) /* turn off memory mapped i/o */ 3315 outw(sc->asic_addr + ED_HPP_OPTION, 3316 sc->hpp_options); 3317 3318 return (total_len); 3319 } 3320 3321 static void 3322 ed_setrcr(sc) 3323 struct ed_softc *sc; 3324 { 3325 struct ifnet *ifp = (struct ifnet *)sc; 3326 int i; 3327 3328 /* set page 1 registers */ 3329 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP); 3330 3331 if (ifp->if_flags & IFF_PROMISC) { 3332 3333 /* 3334 * Reconfigure the multicast filter. 3335 */ 3336 for (i = 0; i < 8; i++) 3337 outb(sc->nic_addr + ED_P1_MAR(i), 0xff); 3338 3339 /* 3340 * And turn on promiscuous mode. Also enable reception of 3341 * runts and packets with CRC & alignment errors. 3342 */ 3343 /* Set page 0 registers */ 3344 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3345 3346 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM | 3347 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP); 3348 } else { 3349 /* set up multicast addresses and filter modes */ 3350 if (ifp->if_flags & IFF_MULTICAST) { 3351 u_long mcaf[2]; 3352 3353 if (ifp->if_flags & IFF_ALLMULTI) { 3354 mcaf[0] = 0xffffffff; 3355 mcaf[1] = 0xffffffff; 3356 } else 3357 ds_getmcaf(sc, mcaf); 3358 3359 /* 3360 * Set multicast filter on chip. 3361 */ 3362 for (i = 0; i < 8; i++) 3363 outb(sc->nic_addr + ED_P1_MAR(i), ((u_char *) mcaf)[i]); 3364 3365 /* Set page 0 registers */ 3366 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3367 3368 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB); 3369 } else { 3370 3371 /* 3372 * Initialize multicast address hashing registers to 3373 * not accept multicasts. 3374 */ 3375 for (i = 0; i < 8; ++i) 3376 outb(sc->nic_addr + ED_P1_MAR(i), 0x00); 3377 3378 /* Set page 0 registers */ 3379 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP); 3380 3381 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB); 3382 } 3383 } 3384 3385 /* 3386 * Start interface. 3387 */ 3388 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA); 3389 } 3390 3391 /* 3392 * Compute crc for ethernet address 3393 */ 3394 static u_long 3395 ds_crc(ep) 3396 u_char *ep; 3397 { 3398 #define POLYNOMIAL 0x04c11db6 3399 register u_long crc = 0xffffffffL; 3400 register int carry, i, j; 3401 register u_char b; 3402 3403 for (i = 6; --i >= 0;) { 3404 b = *ep++; 3405 for (j = 8; --j >= 0;) { 3406 carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); 3407 crc <<= 1; 3408 b >>= 1; 3409 if (carry) 3410 crc = ((crc ^ POLYNOMIAL) | carry); 3411 } 3412 } 3413 return crc; 3414 #undef POLYNOMIAL 3415 } 3416 3417 /* 3418 * Compute the multicast address filter from the 3419 * list of multicast addresses we need to listen to. 3420 */ 3421 static void 3422 ds_getmcaf(sc, mcaf) 3423 struct ed_softc *sc; 3424 u_long *mcaf; 3425 { 3426 register u_int index; 3427 register u_char *af = (u_char *) mcaf; 3428 struct ifmultiaddr *ifma; 3429 3430 mcaf[0] = 0; 3431 mcaf[1] = 0; 3432 3433 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma; 3434 ifma = ifma->ifma_link.le_next) { 3435 if (ifma->ifma_addr->sa_family != AF_LINK) 3436 continue; 3437 index = ds_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)) 3438 >> 26; 3439 af[index >> 3] |= 1 << (index & 7); 3440 } 3441 } 3442 3443 /* 3444 * support PnP cards if we are using 'em 3445 */ 3446 3447 #if NPNP > 0 3448 3449 static pnpid_t edpnp_ids[] = { 3450 { 0xd680d041, "NE2000"}, 3451 { 0 } 3452 }; 3453 3454 static char *edpnp_probe(u_long csn, u_long vend_id); 3455 static void edpnp_attach(u_long csn, u_long vend_id, char *name, 3456 struct isa_device *dev); 3457 static u_long nedpnp = NED; 3458 3459 static struct pnp_device edpnp = { 3460 "edpnp", 3461 edpnp_probe, 3462 edpnp_attach, 3463 &nedpnp, 3464 &net_imask 3465 }; 3466 DATA_SET (pnpdevice_set, edpnp); 3467 3468 static char * 3469 edpnp_probe(u_long csn, u_long vend_id) 3470 { 3471 pnpid_t *id; 3472 char *s = NULL; 3473 3474 for(id = edpnp_ids; id->vend_id != 0; id++) { 3475 if (vend_id == id->vend_id) { 3476 s = id->id_str; 3477 break; 3478 } 3479 } 3480 3481 if (s) { 3482 struct pnp_cinfo d; 3483 read_pnp_parms(&d, 0); 3484 if (d.enable == 0 || d.flags & 1) { 3485 printf("CSN %lu is disabled.\n", csn); 3486 return (NULL); 3487 } 3488 3489 } 3490 3491 return (s); 3492 } 3493 3494 static void 3495 edpnp_attach(u_long csn, u_long vend_id, char *name, struct isa_device *dev) 3496 { 3497 struct pnp_cinfo d; 3498 struct isa_device *dvp; 3499 3500 if (dev->id_unit >= NEDTOT) 3501 return; 3502 3503 if (read_pnp_parms(&d, 0) == 0) { 3504 printf("failed to read pnp parms\n"); 3505 return; 3506 } 3507 3508 write_pnp_parms(&d, 0); 3509 3510 enable_pnp_card(); 3511 3512 dev->id_iobase = d.port[0]; 3513 dev->id_irq = (1 << d.irq[0]); 3514 dev->id_ointr = edintr; 3515 dev->id_drq = -1; 3516 3517 if (dev->id_driver == NULL) { 3518 dev->id_driver = &eddriver; 3519 dvp = find_isadev(isa_devtab_net, &eddriver, 0); 3520 if (dvp != NULL) 3521 dev->id_id = dvp->id_id; 3522 } 3523 3524 if ((dev->id_alive = ed_probe(dev)) != 0) 3525 ed_attach_isa(dev); 3526 else 3527 printf("ed%d: probe failed\n", dev->id_unit); 3528 } 3529 #endif
Cache object: 1b10449b840352e9782065c47eff5546
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