The Design and Implementation of the FreeBSD Operating System, Second Edition
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FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/if_ed.c

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    1 /*
    2  * Copyright (c) 1995, David Greenman
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice unmodified, this list of conditions, and the following
   10  *    disclaimer.
   11  * 2. Redistributions in binary form must reproduce the above copyright
   12  *    notice, this list of conditions and the following disclaimer in the
   13  *    documentation and/or other materials provided with the distribution.
   14  *
   15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
   16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
   17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
   18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
   19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
   20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
   21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
   22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
   23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
   24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
   25  * SUCH DAMAGE.
   26  *
   27  * $FreeBSD: src/sys/i386/isa/if_ed.c,v 1.107.2.11 1999/09/05 08:12:44 peter Exp $
   28  */
   29 
   30 /*
   31  * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
   32  *   adapters. By David Greenman, 29-April-1993
   33  *
   34  * Currently supports the Western Digital/SMC 8003 and 8013 series,
   35  *   the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
   36  *   and a variety of similar clones.
   37  *
   38  */
   39 
   40 #include "ed.h"
   41 #include "bpfilter.h"
   42 
   43 #include <sys/param.h>
   44 #include <sys/kernel.h>
   45 #include <sys/systm.h>
   46 #include <sys/conf.h>
   47 #include <sys/errno.h>
   48 #include <sys/ioctl.h>
   49 #include <sys/mbuf.h>
   50 #include <sys/socket.h>
   51 #include <sys/syslog.h>
   52 
   53 #include <net/if.h>
   54 #include <net/if_dl.h>
   55 #include <net/if_mib.h>
   56 #include <net/if_types.h>
   57 
   58 #ifdef INET
   59 #include <netinet/in.h>
   60 #include <netinet/in_systm.h>
   61 #include <netinet/in_var.h>
   62 #include <netinet/ip.h>
   63 #include <netinet/if_ether.h>
   64 #endif
   65 
   66 #ifdef IPX
   67 #include <netipx/ipx.h>
   68 #include <netipx/ipx_if.h>
   69 #endif
   70 
   71 #ifdef NS
   72 #include <netns/ns.h>
   73 #include <netns/ns_if.h>
   74 #endif
   75 
   76 #if NBPFILTER > 0
   77 #include <net/bpf.h>
   78 #include <net/bpfdesc.h>
   79 #endif
   80 #ifdef BRIDGE
   81 #include <net/bridge.h>
   82 #endif
   83 
   84 #include <machine/clock.h>
   85 #include <machine/md_var.h>
   86 
   87 #include <i386/isa/isa_device.h>
   88 #include <i386/isa/icu.h>
   89 #include <i386/isa/if_edreg.h>
   90 
   91 /*
   92  * ed_softc: per line info and status
   93  */
   94 struct ed_softc {
   95         struct arpcom arpcom;   /* ethernet common */
   96 
   97         char   *type_str;       /* pointer to type string */
   98         u_char  vendor;         /* interface vendor */
   99         u_char  type;           /* interface type code */
  100         u_char  gone;           /* HW missing, presumed having a good time */
  101 
  102         u_short asic_addr;      /* ASIC I/O bus address */
  103         u_short nic_addr;       /* NIC (DS8390) I/O bus address */
  104 
  105 /*
  106  * The following 'proto' variable is part of a work-around for 8013EBT asics
  107  *      being write-only. It's sort of a prototype/shadow of the real thing.
  108  */
  109         u_char  wd_laar_proto;
  110         u_char  cr_proto;
  111         u_char  isa16bit;       /* width of access to card 0=8 or 1=16 */
  112         int     is790;          /* set by the probe code if the card is 790
  113                                  * based */
  114 
  115 /*
  116  * HP PC LAN PLUS card support.
  117  */
  118 
  119         u_short hpp_options;    /* flags controlling behaviour of the HP card */
  120         u_short hpp_id;         /* software revision and other fields */
  121         caddr_t hpp_mem_start;  /* Memory-mapped IO register address */
  122 
  123         caddr_t mem_start;      /* NIC memory start address */
  124         caddr_t mem_end;        /* NIC memory end address */
  125         u_long  mem_size;       /* total NIC memory size */
  126         caddr_t mem_ring;       /* start of RX ring-buffer (in NIC mem) */
  127 
  128         u_char  mem_shared;     /* NIC memory is shared with host */
  129         u_char  xmit_busy;      /* transmitter is busy */
  130         u_char  txb_cnt;        /* number of transmit buffers */
  131         u_char  txb_inuse;      /* number of TX buffers currently in-use */
  132 
  133         u_char  txb_new;        /* pointer to where new buffer will be added */
  134         u_char  txb_next_tx;    /* pointer to next buffer ready to xmit */
  135         u_short txb_len[8];     /* buffered xmit buffer lengths */
  136         u_char  tx_page_start;  /* first page of TX buffer area */
  137         u_char  rec_page_start; /* first page of RX ring-buffer */
  138         u_char  rec_page_stop;  /* last page of RX ring-buffer */
  139         u_char  next_packet;    /* pointer to next unread RX packet */
  140         struct  ifmib_iso_8802_3 mibdata; /* stuff for network mgmt */
  141 };
  142 
  143 static struct ed_softc ed_softc[NED];
  144 
  145 static int ed_attach            __P((struct ed_softc *, int, int));
  146 static int ed_attach_isa        __P((struct isa_device *));
  147 
  148 static void ed_init             __P((void *));
  149 static int ed_ioctl             __P((struct ifnet *, int, caddr_t));
  150 static int ed_probe             __P((struct isa_device *));
  151 static void ed_start            __P((struct ifnet *));
  152 static void ed_reset            __P((struct ifnet *));
  153 static void ed_watchdog         __P((struct ifnet *));
  154 
  155 static void ed_stop             __P((struct ed_softc *));
  156 static int ed_probe_generic8390 __P((struct ed_softc *));
  157 static int ed_probe_WD80x3      __P((struct isa_device *));
  158 static int ed_probe_3Com        __P((struct isa_device *));
  159 static int ed_probe_Novell      __P((struct isa_device *));
  160 static int ed_probe_Novell_generic __P((struct ed_softc *, int, int, int));
  161 static int ed_probe_HP_pclanp   __P((struct isa_device *));
  162 
  163 #include "pci.h"
  164 #if NPCI > 0
  165 void *ed_attach_NE2000_pci      __P((int, int));
  166 #endif
  167 
  168 #include "card.h"
  169 #if NCARD > 0
  170 static int ed_probe_pccard      __P((struct isa_device *, u_char *));
  171 #endif
  172 
  173 static void    ds_getmcaf __P((struct ed_softc *, u_long *));
  174 
  175 static void ed_get_packet(struct ed_softc *, char *, /* u_short */ int, int);
  176 
  177 static void     ed_rint __P((struct ed_softc *));
  178 static void     ed_xmit __P((struct ed_softc *));
  179 static char *   ed_ring_copy __P((struct ed_softc *, char *, char *,
  180                                   /* u_short */ int));
  181 static void     ed_hpp_set_physical_link __P((struct ed_softc *));
  182 static void     ed_hpp_readmem __P((struct ed_softc *, int, unsigned char *,
  183                                     /* u_short */ int));
  184 static u_short  ed_hpp_write_mbufs __P((struct ed_softc *, struct mbuf *,
  185                                         int));
  186 
  187 static void     ed_pio_readmem __P((struct ed_softc *, int, unsigned char *,
  188                                     /* u_short */ int));
  189 static void     ed_pio_writemem __P((struct ed_softc *, char *,
  190                                      /* u_short */ int, /* u_short */ int));
  191 static u_short  ed_pio_write_mbufs __P((struct ed_softc *, struct mbuf *,
  192                                         int));
  193 void edintr_sc                  __P((struct ed_softc *));
  194 
  195 static void    ed_setrcr(struct ed_softc *);
  196 
  197 static u_long ds_crc(u_char *ep);
  198 
  199 #if NCARD > 0
  200 #include <sys/select.h>
  201 #include <pccard/cardinfo.h>
  202 #include <pccard/driver.h>
  203 #include <pccard/slot.h>
  204 
  205 /*
  206  *      PC-Card (PCMCIA) specific code.
  207  */
  208 static int edinit(struct pccard_devinfo *);             /* init device */
  209 static void edunload(struct pccard_devinfo *);          /* Disable driver */
  210 static int card_intr(struct pccard_devinfo *);          /* Interrupt handler */
  211 
  212 static struct pccard_device ed_info = {
  213         "ed",
  214         edinit,
  215         edunload,
  216         card_intr,
  217         0,                      /* Attributes - presently unused */
  218         &net_imask              /* Interrupt mask for device */
  219                                 /* XXX - Should this also include net_imask? */
  220 };
  221 
  222 DATA_SET(pccarddrv_set, ed_info);
  223 
  224 /*
  225  *      Initialize the device - called from Slot manager.
  226  */
  227 static int
  228 edinit(struct pccard_devinfo *devi)
  229 {
  230         struct ed_softc *sc = &ed_softc[devi->isahd.id_unit];
  231 
  232         /* validate unit number. */
  233         if (devi->isahd.id_unit >= NED)
  234                 return(ENODEV);
  235         /*
  236          * Probe the device. If a value is returned, the
  237          * device was found at the location.
  238          */
  239         sc->gone = 0;
  240         if (ed_probe_pccard(&devi->isahd, devi->misc) == 0)
  241                 return(ENXIO);
  242         if (ed_attach_isa(&devi->isahd) == 0)
  243                 return(ENXIO);
  244 
  245         return(0);
  246 }
  247 
  248 /*
  249  *      edunload - unload the driver and clear the table.
  250  *      XXX TODO:
  251  *      This is usually called when the card is ejected, but
  252  *      can be caused by a modunload of a controller driver.
  253  *      The idea is to reset the driver's view of the device
  254  *      and ensure that any driver entry points such as
  255  *      read and write do not hang.
  256  */
  257 static void
  258 edunload(struct pccard_devinfo *devi)
  259 {
  260         struct ed_softc *sc = &ed_softc[devi->isahd.id_unit];
  261         struct ifnet *ifp = &sc->arpcom.ac_if;
  262 
  263         if (sc->gone) {
  264                 printf("ed%d: already unloaded\n", devi->isahd.id_unit);
  265                 return;
  266         }
  267         ifp->if_flags &= ~IFF_RUNNING;
  268         if_down(ifp);
  269         sc->gone = 1;
  270         printf("ed%d: unload\n", devi->isahd.id_unit);
  271 }
  272 
  273 /*
  274  *      card_intr - Shared interrupt called from
  275  *      front end of PC-Card handler.
  276  */
  277 static int
  278 card_intr(struct pccard_devinfo *devi)
  279 {
  280         edintr_sc(&ed_softc[devi->isahd.id_unit]);
  281         return(1);
  282 }
  283 #endif /* NCARD > 0 */
  284 
  285 struct isa_driver eddriver = {
  286         ed_probe,
  287         ed_attach_isa,
  288         "ed",
  289         1               /* We are ultra sensitive */
  290 };
  291 
  292 /*
  293  * Interrupt conversion table for WD/SMC ASIC/83C584
  294  * (IRQ* are defined in icu.h)
  295  */
  296 static unsigned short ed_intr_mask[] = {
  297         IRQ9,
  298         IRQ3,
  299         IRQ5,
  300         IRQ7,
  301         IRQ10,
  302         IRQ11,
  303         IRQ15,
  304         IRQ4
  305 };
  306 
  307 /*
  308  * Interrupt conversion table for 83C790
  309  */
  310 static unsigned short ed_790_intr_mask[] = {
  311         0,
  312         IRQ9,
  313         IRQ3,
  314         IRQ5,
  315         IRQ7,
  316         IRQ10,
  317         IRQ11,
  318         IRQ15
  319 };
  320 
  321 /*
  322  * Interrupt conversion table for the HP PC LAN+
  323  */
  324 
  325 static unsigned short ed_hpp_intr_mask[] = {
  326         0,              /* 0 */
  327         0,              /* 1 */
  328         0,              /* 2 */
  329         IRQ3,           /* 3 */
  330         IRQ4,           /* 4 */
  331         IRQ5,           /* 5 */
  332         IRQ6,           /* 6 */
  333         IRQ7,           /* 7 */
  334         0,              /* 8 */
  335         IRQ9,           /* 9 */
  336         IRQ10,          /* 10 */
  337         IRQ11,          /* 11 */
  338         IRQ12,          /* 12 */
  339         0,              /* 13 */
  340         0,              /* 14 */
  341         IRQ15           /* 15 */
  342 };
  343 
  344 /*
  345  * Determine if the device is present
  346  *
  347  *   on entry:
  348  *      a pointer to an isa_device struct
  349  *   on exit:
  350  *      NULL if device not found
  351  *      or # of i/o addresses used (if found)
  352  */
  353 static int
  354 ed_probe(isa_dev)
  355         struct isa_device *isa_dev;
  356 {
  357         int     nports;
  358 
  359         nports = ed_probe_WD80x3(isa_dev);
  360         if (nports)
  361                 return (nports);
  362 
  363         nports = ed_probe_3Com(isa_dev);
  364         if (nports)
  365                 return (nports);
  366 
  367         nports = ed_probe_Novell(isa_dev);
  368         if (nports)
  369                 return (nports);
  370 
  371         nports = ed_probe_HP_pclanp(isa_dev);
  372         if (nports)
  373                 return (nports);
  374 
  375         return (0);
  376 }
  377 
  378 /*
  379  * Generic probe routine for testing for the existance of a DS8390.
  380  *      Must be called after the NIC has just been reset. This routine
  381  *      works by looking at certain register values that are guaranteed
  382  *      to be initialized a certain way after power-up or reset. Seems
  383  *      not to currently work on the 83C690.
  384  *
  385  * Specifically:
  386  *
  387  *      Register                        reset bits      set bits
  388  *      Command Register (CR)           TXP, STA        RD2, STP
  389  *      Interrupt Status (ISR)                          RST
  390  *      Interrupt Mask (IMR)            All bits
  391  *      Data Control (DCR)                              LAS
  392  *      Transmit Config. (TCR)          LB1, LB0
  393  *
  394  * We only look at the CR and ISR registers, however, because looking at
  395  *      the others would require changing register pages (which would be
  396  *      intrusive if this isn't an 8390).
  397  *
  398  * Return 1 if 8390 was found, 0 if not.
  399  */
  400 
  401 static int
  402 ed_probe_generic8390(sc)
  403         struct ed_softc *sc;
  404 {
  405         if ((inb(sc->nic_addr + ED_P0_CR) &
  406              (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
  407             (ED_CR_RD2 | ED_CR_STP))
  408                 return (0);
  409         if ((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
  410                 return (0);
  411 
  412         return (1);
  413 }
  414 
  415 /*
  416  * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
  417  */
  418 static int
  419 ed_probe_WD80x3(isa_dev)
  420         struct isa_device *isa_dev;
  421 {
  422         struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
  423         int     i;
  424         u_int   memsize, maddr;
  425         u_char  iptr, isa16bit, sum;
  426 
  427         sc->asic_addr = isa_dev->id_iobase;
  428         sc->nic_addr = sc->asic_addr + ED_WD_NIC_OFFSET;
  429         sc->is790 = 0;
  430 
  431 #ifdef TOSH_ETHER
  432         outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_POW);
  433         DELAY(10000);
  434 #endif
  435 
  436         /*
  437          * Attempt to do a checksum over the station address PROM. If it
  438          * fails, it's probably not a SMC/WD board. There is a problem with
  439          * this, though: some clone WD boards don't pass the checksum test.
  440          * Danpex boards for one.
  441          */
  442         for (sum = 0, i = 0; i < 8; ++i)
  443                 sum += inb(sc->asic_addr + ED_WD_PROM + i);
  444 
  445         if (sum != ED_WD_ROM_CHECKSUM_TOTAL) {
  446 
  447                 /*
  448                  * Checksum is invalid. This often happens with cheap WD8003E
  449                  * clones.  In this case, the checksum byte (the eighth byte)
  450                  * seems to always be zero.
  451                  */
  452                 if (inb(sc->asic_addr + ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
  453                     inb(sc->asic_addr + ED_WD_PROM + 7) != 0)
  454                         return (0);
  455         }
  456         /* reset card to force it into a known state. */
  457 #ifdef TOSH_ETHER
  458         outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
  459 #else
  460         outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_RST);
  461 #endif
  462         DELAY(100);
  463         outb(sc->asic_addr + ED_WD_MSR, inb(sc->asic_addr + ED_WD_MSR) & ~ED_WD_MSR_RST);
  464         /* wait in the case this card is reading it's EEROM */
  465         DELAY(5000);
  466 
  467         sc->vendor = ED_VENDOR_WD_SMC;
  468         sc->type = inb(sc->asic_addr + ED_WD_CARD_ID);
  469 
  470         /*
  471          * Set initial values for width/size.
  472          */
  473         memsize = 8192;
  474         isa16bit = 0;
  475         switch (sc->type) {
  476         case ED_TYPE_WD8003S:
  477                 sc->type_str = "WD8003S";
  478                 break;
  479         case ED_TYPE_WD8003E:
  480                 sc->type_str = "WD8003E";
  481                 break;
  482         case ED_TYPE_WD8003EB:
  483                 sc->type_str = "WD8003EB";
  484                 break;
  485         case ED_TYPE_WD8003W:
  486                 sc->type_str = "WD8003W";
  487                 break;
  488         case ED_TYPE_WD8013EBT:
  489                 sc->type_str = "WD8013EBT";
  490                 memsize = 16384;
  491                 isa16bit = 1;
  492                 break;
  493         case ED_TYPE_WD8013W:
  494                 sc->type_str = "WD8013W";
  495                 memsize = 16384;
  496                 isa16bit = 1;
  497                 break;
  498         case ED_TYPE_WD8013EP:  /* also WD8003EP */
  499                 if (inb(sc->asic_addr + ED_WD_ICR)
  500                     & ED_WD_ICR_16BIT) {
  501                         isa16bit = 1;
  502                         memsize = 16384;
  503                         sc->type_str = "WD8013EP";
  504                 } else {
  505                         sc->type_str = "WD8003EP";
  506                 }
  507                 break;
  508         case ED_TYPE_WD8013WC:
  509                 sc->type_str = "WD8013WC";
  510                 memsize = 16384;
  511                 isa16bit = 1;
  512                 break;
  513         case ED_TYPE_WD8013EBP:
  514                 sc->type_str = "WD8013EBP";
  515                 memsize = 16384;
  516                 isa16bit = 1;
  517                 break;
  518         case ED_TYPE_WD8013EPC:
  519                 sc->type_str = "WD8013EPC";
  520                 memsize = 16384;
  521                 isa16bit = 1;
  522                 break;
  523         case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
  524         case ED_TYPE_SMC8216T:
  525                 if (sc->type == ED_TYPE_SMC8216C) {
  526                         sc->type_str = "SMC8216/SMC8216C";
  527                 } else {
  528                         sc->type_str = "SMC8216T";
  529                 }
  530 
  531                 outb(sc->asic_addr + ED_WD790_HWR,
  532                     inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH);
  533                 switch (inb(sc->asic_addr + ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
  534                 case ED_WD790_RAR_SZ64:
  535                         memsize = 65536;
  536                         break;
  537                 case ED_WD790_RAR_SZ32:
  538                         memsize = 32768;
  539                         break;
  540                 case ED_WD790_RAR_SZ16:
  541                         memsize = 16384;
  542                         break;
  543                 case ED_WD790_RAR_SZ8:
  544                         /* 8216 has 16K shared mem -- 8416 has 8K */
  545                         if (sc->type == ED_TYPE_SMC8216C) {
  546                                 sc->type_str = "SMC8416C/SMC8416BT";
  547                         } else {
  548                                 sc->type_str = "SMC8416T";
  549                         }
  550                         memsize = 8192;
  551                         break;
  552                 }
  553                 outb(sc->asic_addr + ED_WD790_HWR,
  554                     inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
  555 
  556                 isa16bit = 1;
  557                 sc->is790 = 1;
  558                 break;
  559 #ifdef TOSH_ETHER
  560         case ED_TYPE_TOSHIBA1:
  561                 sc->type_str = "Toshiba1";
  562                 memsize = 32768;
  563                 isa16bit = 1;
  564                 break;
  565         case ED_TYPE_TOSHIBA4:
  566                 sc->type_str = "Toshiba4";
  567                 memsize = 32768;
  568                 isa16bit = 1;
  569                 break;
  570 #endif
  571         default:
  572                 sc->type_str = "";
  573                 break;
  574         }
  575 
  576         /*
  577          * Make some adjustments to initial values depending on what is found
  578          * in the ICR.
  579          */
  580         if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
  581 #ifdef TOSH_ETHER
  582           && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
  583 #endif
  584             && ((inb(sc->asic_addr + ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
  585                 isa16bit = 0;
  586                 memsize = 8192;
  587         }
  588 
  589 #if ED_DEBUG
  590         printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
  591                sc->type, sc->type_str, isa16bit, memsize, isa_dev->id_msize);
  592         for (i = 0; i < 8; i++)
  593                 printf("%x -> %x\n", i, inb(sc->asic_addr + i));
  594 #endif
  595 
  596         /*
  597          * Allow the user to override the autoconfiguration
  598          */
  599         if (isa_dev->id_msize)
  600                 memsize = isa_dev->id_msize;
  601 
  602         maddr = (u_int) isa_dev->id_maddr & 0xffffff;
  603         if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
  604                 printf("ed%d: Invalid ISA memory address range configured: 0x%x - 0x%x\n",
  605                     isa_dev->id_unit, maddr, maddr + memsize);
  606                 return 0;
  607         }
  608 
  609         /*
  610          * (note that if the user specifies both of the following flags that
  611          * '8bit' mode intentionally has precedence)
  612          */
  613         if (isa_dev->id_flags & ED_FLAGS_FORCE_16BIT_MODE)
  614                 isa16bit = 1;
  615         if (isa_dev->id_flags & ED_FLAGS_FORCE_8BIT_MODE)
  616                 isa16bit = 0;
  617 
  618         /*
  619          * If possible, get the assigned interrupt number from the card and
  620          * use it.
  621          */
  622         if ((sc->type & ED_WD_SOFTCONFIG) && (!sc->is790)) {
  623 
  624                 /*
  625                  * Assemble together the encoded interrupt number.
  626                  */
  627                 iptr = (inb(isa_dev->id_iobase + ED_WD_ICR) & ED_WD_ICR_IR2) |
  628                     ((inb(isa_dev->id_iobase + ED_WD_IRR) &
  629                       (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
  630 
  631                 /*
  632                  * If no interrupt specified (or "?"), use what the board tells us.
  633                  */
  634                 if (isa_dev->id_irq <= 0)
  635                         isa_dev->id_irq = ed_intr_mask[iptr];
  636 
  637                 /*
  638                  * Enable the interrupt.
  639                  */
  640                 outb(isa_dev->id_iobase + ED_WD_IRR,
  641                      inb(isa_dev->id_iobase + ED_WD_IRR) | ED_WD_IRR_IEN);
  642         }
  643         if (sc->is790) {
  644                 outb(isa_dev->id_iobase + ED_WD790_HWR,
  645                   inb(isa_dev->id_iobase + ED_WD790_HWR) | ED_WD790_HWR_SWH);
  646                 iptr = (((inb(isa_dev->id_iobase + ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
  647                         (inb(isa_dev->id_iobase + ED_WD790_GCR) &
  648                          (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
  649                 outb(isa_dev->id_iobase + ED_WD790_HWR,
  650                  inb(isa_dev->id_iobase + ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
  651 
  652                 /*
  653                  * If no interrupt specified (or "?"), use what the board tells us.
  654                  */
  655                 if (isa_dev->id_irq <= 0)
  656                         isa_dev->id_irq = ed_790_intr_mask[iptr];
  657 
  658                 /*
  659                  * Enable interrupts.
  660                  */
  661                 outb(isa_dev->id_iobase + ED_WD790_ICR,
  662                   inb(isa_dev->id_iobase + ED_WD790_ICR) | ED_WD790_ICR_EIL);
  663         }
  664         if (isa_dev->id_irq <= 0) {
  665                 printf("ed%d: %s cards don't support auto-detected/assigned interrupts.\n",
  666                     isa_dev->id_unit, sc->type_str);
  667                 return (0);
  668         }
  669         sc->isa16bit = isa16bit;
  670         sc->mem_shared = 1;
  671         isa_dev->id_msize = memsize;
  672         sc->mem_start = (caddr_t) isa_dev->id_maddr;
  673 
  674         /*
  675          * allocate one xmit buffer if < 16k, two buffers otherwise
  676          */
  677         if ((memsize < 16384) ||
  678             (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
  679                 sc->txb_cnt = 1;
  680         } else {
  681                 sc->txb_cnt = 2;
  682         }
  683         sc->tx_page_start = ED_WD_PAGE_OFFSET;
  684         sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
  685         sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
  686         sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
  687         sc->mem_size = memsize;
  688         sc->mem_end = sc->mem_start + memsize;
  689 
  690         /*
  691          * Get station address from on-board ROM
  692          */
  693         for (i = 0; i < ETHER_ADDR_LEN; ++i)
  694                 sc->arpcom.ac_enaddr[i] = inb(sc->asic_addr + ED_WD_PROM + i);
  695 
  696         /*
  697          * Set upper address bits and 8/16 bit access to shared memory.
  698          */
  699         if (isa16bit) {
  700                 if (sc->is790) {
  701                         sc->wd_laar_proto = inb(sc->asic_addr + ED_WD_LAAR);
  702                 } else {
  703                         sc->wd_laar_proto = ED_WD_LAAR_L16EN |
  704                             ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
  705                 }
  706                 /*
  707                  * Enable 16bit access
  708                  */
  709                 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto |
  710                     ED_WD_LAAR_M16EN);
  711         } else {
  712                 if (((sc->type & ED_WD_SOFTCONFIG) ||
  713 #ifdef TOSH_ETHER
  714                     (sc->type == ED_TYPE_TOSHIBA1) || (sc->type == ED_TYPE_TOSHIBA4) ||
  715 #endif
  716                     (sc->type == ED_TYPE_WD8013EBT)) && (!sc->is790)) {
  717                         sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
  718                             ED_WD_LAAR_ADDRHI;
  719                         outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto);
  720                 }
  721         }
  722 
  723         /*
  724          * Set address and enable interface shared memory.
  725          */
  726         if (!sc->is790) {
  727 #ifdef TOSH_ETHER
  728                 outb(sc->asic_addr + ED_WD_MSR + 1, ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
  729                 outb(sc->asic_addr + ED_WD_MSR + 2, ((kvtop(sc->mem_start) >> 16) & 0x0f));
  730                 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB | ED_WD_MSR_POW);
  731 
  732 #else
  733                 outb(sc->asic_addr + ED_WD_MSR, ((kvtop(sc->mem_start) >> 13) &
  734                     ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
  735 #endif
  736                 sc->cr_proto = ED_CR_RD2;
  737         } else {
  738                 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
  739                 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) | ED_WD790_HWR_SWH));
  740                 outb(sc->asic_addr + ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
  741                      ((kvtop(sc->mem_start) >> 11) & 0x40) |
  742                      (inb(sc->asic_addr + ED_WD790_RAR) & 0xb0));
  743                 outb(sc->asic_addr + ED_WD790_HWR, (inb(sc->asic_addr + ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
  744                 sc->cr_proto = 0;
  745         }
  746 
  747 #if 0
  748         printf("starting memory performance test at 0x%x, size %d...\n",
  749                 sc->mem_start, memsize*16384);
  750         for (i = 0; i < 16384; i++)
  751                 bzero(sc->mem_start, memsize);
  752         printf("***DONE***\n");
  753 #endif
  754 
  755         /*
  756          * Now zero memory and verify that it is clear
  757          */
  758         bzero(sc->mem_start, memsize);
  759 
  760         for (i = 0; i < memsize; ++i) {
  761                 if (sc->mem_start[i]) {
  762                         printf("ed%d: failed to clear shared memory at %lx - check configuration\n",
  763                             isa_dev->id_unit, kvtop(sc->mem_start + i));
  764 
  765                         /*
  766                          * Disable 16 bit access to shared memory
  767                          */
  768                         if (isa16bit) {
  769                                 if (sc->is790) {
  770                                         outb(sc->asic_addr + ED_WD_MSR, 0x00);
  771                                 }
  772                                 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
  773                                     ~ED_WD_LAAR_M16EN);
  774                         }
  775                         return (0);
  776                 }
  777         }
  778 
  779         /*
  780          * Disable 16bit access to shared memory - we leave it
  781          * disabled so that 1) machines reboot properly when the board
  782          * is set 16 bit mode and there are conflicting 8bit
  783          * devices/ROMS in the same 128k address space as this boards
  784          * shared memory. and 2) so that other 8 bit devices with
  785          * shared memory can be used in this 128k region, too.
  786          */
  787         if (isa16bit) {
  788                 if (sc->is790) {
  789                         outb(sc->asic_addr + ED_WD_MSR, 0x00);
  790                 }
  791                 outb(sc->asic_addr + ED_WD_LAAR, sc->wd_laar_proto &
  792                     ~ED_WD_LAAR_M16EN);
  793         }
  794         return (ED_WD_IO_PORTS);
  795 }
  796 
  797 /*
  798  * Probe and vendor-specific initialization routine for 3Com 3c503 boards
  799  */
  800 static int
  801 ed_probe_3Com(isa_dev)
  802         struct isa_device *isa_dev;
  803 {
  804         struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
  805         int     i;
  806         u_int   memsize;
  807         u_char  isa16bit;
  808 
  809         sc->asic_addr = isa_dev->id_iobase + ED_3COM_ASIC_OFFSET;
  810         sc->nic_addr = isa_dev->id_iobase + ED_3COM_NIC_OFFSET;
  811 
  812         /*
  813          * Verify that the kernel configured I/O address matches the board
  814          * configured address
  815          */
  816         switch (inb(sc->asic_addr + ED_3COM_BCFR)) {
  817         case ED_3COM_BCFR_300:
  818                 if (isa_dev->id_iobase != 0x300)
  819                         return (0);
  820                 break;
  821         case ED_3COM_BCFR_310:
  822                 if (isa_dev->id_iobase != 0x310)
  823                         return (0);
  824                 break;
  825         case ED_3COM_BCFR_330:
  826                 if (isa_dev->id_iobase != 0x330)
  827                         return (0);
  828                 break;
  829         case ED_3COM_BCFR_350:
  830                 if (isa_dev->id_iobase != 0x350)
  831                         return (0);
  832                 break;
  833         case ED_3COM_BCFR_250:
  834                 if (isa_dev->id_iobase != 0x250)
  835                         return (0);
  836                 break;
  837         case ED_3COM_BCFR_280:
  838                 if (isa_dev->id_iobase != 0x280)
  839                         return (0);
  840                 break;
  841         case ED_3COM_BCFR_2A0:
  842                 if (isa_dev->id_iobase != 0x2a0)
  843                         return (0);
  844                 break;
  845         case ED_3COM_BCFR_2E0:
  846                 if (isa_dev->id_iobase != 0x2e0)
  847                         return (0);
  848                 break;
  849         default:
  850                 return (0);
  851         }
  852 
  853         /*
  854          * Verify that the kernel shared memory address matches the board
  855          * configured address.
  856          */
  857         switch (inb(sc->asic_addr + ED_3COM_PCFR)) {
  858         case ED_3COM_PCFR_DC000:
  859                 if (kvtop(isa_dev->id_maddr) != 0xdc000)
  860                         return (0);
  861                 break;
  862         case ED_3COM_PCFR_D8000:
  863                 if (kvtop(isa_dev->id_maddr) != 0xd8000)
  864                         return (0);
  865                 break;
  866         case ED_3COM_PCFR_CC000:
  867                 if (kvtop(isa_dev->id_maddr) != 0xcc000)
  868                         return (0);
  869                 break;
  870         case ED_3COM_PCFR_C8000:
  871                 if (kvtop(isa_dev->id_maddr) != 0xc8000)
  872                         return (0);
  873                 break;
  874         default:
  875                 return (0);
  876         }
  877 
  878 
  879         /*
  880          * Reset NIC and ASIC. Enable on-board transceiver throughout reset
  881          * sequence because it'll lock up if the cable isn't connected if we
  882          * don't.
  883          */
  884         outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
  885 
  886         /*
  887          * Wait for a while, then un-reset it
  888          */
  889         DELAY(50);
  890 
  891         /*
  892          * The 3Com ASIC defaults to rather strange settings for the CR after
  893          * a reset - it's important to set it again after the following outb
  894          * (this is done when we map the PROM below).
  895          */
  896         outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
  897 
  898         /*
  899          * Wait a bit for the NIC to recover from the reset
  900          */
  901         DELAY(5000);
  902 
  903         sc->vendor = ED_VENDOR_3COM;
  904         sc->type_str = "3c503";
  905         sc->mem_shared = 1;
  906         sc->cr_proto = ED_CR_RD2;
  907 
  908         /*
  909          * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
  910          * to it.
  911          */
  912         memsize = 8192;
  913 
  914         /*
  915          * Get station address from on-board ROM
  916          */
  917 
  918         /*
  919          * First, map ethernet address PROM over the top of where the NIC
  920          * registers normally appear.
  921          */
  922         outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
  923 
  924         for (i = 0; i < ETHER_ADDR_LEN; ++i)
  925                 sc->arpcom.ac_enaddr[i] = inb(sc->nic_addr + i);
  926 
  927         /*
  928          * Unmap PROM - select NIC registers. The proper setting of the
  929          * tranceiver is set in ed_init so that the attach code is given a
  930          * chance to set the default based on a compile-time config option
  931          */
  932         outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
  933 
  934         /*
  935          * Determine if this is an 8bit or 16bit board
  936          */
  937 
  938         /*
  939          * select page 0 registers
  940          */
  941         outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
  942 
  943         /*
  944          * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
  945          * board.
  946          */
  947         outb(sc->nic_addr + ED_P0_DCR, 0);
  948 
  949         /*
  950          * select page 2 registers
  951          */
  952         outb(sc->nic_addr + ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
  953 
  954         /*
  955          * The 3c503 forces the WTS bit to a one if this is a 16bit board
  956          */
  957         if (inb(sc->nic_addr + ED_P2_DCR) & ED_DCR_WTS)
  958                 isa16bit = 1;
  959         else
  960                 isa16bit = 0;
  961 
  962         /*
  963          * select page 0 registers
  964          */
  965         outb(sc->nic_addr + ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
  966 
  967         sc->mem_start = (caddr_t) isa_dev->id_maddr;
  968         sc->mem_size = memsize;
  969         sc->mem_end = sc->mem_start + memsize;
  970 
  971         /*
  972          * We have an entire 8k window to put the transmit buffers on the
  973          * 16bit boards. But since the 16bit 3c503's shared memory is only
  974          * fast enough to overlap the loading of one full-size packet, trying
  975          * to load more than 2 buffers can actually leave the transmitter idle
  976          * during the load. So 2 seems the best value. (Although a mix of
  977          * variable-sized packets might change this assumption. Nonetheless,
  978          * we optimize for linear transfers of same-size packets.)
  979          */
  980         if (isa16bit) {
  981                 if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
  982                         sc->txb_cnt = 1;
  983                 else
  984                         sc->txb_cnt = 2;
  985 
  986                 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
  987                 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
  988                 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
  989                     ED_3COM_RX_PAGE_OFFSET_16BIT;
  990                 sc->mem_ring = sc->mem_start;
  991         } else {
  992                 sc->txb_cnt = 1;
  993                 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
  994                 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
  995                 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
  996                     ED_3COM_TX_PAGE_OFFSET_8BIT;
  997                 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
  998         }
  999 
 1000         sc->isa16bit = isa16bit;
 1001 
 1002         /*
 1003          * Initialize GA page start/stop registers. Probably only needed if
 1004          * doing DMA, but what the hell.
 1005          */
 1006         outb(sc->asic_addr + ED_3COM_PSTR, sc->rec_page_start);
 1007         outb(sc->asic_addr + ED_3COM_PSPR, sc->rec_page_stop);
 1008 
 1009         /*
 1010          * Set IRQ. 3c503 only allows a choice of irq 2-5.
 1011          */
 1012         switch (isa_dev->id_irq) {
 1013         case IRQ2:
 1014                 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
 1015                 break;
 1016         case IRQ3:
 1017                 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
 1018                 break;
 1019         case IRQ4:
 1020                 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
 1021                 break;
 1022         case IRQ5:
 1023                 outb(sc->asic_addr + ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
 1024                 break;
 1025         default:
 1026                 printf("ed%d: Invalid irq configuration (%d) must be 3-5,9 for 3c503\n",
 1027                        isa_dev->id_unit, ffs(isa_dev->id_irq) - 1);
 1028                 return (0);
 1029         }
 1030 
 1031         /*
 1032          * Initialize GA configuration register. Set bank and enable shared
 1033          * mem.
 1034          */
 1035         outb(sc->asic_addr + ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
 1036              ED_3COM_GACFR_MBS0);
 1037 
 1038         /*
 1039          * Initialize "Vector Pointer" registers. These gawd-awful things are
 1040          * compared to 20 bits of the address on ISA, and if they match, the
 1041          * shared memory is disabled. We set them to 0xffff0...allegedly the
 1042          * reset vector.
 1043          */
 1044         outb(sc->asic_addr + ED_3COM_VPTR2, 0xff);
 1045         outb(sc->asic_addr + ED_3COM_VPTR1, 0xff);
 1046         outb(sc->asic_addr + ED_3COM_VPTR0, 0x00);
 1047 
 1048         /*
 1049          * Zero memory and verify that it is clear
 1050          */
 1051         bzero(sc->mem_start, memsize);
 1052 
 1053         for (i = 0; i < memsize; ++i)
 1054                 if (sc->mem_start[i]) {
 1055                         printf("ed%d: failed to clear shared memory at %lx - check configuration\n",
 1056                                isa_dev->id_unit, kvtop(sc->mem_start + i));
 1057                         return (0);
 1058                 }
 1059         isa_dev->id_msize = memsize;
 1060         return (ED_3COM_IO_PORTS);
 1061 }
 1062 
 1063 /*
 1064  * Probe and vendor-specific initialization routine for NE1000/2000 boards
 1065  */
 1066 static int
 1067 ed_probe_Novell_generic(sc, port, unit, flags)
 1068         struct ed_softc *sc;
 1069         int port;
 1070         int unit;
 1071         int flags;
 1072 {
 1073         u_int   memsize, n;
 1074         u_char  romdata[16], tmp;
 1075         static char test_pattern[32] = "THIS is A memory TEST pattern";
 1076         char    test_buffer[32];
 1077 
 1078         sc->asic_addr = port + ED_NOVELL_ASIC_OFFSET;
 1079         sc->nic_addr = port + ED_NOVELL_NIC_OFFSET;
 1080 
 1081         /* XXX - do Novell-specific probe here */
 1082 
 1083         /* Reset the board */
 1084 #ifdef GWETHER
 1085         outb(sc->asic_addr + ED_NOVELL_RESET, 0);
 1086         DELAY(200);
 1087 #endif  /* GWETHER */
 1088         tmp = inb(sc->asic_addr + ED_NOVELL_RESET);
 1089 
 1090         /*
 1091          * I don't know if this is necessary; probably cruft leftover from
 1092          * Clarkson packet driver code. Doesn't do a thing on the boards I've
 1093          * tested. -DG [note that a outb(0x84, 0) seems to work here, and is
 1094          * non-invasive...but some boards don't seem to reset and I don't have
 1095          * complete documentation on what the 'right' thing to do is...so we
 1096          * do the invasive thing for now. Yuck.]
 1097          */
 1098         outb(sc->asic_addr + ED_NOVELL_RESET, tmp);
 1099         DELAY(5000);
 1100 
 1101         /*
 1102          * This is needed because some NE clones apparently don't reset the
 1103          * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
 1104          * - this makes the probe invasive! ...Done against my better
 1105          * judgement. -DLG
 1106          */
 1107         outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
 1108 
 1109         DELAY(5000);
 1110 
 1111         /* Make sure that we really have an 8390 based board */
 1112         if (!ed_probe_generic8390(sc))
 1113                 return (0);
 1114 
 1115         sc->vendor = ED_VENDOR_NOVELL;
 1116         sc->mem_shared = 0;
 1117         sc->cr_proto = ED_CR_RD2;
 1118 
 1119         /*
 1120          * Test the ability to read and write to the NIC memory. This has the
 1121          * side affect of determining if this is an NE1000 or an NE2000.
 1122          */
 1123 
 1124         /*
 1125          * This prevents packets from being stored in the NIC memory when the
 1126          * readmem routine turns on the start bit in the CR.
 1127          */
 1128         outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
 1129 
 1130         /* Temporarily initialize DCR for byte operations */
 1131         outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
 1132 
 1133         outb(sc->nic_addr + ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
 1134         outb(sc->nic_addr + ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
 1135 
 1136         sc->isa16bit = 0;
 1137 
 1138         /*
 1139          * Write a test pattern in byte mode. If this fails, then there
 1140          * probably isn't any memory at 8k - which likely means that the board
 1141          * is an NE2000.
 1142          */
 1143         ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
 1144         ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
 1145 
 1146         if (bcmp(test_pattern, test_buffer, sizeof(test_pattern))) {
 1147                 /* not an NE1000 - try NE2000 */
 1148 
 1149                 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
 1150                 outb(sc->nic_addr + ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
 1151                 outb(sc->nic_addr + ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
 1152 
 1153                 sc->isa16bit = 1;
 1154 
 1155                 /*
 1156                  * Write a test pattern in word mode. If this also fails, then
 1157                  * we don't know what this board is.
 1158                  */
 1159                 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
 1160                 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
 1161 
 1162                 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)))
 1163                         return (0);     /* not an NE2000 either */
 1164 
 1165                 sc->type = ED_TYPE_NE2000;
 1166                 sc->type_str = "NE2000";
 1167         } else {
 1168                 sc->type = ED_TYPE_NE1000;
 1169                 sc->type_str = "NE1000";
 1170         }
 1171 
 1172         /* 8k of memory plus an additional 8k if 16bit */
 1173         memsize = 8192 + sc->isa16bit * 8192;
 1174 
 1175 #if 0   /* probably not useful - NE boards only come two ways */
 1176         /* allow kernel config file overrides */
 1177         if (isa_dev->id_msize)
 1178                 memsize = isa_dev->id_msize;
 1179 #endif
 1180 
 1181         sc->mem_size = memsize;
 1182 
 1183         /* NIC memory doesn't start at zero on an NE board */
 1184         /* The start address is tied to the bus width */
 1185         sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
 1186         sc->mem_end = sc->mem_start + memsize;
 1187         sc->tx_page_start = memsize / ED_PAGE_SIZE;
 1188 
 1189 #ifdef GWETHER
 1190         {
 1191                 int     x, i, mstart = 0, msize = 0;
 1192                 char    pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
 1193 
 1194                 for (i = 0; i < ED_PAGE_SIZE; i++)
 1195                         pbuf0[i] = 0;
 1196 
 1197                 /* Clear all the memory. */
 1198                 for (x = 1; x < 256; x++)
 1199                         ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
 1200 
 1201                 /* Search for the start of RAM. */
 1202                 for (x = 1; x < 256; x++) {
 1203                         ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
 1204                         if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
 1205                                 for (i = 0; i < ED_PAGE_SIZE; i++)
 1206                                         pbuf[i] = 255 - x;
 1207                                 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
 1208                                 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
 1209                                 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
 1210                                         mstart = x * ED_PAGE_SIZE;
 1211                                         msize = ED_PAGE_SIZE;
 1212                                         break;
 1213                                 }
 1214                         }
 1215                 }
 1216 
 1217                 if (mstart == 0) {
 1218                         printf("ed%d: Cannot find start of RAM.\n", unit);
 1219                         return 0;
 1220                 }
 1221                 /* Search for the start of RAM. */
 1222                 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
 1223                         ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
 1224                         if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
 1225                                 for (i = 0; i < ED_PAGE_SIZE; i++)
 1226                                         pbuf[i] = 255 - x;
 1227                                 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
 1228                                 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
 1229                                 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
 1230                                         msize += ED_PAGE_SIZE;
 1231                                 else {
 1232                                         break;
 1233                                 }
 1234                         } else {
 1235                                 break;
 1236                         }
 1237                 }
 1238 
 1239                 if (msize == 0) {
 1240                         printf("ed%d: Cannot find any RAM, start : %d, x = %d.\n", unit, mstart, x);
 1241                         return 0;
 1242                 }
 1243                 printf("ed%d: RAM start at %d, size : %d.\n", unit, mstart, msize);
 1244 
 1245                 sc->mem_size = msize;
 1246                 sc->mem_start = (char *) mstart;
 1247                 sc->mem_end = (char *) (msize + mstart);
 1248                 sc->tx_page_start = mstart / ED_PAGE_SIZE;
 1249         }
 1250 #endif  /* GWETHER */
 1251 
 1252         /*
 1253          * Use one xmit buffer if < 16k, two buffers otherwise (if not told
 1254          * otherwise).
 1255          */
 1256         if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
 1257                 sc->txb_cnt = 1;
 1258         else
 1259                 sc->txb_cnt = 2;
 1260 
 1261         sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
 1262         sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
 1263 
 1264         sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
 1265 
 1266         ed_pio_readmem(sc, 0, romdata, 16);
 1267         for (n = 0; n < ETHER_ADDR_LEN; n++)
 1268                 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
 1269 
 1270 #ifdef GWETHER
 1271         if (sc->arpcom.ac_enaddr[2] == 0x86) {
 1272                 sc->type_str = "Gateway AT";
 1273         }
 1274 #endif  /* GWETHER */
 1275 
 1276         /* clear any pending interrupts that might have occurred above */
 1277         outb(sc->nic_addr + ED_P0_ISR, 0xff);
 1278 
 1279         return (ED_NOVELL_IO_PORTS);
 1280 }
 1281 
 1282 static int
 1283 ed_probe_Novell(isa_dev)
 1284         struct isa_device *isa_dev;
 1285 {
 1286         struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
 1287 
 1288         isa_dev->id_maddr = 0;
 1289         return ed_probe_Novell_generic(sc, isa_dev->id_iobase, 
 1290                                        isa_dev->id_unit, isa_dev->id_flags);
 1291 }
 1292 
 1293 #if NCARD > 0
 1294 /*
 1295  * Probe framework for pccards.  Replicates the standard framework, 
 1296  * minus the pccard driver registration and ignores the ether address
 1297  * supplied (from the CIS), relying on the probe to find it instead.
 1298  */
 1299 static int
 1300 ed_probe_pccard(isa_dev, ether)
 1301         struct isa_device *isa_dev;
 1302         u_char *ether;
 1303 {
 1304         int     nports;
 1305 
 1306         nports = ed_probe_WD80x3(isa_dev);
 1307         if (nports)
 1308                 return (nports);
 1309 
 1310         nports = ed_probe_Novell(isa_dev);
 1311         if (nports)
 1312                 return (nports);
 1313 
 1314         return (0);
 1315 }
 1316 
 1317 #endif /* NCARD > 0 */
 1318 
 1319 #define ED_HPP_TEST_SIZE        16
 1320 
 1321 /*
 1322  * Probe and vendor specific initialization for the HP PC Lan+ Cards.
 1323  * (HP Part nos: 27247B and 27252A).
 1324  *
 1325  * The card has an asic wrapper around a DS8390 core.  The asic handles 
 1326  * host accesses and offers both standard register IO and memory mapped 
 1327  * IO.  Memory mapped I/O allows better performance at the expense of greater
 1328  * chance of an incompatibility with existing ISA cards.
 1329  *
 1330  * The card has a few caveats: it isn't tolerant of byte wide accesses, only
 1331  * short (16 bit) or word (32 bit) accesses are allowed.  Some card revisions
 1332  * don't allow 32 bit accesses; these are indicated by a bit in the software
 1333  * ID register (see if_edreg.h).
 1334  * 
 1335  * Other caveats are: we should read the MAC address only when the card
 1336  * is inactive.
 1337  *
 1338  * For more information; please consult the CRYNWR packet driver.
 1339  *
 1340  * The AUI port is turned on using the "link2" option on the ifconfig 
 1341  * command line.
 1342  */
 1343 static int
 1344 ed_probe_HP_pclanp(isa_dev)
 1345         struct isa_device *isa_dev;
 1346 {
 1347         struct ed_softc *sc = &ed_softc[isa_dev->id_unit];
 1348         int n;                          /* temp var */
 1349         int memsize;                    /* mem on board */
 1350         u_char checksum;                /* checksum of board address */
 1351         u_char irq;                     /* board configured IRQ */
 1352         char test_pattern[ED_HPP_TEST_SIZE];    /* read/write areas for */
 1353         char test_buffer[ED_HPP_TEST_SIZE];     /* probing card */
 1354 
 1355 
 1356         /* Fill in basic information */
 1357         sc->asic_addr = isa_dev->id_iobase + ED_HPP_ASIC_OFFSET;
 1358         sc->nic_addr = isa_dev->id_iobase + ED_HPP_NIC_OFFSET;
 1359         sc->is790 = 0;
 1360         sc->isa16bit = 0;       /* the 8390 core needs to be in byte mode */
 1361 
 1362         /* 
 1363          * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53" 
 1364          */
 1365         
 1366         if ((inb(sc->asic_addr + ED_HPP_ID) != 0x50) || 
 1367             (inb(sc->asic_addr + ED_HPP_ID + 1) != 0x48) ||
 1368             ((inb(sc->asic_addr + ED_HPP_ID + 2) & 0xF0) != 0) ||
 1369             (inb(sc->asic_addr + ED_HPP_ID + 3) != 0x53))
 1370                 return 0;
 1371 
 1372         /* 
 1373          * Read the MAC address and verify checksum on the address.
 1374          */
 1375 
 1376         outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_MAC);
 1377         for (n  = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
 1378                 checksum += (sc->arpcom.ac_enaddr[n] = 
 1379                         inb(sc->asic_addr + ED_HPP_MAC_ADDR + n));
 1380         
 1381         checksum += inb(sc->asic_addr + ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
 1382 
 1383         if (checksum != 0xFF)
 1384                 return 0;
 1385 
 1386         /*
 1387          * Verify that the software model number is 0.
 1388          */
 1389         
 1390         outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_ID);
 1391         if (((sc->hpp_id = inw(sc->asic_addr + ED_HPP_PAGE_4)) & 
 1392                 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
 1393                 return 0;
 1394 
 1395         /*
 1396          * Read in and save the current options configured on card.
 1397          */
 1398 
 1399         sc->hpp_options = inw(sc->asic_addr + ED_HPP_OPTION);
 1400 
 1401         sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET | 
 1402                                 ED_HPP_OPTION_CHIP_RESET |
 1403                                 ED_HPP_OPTION_ENABLE_IRQ);
 1404 
 1405         /* 
 1406          * Reset the chip.  This requires writing to the option register
 1407          * so take care to preserve the other bits.
 1408          */
 1409 
 1410         outw(sc->asic_addr + ED_HPP_OPTION, 
 1411                 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET | 
 1412                         ED_HPP_OPTION_CHIP_RESET)));
 1413 
 1414         DELAY(5000);    /* wait for chip reset to complete */
 1415 
 1416         outw(sc->asic_addr + ED_HPP_OPTION,
 1417                 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
 1418                         ED_HPP_OPTION_CHIP_RESET |
 1419                         ED_HPP_OPTION_ENABLE_IRQ)));
 1420 
 1421         DELAY(5000);
 1422 
 1423         if (!(inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST))
 1424                 return 0;       /* reset did not complete */
 1425 
 1426         /*
 1427          * Read out configuration information.
 1428          */
 1429 
 1430         outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
 1431 
 1432         irq = inb(sc->asic_addr + ED_HPP_HW_IRQ);
 1433 
 1434         /*
 1435          * Check for impossible IRQ.
 1436          */
 1437 
 1438         if (irq >= (sizeof(ed_hpp_intr_mask) / sizeof(ed_hpp_intr_mask[0])))
 1439                 return 0;
 1440 
 1441         /* 
 1442          * If the kernel IRQ was specified with a '?' use the cards idea
 1443          * of the IRQ.  If the kernel IRQ was explicitly specified, it
 1444          * should match that of the hardware.
 1445          */
 1446 
 1447         if (isa_dev->id_irq <= 0)
 1448                 isa_dev->id_irq = ed_hpp_intr_mask[irq];
 1449         else if (isa_dev->id_irq != ed_hpp_intr_mask[irq])
 1450                 return 0;
 1451 
 1452         /*
 1453          * Fill in softconfig info.
 1454          */
 1455 
 1456         sc->vendor = ED_VENDOR_HP;
 1457         sc->type = ED_TYPE_HP_PCLANPLUS;
 1458         sc->type_str = "HP-PCLAN+";
 1459 
 1460         sc->mem_shared = 0;     /* we DON'T have dual ported RAM */
 1461         sc->mem_start = 0;      /* we use offsets inside the card RAM */
 1462 
 1463         sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
 1464 
 1465         /*
 1466          * Check if memory mapping of the I/O registers possible.
 1467          */
 1468 
 1469         if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
 1470         {
 1471                 u_long mem_addr;
 1472 
 1473                 /*
 1474                  * determine the memory address from the board.
 1475                  */
 1476                 
 1477                 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
 1478                 mem_addr = (inw(sc->asic_addr + ED_HPP_HW_MEM_MAP) << 8);
 1479 
 1480                 /*
 1481                  * Check that the kernel specified start of memory and
 1482                  * hardware's idea of it match.
 1483                  */
 1484                 
 1485                 if (mem_addr != kvtop(isa_dev->id_maddr))
 1486                         return 0;
 1487 
 1488                 sc->hpp_mem_start = isa_dev->id_maddr;
 1489         }
 1490 
 1491         /*
 1492          * The board has 32KB of memory.  Is there a way to determine
 1493          * this programmatically?
 1494          */
 1495         
 1496         memsize = 32768;
 1497 
 1498         /*
 1499          * Fill in the rest of the soft config structure.
 1500          */
 1501 
 1502         /*
 1503          * The transmit page index.
 1504          */
 1505 
 1506         sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
 1507 
 1508         if (isa_dev->id_flags & ED_FLAGS_NO_MULTI_BUFFERING)
 1509                 sc->txb_cnt = 1;
 1510         else
 1511                 sc->txb_cnt = 2;
 1512 
 1513         /*
 1514          * Memory description
 1515          */
 1516 
 1517         sc->mem_size = memsize;
 1518         sc->mem_ring = sc->mem_start + 
 1519                 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
 1520         sc->mem_end = sc->mem_start + sc->mem_size;
 1521 
 1522         /*
 1523          * Receive area starts after the transmit area and 
 1524          * continues till the end of memory.
 1525          */
 1526 
 1527         sc->rec_page_start = sc->tx_page_start + 
 1528                                 (sc->txb_cnt * ED_TXBUF_SIZE);
 1529         sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
 1530 
 1531 
 1532         sc->cr_proto = 0;       /* value works */
 1533 
 1534         /*
 1535          * Set the wrap registers for string I/O reads.
 1536          */
 1537 
 1538         outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_HW);
 1539         outw(sc->asic_addr + ED_HPP_HW_WRAP,
 1540                 ((sc->rec_page_start / ED_PAGE_SIZE) |
 1541                  (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
 1542 
 1543         /*
 1544          * Reset the register page to normal operation.
 1545          */
 1546 
 1547         outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
 1548 
 1549         /*
 1550          * Verify that we can read/write from adapter memory.
 1551          * Create test pattern.
 1552          */
 1553 
 1554         for (n = 0; n < ED_HPP_TEST_SIZE; n++)
 1555         {
 1556                 test_pattern[n] = (n*n) ^ ~n;
 1557         }
 1558 
 1559 #undef  ED_HPP_TEST_SIZE
 1560 
 1561         /*
 1562          * Check that the memory is accessible thru the I/O ports.
 1563          * Write out the contents of "test_pattern", read back
 1564          * into "test_buffer" and compare the two for any
 1565          * mismatch.
 1566          */
 1567 
 1568         for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
 1569 
 1570                 ed_pio_writemem(sc, test_pattern, (n * ED_PAGE_SIZE), 
 1571                                 sizeof(test_pattern));
 1572                 ed_pio_readmem(sc, (n * ED_PAGE_SIZE), 
 1573                         test_buffer, sizeof(test_pattern));
 1574 
 1575                 if (bcmp(test_pattern, test_buffer, 
 1576                         sizeof(test_pattern)))
 1577                         return 0;
 1578         }
 1579 
 1580         return (ED_HPP_IO_PORTS);
 1581 
 1582 }
 1583 
 1584 /*
 1585  * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
 1586  */
 1587 
 1588 void
 1589 ed_hpp_set_physical_link(struct ed_softc *sc)
 1590 {
 1591         struct ifnet *ifp = &sc->arpcom.ac_if;
 1592         int lan_page;
 1593 
 1594         outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
 1595         lan_page = inw(sc->asic_addr + ED_HPP_PAGE_0);
 1596 
 1597         if (ifp->if_flags & IFF_ALTPHYS) {
 1598 
 1599                 /*
 1600                  * Use the AUI port.
 1601                  */
 1602 
 1603                 lan_page |= ED_HPP_LAN_AUI;
 1604 
 1605                 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
 1606                 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
 1607 
 1608 
 1609         } else {
 1610 
 1611                 /*
 1612                  * Use the ThinLan interface
 1613                  */
 1614 
 1615                 lan_page &= ~ED_HPP_LAN_AUI;
 1616 
 1617                 outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_LAN);
 1618                 outw(sc->asic_addr + ED_HPP_PAGE_0, lan_page);
 1619 
 1620         }
 1621 
 1622         /*
 1623          * Wait for the lan card to re-initialize itself
 1624          */
 1625 
 1626         DELAY(150000);  /* wait 150 ms */
 1627 
 1628         /*
 1629          * Restore normal pages.
 1630          */
 1631 
 1632         outw(sc->asic_addr + ED_HPP_PAGING, ED_HPP_PAGE_PERF);
 1633 
 1634 }
 1635 
 1636 
 1637 /*
 1638  * Install interface into kernel networking data structures
 1639  */
 1640 static int
 1641 ed_attach(sc, unit, flags)
 1642         struct ed_softc *sc;
 1643         int unit;
 1644         int flags;
 1645 {
 1646         struct ifnet *ifp = &sc->arpcom.ac_if;
 1647 
 1648         /*
 1649          * Set interface to stopped condition (reset)
 1650          */
 1651         ed_stop(sc);
 1652 
 1653         if (!ifp->if_name) {
 1654                 /*
 1655                  * Initialize ifnet structure
 1656                  */
 1657                 ifp->if_softc = sc;
 1658                 ifp->if_unit = unit;
 1659                 ifp->if_name = "ed";
 1660                 ifp->if_output = ether_output;
 1661                 ifp->if_start = ed_start;
 1662                 ifp->if_ioctl = ed_ioctl;
 1663                 ifp->if_watchdog = ed_watchdog;
 1664                 ifp->if_init = ed_init;
 1665                 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
 1666                 ifp->if_linkmib = &sc->mibdata;
 1667                 ifp->if_linkmiblen = sizeof sc->mibdata;
 1668                 /*
 1669                  * XXX - should do a better job.
 1670                  */
 1671                 if (sc->is790)
 1672                         sc->mibdata.dot3StatsEtherChipSet =
 1673                                 DOT3CHIPSET(dot3VendorWesternDigital,
 1674                                             dot3ChipSetWesternDigital83C790);
 1675                 else
 1676                         sc->mibdata.dot3StatsEtherChipSet =
 1677                                 DOT3CHIPSET(dot3VendorNational, 
 1678                                             dot3ChipSetNational8390);
 1679                 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
 1680 
 1681                 /*
 1682                  * Set default state for ALTPHYS flag (used to disable the 
 1683                  * tranceiver for AUI operation), based on compile-time 
 1684                  * config option.
 1685                  */
 1686                 if (flags & ED_FLAGS_DISABLE_TRANCEIVER)
 1687                         ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | 
 1688                             IFF_MULTICAST | IFF_ALTPHYS);
 1689                 else
 1690                         ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX |
 1691                             IFF_MULTICAST);
 1692 
 1693                 /*
 1694                  * Attach the interface
 1695                  */
 1696                 if_attach(ifp);
 1697                 ether_ifattach(ifp);
 1698         }
 1699         /* device attach does transition from UNCONFIGURED to IDLE state */
 1700 
 1701         /*
 1702          * Print additional info when attached
 1703          */
 1704         printf("%s%d: address %6D, ", ifp->if_name, ifp->if_unit, 
 1705                 sc->arpcom.ac_enaddr, ":");
 1706 
 1707         if (sc->type_str && (*sc->type_str != 0))
 1708                 printf("type %s ", sc->type_str);
 1709         else
 1710                 printf("type unknown (0x%x) ", sc->type);
 1711 
 1712         if (sc->vendor == ED_VENDOR_HP)
 1713                 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
 1714                         "16-bit" : "32-bit",
 1715                         sc->hpp_mem_start ? "memory mapped" : "regular");
 1716         else
 1717                 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
 1718 
 1719         printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
 1720                          (sc->vendor == ED_VENDOR_HP)) &&
 1721                 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
 1722 
 1723         /*
 1724          * If BPF is in the kernel, call the attach for it
 1725          */
 1726 #if NBPFILTER > 0
 1727         bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header));
 1728 #endif
 1729         return 1;
 1730 }
 1731 
 1732 static int
 1733 ed_attach_isa(isa_dev)
 1734         struct isa_device *isa_dev;
 1735 {
 1736         int unit = isa_dev->id_unit;
 1737         struct ed_softc *sc = &ed_softc[unit];
 1738         int flags = isa_dev->id_flags;
 1739 
 1740         return ed_attach(sc, unit, flags);
 1741 }
 1742 
 1743 #if NPCI > 0
 1744 void *
 1745 ed_attach_NE2000_pci(unit, port)
 1746         int unit;
 1747         int port;
 1748 {
 1749         struct ed_softc *sc = malloc(sizeof *sc, M_DEVBUF, M_NOWAIT);
 1750         int isa_flags = 0;
 1751 
 1752         if (!sc)
 1753                 return sc;
 1754 
 1755         bzero(sc, sizeof *sc);
 1756         if (ed_probe_Novell_generic(sc, port, unit, isa_flags) == 0
 1757             || ed_attach(sc, unit, isa_flags) == 0) {
 1758                 free(sc, M_DEVBUF);
 1759                 return NULL;
 1760         }
 1761         return sc;
 1762 }
 1763 #endif
 1764 
 1765 /*
 1766  * Reset interface.
 1767  */
 1768 static void
 1769 ed_reset(ifp)
 1770         struct ifnet *ifp;
 1771 {
 1772         struct ed_softc *sc = ifp->if_softc;
 1773         int     s;
 1774 
 1775         if (sc->gone)
 1776                 return;
 1777         s = splimp();
 1778 
 1779         /*
 1780          * Stop interface and re-initialize.
 1781          */
 1782         ed_stop(sc);
 1783         ed_init(sc);
 1784 
 1785         (void) splx(s);
 1786 }
 1787 
 1788 /*
 1789  * Take interface offline.
 1790  */
 1791 static void
 1792 ed_stop(sc)
 1793         struct ed_softc *sc;
 1794 {
 1795         int     n = 5000;
 1796 
 1797         if (sc->gone)
 1798                 return;
 1799         /*
 1800          * Stop everything on the interface, and select page 0 registers.
 1801          */
 1802         outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
 1803 
 1804         /*
 1805          * Wait for interface to enter stopped state, but limit # of checks to
 1806          * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
 1807          * just in case it's an old one.
 1808          */
 1809         while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
 1810 }
 1811 
 1812 /*
 1813  * Device timeout/watchdog routine. Entered if the device neglects to
 1814  *      generate an interrupt after a transmit has been started on it.
 1815  */
 1816 static void
 1817 ed_watchdog(ifp)
 1818         struct ifnet *ifp;
 1819 {
 1820         struct ed_softc *sc = ifp->if_softc;
 1821 
 1822         if (sc->gone)
 1823                 return;
 1824         log(LOG_ERR, "ed%d: device timeout\n", ifp->if_unit);
 1825         ifp->if_oerrors++;
 1826 
 1827         ed_reset(ifp);
 1828 }
 1829 
 1830 /*
 1831  * Initialize device.
 1832  */
 1833 static void
 1834 ed_init(xsc)
 1835         void *xsc;
 1836 {
 1837         struct ed_softc *sc = xsc;
 1838         struct ifnet *ifp = &sc->arpcom.ac_if;
 1839         int     i, s;
 1840 
 1841         if (sc->gone)
 1842                 return;
 1843 
 1844         /* address not known */
 1845         if (ifp->if_addrlist == (struct ifaddr *) 0)
 1846                 return;
 1847 
 1848         /*
 1849          * Initialize the NIC in the exact order outlined in the NS manual.
 1850          * This init procedure is "mandatory"...don't change what or when
 1851          * things happen.
 1852          */
 1853         s = splimp();
 1854 
 1855         /* reset transmitter flags */
 1856         sc->xmit_busy = 0;
 1857         ifp->if_timer = 0;
 1858 
 1859         sc->txb_inuse = 0;
 1860         sc->txb_new = 0;
 1861         sc->txb_next_tx = 0;
 1862 
 1863         /* This variable is used below - don't move this assignment */
 1864         sc->next_packet = sc->rec_page_start + 1;
 1865 
 1866         /*
 1867          * Set interface for page 0, Remote DMA complete, Stopped
 1868          */
 1869         outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
 1870 
 1871         if (sc->isa16bit) {
 1872 
 1873                 /*
 1874                  * Set FIFO threshold to 8, No auto-init Remote DMA, byte
 1875                  * order=80x86, word-wide DMA xfers,
 1876                  */
 1877                 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
 1878         } else {
 1879 
 1880                 /*
 1881                  * Same as above, but byte-wide DMA xfers
 1882                  */
 1883                 outb(sc->nic_addr + ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
 1884         }
 1885 
 1886         /*
 1887          * Clear Remote Byte Count Registers
 1888          */
 1889         outb(sc->nic_addr + ED_P0_RBCR0, 0);
 1890         outb(sc->nic_addr + ED_P0_RBCR1, 0);
 1891 
 1892         /*
 1893          * For the moment, don't store incoming packets in memory.
 1894          */
 1895         outb(sc->nic_addr + ED_P0_RCR, ED_RCR_MON);
 1896 
 1897         /*
 1898          * Place NIC in internal loopback mode
 1899          */
 1900         outb(sc->nic_addr + ED_P0_TCR, ED_TCR_LB0);
 1901 
 1902         /*
 1903          * Initialize transmit/receive (ring-buffer) Page Start
 1904          */
 1905         outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start);
 1906         outb(sc->nic_addr + ED_P0_PSTART, sc->rec_page_start);
 1907         /* Set lower bits of byte addressable framing to 0 */
 1908         if (sc->is790)
 1909                 outb(sc->nic_addr + 0x09, 0);
 1910 
 1911         /*
 1912          * Initialize Receiver (ring-buffer) Page Stop and Boundry
 1913          */
 1914         outb(sc->nic_addr + ED_P0_PSTOP, sc->rec_page_stop);
 1915         outb(sc->nic_addr + ED_P0_BNRY, sc->rec_page_start);
 1916 
 1917         /*
 1918          * Clear all interrupts. A '1' in each bit position clears the
 1919          * corresponding flag.
 1920          */
 1921         outb(sc->nic_addr + ED_P0_ISR, 0xff);
 1922 
 1923         /*
 1924          * Enable the following interrupts: receive/transmit complete,
 1925          * receive/transmit error, and Receiver OverWrite.
 1926          *
 1927          * Counter overflow and Remote DMA complete are *not* enabled.
 1928          */
 1929         outb(sc->nic_addr + ED_P0_IMR,
 1930         ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
 1931 
 1932         /*
 1933          * Program Command Register for page 1
 1934          */
 1935         outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
 1936 
 1937         /*
 1938          * Copy out our station address
 1939          */
 1940         for (i = 0; i < ETHER_ADDR_LEN; ++i)
 1941                 outb(sc->nic_addr + ED_P1_PAR0 + i, sc->arpcom.ac_enaddr[i]);
 1942 
 1943         /*
 1944          * Set Current Page pointer to next_packet (initialized above)
 1945          */
 1946         outb(sc->nic_addr + ED_P1_CURR, sc->next_packet);
 1947 
 1948         /*
 1949          * Program Receiver Configuration Register and multicast filter. CR is
 1950          * set to page 0 on return.
 1951          */
 1952         ed_setrcr(sc);
 1953 
 1954         /*
 1955          * Take interface out of loopback
 1956          */
 1957         outb(sc->nic_addr + ED_P0_TCR, 0);
 1958 
 1959         /*
 1960          * If this is a 3Com board, the tranceiver must be software enabled
 1961          * (there is no settable hardware default).
 1962          */
 1963         if (sc->vendor == ED_VENDOR_3COM) {
 1964                 if (ifp->if_flags & IFF_ALTPHYS) {
 1965                         outb(sc->asic_addr + ED_3COM_CR, 0);
 1966                 } else {
 1967                         outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
 1968                 }
 1969         }
 1970 
 1971         /*
 1972          * Set 'running' flag, and clear output active flag.
 1973          */
 1974         ifp->if_flags |= IFF_RUNNING;
 1975         ifp->if_flags &= ~IFF_OACTIVE;
 1976 
 1977         /*
 1978          * ...and attempt to start output
 1979          */
 1980         ed_start(ifp);
 1981 
 1982         (void) splx(s);
 1983 }
 1984 
 1985 /*
 1986  * This routine actually starts the transmission on the interface
 1987  */
 1988 static __inline void
 1989 ed_xmit(sc)
 1990         struct ed_softc *sc;
 1991 {
 1992         struct ifnet *ifp = (struct ifnet *)sc;
 1993         unsigned short len;
 1994 
 1995         if (sc->gone)
 1996                 return;
 1997         len = sc->txb_len[sc->txb_next_tx];
 1998 
 1999         /*
 2000          * Set NIC for page 0 register access
 2001          */
 2002         outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
 2003 
 2004         /*
 2005          * Set TX buffer start page
 2006          */
 2007         outb(sc->nic_addr + ED_P0_TPSR, sc->tx_page_start +
 2008              sc->txb_next_tx * ED_TXBUF_SIZE);
 2009 
 2010         /*
 2011          * Set TX length
 2012          */
 2013         outb(sc->nic_addr + ED_P0_TBCR0, len);
 2014         outb(sc->nic_addr + ED_P0_TBCR1, len >> 8);
 2015 
 2016         /*
 2017          * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
 2018          */
 2019         outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
 2020         sc->xmit_busy = 1;
 2021 
 2022         /*
 2023          * Point to next transmit buffer slot and wrap if necessary.
 2024          */
 2025         sc->txb_next_tx++;
 2026         if (sc->txb_next_tx == sc->txb_cnt)
 2027                 sc->txb_next_tx = 0;
 2028 
 2029         /*
 2030          * Set a timer just in case we never hear from the board again
 2031          */
 2032         ifp->if_timer = 2;
 2033 }
 2034 
 2035 /*
 2036  * Start output on interface.
 2037  * We make two assumptions here:
 2038  *  1) that the current priority is set to splimp _before_ this code
 2039  *     is called *and* is returned to the appropriate priority after
 2040  *     return
 2041  *  2) that the IFF_OACTIVE flag is checked before this code is called
 2042  *     (i.e. that the output part of the interface is idle)
 2043  */
 2044 static void
 2045 ed_start(ifp)
 2046         struct ifnet *ifp;
 2047 {
 2048         struct ed_softc *sc = ifp->if_softc;
 2049         struct mbuf *m0, *m;
 2050         caddr_t buffer;
 2051         int     len;
 2052 
 2053         if (sc->gone) {
 2054                 printf("ed_start(%p) GONE\n",ifp);
 2055                 return;
 2056         }
 2057 outloop:
 2058 
 2059         /*
 2060          * First, see if there are buffered packets and an idle transmitter -
 2061          * should never happen at this point.
 2062          */
 2063         if (sc->txb_inuse && (sc->xmit_busy == 0)) {
 2064                 printf("ed: packets buffered, but transmitter idle\n");
 2065                 ed_xmit(sc);
 2066         }
 2067 
 2068         /*
 2069          * See if there is room to put another packet in the buffer.
 2070          */
 2071         if (sc->txb_inuse == sc->txb_cnt) {
 2072 
 2073                 /*
 2074                  * No room. Indicate this to the outside world and exit.
 2075                  */
 2076                 ifp->if_flags |= IFF_OACTIVE;
 2077                 return;
 2078         }
 2079         IF_DEQUEUE(&ifp->if_snd, m);
 2080         if (m == 0) {
 2081 
 2082                 /*
 2083                  * We are using the !OACTIVE flag to indicate to the outside
 2084                  * world that we can accept an additional packet rather than
 2085                  * that the transmitter is _actually_ active. Indeed, the
 2086                  * transmitter may be active, but if we haven't filled all the
 2087                  * buffers with data then we still want to accept more.
 2088                  */
 2089                 ifp->if_flags &= ~IFF_OACTIVE;
 2090                 return;
 2091         }
 2092 
 2093         /*
 2094          * Copy the mbuf chain into the transmit buffer
 2095          */
 2096 
 2097         m0 = m;
 2098 
 2099         /* txb_new points to next open buffer slot */
 2100         buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
 2101 
 2102         if (sc->mem_shared) {
 2103 
 2104                 /*
 2105                  * Special case setup for 16 bit boards...
 2106                  */
 2107                 if (sc->isa16bit) {
 2108                         switch (sc->vendor) {
 2109 
 2110                                 /*
 2111                                  * For 16bit 3Com boards (which have 16k of
 2112                                  * memory), we have the xmit buffers in a
 2113                                  * different page of memory ('page 0') - so
 2114                                  * change pages.
 2115                                  */
 2116                         case ED_VENDOR_3COM:
 2117                                 outb(sc->asic_addr + ED_3COM_GACFR,
 2118                                      ED_3COM_GACFR_RSEL);
 2119                                 break;
 2120 
 2121                                 /*
 2122                                  * Enable 16bit access to shared memory on
 2123                                  * WD/SMC boards.
 2124                                  */
 2125                         case ED_VENDOR_WD_SMC:{
 2126                                         outb(sc->asic_addr + ED_WD_LAAR,
 2127                                              sc->wd_laar_proto | ED_WD_LAAR_M16EN);
 2128                                         if (sc->is790) {
 2129                                                 outb(sc->asic_addr + ED_WD_MSR, ED_WD_MSR_MENB);
 2130                                         }
 2131                                         break;
 2132                                 }
 2133                         }
 2134                 }
 2135                 for (len = 0; m != 0; m = m->m_next) {
 2136                         bcopy(mtod(m, caddr_t), buffer, m->m_len);
 2137                         buffer += m->m_len;
 2138                         len += m->m_len;
 2139                 }
 2140 
 2141                 /*
 2142                  * Restore previous shared memory access
 2143                  */
 2144                 if (sc->isa16bit) {
 2145                         switch (sc->vendor) {
 2146                         case ED_VENDOR_3COM:
 2147                                 outb(sc->asic_addr + ED_3COM_GACFR,
 2148                                      ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
 2149                                 break;
 2150                         case ED_VENDOR_WD_SMC:{
 2151                                         if (sc->is790) {
 2152                                                 outb(sc->asic_addr + ED_WD_MSR, 0x00);
 2153                                         }
 2154                                         outb(sc->asic_addr + ED_WD_LAAR,
 2155                                             sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
 2156                                         break;
 2157                                 }
 2158                         }
 2159                 }
 2160         } else {
 2161                 len = ed_pio_write_mbufs(sc, m, (int)buffer);
 2162                 if (len == 0)
 2163                         goto outloop;
 2164         }
 2165 
 2166         sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
 2167 
 2168         sc->txb_inuse++;
 2169 
 2170         /*
 2171          * Point to next buffer slot and wrap if necessary.
 2172          */
 2173         sc->txb_new++;
 2174         if (sc->txb_new == sc->txb_cnt)
 2175                 sc->txb_new = 0;
 2176 
 2177         if (sc->xmit_busy == 0)
 2178                 ed_xmit(sc);
 2179 
 2180         /*
 2181          * Tap off here if there is a bpf listener.
 2182          */
 2183 #if NBPFILTER > 0
 2184         if (ifp->if_bpf) {
 2185                 bpf_mtap(ifp, m0);
 2186         }
 2187 #endif
 2188 
 2189         m_freem(m0);
 2190 
 2191         /*
 2192          * Loop back to the top to possibly buffer more packets
 2193          */
 2194         goto outloop;
 2195 }
 2196 
 2197 /*
 2198  * Ethernet interface receiver interrupt.
 2199  */
 2200 static __inline void
 2201 ed_rint(sc)
 2202         struct ed_softc *sc;
 2203 {
 2204         struct ifnet *ifp = &sc->arpcom.ac_if;
 2205         u_char  boundry;
 2206         u_short len;
 2207         struct ed_ring packet_hdr;
 2208         char   *packet_ptr;
 2209 
 2210         if (sc->gone)
 2211                 return;
 2212 
 2213         /*
 2214          * Set NIC to page 1 registers to get 'current' pointer
 2215          */
 2216         outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
 2217 
 2218         /*
 2219          * 'sc->next_packet' is the logical beginning of the ring-buffer -
 2220          * i.e. it points to where new data has been buffered. The 'CURR'
 2221          * (current) register points to the logical end of the ring-buffer -
 2222          * i.e. it points to where additional new data will be added. We loop
 2223          * here until the logical beginning equals the logical end (or in
 2224          * other words, until the ring-buffer is empty).
 2225          */
 2226         while (sc->next_packet != inb(sc->nic_addr + ED_P1_CURR)) {
 2227 
 2228                 /* get pointer to this buffer's header structure */
 2229                 packet_ptr = sc->mem_ring +
 2230                     (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
 2231 
 2232                 /*
 2233                  * The byte count includes a 4 byte header that was added by
 2234                  * the NIC.
 2235                  */
 2236                 if (sc->mem_shared)
 2237                         packet_hdr = *(struct ed_ring *) packet_ptr;
 2238                 else
 2239                         ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
 2240                                        sizeof(packet_hdr));
 2241                 len = packet_hdr.count;
 2242                 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
 2243                     len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
 2244                         /*
 2245                          * Length is a wild value. There's a good chance that
 2246                          * this was caused by the NIC being old and buggy.
 2247                          * The bug is that the length low byte is duplicated in
 2248                          * the high byte. Try to recalculate the length based on
 2249                          * the pointer to the next packet.
 2250                          */
 2251                         /*
 2252                          * NOTE: sc->next_packet is pointing at the current packet.
 2253                          */
 2254                         len &= ED_PAGE_SIZE - 1;        /* preserve offset into page */
 2255                         if (packet_hdr.next_packet >= sc->next_packet) {
 2256                                 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
 2257                         } else {
 2258                                 len += ((packet_hdr.next_packet - sc->rec_page_start) +
 2259                                         (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
 2260                         }
 2261                         /*
 2262                          * Because buffers are aligned on 256-byte boundary,
 2263                          * the length computed above is off by 256 in almost
 2264                          * all cases. Fix it...
 2265                          */
 2266                         if (len & 0xff)
 2267                                  len -= 256 ;
 2268                         if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN 
 2269                                    + sizeof(struct ed_ring)))
 2270                                 sc->mibdata.dot3StatsFrameTooLongs++;
 2271                 }
 2272                 /*
 2273                  * Be fairly liberal about what we allow as a "reasonable" length
 2274                  * so that a [crufty] packet will make it to BPF (and can thus
 2275                  * be analyzed). Note that all that is really important is that
 2276                  * we have a length that will fit into one mbuf cluster or less;
 2277                  * the upper layer protocols can then figure out the length from
 2278                  * their own length field(s).
 2279                  */
 2280                 if ((len > sizeof(struct ed_ring)) &&
 2281                     (len <= MCLBYTES) &&
 2282                     (packet_hdr.next_packet >= sc->rec_page_start) &&
 2283                     (packet_hdr.next_packet < sc->rec_page_stop)) {
 2284                         /*
 2285                          * Go get packet.
 2286                          */
 2287                         ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
 2288                                       len - sizeof(struct ed_ring), packet_hdr.rsr & ED_RSR_PHY);
 2289                         ifp->if_ipackets++;
 2290                 } else {
 2291                         /*
 2292                          * Really BAD. The ring pointers are corrupted.
 2293                          */
 2294                         log(LOG_ERR,
 2295                             "ed%d: NIC memory corrupt - invalid packet length %d\n",
 2296                             ifp->if_unit, len);
 2297                         ifp->if_ierrors++;
 2298                         ed_reset(ifp);
 2299                         return;
 2300                 }
 2301 
 2302                 /*
 2303                  * Update next packet pointer
 2304                  */
 2305                 sc->next_packet = packet_hdr.next_packet;
 2306 
 2307                 /*
 2308                  * Update NIC boundry pointer - being careful to keep it one
 2309                  * buffer behind. (as recommended by NS databook)
 2310                  */
 2311                 boundry = sc->next_packet - 1;
 2312                 if (boundry < sc->rec_page_start)
 2313                         boundry = sc->rec_page_stop - 1;
 2314 
 2315                 /*
 2316                  * Set NIC to page 0 registers to update boundry register
 2317                  */
 2318                 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
 2319 
 2320                 outb(sc->nic_addr + ED_P0_BNRY, boundry);
 2321 
 2322                 /*
 2323                  * Set NIC to page 1 registers before looping to top (prepare
 2324                  * to get 'CURR' current pointer)
 2325                  */
 2326                 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
 2327         }
 2328 }
 2329 
 2330 /*
 2331  * Ethernet interface interrupt processor
 2332  */
 2333 void
 2334 edintr_sc(sc)
 2335         struct ed_softc *sc;
 2336 {
 2337         struct ifnet *ifp = (struct ifnet *)sc;
 2338         u_char  isr;
 2339 
 2340         if (sc->gone)
 2341                 return;
 2342         /*
 2343          * Set NIC to page 0 registers
 2344          */
 2345         outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
 2346 
 2347         /*
 2348          * loop until there are no more new interrupts
 2349          */
 2350         while ((isr = inb(sc->nic_addr + ED_P0_ISR)) != 0) {
 2351 
 2352                 /*
 2353                  * reset all the bits that we are 'acknowledging' by writing a
 2354                  * '1' to each bit position that was set (writing a '1'
 2355                  * *clears* the bit)
 2356                  */
 2357                 outb(sc->nic_addr + ED_P0_ISR, isr);
 2358 
 2359                 /*
 2360                  * Handle transmitter interrupts. Handle these first because
 2361                  * the receiver will reset the board under some conditions.
 2362                  */
 2363                 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
 2364                         u_char  collisions = inb(sc->nic_addr + ED_P0_NCR) & 0x0f;
 2365 
 2366                         /*
 2367                          * Check for transmit error. If a TX completed with an
 2368                          * error, we end up throwing the packet away. Really
 2369                          * the only error that is possible is excessive
 2370                          * collisions, and in this case it is best to allow
 2371                          * the automatic mechanisms of TCP to backoff the
 2372                          * flow. Of course, with UDP we're screwed, but this
 2373                          * is expected when a network is heavily loaded.
 2374                          */
 2375                         (void) inb(sc->nic_addr + ED_P0_TSR);
 2376                         if (isr & ED_ISR_TXE) {
 2377                                 u_char tsr;
 2378 
 2379                                 /*
 2380                                  * Excessive collisions (16)
 2381                                  */
 2382                                 tsr = inb(sc->nic_addr + ED_P0_TSR);
 2383                                 if ((tsr & ED_TSR_ABT)  
 2384                                     && (collisions == 0)) {
 2385 
 2386                                         /*
 2387                                          * When collisions total 16, the
 2388                                          * P0_NCR will indicate 0, and the
 2389                                          * TSR_ABT is set.
 2390                                          */
 2391                                         collisions = 16;
 2392                                         sc->mibdata.dot3StatsExcessiveCollisions++;
 2393                                         sc->mibdata.dot3StatsCollFrequencies[15]++;
 2394                                 }
 2395                                 if (tsr & ED_TSR_OWC)
 2396                                         sc->mibdata.dot3StatsLateCollisions++;
 2397                                 if (tsr & ED_TSR_CDH)
 2398                                         sc->mibdata.dot3StatsSQETestErrors++;
 2399                                 if (tsr & ED_TSR_CRS)
 2400                                         sc->mibdata.dot3StatsCarrierSenseErrors++;
 2401                                 if (tsr & ED_TSR_FU)
 2402                                         sc->mibdata.dot3StatsInternalMacTransmitErrors++;
 2403 
 2404                                 /*
 2405                                  * update output errors counter
 2406                                  */
 2407                                 ifp->if_oerrors++;
 2408                         } else {
 2409 
 2410                                 /*
 2411                                  * Update total number of successfully
 2412                                  * transmitted packets.
 2413                                  */
 2414                                 ifp->if_opackets++;
 2415                         }
 2416 
 2417                         /*
 2418                          * reset tx busy and output active flags
 2419                          */
 2420                         sc->xmit_busy = 0;
 2421                         ifp->if_flags &= ~IFF_OACTIVE;
 2422 
 2423                         /*
 2424                          * clear watchdog timer
 2425                          */
 2426                         ifp->if_timer = 0;
 2427 
 2428                         /*
 2429                          * Add in total number of collisions on last
 2430                          * transmission.
 2431                          */
 2432                         ifp->if_collisions += collisions;
 2433                         switch(collisions) {
 2434                         case 0:
 2435                         case 16:
 2436                                 break;
 2437                         case 1:
 2438                                 sc->mibdata.dot3StatsSingleCollisionFrames++;
 2439                                 sc->mibdata.dot3StatsCollFrequencies[0]++;
 2440                                 break;
 2441                         default:
 2442                                 sc->mibdata.dot3StatsMultipleCollisionFrames++;
 2443                                 sc->mibdata.
 2444                                         dot3StatsCollFrequencies[collisions-1]
 2445                                                 ++;
 2446                                 break;
 2447                         }
 2448 
 2449                         /*
 2450                          * Decrement buffer in-use count if not zero (can only
 2451                          * be zero if a transmitter interrupt occured while
 2452                          * not actually transmitting). If data is ready to
 2453                          * transmit, start it transmitting, otherwise defer
 2454                          * until after handling receiver
 2455                          */
 2456                         if (sc->txb_inuse && --sc->txb_inuse)
 2457                                 ed_xmit(sc);
 2458                 }
 2459 
 2460                 /*
 2461                  * Handle receiver interrupts
 2462                  */
 2463                 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
 2464 
 2465                         /*
 2466                          * Overwrite warning. In order to make sure that a
 2467                          * lockup of the local DMA hasn't occurred, we reset
 2468                          * and re-init the NIC. The NSC manual suggests only a
 2469                          * partial reset/re-init is necessary - but some chips
 2470                          * seem to want more. The DMA lockup has been seen
 2471                          * only with early rev chips - Methinks this bug was
 2472                          * fixed in later revs. -DG
 2473                          */
 2474                         if (isr & ED_ISR_OVW) {
 2475                                 ifp->if_ierrors++;
 2476 #ifdef DIAGNOSTIC
 2477                                 log(LOG_WARNING,
 2478                                     "ed%d: warning - receiver ring buffer overrun\n",
 2479                                     ifp->if_unit);
 2480 #endif
 2481 
 2482                                 /*
 2483                                  * Stop/reset/re-init NIC
 2484                                  */
 2485                                 ed_reset(ifp);
 2486                         } else {
 2487 
 2488                                 /*
 2489                                  * Receiver Error. One or more of: CRC error,
 2490                                  * frame alignment error FIFO overrun, or
 2491                                  * missed packet.
 2492                                  */
 2493                                 if (isr & ED_ISR_RXE) {
 2494                                         u_char rsr;
 2495                                         rsr = inb(sc->nic_addr + ED_P0_RSR);
 2496                                         if (rsr & ED_RSR_CRC)
 2497                                                 sc->mibdata.dot3StatsFCSErrors++;
 2498                                         if (rsr & ED_RSR_FAE)
 2499                                                 sc->mibdata.dot3StatsAlignmentErrors++;
 2500                                         if (rsr & ED_RSR_FO)
 2501                                                 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
 2502                                         ifp->if_ierrors++;
 2503 #ifdef ED_DEBUG
 2504                                         printf("ed%d: receive error %x\n", ifp->if_unit,
 2505                                                inb(sc->nic_addr + ED_P0_RSR));
 2506 #endif
 2507                                 }
 2508 
 2509                                 /*
 2510                                  * Go get the packet(s) XXX - Doing this on an
 2511                                  * error is dubious because there shouldn't be
 2512                                  * any data to get (we've configured the
 2513                                  * interface to not accept packets with
 2514                                  * errors).
 2515                                  */
 2516 
 2517                                 /*
 2518                                  * Enable 16bit access to shared memory first
 2519                                  * on WD/SMC boards.
 2520                                  */
 2521                                 if (sc->isa16bit &&
 2522                                     (sc->vendor == ED_VENDOR_WD_SMC)) {
 2523 
 2524                                         outb(sc->asic_addr + ED_WD_LAAR,
 2525                                              sc->wd_laar_proto | ED_WD_LAAR_M16EN);
 2526                                         if (sc->is790) {
 2527                                                 outb(sc->asic_addr + ED_WD_MSR,
 2528                                                      ED_WD_MSR_MENB);
 2529                                         }
 2530                                 }
 2531                                 ed_rint(sc);
 2532 
 2533                                 /* disable 16bit access */
 2534                                 if (sc->isa16bit &&
 2535                                     (sc->vendor == ED_VENDOR_WD_SMC)) {
 2536 
 2537                                         if (sc->is790) {
 2538                                                 outb(sc->asic_addr + ED_WD_MSR, 0x00);
 2539                                         }
 2540                                         outb(sc->asic_addr + ED_WD_LAAR,
 2541                                              sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
 2542                                 }
 2543                         }
 2544                 }
 2545 
 2546                 /*
 2547                  * If it looks like the transmitter can take more data,
 2548                  * attempt to start output on the interface. This is done
 2549                  * after handling the receiver to give the receiver priority.
 2550                  */
 2551                 if ((ifp->if_flags & IFF_OACTIVE) == 0)
 2552                         ed_start(ifp);
 2553 
 2554                 /*
 2555                  * return NIC CR to standard state: page 0, remote DMA
 2556                  * complete, start (toggling the TXP bit off, even if was just
 2557                  * set in the transmit routine, is *okay* - it is 'edge'
 2558                  * triggered from low to high)
 2559                  */
 2560                 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
 2561 
 2562                 /*
 2563                  * If the Network Talley Counters overflow, read them to reset
 2564                  * them. It appears that old 8390's won't clear the ISR flag
 2565                  * otherwise - resulting in an infinite loop.
 2566                  */
 2567                 if (isr & ED_ISR_CNT) {
 2568                         (void) inb(sc->nic_addr + ED_P0_CNTR0);
 2569                         (void) inb(sc->nic_addr + ED_P0_CNTR1);
 2570                         (void) inb(sc->nic_addr + ED_P0_CNTR2);
 2571                 }
 2572         }
 2573 }
 2574 
 2575 void 
 2576 edintr(unit)
 2577         int unit;
 2578 {
 2579         edintr_sc (&ed_softc[unit]);
 2580 }
 2581 
 2582 /*
 2583  * Process an ioctl request. This code needs some work - it looks
 2584  *      pretty ugly.
 2585  */
 2586 static int
 2587 ed_ioctl(ifp, command, data)
 2588         register struct ifnet *ifp;
 2589         int     command;
 2590         caddr_t data;
 2591 {
 2592         struct ed_softc *sc = ifp->if_softc;
 2593         struct ifreq *ifr = (struct ifreq *) data;
 2594         int     s, error = 0;
 2595 
 2596         if (sc->gone) {
 2597                 ifp->if_flags &= ~IFF_RUNNING;
 2598                 return ENXIO;
 2599         }
 2600         s = splimp();
 2601 
 2602         switch (command) {
 2603 
 2604         case SIOCSIFADDR:
 2605         case SIOCGIFADDR:
 2606                 ether_ioctl(ifp, command, data);
 2607                 break;
 2608 
 2609         case SIOCSIFFLAGS:
 2610 
 2611                 /*
 2612                  * If the interface is marked up and stopped, then start it.
 2613                  * If it is marked down and running, then stop it.
 2614                  */
 2615                 if (ifp->if_flags & IFF_UP) {
 2616                         if ((ifp->if_flags & IFF_RUNNING) == 0)
 2617                                 ed_init(ifp->if_softc);
 2618                 } else {
 2619                         if (ifp->if_flags & IFF_RUNNING) {
 2620                                 ed_stop(sc);
 2621                                 ifp->if_flags &= ~IFF_RUNNING;
 2622                         }
 2623                 }
 2624 
 2625 #if NBPFILTER > 0
 2626 
 2627                 /*
 2628                  * Promiscuous flag may have changed, so reprogram the RCR.
 2629                  */
 2630                 ed_setrcr(sc);
 2631 #endif
 2632 
 2633                 /*
 2634                  * An unfortunate hack to provide the (required) software
 2635                  * control of the tranceiver for 3Com boards. The ALTPHYS flag
 2636                  * disables the tranceiver if set.
 2637                  */
 2638                 if (sc->vendor == ED_VENDOR_3COM) {
 2639                         if (ifp->if_flags & IFF_ALTPHYS) {
 2640                                 outb(sc->asic_addr + ED_3COM_CR, 0);
 2641                         } else {
 2642                                 outb(sc->asic_addr + ED_3COM_CR, ED_3COM_CR_XSEL);
 2643                         }
 2644                 } else if (sc->vendor == ED_VENDOR_HP) 
 2645                         ed_hpp_set_physical_link(sc);
 2646                 break;
 2647 
 2648         case SIOCADDMULTI:
 2649         case SIOCDELMULTI:
 2650                 /*
 2651                  * Update out multicast list.
 2652                  */
 2653                 error = (command == SIOCADDMULTI) ?
 2654                     ether_addmulti(ifr, &sc->arpcom) :
 2655                     ether_delmulti(ifr, &sc->arpcom);
 2656 
 2657                 if (error == ENETRESET) {
 2658 
 2659                         /*
 2660                          * Multicast list has changed; set the hardware filter
 2661                          * accordingly.
 2662                          */
 2663                         ed_setrcr(sc);
 2664                         error = 0;
 2665                 }
 2666                 break;
 2667 
 2668         case SIOCSIFMTU:
 2669                 /*
 2670                  * Set the interface MTU.
 2671                  */
 2672                 if (ifr->ifr_mtu > ETHERMTU) {
 2673                         error = EINVAL;
 2674                 } else {
 2675                         ifp->if_mtu = ifr->ifr_mtu;
 2676                 }
 2677                 break;
 2678 
 2679         default:
 2680                 error = EINVAL;
 2681         }
 2682         (void) splx(s);
 2683         return (error);
 2684 }
 2685 
 2686 /*
 2687  * Given a source and destination address, copy 'amount' of a packet from
 2688  *      the ring buffer into a linear destination buffer. Takes into account
 2689  *      ring-wrap.
 2690  */
 2691 static __inline char *
 2692 ed_ring_copy(sc, src, dst, amount)
 2693         struct ed_softc *sc;
 2694         char   *src;
 2695         char   *dst;
 2696         u_short amount;
 2697 {
 2698         u_short tmp_amount;
 2699 
 2700         /* does copy wrap to lower addr in ring buffer? */
 2701         if (src + amount > sc->mem_end) {
 2702                 tmp_amount = sc->mem_end - src;
 2703 
 2704                 /* copy amount up to end of NIC memory */
 2705                 if (sc->mem_shared)
 2706                         bcopy(src, dst, tmp_amount);
 2707                 else
 2708                         ed_pio_readmem(sc, (int)src, dst, tmp_amount);
 2709 
 2710                 amount -= tmp_amount;
 2711                 src = sc->mem_ring;
 2712                 dst += tmp_amount;
 2713         }
 2714         if (sc->mem_shared)
 2715                 bcopy(src, dst, amount);
 2716         else
 2717                 ed_pio_readmem(sc, (int)src, dst, amount);
 2718 
 2719         return (src + amount);
 2720 }
 2721 
 2722 /*
 2723  * Retreive packet from shared memory and send to the next level up via
 2724  *      ether_input(). If there is a BPF listener, give a copy to BPF, too.
 2725  */
 2726 static void
 2727 ed_get_packet(sc, buf, len, multicast)
 2728         struct ed_softc *sc;
 2729         char   *buf;
 2730         u_short len;
 2731         int     multicast;
 2732 {
 2733         struct ether_header *eh;
 2734         struct mbuf *m;
 2735 
 2736         /* Allocate a header mbuf */
 2737         MGETHDR(m, M_DONTWAIT, MT_DATA);
 2738         if (m == NULL)
 2739                 return;
 2740         m->m_pkthdr.rcvif = &sc->arpcom.ac_if;
 2741         m->m_pkthdr.len = m->m_len = len;
 2742 
 2743         /*
 2744          * We always put the received packet in a single buffer -
 2745          * either with just an mbuf header or in a cluster attached
 2746          * to the header. The +2 is to compensate for the alignment
 2747          * fixup below.
 2748          */
 2749         if ((len + 2) > MHLEN) {
 2750                 /* Attach an mbuf cluster */
 2751                 MCLGET(m, M_DONTWAIT);
 2752 
 2753                 /* Insist on getting a cluster */
 2754                 if ((m->m_flags & M_EXT) == 0) {
 2755                         m_freem(m);
 2756                         return;
 2757                 }
 2758         }
 2759 
 2760         /*
 2761          * The +2 is to longword align the start of the real packet.
 2762          * This is important for NFS.
 2763          */
 2764         m->m_data += 2;
 2765         eh = mtod(m, struct ether_header *);
 2766 
 2767 #ifdef BRIDGE
 2768         /*
 2769          * Get link layer header, invoke brige_in, then
 2770          * depending on the outcome of the test fetch the rest of the
 2771          * packet and either pass up or call bdg_forward.
 2772          */
 2773         if (do_bridge) {
 2774             struct ifnet *ifp ;
 2775             int need_more = 1 ; /* in case not bpf */
 2776 
 2777 #if NBPFILTER > 0
 2778             if (sc->arpcom.ac_if.if_bpf) {
 2779                 need_more = 0 ;
 2780                 ed_ring_copy(sc, buf, (char *)eh, len);
 2781                 bpf_mtap(&sc->arpcom.ac_if, m);
 2782             } else
 2783 #endif
 2784             ed_ring_copy(sc, buf, (char *)eh, 14);
 2785             ifp = bridge_in(m);
 2786             if (ifp == BDG_DROP) {
 2787                 m_freem(m);
 2788                 return ;
 2789             }
 2790             /* else fetch rest of pkt and continue */
 2791             if (need_more && len > 14)
 2792                 ed_ring_copy(sc, buf+14, (char *)(eh+1), len - 14);
 2793             if (ifp != BDG_LOCAL )
 2794                 bdg_forward(&m, ifp); /* not local, need forwarding */
 2795             if (ifp == BDG_LOCAL || ifp == BDG_BCAST || ifp == BDG_MCAST)
 2796                 goto getit ;
 2797             /* not local and not multicast, just drop it */
 2798             if (m)
 2799                 m_freem(m);
 2800             return ;
 2801         }
 2802 #endif
 2803         /*
 2804          * Get packet, including link layer address, from interface.
 2805          */
 2806         ed_ring_copy(sc, buf, (char *)eh, len);
 2807 
 2808 #if NBPFILTER > 0
 2809         /*
 2810          * Check if there's a BPF listener on this interface. If so, hand off
 2811          * the raw packet to bpf.
 2812          */
 2813         if (sc->arpcom.ac_if.if_bpf)
 2814                 bpf_mtap(&sc->arpcom.ac_if, m);
 2815 #endif
 2816 
 2817         /*
 2818          * If we are in promiscuous mode, we have to check if
 2819          * this packet is really ours.
 2820          */
 2821         if ((sc->arpcom.ac_if.if_flags & IFF_PROMISC) &&
 2822                 bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr,
 2823                     sizeof(eh->ether_dhost)) != 0 && multicast == 0) {
 2824                 m_freem(m);
 2825                 return;
 2826         }
 2827 
 2828 getit:
 2829         /*
 2830          * Remove link layer address.
 2831          */
 2832         m->m_pkthdr.len = m->m_len = len - sizeof(struct ether_header);
 2833         m->m_data += sizeof(struct ether_header);
 2834 
 2835         ether_input(&sc->arpcom.ac_if, eh, m);
 2836         return;
 2837 }
 2838 
 2839 /*
 2840  * Supporting routines
 2841  */
 2842 
 2843 /*
 2844  * Given a NIC memory source address and a host memory destination
 2845  *      address, copy 'amount' from NIC to host using Programmed I/O.
 2846  *      The 'amount' is rounded up to a word - okay as long as mbufs
 2847  *              are word sized.
 2848  *      This routine is currently Novell-specific.
 2849  */
 2850 static void
 2851 ed_pio_readmem(sc, src, dst, amount)
 2852         struct ed_softc *sc;
 2853         int src;
 2854         unsigned char *dst;
 2855         unsigned short amount;
 2856 {
 2857         /* HP cards need special handling */
 2858         if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
 2859                 ed_hpp_readmem(sc, src, dst, amount);
 2860                 return;
 2861         }
 2862                 
 2863         /* Regular Novell cards */
 2864         /* select page 0 registers */
 2865         outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
 2866 
 2867         /* round up to a word */
 2868         if (amount & 1)
 2869                 ++amount;
 2870 
 2871         /* set up DMA byte count */
 2872         outb(sc->nic_addr + ED_P0_RBCR0, amount);
 2873         outb(sc->nic_addr + ED_P0_RBCR1, amount >> 8);
 2874 
 2875         /* set up source address in NIC mem */
 2876         outb(sc->nic_addr + ED_P0_RSAR0, src);
 2877         outb(sc->nic_addr + ED_P0_RSAR1, src >> 8);
 2878 
 2879         outb(sc->nic_addr + ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
 2880 
 2881         if (sc->isa16bit) {
 2882                 insw(sc->asic_addr + ED_NOVELL_DATA, dst, amount / 2);
 2883         } else
 2884                 insb(sc->asic_addr + ED_NOVELL_DATA, dst, amount);
 2885 
 2886 }
 2887 
 2888 /*
 2889  * Stripped down routine for writing a linear buffer to NIC memory.
 2890  *      Only used in the probe routine to test the memory. 'len' must
 2891  *      be even.
 2892  */
 2893 static void
 2894 ed_pio_writemem(sc, src, dst, len)
 2895         struct ed_softc *sc;
 2896         char   *src;
 2897         unsigned short dst;
 2898         unsigned short len;
 2899 {
 2900         int     maxwait = 200;  /* about 240us */
 2901 
 2902         if (sc->vendor == ED_VENDOR_NOVELL) {
 2903 
 2904                 /* select page 0 registers */
 2905                 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
 2906 
 2907                 /* reset remote DMA complete flag */
 2908                 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
 2909 
 2910                 /* set up DMA byte count */
 2911                 outb(sc->nic_addr + ED_P0_RBCR0, len);
 2912                 outb(sc->nic_addr + ED_P0_RBCR1, len >> 8);
 2913 
 2914                 /* set up destination address in NIC mem */
 2915                 outb(sc->nic_addr + ED_P0_RSAR0, dst);
 2916                 outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
 2917 
 2918                 /* set remote DMA write */
 2919                 outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
 2920 
 2921                 if (sc->isa16bit)
 2922                         outsw(sc->asic_addr + ED_NOVELL_DATA, src, len / 2);
 2923                 else
 2924                         outsb(sc->asic_addr + ED_NOVELL_DATA, src, len);
 2925 
 2926                 /*
 2927                  * Wait for remote DMA complete. This is necessary because on the
 2928                  * transmit side, data is handled internally by the NIC in bursts and
 2929                  * we can't start another remote DMA until this one completes. Not
 2930                  * waiting causes really bad things to happen - like the NIC
 2931                  * irrecoverably jamming the ISA bus.
 2932                  */
 2933                 while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
 2934 
 2935         } else if ((sc->vendor == ED_VENDOR_HP) && 
 2936                    (sc->type == ED_TYPE_HP_PCLANPLUS)) { 
 2937 
 2938                 /* HP PCLAN+ */
 2939 
 2940                 /* reset remote DMA complete flag */
 2941                 outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
 2942 
 2943                 /* program the write address in RAM */
 2944                 outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
 2945 
 2946                 if (sc->hpp_mem_start) {
 2947                         u_short *s = (u_short *) src;
 2948                         volatile u_short *d = (u_short *) sc->hpp_mem_start;
 2949                         u_short *const fence = s + (len >> 1);
 2950 
 2951                         /*
 2952                          * Enable memory mapped access.
 2953                          */
 2954 
 2955                         outw(sc->asic_addr + ED_HPP_OPTION, 
 2956                              sc->hpp_options & 
 2957                                 ~(ED_HPP_OPTION_MEM_DISABLE | 
 2958                                   ED_HPP_OPTION_BOOT_ROM_ENB));
 2959 
 2960                         /*
 2961                          * Copy to NIC memory.
 2962                          */
 2963 
 2964                         while (s < fence)
 2965                                 *d = *s++;
 2966 
 2967                         /*
 2968                          * Restore Boot ROM access.
 2969                          */
 2970 
 2971                         outw(sc->asic_addr + ED_HPP_OPTION,
 2972                              sc->hpp_options);
 2973 
 2974                 } else {
 2975                         /* write data using I/O writes */
 2976                         outsw(sc->asic_addr + ED_HPP_PAGE_4, src, len / 2);
 2977                 }
 2978 
 2979         }
 2980 }
 2981 
 2982 /*
 2983  * Write an mbuf chain to the destination NIC memory address using
 2984  *      programmed I/O.
 2985  */
 2986 static u_short
 2987 ed_pio_write_mbufs(sc, m, dst)
 2988         struct ed_softc *sc;
 2989         struct mbuf *m;
 2990         int dst;
 2991 {
 2992         struct ifnet *ifp = (struct ifnet *)sc;
 2993         unsigned short total_len, dma_len;
 2994         struct mbuf *mp;
 2995         int     maxwait = 200;  /* about 240us */
 2996 
 2997         /*  HP PC Lan+ cards need special handling */
 2998         if ((sc->vendor == ED_VENDOR_HP) && 
 2999             (sc->type == ED_TYPE_HP_PCLANPLUS)) {
 3000                 return ed_hpp_write_mbufs(sc, m, dst);
 3001         }
 3002 
 3003         /* First, count up the total number of bytes to copy */
 3004         for (total_len = 0, mp = m; mp; mp = mp->m_next)
 3005                 total_len += mp->m_len;
 3006 
 3007         dma_len = total_len;
 3008         if (sc->isa16bit && (dma_len & 1))
 3009                 dma_len++;
 3010 
 3011         /* select page 0 registers */
 3012         outb(sc->nic_addr + ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
 3013 
 3014         /* reset remote DMA complete flag */
 3015         outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
 3016 
 3017         /* set up DMA byte count */
 3018         outb(sc->nic_addr + ED_P0_RBCR0, dma_len);
 3019         outb(sc->nic_addr + ED_P0_RBCR1, dma_len >> 8);
 3020 
 3021         /* set up destination address in NIC mem */
 3022         outb(sc->nic_addr + ED_P0_RSAR0, dst);
 3023         outb(sc->nic_addr + ED_P0_RSAR1, dst >> 8);
 3024 
 3025         /* set remote DMA write */
 3026         outb(sc->nic_addr + ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
 3027 
 3028   /*
 3029    * Transfer the mbuf chain to the NIC memory.
 3030    * 16-bit cards require that data be transferred as words, and only words.
 3031    * So that case requires some extra code to patch over odd-length mbufs.
 3032    */
 3033 
 3034         if (!sc->isa16bit) {
 3035                 /* NE1000s are easy */
 3036                 while (m) {
 3037                         if (m->m_len) {
 3038                                 outsb(sc->asic_addr + ED_NOVELL_DATA,
 3039                                       m->m_data, m->m_len);
 3040                         }
 3041                         m = m->m_next;
 3042                 }
 3043         } else {
 3044                 /* NE2000s are a pain */
 3045                 unsigned char *data;
 3046                 int len, wantbyte;
 3047                 unsigned char savebyte[2];
 3048 
 3049                 wantbyte = 0;
 3050 
 3051                 while (m) {
 3052                         len = m->m_len;
 3053                         if (len) {
 3054                                 data = mtod(m, caddr_t);
 3055                                 /* finish the last word */
 3056                                 if (wantbyte) {
 3057                                         savebyte[1] = *data;
 3058                                         outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
 3059                                         data++;
 3060                                         len--;
 3061                                         wantbyte = 0;
 3062                                 }
 3063                                 /* output contiguous words */
 3064                                 if (len > 1) {
 3065                                         outsw(sc->asic_addr + ED_NOVELL_DATA,
 3066                                               data, len >> 1);
 3067                                         data += len & ~1;
 3068                                         len &= 1;
 3069                                 }
 3070                                 /* save last byte, if necessary */
 3071                                 if (len == 1) {
 3072                                         savebyte[0] = *data;
 3073                                         wantbyte = 1;
 3074                                 }
 3075                         }
 3076                         m = m->m_next;
 3077                 }
 3078                 /* spit last byte */
 3079                 if (wantbyte) {
 3080                         outw(sc->asic_addr + ED_NOVELL_DATA, *(u_short *)savebyte);
 3081                 }
 3082         }
 3083 
 3084         /*
 3085          * Wait for remote DMA complete. This is necessary because on the
 3086          * transmit side, data is handled internally by the NIC in bursts and
 3087          * we can't start another remote DMA until this one completes. Not
 3088          * waiting causes really bad things to happen - like the NIC
 3089          * irrecoverably jamming the ISA bus.
 3090          */
 3091         while (((inb(sc->nic_addr + ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
 3092 
 3093         if (!maxwait) {
 3094                 log(LOG_WARNING, "ed%d: remote transmit DMA failed to complete\n",
 3095                     ifp->if_unit);
 3096                 ed_reset(ifp);
 3097                 return(0);
 3098         }
 3099         return (total_len);
 3100 }
 3101 
 3102 /*
 3103  * Support routines to handle the HP PC Lan+ card.
 3104  */
 3105 
 3106 /*
 3107  * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
 3108  * IO.
 3109  */
 3110 
 3111 static void
 3112 ed_hpp_readmem(sc, src, dst, amount)
 3113         struct ed_softc *sc; 
 3114         unsigned short src;
 3115         unsigned char *dst;
 3116         unsigned short amount;
 3117 {
 3118 
 3119         int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
 3120 
 3121 
 3122         /* Program the source address in RAM */
 3123         outw(sc->asic_addr + ED_HPP_PAGE_2, src);
 3124 
 3125         /*
 3126          * The HP PC Lan+ card supports word reads as well as
 3127          * a memory mapped i/o port that is aliased to every 
 3128          * even address on the board.
 3129          */
 3130 
 3131         if (sc->hpp_mem_start) {
 3132 
 3133                 /* Enable memory mapped access.  */
 3134                 outw(sc->asic_addr + ED_HPP_OPTION, 
 3135                      sc->hpp_options & 
 3136                         ~(ED_HPP_OPTION_MEM_DISABLE | 
 3137                           ED_HPP_OPTION_BOOT_ROM_ENB));
 3138 
 3139                 if (use_32bit_access && (amount > 3)) {
 3140                         u_long *dl = (u_long *) dst;    
 3141                         volatile u_long *const sl = 
 3142                                 (u_long *) sc->hpp_mem_start;
 3143                         u_long *const fence = dl + (amount >> 2);
 3144                         
 3145                         /* Copy out NIC data.  We could probably write this
 3146                            as a `movsl'. The currently generated code is lousy.
 3147                            */
 3148 
 3149                         while (dl < fence)
 3150                                 *dl++ = *sl;
 3151                 
 3152                         dst += (amount & ~3);
 3153                         amount &= 3;
 3154 
 3155                 } 
 3156 
 3157                 /* Finish off any words left, as a series of short reads */
 3158                 if (amount > 1) {
 3159                         u_short *d = (u_short *) dst;   
 3160                         volatile u_short *const s = 
 3161                                 (u_short *) sc->hpp_mem_start;
 3162                         u_short *const fence = d + (amount >> 1);
 3163                         
 3164                         /* Copy out NIC data.  */
 3165 
 3166                         while (d < fence)
 3167                                 *d++ = *s;
 3168         
 3169                         dst += (amount & ~1);
 3170                         amount &= 1;
 3171                 }
 3172 
 3173                 /*
 3174                  * read in a byte; however we need to always read 16 bits
 3175                  * at a time or the hardware gets into a funny state
 3176                  */
 3177 
 3178                 if (amount == 1) {
 3179                         /* need to read in a short and copy LSB */
 3180                         volatile u_short *const s = 
 3181                                 (volatile u_short *) sc->hpp_mem_start;
 3182                         
 3183                         *dst = (*s) & 0xFF;     
 3184                 }
 3185 
 3186                 /* Restore Boot ROM access.  */
 3187 
 3188                 outw(sc->asic_addr + ED_HPP_OPTION,
 3189                      sc->hpp_options);
 3190 
 3191 
 3192         } else { 
 3193                 /* Read in data using the I/O port */
 3194                 if (use_32bit_access && (amount > 3)) {
 3195                         insl(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 2);
 3196                         dst += (amount & ~3);
 3197                         amount &= 3;
 3198                 }
 3199                 if (amount > 1) {
 3200                         insw(sc->asic_addr + ED_HPP_PAGE_4, dst, amount >> 1);
 3201                         dst += (amount & ~1);
 3202                         amount &= 1;
 3203                 }
 3204                 if (amount == 1) { /* read in a short and keep the LSB */
 3205                         *dst = inw(sc->asic_addr + ED_HPP_PAGE_4) & 0xFF;
 3206                 }
 3207         }
 3208 }
 3209 
 3210 /*
 3211  * Write to HP PC Lan+ NIC memory.  Access to the NIC can be by using 
 3212  * outsw() or via the memory mapped interface to the same register.
 3213  * Writes have to be in word units; byte accesses won't work and may cause
 3214  * the NIC to behave wierdly. Long word accesses are permitted if the ASIC
 3215  * allows it.
 3216  */
 3217 
 3218 static u_short
 3219 ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
 3220 {
 3221         int len, wantbyte;
 3222         unsigned short total_len;
 3223         unsigned char savebyte[2];
 3224         volatile u_short * const d = 
 3225                 (volatile u_short *) sc->hpp_mem_start;
 3226         int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
 3227 
 3228         /* select page 0 registers */
 3229         outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
 3230 
 3231         /* reset remote DMA complete flag */
 3232         outb(sc->nic_addr + ED_P0_ISR, ED_ISR_RDC);
 3233 
 3234         /* program the write address in RAM */
 3235         outw(sc->asic_addr + ED_HPP_PAGE_0, dst);
 3236 
 3237         if (sc->hpp_mem_start)  /* enable memory mapped I/O */
 3238                 outw(sc->asic_addr + ED_HPP_OPTION, sc->hpp_options & 
 3239                         ~(ED_HPP_OPTION_MEM_DISABLE |
 3240                         ED_HPP_OPTION_BOOT_ROM_ENB));
 3241 
 3242         wantbyte = 0;
 3243         total_len = 0;
 3244 
 3245         if (sc->hpp_mem_start) {        /* Memory mapped I/O port */
 3246                 while (m) {
 3247                         total_len += (len = m->m_len);
 3248                         if (len) {
 3249                                 caddr_t data = mtod(m, caddr_t);
 3250                                 /* finish the last word of the previous mbuf */
 3251                                 if (wantbyte) {
 3252                                         savebyte[1] = *data;
 3253                                         *d = *((ushort *) savebyte);
 3254                                         data++; len--; wantbyte = 0;
 3255                                 }
 3256                                 /* output contiguous words */
 3257                                 if ((len > 3) && (use_32bit_accesses)) {
 3258                                         volatile u_long *const dl = 
 3259                                                 (volatile u_long *) d;
 3260                                         u_long *sl = (u_long *) data;
 3261                                         u_long *fence = sl + (len >> 2);
 3262 
 3263                                         while (sl < fence)
 3264                                                 *dl = *sl++;
 3265 
 3266                                         data += (len & ~3);
 3267                                         len &= 3;
 3268                                 }
 3269                                 /* finish off remain 16 bit writes */
 3270                                 if (len > 1) {
 3271                                         u_short *s = (u_short *) data;
 3272                                         u_short *fence = s + (len >> 1);
 3273 
 3274                                         while (s < fence)
 3275                                                 *d = *s++;
 3276 
 3277                                         data += (len & ~1); 
 3278                                         len &= 1;
 3279                                 }
 3280                                 /* save last byte if needed */
 3281                                 if (wantbyte = (len == 1)) 
 3282                                         savebyte[0] = *data;
 3283                         }
 3284                         m = m->m_next;  /* to next mbuf */
 3285                 }
 3286                 if (wantbyte) /* write last byte */
 3287                         *d = *((u_short *) savebyte);
 3288         } else {
 3289                 /* use programmed I/O */
 3290                 while (m) {
 3291                         total_len += (len = m->m_len);
 3292                         if (len) {
 3293                                 caddr_t data = mtod(m, caddr_t);
 3294                                 /* finish the last word of the previous mbuf */
 3295                                 if (wantbyte) {
 3296                                         savebyte[1] = *data;
 3297                                         outw(sc->asic_addr + ED_HPP_PAGE_4, 
 3298                                              *((u_short *)savebyte));
 3299                                         data++; 
 3300                                         len--; 
 3301                                         wantbyte = 0;
 3302                                 }
 3303                                 /* output contiguous words */
 3304                                 if ((len > 3) && use_32bit_accesses) {
 3305                                         outsl(sc->asic_addr + ED_HPP_PAGE_4,
 3306                                                 data, len >> 2);
 3307                                         data += (len & ~3);
 3308                                         len &= 3;
 3309                                 }
 3310                                 /* finish off remaining 16 bit accesses */
 3311                                 if (len > 1) {
 3312                                         outsw(sc->asic_addr + ED_HPP_PAGE_4,
 3313                                               data, len >> 1);
 3314                                         data += (len & ~1);
 3315                                         len &= 1;
 3316                                 }
 3317                                 if (wantbyte = (len == 1)) 
 3318                                         savebyte[0] = *data;
 3319 
 3320                         } /* if len != 0 */
 3321                         m = m->m_next;
 3322                 }
 3323                 if (wantbyte) /* spit last byte */
 3324                         outw(sc->asic_addr + ED_HPP_PAGE_4, 
 3325                                 *(u_short *)savebyte);
 3326 
 3327         }
 3328 
 3329         if (sc->hpp_mem_start)  /* turn off memory mapped i/o */
 3330                 outw(sc->asic_addr + ED_HPP_OPTION,
 3331                      sc->hpp_options);
 3332 
 3333         return (total_len);
 3334 }
 3335 
 3336 static void
 3337 ed_setrcr(sc)
 3338         struct ed_softc *sc;
 3339 {
 3340         struct ifnet *ifp = (struct ifnet *)sc;
 3341         int     i;
 3342 
 3343         /* set page 1 registers */
 3344         outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
 3345 
 3346         if (ifp->if_flags & IFF_PROMISC) {
 3347 
 3348                 /*
 3349                  * Reconfigure the multicast filter.
 3350                  */
 3351                 for (i = 0; i < 8; i++)
 3352                         outb(sc->nic_addr + ED_P1_MAR0 + i, 0xff);
 3353 
 3354                 /*
 3355                  * And turn on promiscuous mode. Also enable reception of
 3356                  * runts and packets with CRC & alignment errors.
 3357                  */
 3358                 /* Set page 0 registers */
 3359                 outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
 3360 
 3361                 outb(sc->nic_addr + ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
 3362                      ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP);
 3363         } else {
 3364                 /* set up multicast addresses and filter modes */
 3365                 if (ifp->if_flags & IFF_MULTICAST) {
 3366                         u_long  mcaf[2];
 3367 
 3368                         if (ifp->if_flags & IFF_ALLMULTI) {
 3369                                 mcaf[0] = 0xffffffff;
 3370                                 mcaf[1] = 0xffffffff;
 3371                         } else
 3372                                 ds_getmcaf(sc, mcaf);
 3373 
 3374                         /*
 3375                          * Set multicast filter on chip.
 3376                          */
 3377                         for (i = 0; i < 8; i++)
 3378                                 outb(sc->nic_addr + ED_P1_MAR0 + i, ((u_char *) mcaf)[i]);
 3379 
 3380                         /* Set page 0 registers */
 3381                         outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
 3382 
 3383                         outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AM | ED_RCR_AB);
 3384                 } else {
 3385 
 3386                         /*
 3387                          * Initialize multicast address hashing registers to
 3388                          * not accept multicasts.
 3389                          */
 3390                         for (i = 0; i < 8; ++i)
 3391                                 outb(sc->nic_addr + ED_P1_MAR0 + i, 0x00);
 3392 
 3393                         /* Set page 0 registers */
 3394                         outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STP);
 3395 
 3396                         outb(sc->nic_addr + ED_P0_RCR, ED_RCR_AB);
 3397                 }
 3398         }
 3399 
 3400         /*
 3401          * Start interface.
 3402          */
 3403         outb(sc->nic_addr + ED_P0_CR, sc->cr_proto | ED_CR_STA);
 3404 }
 3405 
 3406 /*
 3407  * Compute crc for ethernet address
 3408  */
 3409 static u_long
 3410 ds_crc(ep)
 3411         u_char *ep;
 3412 {
 3413 #define POLYNOMIAL 0x04c11db6
 3414         register u_long crc = 0xffffffffL;
 3415         register int carry, i, j;
 3416         register u_char b;
 3417 
 3418         for (i = 6; --i >= 0;) {
 3419                 b = *ep++;
 3420                 for (j = 8; --j >= 0;) {
 3421                         carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01);
 3422                         crc <<= 1;
 3423                         b >>= 1;
 3424                         if (carry)
 3425                                 crc = ((crc ^ POLYNOMIAL) | carry);
 3426                 }
 3427         }
 3428         return crc;
 3429 #undef POLYNOMIAL
 3430 }
 3431 
 3432 /*
 3433  * Compute the multicast address filter from the
 3434  * list of multicast addresses we need to listen to.
 3435  */
 3436 static void
 3437 ds_getmcaf(sc, mcaf)
 3438         struct ed_softc *sc;
 3439         u_long *mcaf;
 3440 {
 3441         register u_int index;
 3442         register u_char *af = (u_char *) mcaf;
 3443         register struct ether_multi *enm;
 3444         register struct ether_multistep step;
 3445 
 3446         mcaf[0] = 0;
 3447         mcaf[1] = 0;
 3448 
 3449         ETHER_FIRST_MULTI(step, &sc->arpcom, enm);
 3450         while (enm != NULL) {
 3451                 if (bcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) {
 3452                         mcaf[0] = 0xffffffff;
 3453                         mcaf[1] = 0xffffffff;
 3454                         return;
 3455                 }
 3456                 index = ds_crc(enm->enm_addrlo) >> 26;
 3457                 af[index >> 3] |= 1 << (index & 7);
 3458 
 3459                 ETHER_NEXT_MULTI(step, enm);
 3460         }
 3461 }

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