1 /*
2 * Copyright (C) 1993, David Greenman. This software may be used, modified,
3 * copied, distributed, and sold, in both source and binary form provided
4 * that the above copyright and these terms are retained. Under no
5 * circumstances is the author responsible for the proper functioning
6 * of this software, nor does the author assume any responsibility
7 * for damages incurred with its use.
8 *
9 * $FreeBSD$
10 */
11 /*
12 * National Semiconductor DS8390 NIC register definitions
13 *
14 *
15 * Modification history
16 *
17 * Revision 2.2 1993/11/29 16:33:39 davidg
18 * From Thomas Sandford <t.d.g.sandford@comp.brad.ac.uk>
19 * Add support for the 8013W board type
20 *
21 * Revision 2.1 1993/11/22 10:52:33 davidg
22 * patch to add support for SMC8216 (Elite-Ultra) boards
23 * from Glen H. Lowe
24 *
25 * Revision 2.0 93/09/29 00:37:15 davidg
26 * changed double buffering flag to multi buffering
27 * made changes/additions for 3c503 multi-buffering
28 * ...companion to Rev. 2.0 of 'ed' driver.
29 *
30 * Revision 1.1 93/06/23 03:01:07 davidg
31 * Initial revision
32 *
33 */
34
35 /*
36 * Page 0 register offsets
37 */
38 #define ED_P0_CR 0x00 /* Command Register */
39
40 #define ED_P0_CLDA0 0x01 /* Current Local DMA Addr low (read) */
41 #define ED_P0_PSTART 0x01 /* Page Start register (write) */
42
43 #define ED_P0_CLDA1 0x02 /* Current Local DMA Addr high (read) */
44 #define ED_P0_PSTOP 0x02 /* Page Stop register (write) */
45
46 #define ED_P0_BNRY 0x03 /* Boundary Pointer */
47
48 #define ED_P0_TSR 0x04 /* Transmit Status Register (read) */
49 #define ED_P0_TPSR 0x04 /* Transmit Page Start (write) */
50
51 #define ED_P0_NCR 0x05 /* Number of Collisions Reg (read) */
52 #define ED_P0_TBCR0 0x05 /* Transmit Byte count, low (write) */
53
54 #define ED_P0_FIFO 0x06 /* FIFO register (read) */
55 #define ED_P0_TBCR1 0x06 /* Transmit Byte count, high (write) */
56
57 #define ED_P0_ISR 0x07 /* Interrupt Status Register */
58
59 #define ED_P0_CRDA0 0x08 /* Current Remote DMA Addr low (read) */
60 #define ED_P0_RSAR0 0x08 /* Remote Start Address low (write) */
61
62 #define ED_P0_CRDA1 0x09 /* Current Remote DMA Addr high (read) */
63 #define ED_P0_RSAR1 0x09 /* Remote Start Address high (write) */
64
65 #define ED_P0_RBCR0 0x0a /* Remote Byte Count low (write) */
66
67 #define ED_P0_RBCR1 0x0b /* Remote Byte Count high (write) */
68
69 #define ED_P0_RSR 0x0c /* Receive Status (read) */
70 #define ED_P0_RCR 0x0c /* Receive Configuration Reg (write) */
71
72 #define ED_P0_CNTR0 0x0d /* frame alignment error counter (read) */
73 #define ED_P0_TCR 0x0d /* Transmit Configuration Reg (write) */
74
75 #define ED_P0_CNTR1 0x0e /* CRC error counter (read) */
76 #define ED_P0_DCR 0x0e /* Data Configuration Reg (write) */
77
78 #define ED_P0_CNTR2 0x0f /* missed packet counter (read) */
79 #define ED_P0_IMR 0x0f /* Interrupt Mask Register (write) */
80
81 /*
82 * Page 1 register offsets
83 */
84 #define ED_P1_CR 0x00 /* Command Register */
85 #define ED_P1_PAR0 0x01 /* Physical Address Register 0 */
86 #define ED_P1_PAR1 0x02 /* Physical Address Register 1 */
87 #define ED_P1_PAR2 0x03 /* Physical Address Register 2 */
88 #define ED_P1_PAR3 0x04 /* Physical Address Register 3 */
89 #define ED_P1_PAR4 0x05 /* Physical Address Register 4 */
90 #define ED_P1_PAR5 0x06 /* Physical Address Register 5 */
91 #define ED_P1_PAR(i) (ED_P1_PAR0 + i)
92 #define ED_P1_CURR 0x07 /* Current RX ring-buffer page */
93 #define ED_P1_MAR0 0x08 /* Multicast Address Register 0 */
94 #define ED_P1_MAR1 0x09 /* Multicast Address Register 1 */
95 #define ED_P1_MAR2 0x0a /* Multicast Address Register 2 */
96 #define ED_P1_MAR3 0x0b /* Multicast Address Register 3 */
97 #define ED_P1_MAR4 0x0c /* Multicast Address Register 4 */
98 #define ED_P1_MAR5 0x0d /* Multicast Address Register 5 */
99 #define ED_P1_MAR6 0x0e /* Multicast Address Register 6 */
100 #define ED_P1_MAR7 0x0f /* Multicast Address Register 7 */
101 #define ED_P1_MAR(i) (ED_P1_MAR0 + i)
102
103 /*
104 * Page 2 register offsets
105 */
106 #define ED_P2_CR 0x00 /* Command Register */
107 #define ED_P2_PSTART 0x01 /* Page Start (read) */
108 #define ED_P2_CLDA0 0x01 /* Current Local DMA Addr 0 (write) */
109 #define ED_P2_PSTOP 0x02 /* Page Stop (read) */
110 #define ED_P2_CLDA1 0x02 /* Current Local DMA Addr 1 (write) */
111 #define ED_P2_RNPP 0x03 /* Remote Next Packet Pointer */
112 #define ED_P2_TPSR 0x04 /* Transmit Page Start (read) */
113 #define ED_P2_LNPP 0x05 /* Local Next Packet Pointer */
114 #define ED_P2_ACU 0x06 /* Address Counter Upper */
115 #define ED_P2_ACL 0x07 /* Address Counter Lower */
116 #define ED_P2_RCR 0x0c /* Receive Configuration Register (read) */
117 #define ED_P2_TCR 0x0d /* Transmit Configuration Register (read) */
118 #define ED_P2_DCR 0x0e /* Data Configuration Register (read) */
119 #define ED_P2_IMR 0x0f /* Interrupt Mask Register (read) */
120
121 /*
122 * Command Register (CR) definitions
123 */
124
125 /*
126 * STP: SToP. Software reset command. Takes the controller offline. No
127 * packets will be received or transmitted. Any reception or
128 * transmission in progress will continue to completion before
129 * entering reset state. To exit this state, the STP bit must
130 * reset and the STA bit must be set. The software reset has
131 * executed only when indicated by the RST bit in the ISR being
132 * set.
133 */
134 #define ED_CR_STP 0x01
135
136 /*
137 * STA: STArt. This bit is used to activate the NIC after either power-up,
138 * or when the NIC has been put in reset mode by software command
139 * or error.
140 */
141 #define ED_CR_STA 0x02
142
143 /*
144 * TXP: Transmit Packet. This bit must be set to indicate transmission of
145 * a packet. TXP is internally reset either after the transmission is
146 * completed or aborted. This bit should be set only after the Transmit
147 * Byte Count and Transmit Page Start register have been programmed.
148 */
149 #define ED_CR_TXP 0x04
150
151 /*
152 * RD0, RD1, RD2: Remote DMA Command. These three bits control the operation
153 * of the remote DMA channel. RD2 can be set to abort any remote DMA
154 * command in progress. The Remote Byte Count registers should be cleared
155 * when a remote DMA has been aborted. The Remote Start Addresses are not
156 * restored to the starting address if the remote DMA is aborted.
157 *
158 * RD2 RD1 RD0 function
159 * 0 0 0 not allowed
160 * 0 0 1 remote read
161 * 0 1 0 remote write
162 * 0 1 1 send packet
163 * 1 X X abort
164 */
165 #define ED_CR_RD0 0x08
166 #define ED_CR_RD1 0x10
167 #define ED_CR_RD2 0x20
168
169 /*
170 * PS0, PS1: Page Select. The two bits select which register set or 'page' to
171 * access.
172 *
173 * PS1 PS0 page
174 * 0 0 0
175 * 0 1 1
176 * 1 0 2
177 * 1 1 reserved
178 */
179 #define ED_CR_PS0 0x40
180 #define ED_CR_PS1 0x80
181 /* bit encoded aliases */
182 #define ED_CR_PAGE_0 0x00 /* (for consistency) */
183 #define ED_CR_PAGE_1 0x40
184 #define ED_CR_PAGE_2 0x80
185
186 /*
187 * Interrupt Status Register (ISR) definitions
188 */
189
190 /*
191 * PRX: Packet Received. Indicates packet received with no errors.
192 */
193 #define ED_ISR_PRX 0x01
194
195 /*
196 * PTX: Packet Transmitted. Indicates packet transmitted with no errors.
197 */
198 #define ED_ISR_PTX 0x02
199
200 /*
201 * RXE: Receive Error. Indicates that a packet was received with one or more
202 * the following errors: CRC error, frame alignment error, FIFO overrun,
203 * missed packet.
204 */
205 #define ED_ISR_RXE 0x04
206
207 /*
208 * TXE: Transmission Error. Indicates that an attempt to transmit a packet
209 * resulted in one or more of the following errors: excessive
210 * collisions, FIFO underrun.
211 */
212 #define ED_ISR_TXE 0x08
213
214 /*
215 * OVW: OverWrite. Indicates a receive ring-buffer overrun. Incoming network
216 * would exceed (has exceeded?) the boundary pointer, resulting in data
217 * that was previously received and not yet read from the buffer to be
218 * overwritten.
219 */
220 #define ED_ISR_OVW 0x10
221
222 /*
223 * CNT: Counter Overflow. Set when the MSB of one or more of the Network Talley
224 * Counters has been set.
225 */
226 #define ED_ISR_CNT 0x20
227
228 /*
229 * RDC: Remote Data Complete. Indicates that a Remote DMA operation has completed.
230 */
231 #define ED_ISR_RDC 0x40
232
233 /*
234 * RST: Reset status. Set when the NIC enters the reset state and cleared when a
235 * Start Command is issued to the CR. This bit is also set when a receive
236 * ring-buffer overrun (OverWrite) occurs and is cleared when one or more
237 * packets have been removed from the ring. This is a read-only bit.
238 */
239 #define ED_ISR_RST 0x80
240
241 /*
242 * Interrupt Mask Register (IMR) definitions
243 */
244
245 /*
246 * PRXE: Packet Received interrupt Enable. If set, a received packet will cause
247 * an interrupt.
248 */
249 #define ED_IMR_PRXE 0x01
250
251 /*
252 * PTXE: Packet Transmit interrupt Enable. If set, an interrupt is generated when
253 * a packet transmission completes.
254 */
255 #define ED_IMR_PTXE 0x02
256
257 /*
258 * RXEE: Receive Error interrupt Enable. If set, an interrupt will occur whenever a
259 * packet is received with an error.
260 */
261 #define ED_IMR_RXEE 0x04
262
263 /*
264 * TXEE: Transmit Error interrupt Enable. If set, an interrupt will occur whenever
265 * a transmission results in an error.
266 */
267 #define ED_IMR_TXEE 0x08
268
269 /*
270 * OVWE: OverWrite error interrupt Enable. If set, an interrupt is generated whenever
271 * the receive ring-buffer is overrun. i.e. when the boundary pointer is exceeded.
272 */
273 #define ED_IMR_OVWE 0x10
274
275 /*
276 * CNTE: Counter overflow interrupt Enable. If set, an interrupt is generated whenever
277 * the MSB of one or more of the Network Statistics counters has been set.
278 */
279 #define ED_IMR_CNTE 0x20
280
281 /*
282 * RDCE: Remote DMA Complete interrupt Enable. If set, an interrupt is generated
283 * when a remote DMA transfer has completed.
284 */
285 #define ED_IMR_RDCE 0x40
286
287 /*
288 * bit 7 is unused/reserved
289 */
290
291 /*
292 * Data Configuration Register (DCR) definitions
293 */
294
295 /*
296 * WTS: Word Transfer Select. WTS establishes byte or word transfers for
297 * both remote and local DMA transfers
298 */
299 #define ED_DCR_WTS 0x01
300
301 /*
302 * BOS: Byte Order Select. BOS sets the byte order for the host.
303 * Should be 0 for 80x86, and 1 for 68000 series processors
304 */
305 #define ED_DCR_BOS 0x02
306
307 /*
308 * LAS: Long Address Select. When LAS is 1, the contents of the remote
309 * DMA registers RSAR0 and RSAR1 are used to provide A16-A31
310 */
311 #define ED_DCR_LAS 0x04
312
313 /*
314 * LS: Loopback Select. When 0, loopback mode is selected. Bits D1 and D2
315 * of the TCR must also be programmed for loopback operation.
316 * When 1, normal operation is selected.
317 */
318 #define ED_DCR_LS 0x08
319
320 /*
321 * AR: Auto-initialize Remote. When 0, data must be removed from ring-buffer
322 * under program control. When 1, remote DMA is automatically initiated
323 * and the boundary pointer is automatically updated
324 */
325 #define ED_DCR_AR 0x10
326
327 /*
328 * FT0, FT1: Fifo Threshold select.
329 * FT1 FT0 Word-width Byte-width
330 * 0 0 1 word 2 bytes
331 * 0 1 2 words 4 bytes
332 * 1 0 4 words 8 bytes
333 * 1 1 8 words 12 bytes
334 *
335 * During transmission, the FIFO threshold indicates the number of bytes
336 * or words that the FIFO has filled from the local DMA before BREQ is
337 * asserted. The transmission threshold is 16 bytes minus the receiver
338 * threshold.
339 */
340 #define ED_DCR_FT0 0x20
341 #define ED_DCR_FT1 0x40
342
343 /*
344 * bit 7 (0x80) is unused/reserved
345 */
346
347 /*
348 * Transmit Configuration Register (TCR) definitions
349 */
350
351 /*
352 * CRC: Inhibit CRC. If 0, CRC will be appended by the transmitter, if 0, CRC
353 * is not appended by the transmitter.
354 */
355 #define ED_TCR_CRC 0x01
356
357 /*
358 * LB0, LB1: Loopback control. These two bits set the type of loopback that is
359 * to be performed.
360 *
361 * LB1 LB0 mode
362 * 0 0 0 - normal operation (DCR_LS = 0)
363 * 0 1 1 - internal loopback (DCR_LS = 0)
364 * 1 0 2 - external loopback (DCR_LS = 1)
365 * 1 1 3 - external loopback (DCR_LS = 0)
366 */
367 #define ED_TCR_LB0 0x02
368 #define ED_TCR_LB1 0x04
369
370 /*
371 * ATD: Auto Transmit Disable. Clear for normal operation. When set, allows
372 * another station to disable the NIC's transmitter by transmitting to
373 * a multicast address hashing to bit 62. Reception of a multicast address
374 * hashing to bit 63 enables the transmitter.
375 */
376 #define ED_TCR_ATD 0x08
377
378 /*
379 * OFST: Collision Offset enable. This bit when set modifies the backoff
380 * algorithm to allow prioritization of nodes.
381 */
382 #define ED_TCR_OFST 0x10
383
384 /*
385 * bits 5, 6, and 7 are unused/reserved
386 */
387
388 /*
389 * Transmit Status Register (TSR) definitions
390 */
391
392 /*
393 * PTX: Packet Transmitted. Indicates successful transmission of packet.
394 */
395 #define ED_TSR_PTX 0x01
396
397 /*
398 * bit 1 (0x02) is unused/reserved
399 */
400
401 /*
402 * COL: Transmit Collided. Indicates that the transmission collided at least
403 * once with another station on the network.
404 */
405 #define ED_TSR_COL 0x04
406
407 /*
408 * ABT: Transmit aborted. Indicates that the transmission was aborted due to
409 * excessive collisions.
410 */
411 #define ED_TSR_ABT 0x08
412
413 /*
414 * CRS: Carrier Sense Lost. Indicates that carrier was lost during the
415 * transmission of the packet. (Transmission is not aborted because
416 * of a loss of carrier)
417 */
418 #define ED_TSR_CRS 0x10
419
420 /*
421 * FU: FIFO Underrun. Indicates that the NIC wasn't able to access bus/
422 * transmission memory before the FIFO emptied. Transmission of the
423 * packet was aborted.
424 */
425 #define ED_TSR_FU 0x20
426
427 /*
428 * CDH: CD Heartbeat. Indicates that the collision detection circuitry
429 * isn't working correctly during a collision heartbeat test.
430 */
431 #define ED_TSR_CDH 0x40
432
433 /*
434 * OWC: Out of Window Collision: Indicates that a collision occurred after
435 * a slot time (51.2us). The transmission is rescheduled just as in
436 * normal collisions.
437 */
438 #define ED_TSR_OWC 0x80
439
440 /*
441 * Receiver Configuration Register (RCR) definitions
442 */
443
444 /*
445 * SEP: Save Errored Packets. If 0, error packets are discarded. If set to 1,
446 * packets with CRC and frame errors are not discarded.
447 */
448 #define ED_RCR_SEP 0x01
449
450 /*
451 * AR: Accept Runt packet. If 0, packet with less than 64 byte are discarded.
452 * If set to 1, packets with less than 64 byte are not discarded.
453 */
454 #define ED_RCR_AR 0x02
455
456 /*
457 * AB: Accept Broadcast. If set, packets sent to the broadcast address will be
458 * accepted.
459 */
460 #define ED_RCR_AB 0x04
461
462 /*
463 * AM: Accept Multicast. If set, packets sent to a multicast address are checked
464 * for a match in the hashing array. If clear, multicast packets are ignored.
465 */
466 #define ED_RCR_AM 0x08
467
468 /*
469 * PRO: Promiscuous Physical. If set, all packets with a physical addresses are
470 * accepted. If clear, a physical destination address must match this
471 * station's address. Note: for full promiscuous mode, RCR_AB and RCR_AM
472 * must also be set. In addition, the multicast hashing array must be set
473 * to all 1's so that all multicast addresses are accepted.
474 */
475 #define ED_RCR_PRO 0x10
476
477 /*
478 * MON: Monitor Mode. If set, packets will be checked for good CRC and framing,
479 * but are not stored in the ring-buffer. If clear, packets are stored (normal
480 * operation).
481 */
482 #define ED_RCR_MON 0x20
483
484 /*
485 * bits 6 and 7 are unused/reserved.
486 */
487
488 /*
489 * Receiver Status Register (RSR) definitions
490 */
491
492 /*
493 * PRX: Packet Received without error.
494 */
495 #define ED_RSR_PRX 0x01
496
497 /*
498 * CRC: CRC error. Indicates that a packet has a CRC error. Also set for frame
499 * alignment errors.
500 */
501 #define ED_RSR_CRC 0x02
502
503 /*
504 * FAE: Frame Alignment Error. Indicates that the incoming packet did not end on
505 * a byte boundary and the CRC did not match at the last byte boundary.
506 */
507 #define ED_RSR_FAE 0x04
508
509 /*
510 * FO: FIFO Overrun. Indicates that the FIFO was not serviced (during local DMA)
511 * causing it to overrun. Reception of the packet is aborted.
512 */
513 #define ED_RSR_FO 0x08
514
515 /*
516 * MPA: Missed Packet. Indicates that the received packet couldn't be stored in
517 * the ring-buffer because of insufficient buffer space (exceeding the
518 * boundary pointer), or because the transfer to the ring-buffer was inhibited
519 * by RCR_MON - monitor mode.
520 */
521 #define ED_RSR_MPA 0x10
522
523 /*
524 * PHY: Physical address. If 0, the packet received was sent to a physical address.
525 * If 1, the packet was accepted because of a multicast/broadcast address
526 * match.
527 */
528 #define ED_RSR_PHY 0x20
529
530 /*
531 * DIS: Receiver Disabled. Set to indicate that the receiver has entered monitor
532 * mode. Cleared when the receiver exits monitor mode.
533 */
534 #define ED_RSR_DIS 0x40
535
536 /*
537 * DFR: Deferring. Set to indicate a 'jabber' condition. The CRS and COL inputs
538 * are active, and the transceiver has set the CD line as a result of the
539 * jabber.
540 */
541 #define ED_RSR_DFR 0x80
542
543 /*
544 * receive ring descriptor
545 *
546 * The National Semiconductor DS8390 Network interface controller uses
547 * the following receive ring headers. The way this works is that the
548 * memory on the interface card is chopped up into 256 bytes blocks.
549 * A contiguous portion of those blocks are marked for receive packets
550 * by setting start and end block #'s in the NIC. For each packet that
551 * is put into the receive ring, one of these headers (4 bytes each) is
552 * tacked onto the front. The first byte is a copy of the receiver status
553 * register at the time the packet was received.
554 */
555 struct ed_ring {
556 u_char rsr; /* receiver status */
557 u_char next_packet; /* pointer to next packet */
558 u_short count; /* bytes in packet (length + 4) */
559 };
560
561 /*
562 * Common constants
563 */
564 #define ED_PAGE_SIZE 256 /* Size of RAM pages in bytes */
565 #define ED_TXBUF_SIZE 6 /* Size of TX buffer in pages */
566
567 /*
568 * Vendor types
569 */
570 #define ED_VENDOR_WD_SMC 0x00 /* Western Digital/SMC */
571 #define ED_VENDOR_3COM 0x01 /* 3Com */
572 #define ED_VENDOR_NOVELL 0x02 /* Novell */
573 #define ED_VENDOR_PCCARD 0x03 /* PCMCIA/PCCARD */
574 #define ED_VENDOR_HP 0x04 /* Hewlett Packard */
575
576 /*
577 * Compile-time config flags
578 */
579 /*
580 * this sets the default for enabling/disabling the transceiver
581 */
582 #define ED_FLAGS_DISABLE_TRANCEIVER 0x0001
583
584 /*
585 * This forces the board to be used in 8/16bit mode even if it
586 * autoconfigs differently
587 */
588 #define ED_FLAGS_FORCE_8BIT_MODE 0x0002
589 #define ED_FLAGS_FORCE_16BIT_MODE 0x0004
590
591 /*
592 * This disables the use of double transmit buffers.
593 */
594 #define ED_FLAGS_NO_MULTI_BUFFERING 0x0008
595
596 /*
597 * This forces all operations with the NIC memory to use Programmed
598 * I/O (i.e. not via shared memory)
599 */
600 #define ED_FLAGS_FORCE_PIO 0x0010
601
602 /*
603 * Definitions for Western digital/SMC WD80x3 series ASIC
604 */
605 /*
606 * Memory Select Register (MSR)
607 */
608 #define ED_WD_MSR 0
609
610 /* next three definitions for Toshiba */
611 #define ED_WD_MSR_POW 0x02 /* 0 = power save, 1 = normal (R/W) */
612 #define ED_WD_MSR_BSY 0x04 /* gate array busy (R) */
613 #define ED_WD_MSR_LEN 0x20 /* data bus width, 0 = 16 bits,
614 1 = 8 bits (R/W) */
615 #define ED_WD_MSR_ADDR 0x3f /* Memory decode bits 18-13 */
616 #define ED_WD_MSR_MENB 0x40 /* Memory enable */
617 #define ED_WD_MSR_RST 0x80 /* Reset board */
618
619 /*
620 * Interface Configuration Register (ICR)
621 */
622 #define ED_WD_ICR 1
623
624 #define ED_WD_ICR_16BIT 0x01 /* 16-bit interface */
625 #define ED_WD_ICR_OAR 0x02 /* select register. 0=BIO 1=EAR */
626 #define ED_WD_ICR_IR2 0x04 /* high order bit of encoded IRQ */
627 #define ED_WD_ICR_MSZ 0x08 /* memory size (0=8k 1=32k) */
628 #define ED_WD_ICR_RLA 0x10 /* recall LAN address */
629 #define ED_WD_ICR_RX7 0x20 /* recall all but i/o and LAN address */
630 #define ED_WD_ICR_RIO 0x40 /* recall i/o address */
631 #define ED_WD_ICR_STO 0x80 /* store to non-volatile memory */
632 #ifdef TOSH_ETHER
633 #define ED_WD_ICR_MEM 0xe0 /* shared mem address A15-A13 (R/W) */
634 #define ED_WD_ICR_MSZ1 0x0f /* memory size, 0x08 = 64K, 0x04 = 32K,
635 0x02 = 16K, 0x01 = 8K */
636 /* 64K can only be used if mem address
637 above 1Mb */
638 /* IAR holds address A23-A16 (R/W) */
639 #endif
640
641 /*
642 * IO Address Register (IAR)
643 */
644 #define ED_WD_IAR 2
645
646 /*
647 * EEROM Address Register
648 */
649 #define ED_WD_EAR 3
650
651 /*
652 * Interrupt Request Register (IRR)
653 */
654 #define ED_WD_IRR 4
655
656 #define ED_WD_IRR_0WS 0x01 /* use 0 wait-states on 8 bit bus */
657 #define ED_WD_IRR_OUT1 0x02 /* WD83C584 pin 1 output */
658 #define ED_WD_IRR_OUT2 0x04 /* WD83C584 pin 2 output */
659 #define ED_WD_IRR_OUT3 0x08 /* WD83C584 pin 3 output */
660 #define ED_WD_IRR_FLASH 0x10 /* Flash RAM is in the ROM socket */
661
662 /*
663 * The three bits of the encoded IRQ are decoded as follows:
664 *
665 * IR2 IR1 IR0 IRQ
666 * 0 0 0 2/9
667 * 0 0 1 3
668 * 0 1 0 5
669 * 0 1 1 7
670 * 1 0 0 10
671 * 1 0 1 11
672 * 1 1 0 15
673 * 1 1 1 4
674 */
675 #define ED_WD_IRR_IR0 0x20 /* bit 0 of encoded IRQ */
676 #define ED_WD_IRR_IR1 0x40 /* bit 1 of encoded IRQ */
677 #define ED_WD_IRR_IEN 0x80 /* Interrupt enable */
678
679 /*
680 * LA Address Register (LAAR)
681 */
682 #define ED_WD_LAAR 5
683
684 #define ED_WD_LAAR_ADDRHI 0x1f /* bits 23-19 of RAM address */
685 #define ED_WD_LAAR_0WS16 0x20 /* enable 0 wait-states on 16 bit bus */
686 #define ED_WD_LAAR_L16EN 0x40 /* enable 16-bit operation */
687 #define ED_WD_LAAR_M16EN 0x80 /* enable 16-bit memory access */
688
689 /* i/o base offset to station address/card-ID PROM */
690 #define ED_WD_PROM 8
691
692 /*
693 * 83C790 specific registers
694 */
695 /*
696 * Hardware Support Register (HWR) ('790)
697 */
698 #define ED_WD790_HWR 4
699
700 #define WD_WD790_HWR_NUKE 0x10 /* hardware reset */
701 #define ED_WD790_HWR_LPRM 0x40 /* LAN PROM select */
702 #define ED_WD790_HWR_SWH 0x80 /* switch register set */
703
704 /*
705 * ICR790 Interrupt Control Register for the 83C790
706 */
707 #define ED_WD790_ICR 6
708
709 #define ED_WD790_ICR_EIL 0x01 /* enable interrupts */
710
711 /*
712 * REV/IOPA Revision / I/O Pipe register for the 83C79X
713 */
714 #define ED_WD790_REV 7
715
716 #define ED_WD790 0x20
717 #define ED_WD795 0x40
718
719 /*
720 * 79X RAM Address Register (RAR)
721 * Enabled with SWH bit=1 in HWR register
722 */
723 #define ED_WD790_RAR 0x0b
724
725 #define ED_WD790_RAR_SZ8 0x00 /* 8k memory buffer */
726 #define ED_WD790_RAR_SZ16 0x10 /* 16k memory buffer */
727 #define ED_WD790_RAR_SZ32 0x20 /* 32k memory buffer */
728 #define ED_WD790_RAR_SZ64 0x30 /* 64k memory buffer */
729
730 /*
731 * General Control Register (GCR)
732 * Enabled with SWH bit=1 in HWR register
733 */
734 #define ED_WD790_GCR 0x0d
735
736 #define ED_WD790_GCR_IR0 0x04 /* bit 0 of encoded IRQ */
737 #define ED_WD790_GCR_IR1 0x08 /* bit 1 of encoded IRQ */
738 #define ED_WD790_GCR_ZWSEN 0x20 /* zero wait state enable */
739 #define ED_WD790_GCR_IR2 0x40 /* bit 2 of encoded IRQ */
740 #define ED_WD790_GCR_LIT 0x01 /* Link Integrity Test Enable */
741 /*
742 * The three bits of the encoded IRQ are decoded as follows:
743 *
744 * IR2 IR1 IR0 IRQ
745 * 0 0 0 none
746 * 0 0 1 9
747 * 0 1 0 3
748 * 0 1 1 5
749 * 1 0 0 7
750 * 1 0 1 10
751 * 1 1 0 11
752 * 1 1 1 15
753 */
754
755 /* i/o base offset to CARD ID */
756 #define ED_WD_CARD_ID ED_WD_PROM+6
757
758 /* Board type codes in card ID */
759 #define ED_TYPE_WD8003S 0x02
760 #define ED_TYPE_WD8003E 0x03
761 #define ED_TYPE_WD8013EBT 0x05
762 #define ED_TYPE_TOSHIBA1 0x11 /* named PCETA1 */
763 #define ED_TYPE_TOSHIBA2 0x12 /* named PCETA2 */
764 #define ED_TYPE_TOSHIBA3 0x13 /* named PCETB */
765 #define ED_TYPE_TOSHIBA4 0x14 /* named PCETC */
766 #define ED_TYPE_WD8003W 0x24
767 #define ED_TYPE_WD8003EB 0x25
768 #define ED_TYPE_WD8013W 0x26
769 #define ED_TYPE_WD8013EP 0x27
770 #define ED_TYPE_WD8013WC 0x28
771 #define ED_TYPE_WD8013EPC 0x29
772 #define ED_TYPE_SMC8216T 0x2a
773 #define ED_TYPE_SMC8216C 0x2b
774 #define ED_TYPE_WD8013EBP 0x2c
775
776 /* Bit definitions in card ID */
777 #define ED_WD_REV_MASK 0x1f /* Revision mask */
778 #define ED_WD_SOFTCONFIG 0x20 /* Soft config */
779 #define ED_WD_LARGERAM 0x40 /* Large RAM */
780 #define ED_MICROCHANEL 0x80 /* Microchannel bus (vs. isa) */
781
782 /*
783 * Checksum total. All 8 bytes in station address PROM will add up to this
784 */
785 #ifdef TOSH_ETHER
786 #define ED_WD_ROM_CHECKSUM_TOTAL 0xA5
787 #else
788 #define ED_WD_ROM_CHECKSUM_TOTAL 0xFF
789 #endif
790
791 #define ED_WD_NIC_OFFSET 0x10 /* I/O base offset to NIC */
792 #define ED_WD_ASIC_OFFSET 0 /* I/O base offset to ASIC */
793 #define ED_WD_IO_PORTS 32 /* # of i/o addresses used */
794
795 #define ED_WD_PAGE_OFFSET 0 /* page offset for NIC access to mem */
796
797 /*
798 * Definitions for 3Com 3c503
799 */
800 #define ED_3COM_NIC_OFFSET 0
801 #define ED_3COM_ASIC_OFFSET 0x400 /* offset to nic i/o regs */
802
803 /*
804 * XXX - The I/O address range is fragmented in the 3c503; this is the
805 * number of regs at iobase.
806 */
807 #define ED_3COM_IO_PORTS 16 /* # of i/o addresses used */
808
809 /* tx memory starts in second bank on 8bit cards */
810 #define ED_3COM_TX_PAGE_OFFSET_8BIT 0x20
811
812 /* tx memory starts in first bank on 16bit cards */
813 #define ED_3COM_TX_PAGE_OFFSET_16BIT 0x0
814
815 /* ...and rx memory starts in second bank */
816 #define ED_3COM_RX_PAGE_OFFSET_16BIT 0x20
817
818
819 /*
820 * Page Start Register. Must match PSTART in NIC
821 */
822 #define ED_3COM_PSTR 0
823
824 /*
825 * Page Stop Register. Must match PSTOP in NIC
826 */
827 #define ED_3COM_PSPR 1
828
829 /*
830 * Drq Timer Register. Determines number of bytes to be transfered during
831 * a DMA burst.
832 */
833 #define ED_3COM_DQTR 2
834
835 /*
836 * Base Configuration Register. Read-only register which contains the
837 * board-configured I/O base address of the adapter. Bit encoded.
838 */
839 #define ED_3COM_BCFR 3
840
841 #define ED_3COM_BCFR_2E0 0x01
842 #define ED_3COM_BCFR_2A0 0x02
843 #define ED_3COM_BCFR_280 0x04
844 #define ED_3COM_BCFR_250 0x08
845 #define ED_3COM_BCFR_350 0x10
846 #define ED_3COM_BCFR_330 0x20
847 #define ED_3COM_BCFR_310 0x40
848 #define ED_3COM_BCFR_300 0x80
849
850 /*
851 * EPROM Configuration Register. Read-only register which contains the
852 * board-configured memory base address. Bit encoded.
853 */
854 #define ED_3COM_PCFR 4
855
856 #define ED_3COM_PCFR_C8000 0x10
857 #define ED_3COM_PCFR_CC000 0x20
858 #define ED_3COM_PCFR_D8000 0x40
859 #define ED_3COM_PCFR_DC000 0x80
860
861 /*
862 * GA Configuration Register. Gate-Array Configuration Register.
863 */
864 #define ED_3COM_GACFR 5
865
866 /*
867 * mbs2 mbs1 mbs0 start address
868 * 0 0 0 0x0000
869 * 0 0 1 0x2000
870 * 0 1 0 0x4000
871 * 0 1 1 0x6000
872 *
873 * Note that with adapters with only 8K, the setting for 0x2000 must
874 * always be used.
875 */
876 #define ED_3COM_GACFR_MBS0 0x01
877 #define ED_3COM_GACFR_MBS1 0x02
878 #define ED_3COM_GACFR_MBS2 0x04
879
880 #define ED_3COM_GACFR_RSEL 0x08 /* enable shared memory */
881 #define ED_3COM_GACFR_TEST 0x10 /* for GA testing */
882 #define ED_3COM_GACFR_OWS 0x20 /* select 0WS access to GA */
883 #define ED_3COM_GACFR_TCM 0x40 /* Mask DMA interrupts */
884 #define ED_3COM_GACFR_NIM 0x80 /* Mask NIC interrupts */
885
886 /*
887 * Control Register. Miscellaneous control functions.
888 */
889 #define ED_3COM_CR 6
890
891 #define ED_3COM_CR_RST 0x01 /* Reset GA and NIC */
892 #define ED_3COM_CR_XSEL 0x02 /* Transceiver select. BNC=1(def) AUI=0 */
893 #define ED_3COM_CR_EALO 0x04 /* window EA PROM 0-15 to I/O base */
894 #define ED_3COM_CR_EAHI 0x08 /* window EA PROM 16-31 to I/O base */
895 #define ED_3COM_CR_SHARE 0x10 /* select interrupt sharing option */
896 #define ED_3COM_CR_DBSEL 0x20 /* Double buffer select */
897 #define ED_3COM_CR_DDIR 0x40 /* DMA direction select */
898 #define ED_3COM_CR_START 0x80 /* Start DMA controller */
899
900 /*
901 * Status Register. Miscellaneous status information.
902 */
903 #define ED_3COM_STREG 7
904
905 #define ED_3COM_STREG_REV 0x07 /* GA revision */
906 #define ED_3COM_STREG_DIP 0x08 /* DMA in progress */
907 #define ED_3COM_STREG_DTC 0x10 /* DMA terminal count */
908 #define ED_3COM_STREG_OFLW 0x20 /* Overflow */
909 #define ED_3COM_STREG_UFLW 0x40 /* Underflow */
910 #define ED_3COM_STREG_DPRDY 0x80 /* Data port ready */
911
912 /*
913 * Interrupt/DMA Configuration Register
914 */
915 #define ED_3COM_IDCFR 8
916
917 #define ED_3COM_IDCFR_DRQ0 0x01 /* DMA request 1 select */
918 #define ED_3COM_IDCFR_DRQ1 0x02 /* DMA request 2 select */
919 #define ED_3COM_IDCFR_DRQ2 0x04 /* DMA request 3 select */
920 #define ED_3COM_IDCFR_UNUSED 0x08 /* not used */
921 #define ED_3COM_IDCFR_IRQ2 0x10 /* Interrupt request 2 select */
922 #define ED_3COM_IDCFR_IRQ3 0x20 /* Interrupt request 3 select */
923 #define ED_3COM_IDCFR_IRQ4 0x40 /* Interrupt request 4 select */
924 #define ED_3COM_IDCFR_IRQ5 0x80 /* Interrupt request 5 select */
925
926 /*
927 * DMA Address Register MSB
928 */
929 #define ED_3COM_DAMSB 9
930
931 /*
932 * DMA Address Register LSB
933 */
934 #define ED_3COM_DALSB 0x0a
935
936 /*
937 * Vector Pointer Register 2
938 */
939 #define ED_3COM_VPTR2 0x0b
940
941 /*
942 * Vector Pointer Register 1
943 */
944 #define ED_3COM_VPTR1 0x0c
945
946 /*
947 * Vector Pointer Register 0
948 */
949 #define ED_3COM_VPTR0 0x0d
950
951 /*
952 * Register File Access MSB
953 */
954 #define ED_3COM_RFMSB 0x0e
955
956 /*
957 * Register File Access LSB
958 */
959 #define ED_3COM_RFLSB 0x0f
960
961 /*
962 * Definitions for Novell NE1000/2000 boards
963 */
964
965 /*
966 * Board type codes
967 */
968 #define ED_TYPE_NE1000 0x01
969 #define ED_TYPE_NE2000 0x02
970
971 /*
972 * Register offsets/total
973 */
974 #define ED_NOVELL_NIC_OFFSET 0x00
975 #define ED_NOVELL_ASIC_OFFSET 0x10
976 #define ED_NOVELL_IO_PORTS 32
977
978 /*
979 * Remote DMA data register; for reading or writing to the NIC mem
980 * via programmed I/O (offset from ASIC base)
981 */
982 #define ED_NOVELL_DATA 0x00
983
984 /*
985 * Reset register; reading from this register causes a board reset
986 */
987 #define ED_NOVELL_RESET 0x0f
988
989 /*
990 * Definitions for PCCARD
991 */
992 #define ED_PC_PAGE_OFFSET 0x40 /* page offset for NIC access to mem */
993 #define ED_PC_IO_PORTS 32
994 #define ED_PC_ASIC_OFFSET 0x10
995 #define ED_PC_RESET 0x0f /* Reset(offset from ASIC base) */
996 #define ED_PC_MISC 0x08 /* Misc (offset from ASIC base) */
997
998 /*
999 * if_ze.h constants
1000 */
1001
1002 #define ZE_PAGE_OFFSET 0x40 /* mem buffer starts at 0x4000 */
1003
1004 #define ZE_DATA_IO 0x10
1005 #define ZE_MISC 0x18
1006 #define ZE_RESET 0x1F
1007
1008 /*
1009 * Definitions for HP PC LAN Adapter Plus; based on the CRYNWR packet
1010 * driver for the card.
1011 */
1012
1013 #define ED_HPP_ASIC_OFFSET 0x00 /* Offset to ASIC registers */
1014 #define ED_HPP_NIC_OFFSET 0x10 /* Offset to 8390 registers */
1015
1016 #define ED_HPP_ID 0x00 /* ID register, always 0x4850 */
1017 #define ED_HPP_PAGING 0x02 /* Page select register */
1018 #define ED_HPP_OPTION 0x04 /* Bitmask of supported options */
1019 #define ED_HPP_PAGE_0 0x08 /* Page 0 */
1020 #define ED_HPP_PAGE_2 0x0A /* Page 2 */
1021 #define ED_HPP_PAGE_4 0x0C /* Page 4 */
1022 #define ED_HPP_PAGE_6 0x0E /* Page 6 */
1023
1024 /* PERF PAGE */
1025 #define ED_HPP_OUT_ADDR ED_HPP_PAGE_0 /* I/O output location */
1026 #define ED_HPP_IN_ADDR ED_HPP_PAGE_2 /* I/O input location */
1027 #define ED_HPP_DATAPORT ED_HPP_PAGE_4 /* I/O data transfer */
1028 /* MAC PAGE */
1029 #define ED_HPP_MAC_ADDR 0x08 /* Offset of MAC address in MAC page */
1030
1031 #define ED_HPP_IO_PORTS 32 /* Number of IO ports */
1032
1033 #define ED_HPP_TX_PAGE_OFFSET 0x00 /* first page of TX buffer */
1034 #define ED_HPP_RX_PAGE_START 0x06 /* start at page 6 */
1035 #define ED_HPP_RX_PAGE_STOP 0x80 /* end at page 128 */
1036
1037 /*
1038 * Register pages supported.
1039 */
1040
1041 #define ED_HPP_PAGE_PERF 0 /* Normal operation */
1042 #define ED_HPP_PAGE_MAC 1 /* The ethernet address and checksum */
1043 #define ED_HPP_PAGE_HW 2 /* Hardware parameters in EEPROM */
1044 #define ED_HPP_PAGE_LAN 4 /* Transciever selection etc */
1045 #define ED_HPP_PAGE_ID 6 /* ID */
1046
1047 /*
1048 * Options supported.
1049 */
1050
1051 #define ED_HPP_OPTION_NIC_RESET 0x0001 /* active low */
1052 #define ED_HPP_OPTION_CHIP_RESET 0x0002 /* active low */
1053 #define ED_HPP_OPTION_ENABLE_IRQ 0x0004
1054 #define ED_HPP_OPTION_FAKE_INTR 0x0008
1055 #define ED_HPP_OPTION_BOOT_ROM_ENB 0x0010
1056 #define ED_HPP_OPTION_IO_ENB 0x0020
1057 #define ED_HPP_OPTION_MEM_ENABLE 0x0040
1058 #define ED_HPP_OPTION_ZERO_WAIT 0x0080
1059 #define ED_HPP_OPTION_MEM_DISABLE 0x1000
1060
1061 /*
1062 * Page ID configuration.
1063 */
1064
1065 #define ED_HPP_ID_REVISION_MASK 0x0300 /* revision id */
1066 #define ED_HPP_ID_SOFT_MODEL_MASK 0xFC00 /* soft model number */
1067 #define ED_HPP_ID_16_BIT_ACCESS 0x0010 /* if set use 16 bit accesses */
1068 #define ED_HPP_ID_TWISTED_PAIR 0x0040
1069
1070 /*
1071 * Hardware configuration.
1072 */
1073
1074 #define ED_HPP_HW_MEM_MAP 0x09 /* low mem map location in HW page */
1075 #define ED_HPP_HW_ID 0x0C /* revision number, capabilities */
1076 #define ED_HPP_HW_IRQ 0x0D /* IRQ channel register in HW page */
1077 #define ED_HPP_HW_WRAP 0x0E /* mem wrap page for rcv */
1078
1079 /*
1080 * Lan configuration
1081 */
1082
1083 #define ED_HPP_LAN_AUI 0x01 /* Use AUI */
1084 #define ED_HPP_LAN_TL 0x40 /* Don't use AUI */
1085
1086 /*
1087 * Card types.
1088 */
1089
1090 #define ED_TYPE_HP_PCLANPLUS 0x00
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