1 /*
2 * Copyright (c) 1993 Dean Huxley (dean@fsa.ca)
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. All advertising materials mentioning features or use of this software
14 * must display the following acknowledgement:
15 * This product includes software developed by Dean Huxley.
16 * 4. The name of Dean Huxley may not be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 /*
32 * Register offsets from base.
33 */
34 #define EG_COMMAND 0x00
35 #define EG_STATUS 0x02
36 #define EG_DATA 0x04
37 #define EG_CONTROL 0x06
38
39 /*
40 * Host Control Register bits
41 * EG_CTL_ATTN - does a soft reset
42 * EG_CTL_FLSH - flushes the data register
43 * EG_CTL_RESET - does a hard reset
44 * EG_CTL_DMAE - Used with DIR bit, enables DMA transfers to/from data reg.
45 * EG_CTL_DIR - if clear then host -> adapter, if set then adapter -> host
46 * EG_CTL_TCEN - terminal count enable. enables host interrupt after DMA.
47 * EG_CTL_CMDE - command reg interrupt enable. (when it is written)
48 * EG_CTL_HSF1 - Host status flag 1
49 * EG_CTL_HSF2 - Host status flag 2
50 */
51
52 #define EG_CTL_ATTN 0x80
53 #define EG_CTL_FLSH 0x40
54 #define EG_CTL_RESET (EG_CTL_ATTN|EG_CTL_FLSH)
55 #define EG_CTL_DMAE 0x20
56 #define EG_CTL_DIR 0x10
57 #define EG_CTL_TCEN 0x08
58 #define EG_CTL_CMDE 0x04
59 #define EG_CTL_HSF2 0x02
60 #define EG_CTL_HSF1 0x01
61
62 /*
63 * Host Status Register bits
64 * EG_STAT_HRDY - Data Register ready
65 * EG_STAT_HCRE - Host Command Register empty
66 * EG_STAT_ACRF - Adapter Command register full
67 * EG_STAT_DIR - Direction flag, 0 = host -> adapter, 1 = adapter -> host
68 * EG_STAT_DONE - DMA done
69 * EG_STAT_ASF1 - Adapter status flag 1
70 * EG_STAT_ASF2 - Adapter status flag 2
71 * EG_STAT_ASF3 - Adapter status flag 3
72 */
73
74 #define EG_STAT_HRDY 0x80
75 #define EG_STAT_HCRE 0x40
76 #define EG_STAT_ACRF 0x20
77 #define EG_STAT_DIR 0x10
78 #define EG_STAT_DONE 0x08
79 #define EG_STAT_ASF3 0x04
80 #define EG_STAT_ASF2 0x02
81 #define EG_STAT_ASF1 0x01
82
83 #define EG_PCB_NULL 0x00
84 #define EG_PCB_ACCEPT 0x01
85 #define EG_PCB_REJECT 0x02
86 #define EG_PCB_DONE 0x03
87 #define EG_PCB_STAT 0x03
88
89 #define EG_CMD_CONFIG82586 0x02
90 #define EG_CMD_GETEADDR 0x03
91 #define EG_CMD_RECVPACKET 0x08
92 #define EG_CMD_SENDPACKET 0x09
93 #define EG_CMD_GETSTATS 0x0a
94 #define EG_CMD_SETEADDR 0x10
95 #define EG_CMD_GETINFO 0x11
96
97 #define EG_RSP_CONFIG82586 0x32
98 #define EG_RSP_GETEADDR 0x33
99 #define EG_RSP_RECVPACKET 0x38
100 #define EG_RSP_SENDPACKET 0x39
101 #define EG_RSP_GETSTATS 0x3a
102 #define EG_RSP_SETEADDR 0x40
103 #define EG_RSP_GETINFO 0x41
Cache object: cedb0005fdbc7fa8eecfd139e7b80867
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