1 /*
2 * Copyright (c) 1993 Herb Peyerl (hpeyerl@novatel.ca) All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: 1. Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer. 2. The name
8 * of the author may not be used to endorse or promote products derived from
9 * this software without specific prior written permission
10 *
11 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
12 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
14 * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
15 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
16 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
17 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
18 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
19 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
20 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 *
22 * if_epreg.h,v 1.4 1994/11/13 10:12:37 gibbs Exp Modified by:
23 *
24 October 2, 1994
25
26 Modified by: Andres Vega Garcia
27
28 INRIA - Sophia Antipolis, France
29 e-mail: avega@sophia.inria.fr
30 finger: avega@pax.inria.fr
31
32 */
33 /*
34 * $FreeBSD: src/sys/i386/isa/if_epreg.h,v 1.17.2.4 1999/09/05 08:12:50 peter Exp $
35 *
36 * Promiscuous mode added and interrupt logic slightly changed
37 * to reduce the number of adapter failures. Transceiver select
38 * logic changed to use value from EEPROM. Autoconfiguration
39 * features added.
40 * Done by:
41 * Serge Babkin
42 * Chelindbank (Chelyabinsk, Russia)
43 * babkin@hq.icb.chel.su
44 */
45
46 /*
47 * Pccard support for 3C589 by:
48 * HAMADA Naoki
49 * nao@tom-yam.or.jp
50 */
51
52 /*
53 * Ethernet software status per interface.
54 */
55 struct ep_softc {
56 struct arpcom arpcom; /* Ethernet common part */
57 int ep_io_addr; /* i/o bus address */
58 struct mbuf *top, *mcur;
59 short cur_len;
60 u_short ep_connectors; /* Connectors on this card. */
61 u_char ep_connector; /* Configured connector. */
62 int stat; /* some flags */
63 int gone; /* adapter is not present (for PCCARD) */
64 #define F_RX_FIRST 0x1
65 #define F_PROMISC 0x8
66
67 #define F_ACCESS_32_BITS 0x100
68
69 struct ep_board *epb;
70
71 int unit;
72
73 #ifdef EP_LOCAL_STATS
74 short tx_underrun;
75 short rx_no_first;
76 short rx_no_mbuf;
77 short rx_bpf_disc;
78 short rx_overrunf;
79 short rx_overrunl;
80 #endif
81 };
82
83 struct ep_board {
84 int epb_addr; /* address of this board */
85 char epb_used; /* was this entry already used for configuring ? */
86 /* data from EEPROM for later use */
87 u_short eth_addr[3]; /* Ethernet address */
88 u_short prod_id; /* product ID */
89 u_short res_cfg; /* resource configuration */
90 };
91
92
93 /*
94 * Some global constants
95 */
96 #define TX_INIT_RATE 16
97 #define TX_INIT_MAX_RATE 64
98 #define RX_INIT_LATENCY 64
99 #define RX_INIT_EARLY_THRESH 208 /* not less than MINCLSIZE */
100 #define RX_NEXT_EARLY_THRESH 500
101
102 #define EEPROMSIZE 0x40
103 #define MAX_EEPROMBUSY 1000
104 #define EP_LAST_TAG 0xd7
105 #define EP_MAX_BOARDS 16
106 /*
107 * This `ID' port is a mere hack. There's currently no chance to register
108 * it with config's idea of the ports that are in use.
109 *
110 * "After the automatic configuration is completed, the IDS is in it's initial
111 * state (ID-WAIT), and it monitors all write access to I/O port 01x0h, where
112 * 'x' is any hex digit. If a zero is written to any one of these ports, then
113 * that address is remembered and becomes the ID port. A second zero written
114 * to that port resets the ID sequence to its initial state. The IDS watches
115 * for the ID sequence to be written to the ID port."
116 *
117 * We prefer 0x110 over 0x100 so to not conflict with the Plaque&Pray
118 * ports.
119 */
120 #define EP_ID_PORT 0x110
121 #define EP_IOSIZE 16 /* 16 bytes of I/O space used. */
122
123 /*
124 * some macros to acces long named fields
125 */
126 #define IS_BASE (is->id_iobase)
127 #define BASE (sc->ep_io_addr)
128
129 /*
130 * Commands to read/write EEPROM trough EEPROM command register (Window 0,
131 * Offset 0xa)
132 */
133 #define EEPROM_CMD_RD 0x0080 /* Read: Address required (5 bits) */
134 #define EEPROM_CMD_WR 0x0040 /* Write: Address required (5 bits) */
135 #define EEPROM_CMD_ERASE 0x00c0 /* Erase: Address required (5 bits) */
136 #define EEPROM_CMD_EWEN 0x0030 /* Erase/Write Enable: No data required */
137
138 #define EEPROM_BUSY (1<<15)
139 #define EEPROM_TST_MODE (1<<14)
140
141 /*
142 * Some short functions, worth to let them be a macro
143 */
144 #define is_eeprom_busy(b) (inw((b)+EP_W0_EEPROM_COMMAND)&EEPROM_BUSY)
145 #define GO_WINDOW(x) outw(BASE+EP_COMMAND, WINDOW_SELECT|(x))
146
147 /**************************************************************************
148 * *
149 * These define the EEPROM data structure. They are used in the probe
150 * function to verify the existence of the adapter after having sent
151 * the ID_Sequence.
152 *
153 * There are others but only the ones we use are defined here.
154 *
155 **************************************************************************/
156
157 #define EEPROM_NODE_ADDR_0 0x0 /* Word */
158 #define EEPROM_NODE_ADDR_1 0x1 /* Word */
159 #define EEPROM_NODE_ADDR_2 0x2 /* Word */
160 #define EEPROM_PROD_ID 0x3 /* 0x9[0-f]50 */
161 #define EEPROM_MFG_ID 0x7 /* 0x6d50 */
162 #define EEPROM_ADDR_CFG 0x8 /* Base addr */
163 #define EEPROM_RESOURCE_CFG 0x9 /* IRQ. Bits 12-15 */
164
165 /**************************************************************************
166 * *
167 * These are the registers for the 3Com 3c509 and their bit patterns when *
168 * applicable. They have been taken out the the "EtherLink III Parallel *
169 * Tasking EISA and ISA Technical Reference" "Beta Draft 10/30/92" manual *
170 * from 3com. *
171 * *
172 **************************************************************************/
173
174 #define EP_COMMAND 0x0e /* Write. BASE+0x0e is always a
175 * command reg. */
176 #define EP_STATUS 0x0e /* Read. BASE+0x0e is always status
177 * reg. */
178 #define EP_WINDOW 0x0f /* Read. BASE+0x0f is always window
179 * reg. */
180 /*
181 * Window 0 registers. Setup.
182 */
183 /* Write */
184 #define EP_W0_EEPROM_DATA 0x0c
185 #define EP_W0_EEPROM_COMMAND 0x0a
186 #define EP_W0_RESOURCE_CFG 0x08
187 #define EP_W0_ADDRESS_CFG 0x06
188 #define EP_W0_CONFIG_CTRL 0x04
189 /* Read */
190 #define EP_W0_PRODUCT_ID 0x02
191 #define EP_W0_MFG_ID 0x00
192
193 /*
194 * Window 1 registers. Operating Set.
195 */
196 /* Write */
197 #define EP_W1_TX_PIO_WR_2 0x02
198 #define EP_W1_TX_PIO_WR_1 0x00
199 /* Read */
200 #define EP_W1_FREE_TX 0x0c
201 #define EP_W1_TX_STATUS 0x0b /* byte */
202 #define EP_W1_TIMER 0x0a /* byte */
203 #define EP_W1_RX_STATUS 0x08
204 #define EP_W1_RX_PIO_RD_2 0x02
205 #define EP_W1_RX_PIO_RD_1 0x00
206
207 /*
208 * Window 2 registers. Station Address Setup/Read
209 */
210 /* Read/Write */
211 #define EP_W2_ADDR_5 0x05
212 #define EP_W2_ADDR_4 0x04
213 #define EP_W2_ADDR_3 0x03
214 #define EP_W2_ADDR_2 0x02
215 #define EP_W2_ADDR_1 0x01
216 #define EP_W2_ADDR_0 0x00
217
218 /*
219 * Window 3 registers. FIFO Management.
220 */
221 /* Read */
222 #define EP_W3_FREE_TX 0x0c
223 #define EP_W3_FREE_RX 0x0a
224
225 /*
226 * Window 4 registers. Diagnostics.
227 */
228 /* Read/Write */
229 #define EP_W4_MEDIA_TYPE 0x0a
230 #define EP_W4_CTRLR_STATUS 0x08
231 #define EP_W4_NET_DIAG 0x06
232 #define EP_W4_FIFO_DIAG 0x04
233 #define EP_W4_HOST_DIAG 0x02
234 #define EP_W4_TX_DIAG 0x00
235
236 /*
237 * Window 5 Registers. Results and Internal status.
238 */
239 /* Read */
240 #define EP_W5_READ_0_MASK 0x0c
241 #define EP_W5_INTR_MASK 0x0a
242 #define EP_W5_RX_FILTER 0x08
243 #define EP_W5_RX_EARLY_THRESH 0x06
244 #define EP_W5_TX_AVAIL_THRESH 0x02
245 #define EP_W5_TX_START_THRESH 0x00
246
247 /*
248 * Window 6 registers. Statistics.
249 */
250 /* Read/Write */
251 #define TX_TOTAL_OK 0x0c
252 #define RX_TOTAL_OK 0x0a
253 #define TX_DEFERRALS 0x08
254 #define RX_FRAMES_OK 0x07
255 #define TX_FRAMES_OK 0x06
256 #define RX_OVERRUNS 0x05
257 #define TX_COLLISIONS 0x04
258 #define TX_AFTER_1_COLLISION 0x03
259 #define TX_AFTER_X_COLLISIONS 0x02
260 #define TX_NO_SQE 0x01
261 #define TX_CD_LOST 0x00
262
263 /****************************************
264 *
265 * Register definitions.
266 *
267 ****************************************/
268
269 /*
270 * Command register. All windows.
271 *
272 * 16 bit register.
273 * 15-11: 5-bit code for command to be executed.
274 * 10-0: 11-bit arg if any. For commands with no args;
275 * this can be set to anything.
276 */
277 #define GLOBAL_RESET (u_short) 0x0000 /* Wait at least 1ms
278 * after issuing */
279 #define WINDOW_SELECT (u_short) (0x1<<11)
280 #define START_TRANSCEIVER (u_short) (0x2<<11) /* Read ADDR_CFG reg to
281 * determine whether
282 * this is needed. If
283 * so; wait 800 uSec
284 * before using trans-
285 * ceiver. */
286 #define RX_DISABLE (u_short) (0x3<<11) /* state disabled on
287 * power-up */
288 #define RX_ENABLE (u_short) (0x4<<11)
289 #define RX_RESET (u_short) (0x5<<11)
290 #define RX_DISCARD_TOP_PACK (u_short) (0x8<<11)
291 #define TX_ENABLE (u_short) (0x9<<11)
292 #define TX_DISABLE (u_short) (0xa<<11)
293 #define TX_RESET (u_short) (0xb<<11)
294 #define REQ_INTR (u_short) (0xc<<11)
295 #define SET_INTR_MASK (u_short) (0xe<<11)
296 #define SET_RD_0_MASK (u_short) (0xf<<11)
297 #define SET_RX_FILTER (u_short) (0x10<<11)
298 #define FIL_INDIVIDUAL (u_short) (0x1)
299 #define FIL_GROUP (u_short) (0x2)
300 #define FIL_BRDCST (u_short) (0x4)
301 #define FIL_ALL (u_short) (0x8)
302 #define SET_RX_EARLY_THRESH (u_short) (0x11<<11)
303 #define SET_TX_AVAIL_THRESH (u_short) (0x12<<11)
304 #define SET_TX_START_THRESH (u_short) (0x13<<11)
305 #define STATS_ENABLE (u_short) (0x15<<11)
306 #define STATS_DISABLE (u_short) (0x16<<11)
307 #define STOP_TRANSCEIVER (u_short) (0x17<<11)
308 /*
309 * The following C_* acknowledge the various interrupts. Some of them don't
310 * do anything. See the manual.
311 */
312 #define ACK_INTR (u_short) (0x6800)
313 #define C_INTR_LATCH (u_short) (ACK_INTR|0x1)
314 #define C_CARD_FAILURE (u_short) (ACK_INTR|0x2)
315 #define C_TX_COMPLETE (u_short) (ACK_INTR|0x4)
316 #define C_TX_AVAIL (u_short) (ACK_INTR|0x8)
317 #define C_RX_COMPLETE (u_short) (ACK_INTR|0x10)
318 #define C_RX_EARLY (u_short) (ACK_INTR|0x20)
319 #define C_INT_RQD (u_short) (ACK_INTR|0x40)
320 #define C_UPD_STATS (u_short) (ACK_INTR|0x80)
321 #define C_MASK (u_short) 0xFF /* mask of C_* */
322
323 /*
324 * Status register. All windows.
325 *
326 * 15-13: Window number(0-7).
327 * 12: Command_in_progress.
328 * 11: reserved.
329 * 10: reserved.
330 * 9: reserved.
331 * 8: reserved.
332 * 7: Update Statistics.
333 * 6: Interrupt Requested.
334 * 5: RX Early.
335 * 4: RX Complete.
336 * 3: TX Available.
337 * 2: TX Complete.
338 * 1: Adapter Failure.
339 * 0: Interrupt Latch.
340 */
341 #define S_INTR_LATCH (u_short) (0x1)
342 #define S_CARD_FAILURE (u_short) (0x2)
343 #define S_TX_COMPLETE (u_short) (0x4)
344 #define S_TX_AVAIL (u_short) (0x8)
345 #define S_RX_COMPLETE (u_short) (0x10)
346 #define S_RX_EARLY (u_short) (0x20)
347 #define S_INT_RQD (u_short) (0x40)
348 #define S_UPD_STATS (u_short) (0x80)
349 #define S_MASK (u_short) 0xFF /* mask of S_* */
350 #define S_5_INTS (S_CARD_FAILURE|S_TX_COMPLETE|\
351 S_TX_AVAIL|S_RX_COMPLETE|S_RX_EARLY)
352 #define S_COMMAND_IN_PROGRESS (u_short) (0x1000)
353
354 /* Address Config. Register.
355 * Window 0/Port 06
356 */
357
358 #define ACF_CONNECTOR_BITS 14
359 #define ACF_CONNECTOR_UTP 0
360 #define ACF_CONNECTOR_AUI 1
361 #define ACF_CONNECTOR_BNC 3
362
363 /* Resource configuration register.
364 * Window 0/Port 08
365 *
366 */
367
368 #define SET_IRQ(base,irq) outw((base) + EP_W0_RESOURCE_CFG, \
369 ((inw((base) + EP_W0_RESOURCE_CFG) & 0x0fff) | \
370 ((u_short)(irq)<<12)) ) /* set IRQ i */
371
372 /*
373 * FIFO Registers.
374 * RX Status. Window 1/Port 08
375 *
376 * 15: Incomplete or FIFO empty.
377 * 14: 1: Error in RX Packet 0: Incomplete or no error.
378 * 13-11: Type of error.
379 * 1000 = Overrun.
380 * 1011 = Run Packet Error.
381 * 1100 = Alignment Error.
382 * 1101 = CRC Error.
383 * 1001 = Oversize Packet Error (>1514 bytes)
384 * 0010 = Dribble Bits.
385 * (all other error codes, no errors.)
386 *
387 * 10-0: RX Bytes (0-1514)
388 */
389 #define ERR_RX_INCOMPLETE (u_short) (0x1<<15)
390 #define ERR_RX (u_short) (0x1<<14)
391 #define ERR_RX_OVERRUN (u_short) (0x8<<11)
392 #define ERR_RX_RUN_PKT (u_short) (0xb<<11)
393 #define ERR_RX_ALIGN (u_short) (0xc<<11)
394 #define ERR_RX_CRC (u_short) (0xd<<11)
395 #define ERR_RX_OVERSIZE (u_short) (0x9<<11)
396 #define ERR_RX_DRIBBLE (u_short) (0x2<<11)
397
398 /*
399 * FIFO Registers.
400 * TX Status. Window 1/Port 0B
401 *
402 * Reports the transmit status of a completed transmission. Writing this
403 * register pops the transmit completion stack.
404 *
405 * Window 1/Port 0x0b.
406 *
407 * 7: Complete
408 * 6: Interrupt on successful transmission requested.
409 * 5: Jabber Error (TP Only, TX Reset required. )
410 * 4: Underrun (TX Reset required. )
411 * 3: Maximum Collisions.
412 * 2: TX Status Overflow.
413 * 1-0: Undefined.
414 *
415 */
416 #define TXS_COMPLETE 0x80
417 #define TXS_SUCCES_INTR_REQ 0x40
418 #define TXS_JABBER 0x20
419 #define TXS_UNDERRUN 0x10
420 #define TXS_MAX_COLLISION 0x8
421 #define TXS_STATUS_OVERFLOW 0x4
422
423 /*
424 * Configuration control register.
425 * Window 0/Port 04
426 */
427 /* Read */
428 #define IS_AUI (1<<13)
429 #define IS_BNC (1<<12)
430 #define IS_UTP (1<<9)
431 /* Write */
432 #define ENABLE_DRQ_IRQ 0x0001
433 #define W0_P4_CMD_RESET_ADAPTER 0x4
434 #define W0_P4_CMD_ENABLE_ADAPTER 0x1
435 /*
436 * Media type and status.
437 * Window 4/Port 0A
438 */
439 #define ENABLE_UTP 0xc0
440 #define DISABLE_UTP 0x0
441
442 /*
443 * Misc defines for various things.
444 */
445 #define ACTIVATE_ADAPTER_TO_CONFIG 0xff /* to the id_port */
446 #define MFG_ID 0x6d50 /* in EEPROM and W0 ADDR_CONFIG */
447 #define PROD_ID 0x9150
448
449 #define AUI 0x1
450 #define BNC 0x2
451 #define UTP 0x4
452
453 #define RX_BYTES_MASK (u_short) (0x07ff)
454
455 extern struct ep_board ep_board[];
456 extern int ep_boards;
457 extern u_long ep_unit;
458 extern struct ep_softc *ep_alloc __P((int unit, struct ep_board *epb));
459 extern void ep_free __P((struct ep_softc *sc));
460 extern void ep_intr __P((void *sc));
461 extern int ep_attach __P((struct ep_softc *sc));
462
463 extern u_int16_t get_e __P((struct ep_softc *sc, int offset));
Cache object: 68f1c26f62bc438b07e91a8e2faec7bd
|