1 /*
2 * Hardware specification of various 8696x based Ethernet cards.
3 * Contributed by M. Sekiguchi <seki@sysrap.cs.fujitsu.co.jp>
4 *
5 * All Rights Reserved, Copyright (C) Fujitsu Limited 1995
6 *
7 * This software may be used, modified, copied, distributed, and sold,
8 * in both source and binary form provided that the above copyright,
9 * these terms and the following disclaimer are retained. The name of
10 * the author and/or the contributor may not be used to endorse or
11 * promote products derived from this software without specific prior
12 * written permission.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND THE CONTRIBUTOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR THE CONTRIBUTOR BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27 /* $FreeBSD: src/sys/i386/isa/if_fereg.h,v 1.3.4.1 1999/09/05 08:12:52 peter Exp $ */
28
29 /*
30 * Registers on FMV-180 series' ISA bus interface ASIC.
31 * I'm not sure the following register names are appropriate.
32 * Doesn't it look silly, eh? FIXME.
33 */
34
35 #define FE_FMV0 16 /* Card status register #0 */
36 #define FE_FMV1 17 /* Card status register #1 */
37 #define FE_FMV2 18 /* Card config register #0 */
38 #define FE_FMV3 19 /* Card config register #1 */
39 #define FE_FMV4 20 /* Station address #1 */
40 #define FE_FMV5 21 /* Station address #2 */
41 #define FE_FMV6 22 /* Station address #3 */
42 #define FE_FMV7 23 /* Station address #4 */
43 #define FE_FMV8 24 /* Station address #5 */
44 #define FE_FMV9 25 /* Station address #6 */
45 #define FE_FMV10 26 /* Buffer RAM control register */
46 #define FE_FMV11 27 /* Buffer RAM data register */
47
48 /*
49 * FMV-180 series' ASIC register values.
50 */
51
52 /* FMV0: Card status register #0: Misc info? */
53 #define FE_FMV0_MEDIA 0x07 /* Supported physical media. */
54 #define FE_FMV0_PRRDY 0x10 /* ??? */
55 #define FE_FMV0_PRERR 0x20 /* ??? */
56 #define FE_FMV0_ERRDY 0x40 /* ??? */
57 #define FE_FMV0_IREQ 0x80 /* ??? */
58
59 #define FE_FMV0_MEDIUM_5 0x01 /* 10base5/Dsub */
60 #define FE_FMV0_MEDIUM_2 0x02 /* 10base2/BNC */
61 #define FE_FMV0_MEDIUM_T 0x04 /* 10baseT/RJ45 */
62
63 /* Card status register #1: Hardware revision. */
64 #define FE_FMV1_REV 0x0F /* Card revision */
65 #define FE_FMV1_UPPER 0xF0 /* Usage unknown */
66
67 /* Card config register #0: I/O port address assignment. */
68 #define FE_FMV2_IOS 0x07 /* I/O selection. */
69 #define FE_FMV2_MES 0x38 /* ??? boot ROM? */
70 #define FE_FMV2_IRS 0xC0 /* IRQ selection. */
71
72 #define FE_FMV2_IOS_SHIFT 0
73 #define FE_FMV2_MES_SHIFT 3
74 #define FE_FMV2_IRS_SHIFT 6
75
76 /* Card config register #1: IRQ enable */
77 #define FE_FMV3_IRQENB 0x80 /* IRQ enable. */
78
79 /*
80 * Register(?) specific to AT1700/RE2000.
81 */
82
83 #define FE_ATI_RESET 0x1F /* Write to reset the 86965. */
84
85 /* EEPROM allocation (offsets) of AT1700/RE2000. */
86 #define FE_ATI_EEP_ADDR 0x08 /* Station address. (8-13) */
87 #define FE_ATI_EEP_MEDIA 0x18 /* Media type. */
88 #define FE_ATI_EEP_MAGIC 0x19 /* XXX Magic. */
89 #define FE_ATI_EEP_MODEL 0x1e /* Hardware type. */
90 #define FE_ATI_EEP_REVISION 0x1f /* Hardware revision. */
91
92 /* Value for FE_ATI_EEP_MODEL. */
93 #define FE_ATI_MODEL_AT1700T 0x00
94 #define FE_ATI_MODEL_AT1700BT 0x01
95 #define FE_ATI_MODEL_AT1700FT 0x02
96 #define FE_ATI_MODEL_AT1700AT 0x03
97
98 /*
99 * Registers on MBH10302.
100 */
101
102 #define FE_MBH0 0x10 /* ??? Including interrupt. */
103 #define FE_MBH1 0x11 /* ??? */
104 #define FE_MBH10 0x1A /* Station address. (10 - 15) */
105
106 /* Values to be set in MBH0 register. */
107 #define FE_MBH0_MAGIC 0x0D /* Just a magic constant? */
108 #define FE_MBH0_INTR 0x10 /* Master interrupt control. */
109
110 #define FE_MBH0_INTR_ENABLE 0x10 /* Enable interrupts. */
111 #define FE_MBH0_INTR_DISABLE 0x00 /* Disable interrupts. */
112
113 /*
114 * Registers on RE1000. (*NOT* on RE1000 Plus.)
115 */
116
117 /* IRQ configuration. */
118 #define FE_RE1000_IRQCONF 0x10
119 #define FE_RE1000_IRQCONF_IRQ 0xf0
120 #define FE_RE1000_IRQCONF_IRQSHIFT 4
121
122 /* MAC (station) address. */
123 #define FE_RE1000_MAC0 0x11
124 #define FE_RE1000_MAC1 0x13
125 #define FE_RE1000_MAC2 0x15
126 #define FE_RE1000_MAC3 0x17
127 #define FE_RE1000_MAC4 0x19
128 #define FE_RE1000_MAC5 0x1B
129
130 /* "Check sum" -- an xor of MAC0 through MAC5 */
131 #define FE_RE1000_MACCHK 0x1D
132
Cache object: f441702313975d753df89b1247ecde68
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