The Design and Implementation of the FreeBSD Operating System, Second Edition
Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)


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sys/i386/isa/if_le.c

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    1 /*-
    2  * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com)
    3  * All rights reserved.
    4  *
    5  * Redistribution and use in source and binary forms, with or without
    6  * modification, are permitted provided that the following conditions
    7  * are met:
    8  * 1. Redistributions of source code must retain the above copyright
    9  *    notice, this list of conditions and the following disclaimer.
   10  * 2. The name of the author may not be used to endorse or promote products
   11  *    derived from this software without specific prior written permission
   12  *
   13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
   14  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
   15  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
   16  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
   17  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
   18  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
   19  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
   20  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
   21  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
   22  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
   23  *
   24  * $FreeBSD: releng/5.0/sys/i386/isa/if_le.c 106939 2002-11-15 00:00:15Z sam $
   25  */
   26 
   27 /*
   28  * DEC EtherWORKS 2 Ethernet Controllers
   29  * DEC EtherWORKS 3 Ethernet Controllers
   30  *
   31  * Written by Matt Thomas
   32  * BPF support code stolen directly from if_ec.c
   33  *
   34  *   This driver supports the DEPCA, DE100, DE101, DE200, DE201,
   35  *   DE2002, DE203, DE204, DE205, and DE422 cards.
   36  */
   37 
   38 #include "le.h"
   39 #include "opt_inet.h"
   40 #include "opt_ipx.h"
   41 
   42 #include <sys/param.h>
   43 #include <sys/systm.h>
   44 #include <sys/kernel.h>
   45 #include <sys/mbuf.h>
   46 #include <sys/socket.h>
   47 #include <sys/sockio.h>
   48 #include <sys/malloc.h>
   49 #include <sys/bus.h>
   50 
   51 #include <net/ethernet.h>
   52 #include <net/if.h>
   53 #include <net/if_types.h>
   54 #include <net/if_dl.h>
   55 
   56 #include <netinet/in.h>
   57 #include <netinet/if_ether.h>
   58 
   59 
   60 
   61 #include <i386/isa/isa_device.h>
   62 #include <i386/isa/icu.h>
   63 
   64 #include <vm/vm.h>
   65 #include <vm/pmap.h>
   66 
   67 #include <net/bpf.h>
   68 
   69 #ifndef COMPAT_OLDISA
   70 #error "The le device requires the old isa compatibility shims"
   71 #endif
   72 
   73 /* Forward declarations */
   74 typedef struct le_softc le_softc_t;
   75 typedef struct le_board le_board_t;
   76 
   77 typedef u_short le_mcbits_t;
   78 #define LE_MC_NBPW_LOG2         4
   79 #define LE_MC_NBPW              (1 << LE_MC_NBPW_LOG2)
   80 
   81 #if !defined(LE_NOLEMAC)
   82 /*
   83  * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
   84  *
   85  * Start of DEC EtherWORKS III (LEMAC) dependent structures
   86  *
   87  */
   88 #include <i386/isa/ic/lemac.h>          /* Include LEMAC definitions */
   89 
   90 static int lemac_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
   91 
   92 struct le_lemac_info {
   93     u_int lemac__lastpage;              /* last 2K page */
   94     u_int lemac__memmode;               /* Are we in 2K, 32K, or 64K mode */
   95     u_int lemac__membase;               /* Physical address of start of RAM */
   96     u_int lemac__txctl;                 /* Transmit Control Byte */
   97     u_int lemac__txmax;                 /* Maximum # of outstanding transmits */
   98     le_mcbits_t lemac__mctbl[LEMAC_MCTBL_SIZE/sizeof(le_mcbits_t)];
   99                                         /* local copy of multicast table */
  100     u_char lemac__eeprom[LEMAC_EEP_SIZE]; /* local copy eeprom */
  101     char lemac__prodname[LEMAC_EEP_PRDNMSZ+1]; /* prodname name */
  102 #define lemac_lastpage          le_un.un_lemac.lemac__lastpage
  103 #define lemac_memmode           le_un.un_lemac.lemac__memmode
  104 #define lemac_membase           le_un.un_lemac.lemac__membase
  105 #define lemac_txctl             le_un.un_lemac.lemac__txctl
  106 #define lemac_txmax             le_un.un_lemac.lemac__txmax
  107 #define lemac_mctbl             le_un.un_lemac.lemac__mctbl
  108 #define lemac_eeprom            le_un.un_lemac.lemac__eeprom
  109 #define lemac_prodname          le_un.un_lemac.lemac__prodname
  110 };
  111 #endif /* !defined(LE_NOLEMAC) */
  112 
  113 #if !defined(LE_NOLANCE)
  114 /*
  115  * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  116  *
  117  * Start of DEC EtherWORKS II (LANCE) dependent structures
  118  *
  119  */
  120 
  121 #include <i386/isa/ic/am7990.h>
  122 
  123 #ifndef LN_DOSTATS
  124 #define LN_DOSTATS      1
  125 #endif
  126 
  127 static int depca_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
  128 
  129 typedef struct lance_descinfo lance_descinfo_t;
  130 typedef struct lance_ring lance_ring_t;
  131 
  132 typedef unsigned lance_addr_t;
  133 
  134 struct lance_descinfo {
  135     caddr_t di_addr;                    /* address of descriptor */
  136     lance_addr_t di_bufaddr;            /* LANCE address of buffer owned by descriptor */
  137     unsigned di_buflen;                 /* size of buffer owned by descriptor */
  138     struct mbuf *di_mbuf;               /* mbuf being transmitted/received */
  139 };
  140 
  141 struct lance_ring {
  142     lance_descinfo_t *ri_first;         /* Pointer to first descriptor in ring */
  143     lance_descinfo_t *ri_last;          /* Pointer to last + 1 descriptor in ring */
  144     lance_descinfo_t *ri_nextin;        /* Pointer to next one to be given to HOST */
  145     lance_descinfo_t *ri_nextout;       /* Pointer to next one to be given to LANCE */
  146     unsigned ri_max;                    /* Size of Ring - 1 */
  147     unsigned ri_free;                   /* Number of free rings entires (owned by HOST) */
  148     lance_addr_t ri_heap;                       /* Start of RAM for this ring */
  149     lance_addr_t ri_heapend;            /* End + 1 of RAM for this ring */
  150     lance_addr_t ri_outptr;                     /* Pointer to first output byte */
  151     unsigned ri_outsize;                /* Space remaining for output */
  152 };
  153 
  154 struct le_lance_info {
  155     unsigned lance__csr1;               /* LANCE Address of init block (low 16) */
  156     unsigned lance__csr2;               /* LANCE Address of init block (high 8) */
  157     unsigned lance__csr3;               /* Copy of CSR3 */
  158     unsigned lance__rap;                /* IO Port Offset of RAP */
  159     unsigned lance__rdp;                /* IO Port Offset of RDP */
  160     unsigned lance__ramoffset;          /* Offset to valid LANCE RAM */
  161     unsigned lance__ramsize;            /* Amount of RAM shared by LANCE */
  162     unsigned lance__rxbufsize;          /* Size of a receive buffer */
  163     ln_initb_t lance__initb;            /* local copy of LANCE initblock */
  164     ln_initb_t *lance__raminitb;        /* copy to board's LANCE initblock (debugging) */
  165     ln_desc_t *lance__ramdesc;          /* copy to board's LANCE descriptors (debugging) */
  166     lance_ring_t lance__rxinfo;         /* Receive ring information */
  167     lance_ring_t lance__txinfo;         /* Transmit ring information */
  168 #define lance_csr1              le_un.un_lance.lance__csr1
  169 #define lance_csr2              le_un.un_lance.lance__csr2
  170 #define lance_csr3              le_un.un_lance.lance__csr3
  171 #define lance_rap               le_un.un_lance.lance__rap
  172 #define lance_rdp               le_un.un_lance.lance__rdp
  173 #define lance_ramoffset         le_un.un_lance.lance__ramoffset
  174 #define lance_ramsize           le_un.un_lance.lance__ramsize
  175 #define lance_rxbufsize         le_un.un_lance.lance__rxbufsize
  176 #define lance_initb             le_un.un_lance.lance__initb
  177 #define lance_raminitb          le_un.un_lance.lance__raminitb
  178 #define lance_ramdesc           le_un.un_lance.lance__ramdesc
  179 #define lance_rxinfo            le_un.un_lance.lance__rxinfo
  180 #define lance_txinfo            le_un.un_lance.lance__txinfo
  181 };
  182 #endif /* !defined(LE_NOLANCE) */
  183 
  184 /*
  185  * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  186  *
  187  * Start of Common Code
  188  *
  189  */
  190 
  191 static void (*le_intrvec[NLE])(le_softc_t *sc);
  192 
  193 /*
  194  * Ethernet status, per interface.
  195  */
  196 struct le_softc {
  197     struct arpcom le_ac;                /* Common Ethernet/ARP Structure */
  198     void (*if_init)(le_softc_t *);/* Interface init routine */
  199     void (*if_reset)(le_softc_t *);/* Interface reset routine */
  200     caddr_t le_membase;                 /* Starting memory address (virtual) */
  201     unsigned le_iobase;                 /* Starting I/O base address */
  202     unsigned le_irq;                    /* Interrupt Request Value */
  203     unsigned le_flags;                  /* local copy of if_flags */
  204 #define LE_BRDCSTONLY   0x01000000      /* If only broadcast is enabled */
  205     u_int le_mcmask;                    /* bit mask for CRC-32 for multicast hash */
  206     le_mcbits_t *le_mctbl;              /* pointer to multicast table */
  207     const char *le_prodname;            /* product name DE20x-xx */
  208     u_char le_hwaddr[6];                /* local copy of hwaddr */
  209     union {
  210 #if !defined(LE_NOLEMAC)
  211         struct le_lemac_info un_lemac;  /* LEMAC specific information */
  212 #endif
  213 #if !defined(LE_NOLANCE)
  214         struct le_lance_info un_lance;  /* Am7990 specific information */
  215 #endif
  216     } le_un;
  217 };
  218 #define le_if           le_ac.ac_if
  219 
  220 
  221 static int le_probe(struct isa_device *dvp);
  222 static int le_attach(struct isa_device *dvp);
  223 static ointhand2_t le_intr;
  224 static int le_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
  225 static void le_input(le_softc_t *sc, caddr_t seg1, size_t total_len,
  226                      size_t len2, caddr_t seg2);
  227 static void le_multi_filter(le_softc_t *sc);
  228 static void le_multi_op(le_softc_t *sc, const u_char *mca, int oper_flg);
  229 static int le_read_macaddr(le_softc_t *sc, int ioreg, int skippat);
  230 
  231 #define LE_CRC32_POLY           0xEDB88320UL    /* CRC-32 Poly -- Little Endian */
  232 
  233 struct le_board {
  234     int (*bd_probe)(le_softc_t *sc, const le_board_t *bd, int *msize);
  235 };
  236 
  237 
  238 static le_softc_t le_softc[NLE];
  239 
  240 static const le_board_t le_boards[] = {
  241 #if !defined(LE_NOLEMAC)
  242     { lemac_probe },                    /* DE20[345] */
  243 #endif
  244 #if !defined(LE_NOLANCE)
  245     { depca_probe },                    /* DE{20[012],422} */
  246 #endif
  247     { NULL }                            /* Must Be Last! */
  248 };
  249 
  250 /*
  251  * This tells the autoconf code how to set us up.
  252  */
  253 struct isa_driver ledriver = {
  254         INTR_TYPE_NET,
  255         le_probe,
  256         le_attach,
  257         "le",
  258 };
  259 COMPAT_ISA_DRIVER(le, ledriver);
  260 
  261 static unsigned le_intrs[NLE];
  262 
  263 #define LE_ADDREQUAL(a1, a2) \
  264         (((u_short *)a1)[0] == ((u_short *)a2)[0] \
  265          || ((u_short *)a1)[1] == ((u_short *)a2)[1] \
  266          || ((u_short *)a1)[2] == ((u_short *)a2)[2])
  267 #define LE_ADDRBRDCST(a1) \
  268         (((u_short *)a1)[0] == 0xFFFFU \
  269          || ((u_short *)a1)[1] == 0xFFFFU \
  270          || ((u_short *)a1)[2] == 0xFFFFU)
  271 
  272 #define LE_INL(sc, reg) \
  273 ({ u_int data; \
  274         __asm __volatile("inl %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
  275         data; })
  276 
  277 
  278 #define LE_OUTL(sc, reg, data) \
  279         ({__asm __volatile("outl %0, %1"::"a" ((u_int)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
  280 
  281 #define LE_INW(sc, reg) \
  282 ({ u_short data; \
  283         __asm __volatile("inw %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
  284         data; })
  285 
  286 
  287 #define LE_OUTW(sc, reg, data) \
  288         ({__asm __volatile("outw %0, %1"::"a" ((u_short)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
  289 
  290 #define LE_INB(sc, reg) \
  291 ({ u_char data; \
  292         __asm __volatile("inb %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
  293         data; })
  294 
  295 
  296 #define LE_OUTB(sc, reg, data) \
  297         ({__asm __volatile("outb %0, %1"::"a" ((u_char)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
  298 
  299 #define MEMCPY(to, from, len)           bcopy(from, to, len)
  300 #define MEMSET(where, what, howmuch)    bzero(where, howmuch)
  301 #define MEMCMP(l, r, len)               bcmp(l, r, len)
  302 
  303 
  304 static int
  305 le_probe(
  306     struct isa_device *dvp)
  307 {
  308     le_softc_t *sc = &le_softc[dvp->id_unit];
  309     const le_board_t *bd;
  310     int iospace;
  311 
  312     if (dvp->id_unit >= NLE) {
  313         printf("%s%d not configured -- too many devices\n",
  314                ledriver.name, dvp->id_unit);
  315         return 0;
  316     }
  317 
  318     sc->le_iobase = dvp->id_iobase;
  319     sc->le_membase = (u_char *) dvp->id_maddr;
  320     sc->le_irq = dvp->id_irq;
  321     sc->le_if.if_name = (char *)(uintptr_t)(const void *)ledriver.name;
  322     sc->le_if.if_unit = dvp->id_unit;
  323 
  324     /*
  325      * Find and Initialize board..
  326      */
  327 
  328     sc->le_flags &= ~(IFF_UP|IFF_ALLMULTI);
  329 
  330     for (bd = le_boards; bd->bd_probe != NULL; bd++) {
  331         if ((iospace = (*bd->bd_probe)(sc, bd, &dvp->id_msize)) != 0) {
  332             return iospace;
  333         }
  334     }
  335 
  336     return 0;
  337 }
  338 
  339 static int
  340 le_attach(
  341     struct isa_device *dvp)
  342 {
  343     le_softc_t *sc = &le_softc[dvp->id_unit];
  344     struct ifnet *ifp = &sc->le_if;
  345 
  346     dvp->id_ointr = le_intr;
  347     ifp->if_softc = sc;
  348     ifp->if_mtu = ETHERMTU;
  349     if_printf(ifp, "%s ethernet address %6D\n",
  350         sc->le_prodname,
  351         sc->le_ac.ac_enaddr, ":");
  352 
  353     ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
  354     ifp->if_ioctl = le_ioctl;
  355     ifp->if_type = IFT_ETHER;
  356     ifp->if_addrlen = 6;
  357     ifp->if_hdrlen = 14;
  358 
  359     ether_ifattach(ifp, sc->le_ac.ac_enaddr);
  360 
  361     return 1;
  362 }
  363 
  364 static void
  365 le_intr(
  366     int unit)
  367 {
  368     int s = splimp();
  369 
  370     le_intrs[unit]++;
  371     (*le_intrvec[unit])(&le_softc[unit]);
  372 
  373     splx(s);
  374 }
  375 
  376 #define LE_XTRA         0
  377 
  378 static void
  379 le_input(
  380     le_softc_t *sc,
  381     caddr_t seg1,
  382     size_t total_len,
  383     size_t len1,
  384     caddr_t seg2)
  385 {
  386     struct ifnet *ifp = &sc->le_if;
  387     struct mbuf *m;
  388 
  389     MGETHDR(m, M_DONTWAIT, MT_DATA);
  390     if (m == NULL) {
  391         ifp->if_ierrors++;
  392         return;
  393     }
  394     m->m_pkthdr.len = total_len;
  395     m->m_pkthdr.rcvif = ifp;
  396     if (total_len + LE_XTRA > MHLEN /* >= MINCLSIZE */) {
  397         MCLGET(m, M_DONTWAIT);
  398         if ((m->m_flags & M_EXT) == 0) {
  399             m_free(m);
  400             ifp->if_ierrors++;
  401             return;
  402         }
  403     } else if (total_len + LE_XTRA > MHLEN && MINCLSIZE == (MHLEN+MLEN)) {
  404         MGET(m->m_next, M_DONTWAIT, MT_DATA);
  405         if (m->m_next == NULL) {
  406             m_free(m);
  407             ifp->if_ierrors++;
  408             return;
  409         }
  410         m->m_next->m_len = total_len - MHLEN - LE_XTRA;
  411         len1 = total_len = MHLEN - LE_XTRA;
  412         MEMCPY(mtod(m->m_next, caddr_t), &seg1[MHLEN-LE_XTRA], m->m_next->m_len);
  413     } else if (total_len + LE_XTRA > MHLEN) {
  414         panic("le_input: pkt of unknown length");
  415     }
  416     m->m_data += LE_XTRA;
  417     m->m_len = total_len;
  418     MEMCPY(mtod(m, caddr_t), seg1, len1);
  419     if (seg2 != NULL)
  420         MEMCPY(mtod(m, caddr_t) + len1, seg2, total_len - len1);
  421 
  422     (*ifp->if_input)(ifp, m);
  423 }
  424 
  425 static int
  426 le_ioctl(
  427     struct ifnet *ifp,
  428     u_long cmd,
  429     caddr_t data)
  430 {
  431     le_softc_t *sc = ifp->if_softc;
  432     int s, error = 0;
  433 
  434     if ((sc->le_flags & IFF_UP) == 0)
  435         return EIO;
  436 
  437     s = splimp();
  438 
  439     switch (cmd) {
  440         case SIOCSIFFLAGS: {
  441             sc->if_init(sc);
  442             break;
  443         }
  444 
  445         case SIOCADDMULTI:
  446         case SIOCDELMULTI:
  447             /*
  448              * Update multicast listeners
  449              */
  450                 sc->if_init(sc);
  451                 error = 0;
  452                 break;
  453 
  454         default: {
  455             error = ether_ioctl(ifp, cmd, data);
  456             break;
  457         }
  458     }
  459 
  460     splx(s);
  461     return error;
  462 }
  463 
  464 /*
  465  *  This is the standard method of reading the DEC Address ROMS.
  466  *  I don't understand it but it does work.
  467  */
  468 static int
  469 le_read_macaddr(
  470     le_softc_t *sc,
  471     int ioreg,
  472     int skippat)
  473 {
  474     int cksum, rom_cksum;
  475 
  476     if (!skippat) {
  477         int idx, idx2, found, octet;
  478         static u_char testpat[] = { 0xFF, 0, 0x55, 0xAA, 0xFF, 0, 0x55, 0xAA };
  479         idx2 = found = 0;
  480 
  481         for (idx = 0; idx < 32; idx++) {
  482             octet = LE_INB(sc, ioreg);
  483 
  484             if (octet == testpat[idx2]) {
  485                 if (++idx2 == sizeof testpat) {
  486                     ++found;
  487                     break;
  488                 }
  489             } else {
  490                 idx2 = 0;
  491             }
  492         }
  493 
  494         if (!found)
  495             return -1;
  496     }
  497 
  498     cksum = 0;
  499     sc->le_hwaddr[0] = LE_INB(sc, ioreg);
  500     sc->le_hwaddr[1] = LE_INB(sc, ioreg);
  501 
  502     cksum = *(u_short *) &sc->le_hwaddr[0];
  503 
  504     sc->le_hwaddr[2] = LE_INB(sc, ioreg);
  505     sc->le_hwaddr[3] = LE_INB(sc, ioreg);
  506     cksum *= 2;
  507     if (cksum > 65535) cksum -= 65535;
  508     cksum += *(u_short *) &sc->le_hwaddr[2];
  509     if (cksum > 65535) cksum -= 65535;
  510 
  511     sc->le_hwaddr[4] = LE_INB(sc, ioreg);
  512     sc->le_hwaddr[5] = LE_INB(sc, ioreg);
  513     cksum *= 2;
  514     if (cksum > 65535) cksum -= 65535;
  515     cksum += *(u_short *) &sc->le_hwaddr[4];
  516     if (cksum >= 65535) cksum -= 65535;
  517 
  518     rom_cksum = LE_INB(sc, ioreg);
  519     rom_cksum |= LE_INB(sc, ioreg) << 8;
  520 
  521     if (cksum != rom_cksum)
  522         return -1;
  523     return 0;
  524 }
  525 
  526 static void
  527 le_multi_filter(
  528     le_softc_t *sc)
  529 {
  530     struct ifmultiaddr *ifma;
  531 
  532     MEMSET(sc->le_mctbl, 0, (sc->le_mcmask + 1) / 8);
  533 
  534     if (sc->le_if.if_flags & IFF_ALLMULTI) {
  535         sc->le_flags |= IFF_MULTICAST|IFF_ALLMULTI;
  536         return;
  537     }
  538     sc->le_flags &= ~IFF_MULTICAST;
  539     /* if (interface has had an address assigned) { */
  540         le_multi_op(sc, etherbroadcastaddr, TRUE);
  541         sc->le_flags |= LE_BRDCSTONLY|IFF_MULTICAST;
  542     /* } */
  543 
  544     sc->le_flags |= IFF_MULTICAST;
  545 
  546     TAILQ_FOREACH(ifma, &sc->le_ac.ac_if.if_multiaddrs, ifma_link) {
  547             if (ifma->ifma_addr->sa_family != AF_LINK)
  548                     continue;
  549 
  550             le_multi_op(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1);
  551             sc->le_flags &= ~LE_BRDCSTONLY;
  552     }
  553 }
  554 
  555 static void
  556 le_multi_op(
  557     le_softc_t *sc,
  558     const u_char *mca,
  559     int enable)
  560 {
  561     u_int idx, bit, data, crc = 0xFFFFFFFFUL;
  562 
  563 #ifdef __alpha
  564     for (data = *(__unaligned u_long *) mca, bit = 0; bit < 48; bit++, data >>=
  565 1)
  566         crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
  567 #else
  568     for (idx = 0; idx < 6; idx++)
  569         for (data = *mca++, bit = 0; bit < 8; bit++, data >>= 1)
  570             crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
  571 #endif
  572     /*
  573      * The following two line convert the N bit index into a longword index
  574      * and a longword mask.
  575      */
  576     crc &= sc->le_mcmask;
  577     bit = 1 << (crc & (LE_MC_NBPW -1));
  578     idx = crc >> (LE_MC_NBPW_LOG2);
  579 
  580     /*
  581      * Set or clear hash filter bit in our table.
  582      */
  583     if (enable) {
  584         sc->le_mctbl[idx] |= bit;               /* Set Bit */
  585     } else {
  586         sc->le_mctbl[idx] &= ~bit;              /* Clear Bit */
  587     }
  588 }
  589 
  590 #if !defined(LE_NOLEMAC)
  591 /*
  592  * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
  593  *
  594  * Start of DEC EtherWORKS III (LEMAC) dependent code
  595  *
  596  */
  597 
  598 #define LEMAC_INTR_ENABLE(sc) \
  599         LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_ALL)
  600 
  601 #define LEMAC_INTR_DISABLE(sc) \
  602         LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ~LEMAC_IC_ALL)
  603 
  604 #define LEMAC_64K_MODE(mbase)   (((mbase) >= 0x0A) && ((mbase) <= 0x0F))
  605 #define LEMAC_32K_MODE(mbase)   (((mbase) >= 0x14) && ((mbase) <= 0x1F))
  606 #define LEMAC_2K_MODE(mbase)    ( (mbase) >= 0x40)
  607 
  608 static void lemac_init(le_softc_t *sc);
  609 static void lemac_start(struct ifnet *ifp);
  610 static void lemac_reset(le_softc_t *sc);
  611 static void lemac_intr(le_softc_t *sc);
  612 static void lemac_rne_intr(le_softc_t *sc);
  613 static void lemac_tne_intr(le_softc_t *sc);
  614 static void lemac_txd_intr(le_softc_t *sc, unsigned cs_value);
  615 static void lemac_rxd_intr(le_softc_t *sc, unsigned cs_value);
  616 static int  lemac_read_eeprom(le_softc_t *sc);
  617 static void lemac_init_adapmem(le_softc_t *sc);
  618 
  619 #define LE_MCBITS_ALL_1S        ((le_mcbits_t)~(le_mcbits_t)0)
  620 
  621 static const le_mcbits_t lemac_allmulti_mctbl[16] =  {
  622     LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
  623     LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
  624     LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
  625     LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
  626 };
  627 /*
  628  * An IRQ mapping table.  Less space than switch statement.
  629  */
  630 static const int lemac_irqs[] = { IRQ5, IRQ10, IRQ11, IRQ15 };
  631 
  632 /*
  633  * Some tuning/monitoring variables.
  634  */
  635 static unsigned lemac_deftxmax = 16;    /* see lemac_max above */
  636 static unsigned lemac_txnospc = 0;      /* total # of tranmit starvations */
  637 
  638 static unsigned lemac_tne_intrs = 0;    /* total # of tranmit done intrs */
  639 static unsigned lemac_rne_intrs = 0;    /* total # of receive done intrs */
  640 static unsigned lemac_txd_intrs = 0;    /* total # of tranmit error intrs */
  641 static unsigned lemac_rxd_intrs = 0;    /* total # of receive error intrs */
  642 
  643 
  644 static int
  645 lemac_probe(
  646     le_softc_t *sc,
  647     const le_board_t *bd,
  648     int *msize)
  649 {
  650     int irq, portval;
  651 
  652     LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
  653     DELAY(LEMAC_EEP_DELAY);
  654 
  655     /*
  656      *  Read Ethernet address if card is present.
  657      */
  658     if (le_read_macaddr(sc, LEMAC_REG_APD, 0) < 0)
  659         return 0;
  660 
  661     MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
  662     /*
  663      *  Clear interrupts and set IRQ.
  664      */
  665 
  666     portval = LE_INB(sc, LEMAC_REG_IC) & LEMAC_IC_IRQMSK;
  667     irq = lemac_irqs[portval >> 5];
  668     LE_OUTB(sc, LEMAC_REG_IC, portval);
  669 
  670     /*
  671      *  Make sure settings match.
  672      */
  673 
  674     if (irq != sc->le_irq) {
  675         if_printf(&sc->le_if,
  676             "lemac configuration error: expected IRQ 0x%x actual 0x%x\n",
  677             sc->le_irq, irq);
  678         return 0;
  679     }
  680 
  681     /*
  682      * Try to reset the unit
  683      */
  684     sc->if_init = lemac_init;
  685     sc->le_if.if_start = lemac_start;
  686     sc->if_reset = lemac_reset;
  687     sc->lemac_memmode = 2;
  688     sc->if_reset(sc);
  689     if ((sc->le_flags & IFF_UP) == 0)
  690         return 0;
  691 
  692     /*
  693      *  Check for correct memory base configuration.
  694      */
  695     if (vtophys(sc->le_membase) != sc->lemac_membase) {
  696         if_printf(&sc->le_if,
  697             "lemac configuration error: expected iomem 0x%x actual 0x%x\n",
  698             vtophys(sc->le_membase), sc->lemac_membase);
  699         return 0;
  700     }
  701 
  702     sc->le_prodname = sc->lemac_prodname;
  703     sc->le_mctbl = sc->lemac_mctbl;
  704     sc->le_mcmask = (1 << LEMAC_MCTBL_BITS) - 1;
  705     sc->lemac_txmax = lemac_deftxmax;
  706     *msize = 2048;
  707     le_intrvec[sc->le_if.if_unit] = lemac_intr;
  708 
  709     return LEMAC_IOSPACE;
  710 }
  711 
  712 /*
  713  * Do a hard reset of the board;
  714  */
  715 static void
  716 lemac_reset(
  717     le_softc_t *sc)
  718 {
  719     int portval, cksum;
  720 
  721     /*
  722      * Initialize board..
  723      */
  724 
  725     sc->le_flags &= IFF_UP;
  726     sc->le_if.if_flags &= ~IFF_OACTIVE;
  727     LEMAC_INTR_DISABLE(sc);
  728 
  729     LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
  730     DELAY(LEMAC_EEP_DELAY);
  731 
  732     /* Disable Interrupts */
  733     /* LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ICR_IRQ_SEL); */
  734 
  735     /*
  736      * Read EEPROM information.  NOTE - the placement of this function
  737      * is important because functions hereafter may rely on information
  738      * read from the EEPROM.
  739      */
  740     if ((cksum = lemac_read_eeprom(sc)) != LEMAC_EEP_CKSUM) {
  741         if_printf(&sc->le_if, "reset: EEPROM checksum failed (0x%x)\n", cksum);
  742         return;
  743     }
  744 
  745     /*
  746      *  Force to 2K mode if not already configured.
  747      */
  748 
  749     portval = LE_INB(sc, LEMAC_REG_MBR);
  750     if (!LEMAC_2K_MODE(portval)) {
  751         if (LEMAC_64K_MODE(portval)) {
  752             portval = (((portval * 2) & 0xF) << 4);
  753             sc->lemac_memmode = 64;
  754         } else if (LEMAC_32K_MODE(portval)) {
  755             portval = ((portval & 0xF) << 4);
  756             sc->lemac_memmode = 32;
  757         }
  758         LE_OUTB(sc, LEMAC_REG_MBR, portval);
  759     }
  760     sc->lemac_membase = portval * (2 * 1024) + (512 * 1024);
  761 
  762     /*
  763      *  Initialize Free Memory Queue, Init mcast table with broadcast.
  764      */
  765 
  766     lemac_init_adapmem(sc);
  767     sc->le_flags |= IFF_UP;
  768     return;
  769 }
  770 
  771 static void
  772 lemac_init(
  773     le_softc_t *sc)
  774 {
  775     int s;
  776 
  777     if ((sc->le_flags & IFF_UP) == 0)
  778         return;
  779 
  780     s = splimp();
  781 
  782     /*
  783      * If the interface has the up flag
  784      */
  785     if (sc->le_if.if_flags & IFF_UP) {
  786         int saved_cs = LE_INB(sc, LEMAC_REG_CS);
  787         LE_OUTB(sc, LEMAC_REG_CS, saved_cs | (LEMAC_CS_TXD | LEMAC_CS_RXD));
  788         LE_OUTB(sc, LEMAC_REG_PA0, sc->le_ac.ac_enaddr[0]);
  789         LE_OUTB(sc, LEMAC_REG_PA1, sc->le_ac.ac_enaddr[1]);
  790         LE_OUTB(sc, LEMAC_REG_PA2, sc->le_ac.ac_enaddr[2]);
  791         LE_OUTB(sc, LEMAC_REG_PA3, sc->le_ac.ac_enaddr[3]);
  792         LE_OUTB(sc, LEMAC_REG_PA4, sc->le_ac.ac_enaddr[4]);
  793         LE_OUTB(sc, LEMAC_REG_PA5, sc->le_ac.ac_enaddr[5]);
  794 
  795         LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_IE);
  796 
  797         if (sc->le_if.if_flags & IFF_PROMISC) {
  798             LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE | LEMAC_CS_PME);
  799         } else {
  800             LEMAC_INTR_DISABLE(sc);
  801             le_multi_filter(sc);
  802             LE_OUTB(sc, LEMAC_REG_MPN, 0);
  803             if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
  804                 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], lemac_allmulti_mctbl, sizeof(lemac_allmulti_mctbl));
  805             } else {
  806                 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], sc->lemac_mctbl, sizeof(sc->lemac_mctbl));
  807             }
  808             LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE);
  809         }
  810 
  811         LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
  812 
  813         LEMAC_INTR_ENABLE(sc);
  814         sc->le_if.if_flags |= IFF_RUNNING;
  815     } else {
  816         LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_RXD|LEMAC_CS_TXD);
  817 
  818         LEMAC_INTR_DISABLE(sc);
  819         sc->le_if.if_flags &= ~IFF_RUNNING;
  820     }
  821     splx(s);
  822 }
  823 
  824 /*
  825  * What to do upon receipt of an interrupt.
  826  */
  827 static void
  828 lemac_intr(
  829     le_softc_t *sc)
  830 {
  831     int cs_value;
  832 
  833     LEMAC_INTR_DISABLE(sc);     /* Mask interrupts */
  834 
  835     /*
  836      * Determine cause of interrupt.  Receive events take
  837      * priority over Transmit.
  838      */
  839 
  840     cs_value = LE_INB(sc, LEMAC_REG_CS);
  841 
  842     /*
  843      * Check for Receive Queue not being empty.
  844      * Check for Transmit Done Queue not being empty.
  845      */
  846 
  847     if (cs_value & LEMAC_CS_RNE)
  848         lemac_rne_intr(sc);
  849     if (cs_value & LEMAC_CS_TNE)
  850         lemac_tne_intr(sc);
  851 
  852     /*
  853      * Check for Transmitter Disabled.
  854      * Check for Receiver Disabled.
  855      */
  856 
  857     if (cs_value & LEMAC_CS_TXD)
  858         lemac_txd_intr(sc, cs_value);
  859     if (cs_value & LEMAC_CS_RXD)
  860         lemac_rxd_intr(sc, cs_value);
  861 
  862     /*
  863      * Toggle LED and unmask interrupts.
  864      */
  865 
  866     LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
  867     LEMAC_INTR_ENABLE(sc);              /* Unmask interrupts */
  868 }
  869 
  870 static void
  871 lemac_rne_intr(
  872     le_softc_t *sc)
  873 {
  874     int rxcount, rxlen, rxpg;
  875     u_char *rxptr;
  876 
  877     lemac_rne_intrs++;
  878     rxcount = LE_INB(sc, LEMAC_REG_RQC);
  879     while (rxcount--) {
  880         rxpg = LE_INB(sc, LEMAC_REG_RQ);
  881         LE_OUTB(sc, LEMAC_REG_MPN, rxpg);
  882 
  883         rxptr = sc->le_membase;
  884         sc->le_if.if_ipackets++;
  885         if (*rxptr & LEMAC_RX_OK) {
  886 
  887             /*
  888              * Get receive length - subtract out checksum.
  889              */
  890 
  891             rxlen = ((*(u_int *)rxptr >> 8) & 0x7FF) - 4;
  892             le_input(sc, rxptr + sizeof(u_int), rxlen, rxlen, NULL);
  893         } else { /* end if (*rxptr & LEMAC_RX_OK) */
  894             sc->le_if.if_ierrors++;
  895         }
  896         LE_OUTB(sc, LEMAC_REG_FMQ, rxpg);  /* Return this page to Free Memory Queue */
  897     }  /* end while (recv_count--) */
  898 
  899     return;
  900 }
  901 
  902 static void
  903 lemac_rxd_intr(
  904     le_softc_t *sc,
  905     unsigned cs_value)
  906 {
  907     /*
  908      * Handle CS_RXD (Receiver disabled) here.
  909      *
  910      * Check Free Memory Queue Count. If not equal to zero
  911      * then just turn Receiver back on. If it is equal to
  912      * zero then check to see if transmitter is disabled.
  913      * Process transmit TXD loop once more.  If all else
  914      * fails then do software init (0xC0 to EEPROM Init)
  915      * and rebuild Free Memory Queue.
  916      */
  917 
  918     lemac_rxd_intrs++;
  919 
  920     /*
  921      *  Re-enable Receiver.
  922      */
  923 
  924     cs_value &= ~LEMAC_CS_RXD;
  925     LE_OUTB(sc, LEMAC_REG_CS, cs_value);
  926 
  927     if (LE_INB(sc, LEMAC_REG_FMC) > 0)
  928         return;
  929 
  930     if (cs_value & LEMAC_CS_TXD)
  931         lemac_txd_intr(sc, cs_value);
  932 
  933     if ((LE_INB(sc, LEMAC_REG_CS) & LEMAC_CS_RXD) == 0)
  934         return;
  935 
  936     if_printf(&sc->le_if, "fatal RXD error, attempting recovery\n");
  937 
  938     sc->if_reset(sc);
  939     if (sc->le_flags & IFF_UP) {
  940         lemac_init(sc);
  941         return;
  942     }
  943 
  944     /*
  945      *  Error during initializion.  Mark card as disabled.
  946      */
  947     if_printf(&sc->le_if, "recovery failed -- board disabled\n");
  948     return;
  949 }
  950 
  951 static void
  952 lemac_start(
  953     struct ifnet *ifp)
  954 {
  955     le_softc_t *sc = (le_softc_t *) ifp;
  956     struct ifqueue *ifq = &ifp->if_snd;
  957 
  958     if ((ifp->if_flags & IFF_RUNNING) == 0)
  959         return;
  960 
  961     LEMAC_INTR_DISABLE(sc);
  962 
  963     while (ifq->ifq_head != NULL) {
  964         struct mbuf  *m;
  965         int tx_pg;
  966         u_int txhdr, txoff;
  967 
  968         if (LE_INB(sc, LEMAC_REG_TQC) >= sc->lemac_txmax) {
  969             ifp->if_flags |= IFF_OACTIVE;
  970             break;
  971         }
  972 
  973         tx_pg = LE_INB(sc, LEMAC_REG_FMQ);      /* get free memory page */
  974         /*
  975          * Check for good transmit page.
  976          */
  977         if (tx_pg == 0 || tx_pg > sc->lemac_lastpage) {
  978             lemac_txnospc++;
  979             ifp->if_flags |= IFF_OACTIVE;
  980             break;
  981         }
  982 
  983         IF_DEQUEUE(ifq, m);
  984         LE_OUTB(sc, LEMAC_REG_MPN, tx_pg);      /* Shift 2K window. */
  985 
  986         /*
  987          * The first four bytes of each transmit buffer are for
  988          * control information.  The first byte is the control
  989          * byte, then the length (why not word aligned?), then
  990          * the off to the buffer.
  991          */
  992 
  993         txoff = (mtod(m, u_int) & (sizeof(u_long) - 1)) + LEMAC_TX_HDRSZ;
  994         txhdr = sc->lemac_txctl | (m->m_pkthdr.len << 8) | (txoff << 24);
  995         *(u_int *) sc->le_membase = txhdr;
  996 
  997         /*
  998          * Copy the packet to the board
  999          */
 1000 
 1001         m_copydata(m, 0, m->m_pkthdr.len, sc->le_membase + txoff);
 1002 
 1003         LE_OUTB(sc, LEMAC_REG_TQ, tx_pg);       /* tell chip to transmit this packet */
 1004 
 1005         BPF_MTAP(&sc->le_if, m);
 1006 
 1007         m_freem(m);                     /* free the mbuf */
 1008     }
 1009     LEMAC_INTR_ENABLE(sc);
 1010 }
 1011 
 1012 static void
 1013 lemac_tne_intr(
 1014     le_softc_t *sc)
 1015 {
 1016     int txsts, txcount = LE_INB(sc, LEMAC_REG_TDC);
 1017 
 1018     lemac_tne_intrs++;
 1019     while (txcount--) {
 1020         txsts = LE_INB(sc, LEMAC_REG_TDQ);
 1021         sc->le_if.if_opackets++;                /* another one done */
 1022         if ((txsts & LEMAC_TDQ_COL) != LEMAC_TDQ_NOCOL)
 1023             sc->le_if.if_collisions++;
 1024     }
 1025     sc->le_if.if_flags &= ~IFF_OACTIVE;
 1026     lemac_start(&sc->le_if);
 1027 }
 1028 
 1029 static void
 1030 lemac_txd_intr(
 1031     le_softc_t *sc,
 1032     unsigned cs_value)
 1033 {
 1034     /*
 1035      * Read transmit status, remove transmit buffer from
 1036      * transmit queue and place on free memory queue,
 1037      * then reset transmitter.
 1038      * Increment appropriate counters.
 1039      */
 1040 
 1041     lemac_txd_intrs++;
 1042     sc->le_if.if_oerrors++;
 1043     if (LE_INB(sc, LEMAC_REG_TS) & LEMAC_TS_ECL)
 1044         sc->le_if.if_collisions++;
 1045     sc->le_if.if_flags &= ~IFF_OACTIVE;
 1046 
 1047     LE_OUTB(sc, LEMAC_REG_FMQ, LE_INB(sc, LEMAC_REG_TQ));
 1048                                 /* Get Page number and write it back out */
 1049 
 1050     LE_OUTB(sc, LEMAC_REG_CS, cs_value & ~LEMAC_CS_TXD);
 1051                                 /* Turn back on transmitter */
 1052     return;
 1053 }
 1054 
 1055 static int
 1056 lemac_read_eeprom(
 1057     le_softc_t *sc)
 1058 {
 1059     int word_off, cksum;
 1060 
 1061     u_char *ep;
 1062 
 1063     cksum = 0;
 1064     ep = sc->lemac_eeprom;
 1065     for (word_off = 0; word_off < LEMAC_EEP_SIZE / 2; word_off++) {
 1066         LE_OUTB(sc, LEMAC_REG_PI1, word_off);
 1067         LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEREAD);
 1068 
 1069         DELAY(LEMAC_EEP_DELAY);
 1070 
 1071         *ep = LE_INB(sc, LEMAC_REG_EE1);        cksum += *ep++;
 1072         *ep = LE_INB(sc, LEMAC_REG_EE2);        cksum += *ep++;
 1073     }
 1074 
 1075     /*
 1076      *  Set up Transmit Control Byte for use later during transmit.
 1077      */
 1078 
 1079     sc->lemac_txctl |= LEMAC_TX_FLAGS;
 1080 
 1081     if ((sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_SQE) == 0)
 1082         sc->lemac_txctl &= ~LEMAC_TX_SQE;
 1083 
 1084     if (sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_LAB)
 1085         sc->lemac_txctl |= LEMAC_TX_LAB;
 1086 
 1087     MEMCPY(sc->lemac_prodname, &sc->lemac_eeprom[LEMAC_EEP_PRDNM], LEMAC_EEP_PRDNMSZ);
 1088     sc->lemac_prodname[LEMAC_EEP_PRDNMSZ] = '\0';
 1089 
 1090     return cksum % 256;
 1091 }
 1092 
 1093 static void
 1094 lemac_init_adapmem(
 1095     le_softc_t *sc)
 1096 {
 1097     int pg, conf;
 1098 
 1099     conf = LE_INB(sc, LEMAC_REG_CNF);
 1100 
 1101     if ((sc->lemac_eeprom[LEMAC_EEP_SETUP] & LEMAC_EEP_ST_DRAM) == 0) {
 1102         sc->lemac_lastpage = 63;
 1103         conf &= ~LEMAC_CNF_DRAM;
 1104     } else {
 1105         sc->lemac_lastpage = 127;
 1106         conf |= LEMAC_CNF_DRAM;
 1107     }
 1108 
 1109     LE_OUTB(sc, LEMAC_REG_CNF, conf);
 1110 
 1111     for (pg = 1; pg <= sc->lemac_lastpage; pg++)
 1112         LE_OUTB(sc, LEMAC_REG_FMQ, pg);
 1113 
 1114     return;
 1115 }
 1116 #endif /* !defined(LE_NOLEMAC) */
 1117 
 1118 #if !defined(LE_NOLANCE)
 1119 /*
 1120  * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
 1121  *
 1122  * Start of DEPCA (DE200/DE201/DE202/DE422 etal) support.
 1123  *
 1124  */
 1125 static void depca_intr(le_softc_t *sc);
 1126 static int  lance_init_adapmem(le_softc_t *sc);
 1127 static int  lance_init_ring(le_softc_t *sc, ln_ring_t *rp, lance_ring_t *ri,
 1128                             unsigned ndescs, unsigned bufoffset,
 1129                             unsigned descoffset);
 1130 static void lance_init(le_softc_t *sc);
 1131 static void lance_reset(le_softc_t *sc);
 1132 static void lance_intr(le_softc_t *sc);
 1133 static int  lance_rx_intr(le_softc_t *sc);
 1134 static void lance_start(struct ifnet *ifp);
 1135 static int  lance_tx_intr(le_softc_t *sc);
 1136 
 1137 #define LN_BUFSIZE              /* 380 */ 304   /* 1520 / 4 */
 1138 #define LN_TXDESC_RATIO         2048
 1139 #define LN_DESC_MAX             128
 1140 
 1141 #if LN_DOSTATS
 1142 static struct {
 1143     unsigned lance_rx_misses;
 1144     unsigned lance_rx_badcrc;
 1145     unsigned lance_rx_badalign;
 1146     unsigned lance_rx_badframe;
 1147     unsigned lance_rx_buferror;
 1148     unsigned lance_tx_deferred;
 1149     unsigned lance_tx_single_collisions;
 1150     unsigned lance_tx_multiple_collisions;
 1151     unsigned lance_tx_excessive_collisions;
 1152     unsigned lance_tx_late_collisions;
 1153 
 1154     unsigned lance_memory_errors;
 1155     unsigned lance_inits;
 1156     unsigned lance_tx_intrs;
 1157     unsigned lance_tx_nospc[2];
 1158     unsigned lance_tx_drains[2];
 1159     unsigned lance_tx_orphaned;
 1160     unsigned lance_tx_adoptions;
 1161     unsigned lance_tx_emptied;
 1162     unsigned lance_tx_deftxint;
 1163     unsigned lance_tx_buferror;
 1164     unsigned lance_high_txoutptr;
 1165     unsigned lance_low_txheapsize;
 1166     unsigned lance_low_txfree;
 1167     unsigned lance_tx_intr_hidescs;
 1168     /* unsigned lance_tx_intr_descs[LN_DESC_MAX]; */
 1169 
 1170     unsigned lance_rx_intrs;
 1171     unsigned lance_rx_badsop;
 1172     unsigned lance_rx_contig;
 1173     unsigned lance_rx_noncontig;
 1174     unsigned lance_rx_intr_hidescs;
 1175     unsigned lance_rx_ndescs[4096 / LN_BUFSIZE];
 1176     /* unsigned lance_rx_intr_descs[LN_DESC_MAX]; */
 1177 } lance_stats;
 1178 
 1179 #define LN_STAT(stat)   (lance_stats.lance_ ## stat)
 1180 #define LN_MINSTAT(stat, val)   (LN_STAT(stat > (val)) ? LN_STAT(stat = (val)) : 0)
 1181 #define LN_MAXSTAT(stat, val)   (LN_STAT(stat < (val)) ? LN_STAT(stat = (val)) : 0)
 1182 
 1183 #else
 1184 #define LN_STAT(stat)   0
 1185 #define LN_MINSTAT(stat, val)   0
 1186 #define LN_MAXSTAT(stat, val)   0
 1187 #endif
 1188 
 1189 #define LN_SELCSR(sc, csrno)            (LE_OUTW(sc, sc->lance_rap, csrno))
 1190 #define LN_INQCSR(sc)                   (LE_INW(sc, sc->lance_rap))
 1191 
 1192 #define LN_WRCSR(sc, val)               (LE_OUTW(sc, sc->lance_rdp, val))
 1193 #define LN_RDCSR(sc)                    (LE_INW(sc, sc->lance_rdp))
 1194 
 1195 
 1196 #define LN_ZERO(sc, vaddr, len)         bzero(vaddr, len)
 1197 #define LN_COPYTO(sc, from, to, len)    bcopy(from, to, len)
 1198 
 1199 #define LN_SETFLAG(sc, vaddr, val) \
 1200         (((volatile u_char *) vaddr)[3] = (val))
 1201 
 1202 #define LN_PUTDESC(sc, desc, vaddr) \
 1203         (((volatile u_short *) vaddr)[0] = ((u_short *) desc)[0], \
 1204          ((volatile u_short *) vaddr)[2] = ((u_short *) desc)[2], \
 1205          ((volatile u_short *) vaddr)[1] = ((u_short *) desc)[1])
 1206 
 1207 /*
 1208  * Only get the descriptor flags and length/status.  All else
 1209  * read-only.
 1210  */
 1211 #define LN_GETDESC(sc, desc, vaddr) \
 1212         (((u_short *) desc)[1] = ((volatile u_short *) vaddr)[1], \
 1213          ((u_short *) desc)[3] = ((volatile u_short *) vaddr)[3])
 1214 
 1215 
 1216 /*
 1217  *  These definitions are specific to the DEC "DEPCA-style" NICs.
 1218  *      (DEPCA, DE10x, DE20[012], DE422)
 1219  *
 1220  */
 1221 #define DEPCA_REG_NICSR         0               /* (RW;16) NI Control / Status */
 1222 #define DEPCA_REG_RDP           4               /* (RW:16) LANCE RDP (data) register */
 1223 #define DEPCA_REG_RAP           6               /* (RW:16) LANCE RAP (address) register */
 1224 #define DEPCA_REG_ADDRROM       12              /* (R : 8) DEPCA Ethernet Address ROM */
 1225 #define DEPCA_IOSPACE           16              /* DEPCAs use 16 bytes of IO space */
 1226 
 1227 #define DEPCA_NICSR_LED         0x0001          /* Light the LED on the back of the DEPCA */
 1228 #define DEPCA_NICSR_ENABINTR    0x0002          /* Enable Interrupts */
 1229 #define DEPCA_NICSR_MASKINTR    0x0004          /* Mask Interrupts */
 1230 #define DEPCA_NICSR_AAC         0x0008          /* Address Counter Clear */
 1231 #define DEPCA_NICSR_REMOTEBOOT  0x0010          /* Remote Boot Enabled (ignored) */
 1232 #define DEPCA_NICSR_32KRAM      0x0020          /* DEPCA LANCE RAM size 64K (C) / 32K (S) */
 1233 #define DEPCA_NICSR_LOW32K      0x0040          /* Bank Select (A15 = !This Bit) */
 1234 #define DEPCA_NICSR_SHE         0x0080          /* Shared RAM Enabled (ie hide ROM) */
 1235 #define DEPCA_NICSR_BOOTTMO     0x0100          /* Remote Boot Timeout (ignored) */
 1236 
 1237 #define DEPCA_RDNICSR(sc)       (LE_INW(sc, DEPCA_REG_NICSR))
 1238 #define DEPCA_WRNICSR(sc, val)  (LE_OUTW(sc, DEPCA_REG_NICSR, val))
 1239 
 1240 #define DEPCA_IDSTR_OFFSET      0xC006          /* ID String Offset */
 1241 
 1242 #define DEPCA_REG_EISAID        0x80
 1243 #define DEPCA_EISAID_MASK       0xf0ffffff
 1244 #define DEPCA_EISAID_DE422      0x2042A310
 1245 
 1246 typedef enum {
 1247     DEPCA_CLASSIC,
 1248     DEPCA_DE100, DEPCA_DE101,
 1249     DEPCA_EE100,
 1250     DEPCA_DE200, DEPCA_DE201, DEPCA_DE202,
 1251     DEPCA_DE422,
 1252     DEPCA_UNKNOWN
 1253 } depca_t;
 1254 
 1255 static const char *depca_signatures[] = {
 1256     "DEPCA",
 1257     "DE100", "DE101",
 1258     "EE100",
 1259     "DE200", "DE201", "DE202",
 1260     "DE422",
 1261     NULL
 1262 };
 1263 
 1264 static int
 1265 depca_probe(
 1266     le_softc_t *sc,
 1267     const le_board_t *bd,
 1268     int *msize)
 1269 {
 1270     unsigned nicsr, idx, idstr_offset = DEPCA_IDSTR_OFFSET;
 1271 
 1272     /*
 1273      *  Find out how memory we are dealing with.  Adjust
 1274      *  the ID string offset approriately if we are at
 1275      *  32K.  Make sure the ROM is enabled.
 1276      */
 1277     nicsr = DEPCA_RDNICSR(sc);
 1278     nicsr &= ~(DEPCA_NICSR_SHE|DEPCA_NICSR_LED|DEPCA_NICSR_ENABINTR);
 1279 
 1280     if (nicsr & DEPCA_NICSR_32KRAM) {
 1281         /*
 1282          * Make we are going to read the upper
 1283          * 32K so we do read the ROM.
 1284          */
 1285         sc->lance_ramsize = 32 * 1024;
 1286         nicsr &= ~DEPCA_NICSR_LOW32K;
 1287         sc->lance_ramoffset = 32 * 1024;
 1288         idstr_offset -= sc->lance_ramsize;
 1289     } else {
 1290         sc->lance_ramsize = 64 * 1024;
 1291         sc->lance_ramoffset = 0;
 1292     }
 1293     DEPCA_WRNICSR(sc, nicsr);
 1294 
 1295     sc->le_prodname = NULL;
 1296     for (idx = 0; depca_signatures[idx] != NULL; idx++) {
 1297         if (bcmp(depca_signatures[idx], sc->le_membase + idstr_offset, 5) == 0) {
 1298             sc->le_prodname = depca_signatures[idx];
 1299             break;
 1300         }
 1301     }
 1302 
 1303     if (sc->le_prodname == NULL) {
 1304         /*
 1305          * Try to get the EISA device if it's a DE422.
 1306          */
 1307         if (sc->le_iobase > 0x1000 && (sc->le_iobase & 0x0F00) == 0x0C00
 1308             && (LE_INL(sc, DEPCA_REG_EISAID) & DEPCA_EISAID_MASK)
 1309              == DEPCA_EISAID_DE422) {
 1310             sc->le_prodname = "DE422";
 1311         } else {
 1312             return 0;
 1313         }
 1314     }
 1315     if (idx == DEPCA_CLASSIC)
 1316         sc->lance_ramsize -= 16384;     /* Can't use the ROM area on a DEPCA */
 1317 
 1318     /*
 1319      * Try to read the address ROM.
 1320      *   Stop the LANCE, reset the Address ROM Counter (AAC),
 1321      *   read the NICSR to "clock" in the reset, and then
 1322      *   re-enable the Address ROM Counter.  Now read the
 1323      *   address ROM.
 1324      */
 1325     sc->lance_rdp = DEPCA_REG_RDP;
 1326     sc->lance_rap = DEPCA_REG_RAP;
 1327     sc->lance_csr3 = LN_CSR3_ALE;
 1328     sc->le_mctbl = sc->lance_initb.ln_multi_mask;
 1329     sc->le_mcmask = LN_MC_MASK;
 1330     LN_SELCSR(sc, LN_CSR0);
 1331     LN_WRCSR(sc, LN_CSR0_STOP);
 1332 
 1333     if (idx < DEPCA_DE200) {
 1334         DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) & ~DEPCA_NICSR_AAC);
 1335         DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_AAC);
 1336     }
 1337 
 1338     if (le_read_macaddr(sc, DEPCA_REG_ADDRROM, idx == DEPCA_CLASSIC) < 0)
 1339         return 0;
 1340 
 1341     MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
 1342     /*
 1343      * Renable shared RAM.
 1344      */
 1345     DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_SHE);
 1346 
 1347     le_intrvec[sc->le_if.if_unit] = depca_intr;
 1348     if (!lance_init_adapmem(sc))
 1349         return 0;
 1350 
 1351     sc->if_reset = lance_reset;
 1352     sc->if_init = lance_init;
 1353     sc->le_if.if_start = lance_start;
 1354     DEPCA_WRNICSR(sc, DEPCA_NICSR_SHE | DEPCA_NICSR_ENABINTR);
 1355     sc->if_reset(sc);
 1356 
 1357     LN_STAT(low_txfree = sc->lance_txinfo.ri_max);
 1358     LN_STAT(low_txheapsize = 0xFFFFFFFF);
 1359     *msize = sc->lance_ramsize;
 1360     return DEPCA_IOSPACE;
 1361 }
 1362 
 1363 static void
 1364 depca_intr(
 1365     le_softc_t *sc)
 1366 {
 1367     DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) ^ DEPCA_NICSR_LED);
 1368     lance_intr(sc);
 1369 }
 1370 
 1371 /*
 1372  * Here's as good a place to describe our paritioning of the
 1373  * LANCE shared RAM space.  (NOTE: this driver does not yet support
 1374  * the concept of a LANCE being able to DMA).
 1375  *
 1376  * First is the 24 (00:23) bytes for LANCE Initialization Block
 1377  * Next are the recieve descriptors.  The number is calculated from
 1378  * how many LN_BUFSIZE buffers we can allocate (this number must
 1379  * be a power of 2).  Next are the transmit descriptors.  The amount
 1380  * of transmit descriptors is derived from the size of the RAM
 1381  * divided by 1K.  Now come the receive buffers (one for each receive
 1382  * descriptor).  Finally is the transmit heap.  (no fixed buffers are
 1383  * allocated so as to make the most use of the limited space).
 1384  */
 1385 static int
 1386 lance_init_adapmem(
 1387     le_softc_t *sc)
 1388 {
 1389     lance_addr_t rxbufoffset;
 1390     lance_addr_t rxdescoffset, txdescoffset;
 1391     unsigned rxdescs, txdescs;
 1392 
 1393     /*
 1394      * First calculate how many descriptors we heap.
 1395      * Note this assumes the ramsize is a power of two.
 1396      */
 1397     sc->lance_rxbufsize = LN_BUFSIZE;
 1398     rxdescs = 1;
 1399     while (rxdescs * sc->lance_rxbufsize < sc->lance_ramsize)
 1400         rxdescs *= 2;
 1401     rxdescs /= 2;
 1402     if (rxdescs > LN_DESC_MAX) {
 1403         sc->lance_rxbufsize *= rxdescs / LN_DESC_MAX;
 1404         rxdescs = LN_DESC_MAX;
 1405     }
 1406     txdescs = sc->lance_ramsize / LN_TXDESC_RATIO;
 1407     if (txdescs > LN_DESC_MAX)
 1408         txdescs = LN_DESC_MAX;
 1409 
 1410     /*
 1411      * Now calculate where everything goes in memory
 1412      */
 1413     rxdescoffset = sizeof(ln_initb_t);
 1414     txdescoffset = rxdescoffset + sizeof(ln_desc_t) * rxdescs;
 1415     rxbufoffset  = txdescoffset + sizeof(ln_desc_t) * txdescs;
 1416 
 1417     sc->le_mctbl = (le_mcbits_t *) sc->lance_initb.ln_multi_mask;
 1418     /*
 1419      * Remember these for debugging.
 1420      */
 1421     sc->lance_raminitb = (ln_initb_t *) sc->le_membase;
 1422     sc->lance_ramdesc = (ln_desc_t *) (sc->le_membase + rxdescoffset);
 1423 
 1424     /*
 1425      * Initialize the rings.
 1426      */
 1427     if (!lance_init_ring(sc, &sc->lance_initb.ln_rxring, &sc->lance_rxinfo,
 1428                    rxdescs, rxbufoffset, rxdescoffset))
 1429         return 0;
 1430     sc->lance_rxinfo.ri_heap = rxbufoffset;
 1431     sc->lance_rxinfo.ri_heapend = rxbufoffset + sc->lance_rxbufsize * rxdescs;
 1432 
 1433     if (!lance_init_ring(sc, &sc->lance_initb.ln_txring, &sc->lance_txinfo,
 1434                    txdescs, 0, txdescoffset))
 1435         return 0;
 1436     sc->lance_txinfo.ri_heap = sc->lance_rxinfo.ri_heapend;
 1437     sc->lance_txinfo.ri_heapend = sc->lance_ramsize;
 1438 
 1439     /*
 1440      * Set CSR1 and CSR2 to the address of the init block (which
 1441      * for us is always 0.
 1442      */
 1443     sc->lance_csr1 = LN_ADDR_LO(0 + sc->lance_ramoffset);
 1444     sc->lance_csr2 = LN_ADDR_HI(0 + sc->lance_ramoffset);
 1445     return 1;
 1446 }
 1447 
 1448 static int
 1449 lance_init_ring(
 1450     le_softc_t *sc,
 1451     ln_ring_t *rp,
 1452     lance_ring_t *ri,
 1453     unsigned ndescs,
 1454     lance_addr_t bufoffset,
 1455     lance_addr_t descoffset)
 1456 {
 1457     lance_descinfo_t *di;
 1458 
 1459     /*
 1460      * Initialize the ring pointer in the LANCE InitBlock
 1461      */
 1462     rp->r_addr_lo = LN_ADDR_LO(descoffset + sc->lance_ramoffset);
 1463     rp->r_addr_hi = LN_ADDR_HI(descoffset + sc->lance_ramoffset);
 1464     rp->r_log2_size = ffs(ndescs) - 1;
 1465 
 1466     /*
 1467      * Allocate the ring entry descriptors and initialize
 1468      * our ring information data structure.  All these are
 1469      * our copies and do not live in the LANCE RAM.
 1470      */
 1471     ri->ri_first = (lance_descinfo_t *) malloc(ndescs * sizeof(*di), M_DEVBUF, M_NOWAIT);
 1472     if (ri->ri_first == NULL) {
 1473         printf("lance_init_ring: malloc(%d) failed\n", ndescs * sizeof(*di));
 1474         return 0;
 1475     }
 1476     ri->ri_free = ri->ri_max = ndescs;
 1477     ri->ri_last = ri->ri_first + ri->ri_max;
 1478     for (di = ri->ri_first; di < ri->ri_last; di++) {
 1479         di->di_addr = sc->le_membase + descoffset;
 1480         di->di_mbuf = NULL;
 1481         if (bufoffset) {
 1482             di->di_bufaddr = bufoffset;
 1483             di->di_buflen = sc->lance_rxbufsize;
 1484             bufoffset += sc->lance_rxbufsize;
 1485         }
 1486         descoffset += sizeof(ln_desc_t);
 1487     }
 1488     return 1;
 1489 }
 1490 
 1491 static void
 1492 lance_dumpcsrs(
 1493     le_softc_t *sc,
 1494     const char *id)
 1495 {
 1496     if_printf(&sc->le_if, "%s: nicsr=%04x", id, DEPCA_RDNICSR(sc));
 1497     LN_SELCSR(sc, LN_CSR0); printf(" csr0=%04x", LN_RDCSR(sc));
 1498     LN_SELCSR(sc, LN_CSR1); printf(" csr1=%04x", LN_RDCSR(sc));
 1499     LN_SELCSR(sc, LN_CSR2); printf(" csr2=%04x", LN_RDCSR(sc));
 1500     LN_SELCSR(sc, LN_CSR3); printf(" csr3=%04x\n", LN_RDCSR(sc));
 1501     LN_SELCSR(sc, LN_CSR0);
 1502 }
 1503 
 1504 static void
 1505 lance_reset(
 1506     le_softc_t *sc)
 1507 {
 1508     register int cnt, csr;
 1509 
 1510     /* lance_dumpcsrs(sc, "lance_reset: start"); */
 1511 
 1512     LN_WRCSR(sc, LN_RDCSR(sc) & ~LN_CSR0_ENABINTR);
 1513     LN_WRCSR(sc, LN_CSR0_STOP);
 1514     DELAY(100);
 1515 
 1516     sc->le_flags &= ~IFF_UP;
 1517     sc->le_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
 1518 
 1519     le_multi_filter(sc);                /* initialize the multicast table */
 1520     if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
 1521         sc->lance_initb.ln_multi_mask[0] = 0xFFFFU;
 1522         sc->lance_initb.ln_multi_mask[1] = 0xFFFFU;
 1523         sc->lance_initb.ln_multi_mask[2] = 0xFFFFU;
 1524         sc->lance_initb.ln_multi_mask[3] = 0xFFFFU;
 1525     }
 1526     sc->lance_initb.ln_physaddr[0] = ((u_short *) sc->le_ac.ac_enaddr)[0];
 1527     sc->lance_initb.ln_physaddr[1] = ((u_short *) sc->le_ac.ac_enaddr)[1];
 1528     sc->lance_initb.ln_physaddr[2] = ((u_short *) sc->le_ac.ac_enaddr)[2];
 1529     if (sc->le_if.if_flags & IFF_PROMISC) {
 1530         sc->lance_initb.ln_mode |= LN_MODE_PROMISC;
 1531     } else {
 1532         sc->lance_initb.ln_mode &= ~LN_MODE_PROMISC;
 1533     }
 1534     /*
 1535      * We force the init block to be at the start
 1536      * of the LANCE's RAM buffer.
 1537      */
 1538     LN_COPYTO(sc, &sc->lance_initb, sc->le_membase, sizeof(sc->lance_initb));
 1539     LN_SELCSR(sc, LN_CSR1); LN_WRCSR(sc, sc->lance_csr1);
 1540     LN_SELCSR(sc, LN_CSR2); LN_WRCSR(sc, sc->lance_csr2);
 1541     LN_SELCSR(sc, LN_CSR3); LN_WRCSR(sc, sc->lance_csr3);
 1542 
 1543     /* lance_dumpcsrs(sc, "lance_reset: preinit"); */
 1544 
 1545     /*
 1546      * clear INITDONE and INIT the chip
 1547      */
 1548     LN_SELCSR(sc, LN_CSR0);
 1549     LN_WRCSR(sc, LN_CSR0_INIT|LN_CSR0_INITDONE);
 1550 
 1551     csr = 0;
 1552     cnt = 100;
 1553     while (cnt-- > 0) {
 1554         if (((csr = LN_RDCSR(sc)) & LN_CSR0_INITDONE) != 0)
 1555             break;
 1556         DELAY(10000);
 1557     }
 1558 
 1559     if ((csr & LN_CSR0_INITDONE) == 0) {    /* make sure we got out okay */
 1560         lance_dumpcsrs(sc, "lance_reset: reset failure");
 1561     } else {
 1562         /* lance_dumpcsrs(sc, "lance_reset: end"); */
 1563         sc->le_if.if_flags |= IFF_UP;
 1564         sc->le_flags |= IFF_UP;
 1565     }
 1566 }
 1567 
 1568 static void
 1569 lance_init(
 1570     le_softc_t *sc)
 1571 {
 1572     lance_ring_t *ri;
 1573     lance_descinfo_t *di;
 1574     ln_desc_t desc;
 1575 
 1576     LN_STAT(inits++);
 1577     if (sc->le_if.if_flags & IFF_RUNNING) {
 1578         sc->if_reset(sc);
 1579         lance_tx_intr(sc);
 1580         /*
 1581          * If we were running, requeue any pending transmits.
 1582          */
 1583         ri = &sc->lance_txinfo;
 1584         di = ri->ri_nextout;
 1585         while (ri->ri_free < ri->ri_max) {
 1586             if (--di == ri->ri_first)
 1587                 di = ri->ri_nextout - 1;
 1588             if (di->di_mbuf == NULL)
 1589                 break;
 1590             IF_PREPEND(&sc->le_if.if_snd, di->di_mbuf);
 1591             di->di_mbuf = NULL;
 1592             ri->ri_free++;
 1593         }
 1594     } else {
 1595         sc->if_reset(sc);
 1596     }
 1597 
 1598     /*
 1599      * Reset the transmit ring.  Make sure we own all the buffers.
 1600      * Also reset the transmit heap.
 1601      */
 1602     sc->le_if.if_flags &= ~IFF_OACTIVE;
 1603     ri = &sc->lance_txinfo;
 1604     for (di = ri->ri_first; di < ri->ri_last; di++) {
 1605         if (di->di_mbuf != NULL) {
 1606             m_freem(di->di_mbuf);
 1607             di->di_mbuf = NULL;
 1608         }
 1609         desc.d_flag = 0;
 1610         desc.d_addr_lo = LN_ADDR_LO(ri->ri_heap + sc->lance_ramoffset);
 1611         desc.d_addr_hi = LN_ADDR_HI(ri->ri_heap + sc->lance_ramoffset);
 1612         desc.d_buflen = 0;
 1613         LN_PUTDESC(sc, &desc, di->di_addr);
 1614     }
 1615     ri->ri_nextin = ri->ri_nextout = ri->ri_first;
 1616     ri->ri_free = ri->ri_max;
 1617     ri->ri_outptr = ri->ri_heap;
 1618     ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
 1619 
 1620     ri = &sc->lance_rxinfo;
 1621     desc.d_flag = LN_DFLAG_OWNER;
 1622     desc.d_buflen = 0 - sc->lance_rxbufsize;
 1623     for (di = ri->ri_first; di < ri->ri_last; di++) {
 1624         desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
 1625         desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
 1626         LN_PUTDESC(sc, &desc, di->di_addr);
 1627     }
 1628     ri->ri_nextin = ri->ri_nextout = ri->ri_first;
 1629     ri->ri_outptr = ri->ri_heap;
 1630     ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
 1631     ri->ri_free = 0;
 1632 
 1633     if (sc->le_if.if_flags & IFF_UP) {
 1634         sc->le_if.if_flags |= IFF_RUNNING;
 1635         LN_WRCSR(sc, LN_CSR0_START|LN_CSR0_INITDONE|LN_CSR0_ENABINTR);
 1636         /* lance_dumpcsrs(sc, "lance_init: up"); */
 1637         lance_start(&sc->le_if);
 1638     } else {
 1639         /* lance_dumpcsrs(sc, "lance_init: down"); */
 1640         sc->le_if.if_flags &= ~IFF_RUNNING;
 1641     }
 1642 }
 1643 
 1644 static void
 1645 lance_intr(
 1646     le_softc_t *sc)
 1647 {
 1648     unsigned oldcsr;
 1649 
 1650     oldcsr = LN_RDCSR(sc);
 1651     oldcsr &= ~LN_CSR0_ENABINTR;
 1652     LN_WRCSR(sc, oldcsr);
 1653     LN_WRCSR(sc, LN_CSR0_ENABINTR);
 1654 
 1655     if (oldcsr & LN_CSR0_ERRSUM) {
 1656         if (oldcsr & LN_CSR0_MISS) {
 1657             /*
 1658              *  LN_CSR0_MISS is signaled when the LANCE receiver
 1659              *  loses a packet because it doesn't own a receive
 1660              *  descriptor. Rev. D LANCE chips, which are no
 1661              *  longer used, require a chip reset as described
 1662              *  below.
 1663              */
 1664             LN_STAT(rx_misses++);
 1665         }
 1666         if (oldcsr & LN_CSR0_MEMERROR) {
 1667             LN_STAT(memory_errors++);
 1668             if (oldcsr & (LN_CSR0_RXON|LN_CSR0_TXON)) {
 1669                 lance_init(sc);
 1670                 return;
 1671             }
 1672         }
 1673     }
 1674 
 1675     if ((oldcsr & LN_CSR0_RXINT) && lance_rx_intr(sc)) {
 1676         lance_init(sc);
 1677         return;
 1678     }
 1679 
 1680     if (oldcsr & LN_CSR0_TXINT) {
 1681         if (lance_tx_intr(sc))
 1682             lance_start(&sc->le_if);
 1683     }
 1684 
 1685     if (oldcsr == (LN_CSR0_PENDINTR|LN_CSR0_RXON|LN_CSR0_TXON))
 1686         if_printf(&sc->le_if, "lance_intr: stray interrupt\n");
 1687 }
 1688 
 1689 static int
 1690 lance_rx_intr(
 1691     le_softc_t *sc)
 1692 {
 1693     lance_ring_t *ri = &sc->lance_rxinfo;
 1694     lance_descinfo_t *eop;
 1695     ln_desc_t desc;
 1696     int ndescs, total_len, rxdescs;
 1697 
 1698     LN_STAT(rx_intrs++);
 1699 
 1700     for (rxdescs = 0;;) {
 1701         /*
 1702          * Now to try to find the end of this packet chain.
 1703          */
 1704         for (ndescs = 1, eop = ri->ri_nextin;; ndescs++) {
 1705             /*
 1706              * If we don't own this descriptor, the packet ain't
 1707              * all here so return because we are done.
 1708              */
 1709             LN_GETDESC(sc, &desc, eop->di_addr);
 1710             if (desc.d_flag & LN_DFLAG_OWNER)
 1711                 return 0;
 1712             /*
 1713              * In case we have missed a packet and gotten the
 1714              * LANCE confused, make sure we are pointing at the
 1715              * start of a packet. If we aren't, something is really
 1716              * strange so reinit the LANCE.
 1717              */
 1718             if (desc.d_flag & LN_DFLAG_RxBUFERROR) {
 1719                 LN_STAT(rx_buferror++);
 1720                 return 1;
 1721             }
 1722             if ((desc.d_flag & LN_DFLAG_SOP) && eop != ri->ri_nextin) {
 1723                 LN_STAT(rx_badsop++);
 1724                 return 1;
 1725             }
 1726             if (desc.d_flag & LN_DFLAG_EOP)
 1727                 break;
 1728             if (++eop == ri->ri_last)
 1729                 eop = ri->ri_first;
 1730         }
 1731 
 1732         total_len = (desc.d_status & LN_DSTS_RxLENMASK) - 4;
 1733         if ((desc.d_flag & LN_DFLAG_RxERRSUM) == 0) {
 1734             /*
 1735              * Valid Packet -- If the SOP is less than or equal to the EOP
 1736              * or the length is less than the receive buffer size, then the
 1737              * packet is contiguous in memory and can be copied in one shot.
 1738              * Otherwise we need to copy two segments to get the entire
 1739              * packet.
 1740              */
 1741             if (ri->ri_nextin <= eop || total_len <= ri->ri_heapend - ri->ri_nextin->di_bufaddr) {
 1742                 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
 1743                          total_len, total_len, NULL);
 1744                 LN_STAT(rx_contig++);
 1745             } else {
 1746                 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
 1747                          total_len,
 1748                          ri->ri_heapend - ri->ri_nextin->di_bufaddr,
 1749                          sc->le_membase + ri->ri_first->di_bufaddr);
 1750                 LN_STAT(rx_noncontig++);
 1751             }
 1752         } else {
 1753             /*
 1754              * If the packet is bad, increment the
 1755              * counters.
 1756              */
 1757             sc->le_if.if_ierrors++;
 1758             if (desc.d_flag & LN_DFLAG_RxBADCRC)
 1759                 LN_STAT(rx_badcrc++);
 1760             if (desc.d_flag & LN_DFLAG_RxOVERFLOW)
 1761                 LN_STAT(rx_badalign++);
 1762             if (desc.d_flag & LN_DFLAG_RxFRAMING)
 1763                 LN_STAT(rx_badframe++);
 1764         }
 1765         sc->le_if.if_ipackets++;
 1766         LN_STAT(rx_ndescs[ndescs-1]++);
 1767         rxdescs += ndescs;
 1768         while (ndescs-- > 0) {
 1769             LN_SETFLAG(sc, ri->ri_nextin->di_addr, LN_DFLAG_OWNER);
 1770             if (++ri->ri_nextin == ri->ri_last)
 1771                 ri->ri_nextin = ri->ri_first;
 1772         }
 1773     }
 1774     /* LN_STAT(rx_intr_descs[rxdescs]++); */
 1775     LN_MAXSTAT(rx_intr_hidescs, rxdescs);
 1776 
 1777     return 0;
 1778 }
 1779 
 1780 static void
 1781 lance_start(
 1782     struct ifnet *ifp)
 1783 {
 1784     le_softc_t *sc = (le_softc_t *) ifp;
 1785     struct ifqueue *ifq = &ifp->if_snd;
 1786     lance_ring_t *ri = &sc->lance_txinfo;
 1787     lance_descinfo_t *di;
 1788     ln_desc_t desc;
 1789     unsigned len, slop;
 1790     struct mbuf *m, *m0;
 1791     caddr_t bp;
 1792 
 1793     if ((ifp->if_flags & IFF_RUNNING) == 0)
 1794         return;
 1795 
 1796     for (;;) {
 1797         IF_DEQUEUE(ifq, m);
 1798         if (m == NULL)
 1799             break;
 1800 
 1801         /*
 1802          * Make the packet meets the minimum size for Ethernet.
 1803          * The slop is so that we also use an even number of longwards.
 1804          */
 1805         len = ETHERMIN + sizeof(struct ether_header);
 1806         if (m->m_pkthdr.len > len)
 1807             len = m->m_pkthdr.len;
 1808 
 1809         slop = (8 - len) & 3;
 1810         /*
 1811          * If there are no free ring entries (there must be always
 1812          * one owned by the host), or there's not enough space for
 1813          * this packet, or this packet would wrap around the end
 1814          * of LANCE RAM then wait for the transmits to empty for
 1815          * space and ring entries to become available.
 1816          */
 1817         if (ri->ri_free == 1 || len + slop > ri->ri_outsize) {
 1818             /*
 1819              * Try to see if we can free up anything off the transit ring.
 1820              */
 1821             if (lance_tx_intr(sc) > 0) {
 1822                 LN_STAT(tx_drains[0]++);
 1823                 IF_PREPEND(ifq, m);
 1824                 continue;
 1825             }
 1826             LN_STAT(tx_nospc[0]++);
 1827             break;
 1828         }
 1829 
 1830         if (len + slop > ri->ri_heapend - ri->ri_outptr) {
 1831             /*
 1832              * Since the packet won't fit in the end of the transmit
 1833              * heap, see if there is space at the beginning of the transmit
 1834              * heap.  If not, try again when there is space.
 1835              */
 1836             LN_STAT(tx_orphaned++);
 1837             slop += ri->ri_heapend - ri->ri_outptr;
 1838             if (len + slop > ri->ri_outsize) {
 1839                 LN_STAT(tx_nospc[1]++);
 1840                 break;
 1841             }
 1842             /*
 1843              * Point to the beginning of the heap
 1844              */
 1845             ri->ri_outptr = ri->ri_heap;
 1846             LN_STAT(tx_adoptions++);
 1847         }
 1848 
 1849         /*
 1850          * Initialize the descriptor (saving the buffer address,
 1851          * buffer length, and mbuf) and write the packet out
 1852          * to the board.
 1853          */
 1854         di = ri->ri_nextout;
 1855         di->di_bufaddr = ri->ri_outptr;
 1856         di->di_buflen = len + slop;
 1857         di->di_mbuf = m;
 1858         bp = sc->le_membase + di->di_bufaddr;
 1859         for (m0 = m; m0 != NULL; m0 = m0->m_next) {
 1860             LN_COPYTO(sc, mtod(m0, caddr_t), bp, m0->m_len);
 1861             bp += m0->m_len;
 1862         }
 1863         /*
 1864          * Zero out the remainder if needed (< ETHERMIN).
 1865          */
 1866         if (m->m_pkthdr.len < len)
 1867             LN_ZERO(sc, bp, len - m->m_pkthdr.len);
 1868 
 1869         /*
 1870          * Finally, copy out the descriptor and tell the
 1871          * LANCE to transmit!.
 1872          */
 1873         desc.d_buflen = 0 - len;
 1874         desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
 1875         desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
 1876         desc.d_flag = LN_DFLAG_SOP|LN_DFLAG_EOP|LN_DFLAG_OWNER;
 1877         LN_PUTDESC(sc, &desc, di->di_addr);
 1878         LN_WRCSR(sc, LN_CSR0_TXDEMAND|LN_CSR0_ENABINTR);
 1879 
 1880         /*
 1881          * Do our bookkeeping with our transmit heap.
 1882          * (if we wrap, point back to the beginning).
 1883          */
 1884         ri->ri_outptr += di->di_buflen;
 1885         ri->ri_outsize -= di->di_buflen;
 1886         LN_MAXSTAT(high_txoutptr, ri->ri_outptr);
 1887         LN_MINSTAT(low_txheapsize, ri->ri_outsize);
 1888 
 1889         if (ri->ri_outptr == ri->ri_heapend)
 1890             ri->ri_outptr = ri->ri_heap;
 1891 
 1892         ri->ri_free--;
 1893         if (++ri->ri_nextout == ri->ri_last)
 1894             ri->ri_nextout = ri->ri_first;
 1895         LN_MINSTAT(low_txfree, ri->ri_free);
 1896     }
 1897     if (m != NULL) {
 1898         ifp->if_flags |= IFF_OACTIVE;
 1899         IF_PREPEND(ifq, m);
 1900     }
 1901 }
 1902 
 1903 static int
 1904 lance_tx_intr(
 1905     le_softc_t *sc)
 1906 {
 1907     lance_ring_t *ri = &sc->lance_txinfo;
 1908     unsigned xmits;
 1909 
 1910     LN_STAT(tx_intrs++);
 1911     for (xmits = 0; ri->ri_free < ri->ri_max; ) {
 1912         ln_desc_t desc;
 1913 
 1914         LN_GETDESC(sc, &desc, ri->ri_nextin->di_addr);
 1915         if (desc.d_flag & LN_DFLAG_OWNER)
 1916             break;
 1917 
 1918         if (desc.d_flag & (LN_DFLAG_TxONECOLL|LN_DFLAG_TxMULTCOLL))
 1919             sc->le_if.if_collisions++;
 1920         if (desc.d_flag & LN_DFLAG_TxDEFERRED)
 1921             LN_STAT(tx_deferred++);
 1922         if (desc.d_flag & LN_DFLAG_TxONECOLL)
 1923             LN_STAT(tx_single_collisions++);
 1924         if (desc.d_flag & LN_DFLAG_TxMULTCOLL)
 1925             LN_STAT(tx_multiple_collisions++);
 1926 
 1927         if (desc.d_flag & LN_DFLAG_TxERRSUM) {
 1928             if (desc.d_status & (LN_DSTS_TxUNDERFLOW|LN_DSTS_TxBUFERROR|
 1929                                  LN_DSTS_TxEXCCOLL|LN_DSTS_TxLATECOLL)) {
 1930                 if (desc.d_status & LN_DSTS_TxEXCCOLL) {
 1931                     unsigned tdr;
 1932                     LN_STAT(tx_excessive_collisions++);
 1933                     if ((tdr = (desc.d_status & LN_DSTS_TxTDRMASK)) > 0) {
 1934                         tdr *= 100;
 1935                         if_printf(&sc->le_if, "lance: warning: excessive collisions: TDR %dns (%d-%dm)\n",
 1936                                tdr, (tdr*99)/1000, (tdr*117)/1000);
 1937                     }
 1938                 }
 1939                 if (desc.d_status & LN_DSTS_TxBUFERROR)
 1940                     LN_STAT(tx_buferror++);
 1941                 sc->le_if.if_oerrors++;
 1942                 if ((desc.d_status & LN_DSTS_TxLATECOLL) == 0) {
 1943                     lance_init(sc);
 1944                     return 0;
 1945                 } else {
 1946                     LN_STAT(tx_late_collisions++);
 1947                 }
 1948             }
 1949         }
 1950         m_freem(ri->ri_nextin->di_mbuf);
 1951         ri->ri_nextin->di_mbuf = NULL;
 1952         sc->le_if.if_opackets++;
 1953         ri->ri_free++;
 1954         ri->ri_outsize += ri->ri_nextin->di_buflen;
 1955         if (++ri->ri_nextin == ri->ri_last)
 1956             ri->ri_nextin = ri->ri_first;
 1957         sc->le_if.if_flags &= ~IFF_OACTIVE;
 1958         xmits++;
 1959     }
 1960     if (ri->ri_free == ri->ri_max)
 1961         LN_STAT(tx_emptied++);
 1962     /* LN_STAT(tx_intr_descs[xmits]++); */
 1963     LN_MAXSTAT(tx_intr_hidescs, xmits);
 1964     return xmits;
 1965 }
 1966 #endif /* !defined(LE_NOLANCE) */

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