FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/if_le.c
1 /*-
2 * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com)
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software without specific prior written permission
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 *
24 * $FreeBSD: releng/5.1/sys/i386/isa/if_le.c 113547 2003-04-16 06:27:39Z mdodd $
25 */
26
27 /*
28 * DEC EtherWORKS 2 Ethernet Controllers
29 * DEC EtherWORKS 3 Ethernet Controllers
30 *
31 * Written by Matt Thomas
32 * BPF support code stolen directly from if_ec.c
33 *
34 * This driver supports the DEPCA, DE100, DE101, DE200, DE201,
35 * DE2002, DE203, DE204, DE205, and DE422 cards.
36 */
37
38 #include "le.h"
39 #include "opt_inet.h"
40 #include "opt_ipx.h"
41
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/mbuf.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/malloc.h>
49 #include <sys/bus.h>
50
51 #include <net/ethernet.h>
52 #include <net/if.h>
53 #include <net/if_types.h>
54 #include <net/if_dl.h>
55
56 #include <netinet/in.h>
57 #include <netinet/if_ether.h>
58
59
60
61 #include <i386/isa/isa_device.h>
62 #include <i386/isa/icu.h>
63
64 #include <vm/vm.h>
65 #include <vm/pmap.h>
66
67 #include <net/bpf.h>
68
69 #ifndef COMPAT_OLDISA
70 #error "The le device requires the old isa compatibility shims"
71 #endif
72
73 /* Forward declarations */
74 typedef struct le_softc le_softc_t;
75 typedef struct le_board le_board_t;
76
77 typedef u_short le_mcbits_t;
78 #define LE_MC_NBPW_LOG2 4
79 #define LE_MC_NBPW (1 << LE_MC_NBPW_LOG2)
80
81 #if !defined(LE_NOLEMAC)
82 /*
83 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
84 *
85 * Start of DEC EtherWORKS III (LEMAC) dependent structures
86 *
87 */
88 #include <i386/isa/ic/lemac.h> /* Include LEMAC definitions */
89
90 static int lemac_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
91
92 struct le_lemac_info {
93 u_int lemac__lastpage; /* last 2K page */
94 u_int lemac__memmode; /* Are we in 2K, 32K, or 64K mode */
95 u_int lemac__membase; /* Physical address of start of RAM */
96 u_int lemac__txctl; /* Transmit Control Byte */
97 u_int lemac__txmax; /* Maximum # of outstanding transmits */
98 le_mcbits_t lemac__mctbl[LEMAC_MCTBL_SIZE/sizeof(le_mcbits_t)];
99 /* local copy of multicast table */
100 u_char lemac__eeprom[LEMAC_EEP_SIZE]; /* local copy eeprom */
101 char lemac__prodname[LEMAC_EEP_PRDNMSZ+1]; /* prodname name */
102 #define lemac_lastpage le_un.un_lemac.lemac__lastpage
103 #define lemac_memmode le_un.un_lemac.lemac__memmode
104 #define lemac_membase le_un.un_lemac.lemac__membase
105 #define lemac_txctl le_un.un_lemac.lemac__txctl
106 #define lemac_txmax le_un.un_lemac.lemac__txmax
107 #define lemac_mctbl le_un.un_lemac.lemac__mctbl
108 #define lemac_eeprom le_un.un_lemac.lemac__eeprom
109 #define lemac_prodname le_un.un_lemac.lemac__prodname
110 };
111 #endif /* !defined(LE_NOLEMAC) */
112
113 #if !defined(LE_NOLANCE)
114 /*
115 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
116 *
117 * Start of DEC EtherWORKS II (LANCE) dependent structures
118 *
119 */
120
121 #include <i386/isa/ic/am7990.h>
122
123 #ifndef LN_DOSTATS
124 #define LN_DOSTATS 1
125 #endif
126
127 static int depca_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
128
129 typedef struct lance_descinfo lance_descinfo_t;
130 typedef struct lance_ring lance_ring_t;
131
132 typedef unsigned lance_addr_t;
133
134 struct lance_descinfo {
135 caddr_t di_addr; /* address of descriptor */
136 lance_addr_t di_bufaddr; /* LANCE address of buffer owned by descriptor */
137 unsigned di_buflen; /* size of buffer owned by descriptor */
138 struct mbuf *di_mbuf; /* mbuf being transmitted/received */
139 };
140
141 struct lance_ring {
142 lance_descinfo_t *ri_first; /* Pointer to first descriptor in ring */
143 lance_descinfo_t *ri_last; /* Pointer to last + 1 descriptor in ring */
144 lance_descinfo_t *ri_nextin; /* Pointer to next one to be given to HOST */
145 lance_descinfo_t *ri_nextout; /* Pointer to next one to be given to LANCE */
146 unsigned ri_max; /* Size of Ring - 1 */
147 unsigned ri_free; /* Number of free rings entires (owned by HOST) */
148 lance_addr_t ri_heap; /* Start of RAM for this ring */
149 lance_addr_t ri_heapend; /* End + 1 of RAM for this ring */
150 lance_addr_t ri_outptr; /* Pointer to first output byte */
151 unsigned ri_outsize; /* Space remaining for output */
152 };
153
154 struct le_lance_info {
155 unsigned lance__csr1; /* LANCE Address of init block (low 16) */
156 unsigned lance__csr2; /* LANCE Address of init block (high 8) */
157 unsigned lance__csr3; /* Copy of CSR3 */
158 unsigned lance__rap; /* IO Port Offset of RAP */
159 unsigned lance__rdp; /* IO Port Offset of RDP */
160 unsigned lance__ramoffset; /* Offset to valid LANCE RAM */
161 unsigned lance__ramsize; /* Amount of RAM shared by LANCE */
162 unsigned lance__rxbufsize; /* Size of a receive buffer */
163 ln_initb_t lance__initb; /* local copy of LANCE initblock */
164 ln_initb_t *lance__raminitb; /* copy to board's LANCE initblock (debugging) */
165 ln_desc_t *lance__ramdesc; /* copy to board's LANCE descriptors (debugging) */
166 lance_ring_t lance__rxinfo; /* Receive ring information */
167 lance_ring_t lance__txinfo; /* Transmit ring information */
168 #define lance_csr1 le_un.un_lance.lance__csr1
169 #define lance_csr2 le_un.un_lance.lance__csr2
170 #define lance_csr3 le_un.un_lance.lance__csr3
171 #define lance_rap le_un.un_lance.lance__rap
172 #define lance_rdp le_un.un_lance.lance__rdp
173 #define lance_ramoffset le_un.un_lance.lance__ramoffset
174 #define lance_ramsize le_un.un_lance.lance__ramsize
175 #define lance_rxbufsize le_un.un_lance.lance__rxbufsize
176 #define lance_initb le_un.un_lance.lance__initb
177 #define lance_raminitb le_un.un_lance.lance__raminitb
178 #define lance_ramdesc le_un.un_lance.lance__ramdesc
179 #define lance_rxinfo le_un.un_lance.lance__rxinfo
180 #define lance_txinfo le_un.un_lance.lance__txinfo
181 };
182 #endif /* !defined(LE_NOLANCE) */
183
184 /*
185 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
186 *
187 * Start of Common Code
188 *
189 */
190
191 static void (*le_intrvec[NLE])(le_softc_t *sc);
192
193 /*
194 * Ethernet status, per interface.
195 */
196 struct le_softc {
197 struct arpcom le_ac; /* Common Ethernet/ARP Structure */
198 void (*if_init)(void *);/* Interface init routine */
199 void (*if_reset)(le_softc_t *);/* Interface reset routine */
200 caddr_t le_membase; /* Starting memory address (virtual) */
201 unsigned le_iobase; /* Starting I/O base address */
202 unsigned le_irq; /* Interrupt Request Value */
203 unsigned le_flags; /* local copy of if_flags */
204 #define LE_BRDCSTONLY 0x01000000 /* If only broadcast is enabled */
205 u_int le_mcmask; /* bit mask for CRC-32 for multicast hash */
206 le_mcbits_t *le_mctbl; /* pointer to multicast table */
207 const char *le_prodname; /* product name DE20x-xx */
208 u_char le_hwaddr[6]; /* local copy of hwaddr */
209 union {
210 #if !defined(LE_NOLEMAC)
211 struct le_lemac_info un_lemac; /* LEMAC specific information */
212 #endif
213 #if !defined(LE_NOLANCE)
214 struct le_lance_info un_lance; /* Am7990 specific information */
215 #endif
216 } le_un;
217 };
218 #define le_if le_ac.ac_if
219
220
221 static int le_probe(struct isa_device *dvp);
222 static int le_attach(struct isa_device *dvp);
223 static ointhand2_t le_intr;
224 static int le_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
225 static void le_input(le_softc_t *sc, caddr_t seg1, size_t total_len,
226 size_t len2, caddr_t seg2);
227 static void le_multi_filter(le_softc_t *sc);
228 static void le_multi_op(le_softc_t *sc, const u_char *mca, int oper_flg);
229 static int le_read_macaddr(le_softc_t *sc, int ioreg, int skippat);
230
231 #define LE_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian */
232
233 struct le_board {
234 int (*bd_probe)(le_softc_t *sc, const le_board_t *bd, int *msize);
235 };
236
237
238 static le_softc_t le_softc[NLE];
239
240 static const le_board_t le_boards[] = {
241 #if !defined(LE_NOLEMAC)
242 { lemac_probe }, /* DE20[345] */
243 #endif
244 #if !defined(LE_NOLANCE)
245 { depca_probe }, /* DE{20[012],422} */
246 #endif
247 { NULL } /* Must Be Last! */
248 };
249
250 /*
251 * This tells the autoconf code how to set us up.
252 */
253 struct isa_driver ledriver = {
254 INTR_TYPE_NET,
255 le_probe,
256 le_attach,
257 "le",
258 };
259 COMPAT_ISA_DRIVER(le, ledriver);
260
261 static unsigned le_intrs[NLE];
262
263 #define LE_ADDREQUAL(a1, a2) \
264 (((u_short *)a1)[0] == ((u_short *)a2)[0] \
265 || ((u_short *)a1)[1] == ((u_short *)a2)[1] \
266 || ((u_short *)a1)[2] == ((u_short *)a2)[2])
267 #define LE_ADDRBRDCST(a1) \
268 (((u_short *)a1)[0] == 0xFFFFU \
269 || ((u_short *)a1)[1] == 0xFFFFU \
270 || ((u_short *)a1)[2] == 0xFFFFU)
271
272 #define LE_INL(sc, reg) \
273 ({ u_int data; \
274 __asm __volatile("inl %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
275 data; })
276
277
278 #define LE_OUTL(sc, reg, data) \
279 ({__asm __volatile("outl %0, %1"::"a" ((u_int)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
280
281 #define LE_INW(sc, reg) \
282 ({ u_short data; \
283 __asm __volatile("inw %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
284 data; })
285
286
287 #define LE_OUTW(sc, reg, data) \
288 ({__asm __volatile("outw %0, %1"::"a" ((u_short)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
289
290 #define LE_INB(sc, reg) \
291 ({ u_char data; \
292 __asm __volatile("inb %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
293 data; })
294
295
296 #define LE_OUTB(sc, reg, data) \
297 ({__asm __volatile("outb %0, %1"::"a" ((u_char)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
298
299 #define MEMCPY(to, from, len) bcopy(from, to, len)
300 #define MEMSET(where, what, howmuch) bzero(where, howmuch)
301 #define MEMCMP(l, r, len) bcmp(l, r, len)
302
303
304 static int
305 le_probe(
306 struct isa_device *dvp)
307 {
308 le_softc_t *sc = &le_softc[dvp->id_unit];
309 const le_board_t *bd;
310 int iospace;
311
312 if (dvp->id_unit >= NLE) {
313 printf("%s%d not configured -- too many devices\n",
314 ledriver.name, dvp->id_unit);
315 return 0;
316 }
317
318 sc->le_iobase = dvp->id_iobase;
319 sc->le_membase = (u_char *) dvp->id_maddr;
320 sc->le_irq = dvp->id_irq;
321 sc->le_if.if_name = (char *)(uintptr_t)(const void *)ledriver.name;
322 sc->le_if.if_unit = dvp->id_unit;
323
324 /*
325 * Find and Initialize board..
326 */
327
328 sc->le_flags &= ~(IFF_UP|IFF_ALLMULTI);
329
330 for (bd = le_boards; bd->bd_probe != NULL; bd++) {
331 if ((iospace = (*bd->bd_probe)(sc, bd, &dvp->id_msize)) != 0) {
332 return iospace;
333 }
334 }
335
336 return 0;
337 }
338
339 static int
340 le_attach(
341 struct isa_device *dvp)
342 {
343 le_softc_t *sc = &le_softc[dvp->id_unit];
344 struct ifnet *ifp = &sc->le_if;
345
346 dvp->id_ointr = le_intr;
347 ifp->if_softc = sc;
348 ifp->if_unit = dvp->id_unit;
349 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
350 ifp->if_ioctl = le_ioctl;
351 ifp->if_init = sc->if_init;
352 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
353
354 if_printf(ifp, "%s ethernet address %6D\n",
355 sc->le_prodname,
356 sc->le_ac.ac_enaddr, ":");
357
358 ether_ifattach(ifp, sc->le_ac.ac_enaddr);
359
360 return 1;
361 }
362
363 static void
364 le_intr(
365 int unit)
366 {
367 int s = splimp();
368
369 le_intrs[unit]++;
370 (*le_intrvec[unit])(&le_softc[unit]);
371
372 splx(s);
373 }
374
375 #define LE_XTRA 0
376
377 static void
378 le_input(
379 le_softc_t *sc,
380 caddr_t seg1,
381 size_t total_len,
382 size_t len1,
383 caddr_t seg2)
384 {
385 struct ifnet *ifp = &sc->le_if;
386 struct mbuf *m;
387
388 MGETHDR(m, M_DONTWAIT, MT_DATA);
389 if (m == NULL) {
390 ifp->if_ierrors++;
391 return;
392 }
393 m->m_pkthdr.len = total_len;
394 m->m_pkthdr.rcvif = ifp;
395 if (total_len + LE_XTRA > MHLEN /* >= MINCLSIZE */) {
396 MCLGET(m, M_DONTWAIT);
397 if ((m->m_flags & M_EXT) == 0) {
398 m_free(m);
399 ifp->if_ierrors++;
400 return;
401 }
402 } else if (total_len + LE_XTRA > MHLEN && MINCLSIZE == (MHLEN+MLEN)) {
403 MGET(m->m_next, M_DONTWAIT, MT_DATA);
404 if (m->m_next == NULL) {
405 m_free(m);
406 ifp->if_ierrors++;
407 return;
408 }
409 m->m_next->m_len = total_len - MHLEN - LE_XTRA;
410 len1 = total_len = MHLEN - LE_XTRA;
411 MEMCPY(mtod(m->m_next, caddr_t), &seg1[MHLEN-LE_XTRA], m->m_next->m_len);
412 } else if (total_len + LE_XTRA > MHLEN) {
413 panic("le_input: pkt of unknown length");
414 }
415 m->m_data += LE_XTRA;
416 m->m_len = total_len;
417 MEMCPY(mtod(m, caddr_t), seg1, len1);
418 if (seg2 != NULL)
419 MEMCPY(mtod(m, caddr_t) + len1, seg2, total_len - len1);
420
421 (*ifp->if_input)(ifp, m);
422 }
423
424 static int
425 le_ioctl(
426 struct ifnet *ifp,
427 u_long cmd,
428 caddr_t data)
429 {
430 le_softc_t *sc = ifp->if_softc;
431 int s, error = 0;
432
433 if ((sc->le_flags & IFF_UP) == 0)
434 return EIO;
435
436 s = splimp();
437
438 switch (cmd) {
439 case SIOCSIFFLAGS: {
440 sc->if_init(sc);
441 break;
442 }
443
444 case SIOCADDMULTI:
445 case SIOCDELMULTI:
446 /*
447 * Update multicast listeners
448 */
449 sc->if_init(sc);
450 error = 0;
451 break;
452
453 default: {
454 error = ether_ioctl(ifp, cmd, data);
455 break;
456 }
457 }
458
459 splx(s);
460 return error;
461 }
462
463 /*
464 * This is the standard method of reading the DEC Address ROMS.
465 * I don't understand it but it does work.
466 */
467 static int
468 le_read_macaddr(
469 le_softc_t *sc,
470 int ioreg,
471 int skippat)
472 {
473 int cksum, rom_cksum;
474
475 if (!skippat) {
476 int idx, idx2, found, octet;
477 static u_char testpat[] = { 0xFF, 0, 0x55, 0xAA, 0xFF, 0, 0x55, 0xAA };
478 idx2 = found = 0;
479
480 for (idx = 0; idx < 32; idx++) {
481 octet = LE_INB(sc, ioreg);
482
483 if (octet == testpat[idx2]) {
484 if (++idx2 == sizeof testpat) {
485 ++found;
486 break;
487 }
488 } else {
489 idx2 = 0;
490 }
491 }
492
493 if (!found)
494 return -1;
495 }
496
497 cksum = 0;
498 sc->le_hwaddr[0] = LE_INB(sc, ioreg);
499 sc->le_hwaddr[1] = LE_INB(sc, ioreg);
500
501 cksum = *(u_short *) &sc->le_hwaddr[0];
502
503 sc->le_hwaddr[2] = LE_INB(sc, ioreg);
504 sc->le_hwaddr[3] = LE_INB(sc, ioreg);
505 cksum *= 2;
506 if (cksum > 65535) cksum -= 65535;
507 cksum += *(u_short *) &sc->le_hwaddr[2];
508 if (cksum > 65535) cksum -= 65535;
509
510 sc->le_hwaddr[4] = LE_INB(sc, ioreg);
511 sc->le_hwaddr[5] = LE_INB(sc, ioreg);
512 cksum *= 2;
513 if (cksum > 65535) cksum -= 65535;
514 cksum += *(u_short *) &sc->le_hwaddr[4];
515 if (cksum >= 65535) cksum -= 65535;
516
517 rom_cksum = LE_INB(sc, ioreg);
518 rom_cksum |= LE_INB(sc, ioreg) << 8;
519
520 if (cksum != rom_cksum)
521 return -1;
522 return 0;
523 }
524
525 static void
526 le_multi_filter(
527 le_softc_t *sc)
528 {
529 struct ifmultiaddr *ifma;
530
531 MEMSET(sc->le_mctbl, 0, (sc->le_mcmask + 1) / 8);
532
533 if (sc->le_if.if_flags & IFF_ALLMULTI) {
534 sc->le_flags |= IFF_MULTICAST|IFF_ALLMULTI;
535 return;
536 }
537 sc->le_flags &= ~IFF_MULTICAST;
538 /* if (interface has had an address assigned) { */
539 le_multi_op(sc, sc->le_if.if_broadcastaddr, TRUE);
540 sc->le_flags |= LE_BRDCSTONLY|IFF_MULTICAST;
541 /* } */
542
543 sc->le_flags |= IFF_MULTICAST;
544
545 TAILQ_FOREACH(ifma, &sc->le_ac.ac_if.if_multiaddrs, ifma_link) {
546 if (ifma->ifma_addr->sa_family != AF_LINK)
547 continue;
548
549 le_multi_op(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1);
550 sc->le_flags &= ~LE_BRDCSTONLY;
551 }
552 }
553
554 static void
555 le_multi_op(
556 le_softc_t *sc,
557 const u_char *mca,
558 int enable)
559 {
560 u_int idx, bit, data, crc = 0xFFFFFFFFUL;
561
562 #ifdef __alpha
563 for (data = *(__unaligned u_long *) mca, bit = 0; bit < 48; bit++, data >>=
564 1)
565 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
566 #else
567 for (idx = 0; idx < 6; idx++)
568 for (data = *mca++, bit = 0; bit < 8; bit++, data >>= 1)
569 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
570 #endif
571 /*
572 * The following two line convert the N bit index into a longword index
573 * and a longword mask.
574 */
575 crc &= sc->le_mcmask;
576 bit = 1 << (crc & (LE_MC_NBPW -1));
577 idx = crc >> (LE_MC_NBPW_LOG2);
578
579 /*
580 * Set or clear hash filter bit in our table.
581 */
582 if (enable) {
583 sc->le_mctbl[idx] |= bit; /* Set Bit */
584 } else {
585 sc->le_mctbl[idx] &= ~bit; /* Clear Bit */
586 }
587 }
588
589 #if !defined(LE_NOLEMAC)
590 /*
591 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
592 *
593 * Start of DEC EtherWORKS III (LEMAC) dependent code
594 *
595 */
596
597 #define LEMAC_INTR_ENABLE(sc) \
598 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_ALL)
599
600 #define LEMAC_INTR_DISABLE(sc) \
601 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ~LEMAC_IC_ALL)
602
603 #define LEMAC_64K_MODE(mbase) (((mbase) >= 0x0A) && ((mbase) <= 0x0F))
604 #define LEMAC_32K_MODE(mbase) (((mbase) >= 0x14) && ((mbase) <= 0x1F))
605 #define LEMAC_2K_MODE(mbase) ( (mbase) >= 0x40)
606
607 static void lemac_init(void *);
608 static void lemac_start(struct ifnet *ifp);
609 static void lemac_reset(le_softc_t *sc);
610 static void lemac_intr(le_softc_t *sc);
611 static void lemac_rne_intr(le_softc_t *sc);
612 static void lemac_tne_intr(le_softc_t *sc);
613 static void lemac_txd_intr(le_softc_t *sc, unsigned cs_value);
614 static void lemac_rxd_intr(le_softc_t *sc, unsigned cs_value);
615 static int lemac_read_eeprom(le_softc_t *sc);
616 static void lemac_init_adapmem(le_softc_t *sc);
617
618 #define LE_MCBITS_ALL_1S ((le_mcbits_t)~(le_mcbits_t)0)
619
620 static const le_mcbits_t lemac_allmulti_mctbl[16] = {
621 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
622 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
623 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
624 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
625 };
626 /*
627 * An IRQ mapping table. Less space than switch statement.
628 */
629 static const int lemac_irqs[] = { IRQ5, IRQ10, IRQ11, IRQ15 };
630
631 /*
632 * Some tuning/monitoring variables.
633 */
634 static unsigned lemac_deftxmax = 16; /* see lemac_max above */
635 static unsigned lemac_txnospc = 0; /* total # of tranmit starvations */
636
637 static unsigned lemac_tne_intrs = 0; /* total # of tranmit done intrs */
638 static unsigned lemac_rne_intrs = 0; /* total # of receive done intrs */
639 static unsigned lemac_txd_intrs = 0; /* total # of tranmit error intrs */
640 static unsigned lemac_rxd_intrs = 0; /* total # of receive error intrs */
641
642
643 static int
644 lemac_probe(
645 le_softc_t *sc,
646 const le_board_t *bd,
647 int *msize)
648 {
649 int irq, portval;
650
651 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
652 DELAY(LEMAC_EEP_DELAY);
653
654 /*
655 * Read Ethernet address if card is present.
656 */
657 if (le_read_macaddr(sc, LEMAC_REG_APD, 0) < 0)
658 return 0;
659
660 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
661 /*
662 * Clear interrupts and set IRQ.
663 */
664
665 portval = LE_INB(sc, LEMAC_REG_IC) & LEMAC_IC_IRQMSK;
666 irq = lemac_irqs[portval >> 5];
667 LE_OUTB(sc, LEMAC_REG_IC, portval);
668
669 /*
670 * Make sure settings match.
671 */
672
673 if (irq != sc->le_irq) {
674 if_printf(&sc->le_if,
675 "lemac configuration error: expected IRQ 0x%x actual 0x%x\n",
676 sc->le_irq, irq);
677 return 0;
678 }
679
680 /*
681 * Try to reset the unit
682 */
683 sc->if_init = lemac_init;
684 sc->le_if.if_start = lemac_start;
685 sc->if_reset = lemac_reset;
686 sc->lemac_memmode = 2;
687 sc->if_reset(sc);
688 if ((sc->le_flags & IFF_UP) == 0)
689 return 0;
690
691 /*
692 * Check for correct memory base configuration.
693 */
694 if (vtophys(sc->le_membase) != sc->lemac_membase) {
695 if_printf(&sc->le_if,
696 "lemac configuration error: expected iomem 0x%x actual 0x%x\n",
697 vtophys(sc->le_membase), sc->lemac_membase);
698 return 0;
699 }
700
701 sc->le_prodname = sc->lemac_prodname;
702 sc->le_mctbl = sc->lemac_mctbl;
703 sc->le_mcmask = (1 << LEMAC_MCTBL_BITS) - 1;
704 sc->lemac_txmax = lemac_deftxmax;
705 *msize = 2048;
706 le_intrvec[sc->le_if.if_unit] = lemac_intr;
707
708 return LEMAC_IOSPACE;
709 }
710
711 /*
712 * Do a hard reset of the board;
713 */
714 static void
715 lemac_reset(
716 le_softc_t *sc)
717 {
718 int portval, cksum;
719
720 /*
721 * Initialize board..
722 */
723
724 sc->le_flags &= IFF_UP;
725 sc->le_if.if_flags &= ~IFF_OACTIVE;
726 LEMAC_INTR_DISABLE(sc);
727
728 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
729 DELAY(LEMAC_EEP_DELAY);
730
731 /* Disable Interrupts */
732 /* LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ICR_IRQ_SEL); */
733
734 /*
735 * Read EEPROM information. NOTE - the placement of this function
736 * is important because functions hereafter may rely on information
737 * read from the EEPROM.
738 */
739 if ((cksum = lemac_read_eeprom(sc)) != LEMAC_EEP_CKSUM) {
740 if_printf(&sc->le_if, "reset: EEPROM checksum failed (0x%x)\n", cksum);
741 return;
742 }
743
744 /*
745 * Force to 2K mode if not already configured.
746 */
747
748 portval = LE_INB(sc, LEMAC_REG_MBR);
749 if (!LEMAC_2K_MODE(portval)) {
750 if (LEMAC_64K_MODE(portval)) {
751 portval = (((portval * 2) & 0xF) << 4);
752 sc->lemac_memmode = 64;
753 } else if (LEMAC_32K_MODE(portval)) {
754 portval = ((portval & 0xF) << 4);
755 sc->lemac_memmode = 32;
756 }
757 LE_OUTB(sc, LEMAC_REG_MBR, portval);
758 }
759 sc->lemac_membase = portval * (2 * 1024) + (512 * 1024);
760
761 /*
762 * Initialize Free Memory Queue, Init mcast table with broadcast.
763 */
764
765 lemac_init_adapmem(sc);
766 sc->le_flags |= IFF_UP;
767 return;
768 }
769
770 static void
771 lemac_init(void *xsc)
772 {
773 le_softc_t *sc;
774 int s;
775
776 sc = (le_softc_t *)xsc;
777
778 if ((sc->le_flags & IFF_UP) == 0)
779 return;
780
781 s = splimp();
782
783 /*
784 * If the interface has the up flag
785 */
786 if (sc->le_if.if_flags & IFF_UP) {
787 int saved_cs = LE_INB(sc, LEMAC_REG_CS);
788 LE_OUTB(sc, LEMAC_REG_CS, saved_cs | (LEMAC_CS_TXD | LEMAC_CS_RXD));
789 LE_OUTB(sc, LEMAC_REG_PA0, sc->le_ac.ac_enaddr[0]);
790 LE_OUTB(sc, LEMAC_REG_PA1, sc->le_ac.ac_enaddr[1]);
791 LE_OUTB(sc, LEMAC_REG_PA2, sc->le_ac.ac_enaddr[2]);
792 LE_OUTB(sc, LEMAC_REG_PA3, sc->le_ac.ac_enaddr[3]);
793 LE_OUTB(sc, LEMAC_REG_PA4, sc->le_ac.ac_enaddr[4]);
794 LE_OUTB(sc, LEMAC_REG_PA5, sc->le_ac.ac_enaddr[5]);
795
796 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_IE);
797
798 if (sc->le_if.if_flags & IFF_PROMISC) {
799 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE | LEMAC_CS_PME);
800 } else {
801 LEMAC_INTR_DISABLE(sc);
802 le_multi_filter(sc);
803 LE_OUTB(sc, LEMAC_REG_MPN, 0);
804 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
805 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], lemac_allmulti_mctbl, sizeof(lemac_allmulti_mctbl));
806 } else {
807 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], sc->lemac_mctbl, sizeof(sc->lemac_mctbl));
808 }
809 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE);
810 }
811
812 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
813
814 LEMAC_INTR_ENABLE(sc);
815 sc->le_if.if_flags |= IFF_RUNNING;
816 } else {
817 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_RXD|LEMAC_CS_TXD);
818
819 LEMAC_INTR_DISABLE(sc);
820 sc->le_if.if_flags &= ~IFF_RUNNING;
821 }
822 splx(s);
823 }
824
825 /*
826 * What to do upon receipt of an interrupt.
827 */
828 static void
829 lemac_intr(
830 le_softc_t *sc)
831 {
832 int cs_value;
833
834 LEMAC_INTR_DISABLE(sc); /* Mask interrupts */
835
836 /*
837 * Determine cause of interrupt. Receive events take
838 * priority over Transmit.
839 */
840
841 cs_value = LE_INB(sc, LEMAC_REG_CS);
842
843 /*
844 * Check for Receive Queue not being empty.
845 * Check for Transmit Done Queue not being empty.
846 */
847
848 if (cs_value & LEMAC_CS_RNE)
849 lemac_rne_intr(sc);
850 if (cs_value & LEMAC_CS_TNE)
851 lemac_tne_intr(sc);
852
853 /*
854 * Check for Transmitter Disabled.
855 * Check for Receiver Disabled.
856 */
857
858 if (cs_value & LEMAC_CS_TXD)
859 lemac_txd_intr(sc, cs_value);
860 if (cs_value & LEMAC_CS_RXD)
861 lemac_rxd_intr(sc, cs_value);
862
863 /*
864 * Toggle LED and unmask interrupts.
865 */
866
867 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
868 LEMAC_INTR_ENABLE(sc); /* Unmask interrupts */
869 }
870
871 static void
872 lemac_rne_intr(
873 le_softc_t *sc)
874 {
875 int rxcount, rxlen, rxpg;
876 u_char *rxptr;
877
878 lemac_rne_intrs++;
879 rxcount = LE_INB(sc, LEMAC_REG_RQC);
880 while (rxcount--) {
881 rxpg = LE_INB(sc, LEMAC_REG_RQ);
882 LE_OUTB(sc, LEMAC_REG_MPN, rxpg);
883
884 rxptr = sc->le_membase;
885 sc->le_if.if_ipackets++;
886 if (*rxptr & LEMAC_RX_OK) {
887
888 /*
889 * Get receive length - subtract out checksum.
890 */
891
892 rxlen = ((*(u_int *)rxptr >> 8) & 0x7FF) - 4;
893 le_input(sc, rxptr + sizeof(u_int), rxlen, rxlen, NULL);
894 } else { /* end if (*rxptr & LEMAC_RX_OK) */
895 sc->le_if.if_ierrors++;
896 }
897 LE_OUTB(sc, LEMAC_REG_FMQ, rxpg); /* Return this page to Free Memory Queue */
898 } /* end while (recv_count--) */
899
900 return;
901 }
902
903 static void
904 lemac_rxd_intr(
905 le_softc_t *sc,
906 unsigned cs_value)
907 {
908 /*
909 * Handle CS_RXD (Receiver disabled) here.
910 *
911 * Check Free Memory Queue Count. If not equal to zero
912 * then just turn Receiver back on. If it is equal to
913 * zero then check to see if transmitter is disabled.
914 * Process transmit TXD loop once more. If all else
915 * fails then do software init (0xC0 to EEPROM Init)
916 * and rebuild Free Memory Queue.
917 */
918
919 lemac_rxd_intrs++;
920
921 /*
922 * Re-enable Receiver.
923 */
924
925 cs_value &= ~LEMAC_CS_RXD;
926 LE_OUTB(sc, LEMAC_REG_CS, cs_value);
927
928 if (LE_INB(sc, LEMAC_REG_FMC) > 0)
929 return;
930
931 if (cs_value & LEMAC_CS_TXD)
932 lemac_txd_intr(sc, cs_value);
933
934 if ((LE_INB(sc, LEMAC_REG_CS) & LEMAC_CS_RXD) == 0)
935 return;
936
937 if_printf(&sc->le_if, "fatal RXD error, attempting recovery\n");
938
939 sc->if_reset(sc);
940 if (sc->le_flags & IFF_UP) {
941 lemac_init(sc);
942 return;
943 }
944
945 /*
946 * Error during initializion. Mark card as disabled.
947 */
948 if_printf(&sc->le_if, "recovery failed -- board disabled\n");
949 return;
950 }
951
952 static void
953 lemac_start(
954 struct ifnet *ifp)
955 {
956 le_softc_t *sc = (le_softc_t *) ifp;
957 struct ifqueue *ifq = &ifp->if_snd;
958
959 if ((ifp->if_flags & IFF_RUNNING) == 0)
960 return;
961
962 LEMAC_INTR_DISABLE(sc);
963
964 while (ifq->ifq_head != NULL) {
965 struct mbuf *m;
966 int tx_pg;
967 u_int txhdr, txoff;
968
969 if (LE_INB(sc, LEMAC_REG_TQC) >= sc->lemac_txmax) {
970 ifp->if_flags |= IFF_OACTIVE;
971 break;
972 }
973
974 tx_pg = LE_INB(sc, LEMAC_REG_FMQ); /* get free memory page */
975 /*
976 * Check for good transmit page.
977 */
978 if (tx_pg == 0 || tx_pg > sc->lemac_lastpage) {
979 lemac_txnospc++;
980 ifp->if_flags |= IFF_OACTIVE;
981 break;
982 }
983
984 IF_DEQUEUE(ifq, m);
985 LE_OUTB(sc, LEMAC_REG_MPN, tx_pg); /* Shift 2K window. */
986
987 /*
988 * The first four bytes of each transmit buffer are for
989 * control information. The first byte is the control
990 * byte, then the length (why not word aligned?), then
991 * the off to the buffer.
992 */
993
994 txoff = (mtod(m, u_int) & (sizeof(u_long) - 1)) + LEMAC_TX_HDRSZ;
995 txhdr = sc->lemac_txctl | (m->m_pkthdr.len << 8) | (txoff << 24);
996 *(u_int *) sc->le_membase = txhdr;
997
998 /*
999 * Copy the packet to the board
1000 */
1001
1002 m_copydata(m, 0, m->m_pkthdr.len, sc->le_membase + txoff);
1003
1004 LE_OUTB(sc, LEMAC_REG_TQ, tx_pg); /* tell chip to transmit this packet */
1005
1006 BPF_MTAP(&sc->le_if, m);
1007
1008 m_freem(m); /* free the mbuf */
1009 }
1010 LEMAC_INTR_ENABLE(sc);
1011 }
1012
1013 static void
1014 lemac_tne_intr(
1015 le_softc_t *sc)
1016 {
1017 int txsts, txcount = LE_INB(sc, LEMAC_REG_TDC);
1018
1019 lemac_tne_intrs++;
1020 while (txcount--) {
1021 txsts = LE_INB(sc, LEMAC_REG_TDQ);
1022 sc->le_if.if_opackets++; /* another one done */
1023 if ((txsts & LEMAC_TDQ_COL) != LEMAC_TDQ_NOCOL)
1024 sc->le_if.if_collisions++;
1025 }
1026 sc->le_if.if_flags &= ~IFF_OACTIVE;
1027 lemac_start(&sc->le_if);
1028 }
1029
1030 static void
1031 lemac_txd_intr(
1032 le_softc_t *sc,
1033 unsigned cs_value)
1034 {
1035 /*
1036 * Read transmit status, remove transmit buffer from
1037 * transmit queue and place on free memory queue,
1038 * then reset transmitter.
1039 * Increment appropriate counters.
1040 */
1041
1042 lemac_txd_intrs++;
1043 sc->le_if.if_oerrors++;
1044 if (LE_INB(sc, LEMAC_REG_TS) & LEMAC_TS_ECL)
1045 sc->le_if.if_collisions++;
1046 sc->le_if.if_flags &= ~IFF_OACTIVE;
1047
1048 LE_OUTB(sc, LEMAC_REG_FMQ, LE_INB(sc, LEMAC_REG_TQ));
1049 /* Get Page number and write it back out */
1050
1051 LE_OUTB(sc, LEMAC_REG_CS, cs_value & ~LEMAC_CS_TXD);
1052 /* Turn back on transmitter */
1053 return;
1054 }
1055
1056 static int
1057 lemac_read_eeprom(
1058 le_softc_t *sc)
1059 {
1060 int word_off, cksum;
1061
1062 u_char *ep;
1063
1064 cksum = 0;
1065 ep = sc->lemac_eeprom;
1066 for (word_off = 0; word_off < LEMAC_EEP_SIZE / 2; word_off++) {
1067 LE_OUTB(sc, LEMAC_REG_PI1, word_off);
1068 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEREAD);
1069
1070 DELAY(LEMAC_EEP_DELAY);
1071
1072 *ep = LE_INB(sc, LEMAC_REG_EE1); cksum += *ep++;
1073 *ep = LE_INB(sc, LEMAC_REG_EE2); cksum += *ep++;
1074 }
1075
1076 /*
1077 * Set up Transmit Control Byte for use later during transmit.
1078 */
1079
1080 sc->lemac_txctl |= LEMAC_TX_FLAGS;
1081
1082 if ((sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_SQE) == 0)
1083 sc->lemac_txctl &= ~LEMAC_TX_SQE;
1084
1085 if (sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_LAB)
1086 sc->lemac_txctl |= LEMAC_TX_LAB;
1087
1088 MEMCPY(sc->lemac_prodname, &sc->lemac_eeprom[LEMAC_EEP_PRDNM], LEMAC_EEP_PRDNMSZ);
1089 sc->lemac_prodname[LEMAC_EEP_PRDNMSZ] = '\0';
1090
1091 return cksum % 256;
1092 }
1093
1094 static void
1095 lemac_init_adapmem(
1096 le_softc_t *sc)
1097 {
1098 int pg, conf;
1099
1100 conf = LE_INB(sc, LEMAC_REG_CNF);
1101
1102 if ((sc->lemac_eeprom[LEMAC_EEP_SETUP] & LEMAC_EEP_ST_DRAM) == 0) {
1103 sc->lemac_lastpage = 63;
1104 conf &= ~LEMAC_CNF_DRAM;
1105 } else {
1106 sc->lemac_lastpage = 127;
1107 conf |= LEMAC_CNF_DRAM;
1108 }
1109
1110 LE_OUTB(sc, LEMAC_REG_CNF, conf);
1111
1112 for (pg = 1; pg <= sc->lemac_lastpage; pg++)
1113 LE_OUTB(sc, LEMAC_REG_FMQ, pg);
1114
1115 return;
1116 }
1117 #endif /* !defined(LE_NOLEMAC) */
1118
1119 #if !defined(LE_NOLANCE)
1120 /*
1121 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1122 *
1123 * Start of DEPCA (DE200/DE201/DE202/DE422 etal) support.
1124 *
1125 */
1126 static void depca_intr(le_softc_t *sc);
1127 static int lance_init_adapmem(le_softc_t *sc);
1128 static int lance_init_ring(le_softc_t *sc, ln_ring_t *rp, lance_ring_t *ri,
1129 unsigned ndescs, unsigned bufoffset,
1130 unsigned descoffset);
1131 static void lance_init(void *);
1132 static void lance_reset(le_softc_t *sc);
1133 static void lance_intr(le_softc_t *sc);
1134 static int lance_rx_intr(le_softc_t *sc);
1135 static void lance_start(struct ifnet *ifp);
1136 static int lance_tx_intr(le_softc_t *sc);
1137
1138 #define LN_BUFSIZE /* 380 */ 304 /* 1520 / 4 */
1139 #define LN_TXDESC_RATIO 2048
1140 #define LN_DESC_MAX 128
1141
1142 #if LN_DOSTATS
1143 static struct {
1144 unsigned lance_rx_misses;
1145 unsigned lance_rx_badcrc;
1146 unsigned lance_rx_badalign;
1147 unsigned lance_rx_badframe;
1148 unsigned lance_rx_buferror;
1149 unsigned lance_tx_deferred;
1150 unsigned lance_tx_single_collisions;
1151 unsigned lance_tx_multiple_collisions;
1152 unsigned lance_tx_excessive_collisions;
1153 unsigned lance_tx_late_collisions;
1154
1155 unsigned lance_memory_errors;
1156 unsigned lance_inits;
1157 unsigned lance_tx_intrs;
1158 unsigned lance_tx_nospc[2];
1159 unsigned lance_tx_drains[2];
1160 unsigned lance_tx_orphaned;
1161 unsigned lance_tx_adoptions;
1162 unsigned lance_tx_emptied;
1163 unsigned lance_tx_deftxint;
1164 unsigned lance_tx_buferror;
1165 unsigned lance_high_txoutptr;
1166 unsigned lance_low_txheapsize;
1167 unsigned lance_low_txfree;
1168 unsigned lance_tx_intr_hidescs;
1169 /* unsigned lance_tx_intr_descs[LN_DESC_MAX]; */
1170
1171 unsigned lance_rx_intrs;
1172 unsigned lance_rx_badsop;
1173 unsigned lance_rx_contig;
1174 unsigned lance_rx_noncontig;
1175 unsigned lance_rx_intr_hidescs;
1176 unsigned lance_rx_ndescs[4096 / LN_BUFSIZE];
1177 /* unsigned lance_rx_intr_descs[LN_DESC_MAX]; */
1178 } lance_stats;
1179
1180 #define LN_STAT(stat) (lance_stats.lance_ ## stat)
1181 #define LN_MINSTAT(stat, val) (LN_STAT(stat > (val)) ? LN_STAT(stat = (val)) : 0)
1182 #define LN_MAXSTAT(stat, val) (LN_STAT(stat < (val)) ? LN_STAT(stat = (val)) : 0)
1183
1184 #else
1185 #define LN_STAT(stat) 0
1186 #define LN_MINSTAT(stat, val) 0
1187 #define LN_MAXSTAT(stat, val) 0
1188 #endif
1189
1190 #define LN_SELCSR(sc, csrno) (LE_OUTW(sc, sc->lance_rap, csrno))
1191 #define LN_INQCSR(sc) (LE_INW(sc, sc->lance_rap))
1192
1193 #define LN_WRCSR(sc, val) (LE_OUTW(sc, sc->lance_rdp, val))
1194 #define LN_RDCSR(sc) (LE_INW(sc, sc->lance_rdp))
1195
1196
1197 #define LN_ZERO(sc, vaddr, len) bzero(vaddr, len)
1198 #define LN_COPYTO(sc, from, to, len) bcopy(from, to, len)
1199
1200 #define LN_SETFLAG(sc, vaddr, val) \
1201 (((volatile u_char *) vaddr)[3] = (val))
1202
1203 #define LN_PUTDESC(sc, desc, vaddr) \
1204 (((volatile u_short *) vaddr)[0] = ((u_short *) desc)[0], \
1205 ((volatile u_short *) vaddr)[2] = ((u_short *) desc)[2], \
1206 ((volatile u_short *) vaddr)[1] = ((u_short *) desc)[1])
1207
1208 /*
1209 * Only get the descriptor flags and length/status. All else
1210 * read-only.
1211 */
1212 #define LN_GETDESC(sc, desc, vaddr) \
1213 (((u_short *) desc)[1] = ((volatile u_short *) vaddr)[1], \
1214 ((u_short *) desc)[3] = ((volatile u_short *) vaddr)[3])
1215
1216
1217 /*
1218 * These definitions are specific to the DEC "DEPCA-style" NICs.
1219 * (DEPCA, DE10x, DE20[012], DE422)
1220 *
1221 */
1222 #define DEPCA_REG_NICSR 0 /* (RW;16) NI Control / Status */
1223 #define DEPCA_REG_RDP 4 /* (RW:16) LANCE RDP (data) register */
1224 #define DEPCA_REG_RAP 6 /* (RW:16) LANCE RAP (address) register */
1225 #define DEPCA_REG_ADDRROM 12 /* (R : 8) DEPCA Ethernet Address ROM */
1226 #define DEPCA_IOSPACE 16 /* DEPCAs use 16 bytes of IO space */
1227
1228 #define DEPCA_NICSR_LED 0x0001 /* Light the LED on the back of the DEPCA */
1229 #define DEPCA_NICSR_ENABINTR 0x0002 /* Enable Interrupts */
1230 #define DEPCA_NICSR_MASKINTR 0x0004 /* Mask Interrupts */
1231 #define DEPCA_NICSR_AAC 0x0008 /* Address Counter Clear */
1232 #define DEPCA_NICSR_REMOTEBOOT 0x0010 /* Remote Boot Enabled (ignored) */
1233 #define DEPCA_NICSR_32KRAM 0x0020 /* DEPCA LANCE RAM size 64K (C) / 32K (S) */
1234 #define DEPCA_NICSR_LOW32K 0x0040 /* Bank Select (A15 = !This Bit) */
1235 #define DEPCA_NICSR_SHE 0x0080 /* Shared RAM Enabled (ie hide ROM) */
1236 #define DEPCA_NICSR_BOOTTMO 0x0100 /* Remote Boot Timeout (ignored) */
1237
1238 #define DEPCA_RDNICSR(sc) (LE_INW(sc, DEPCA_REG_NICSR))
1239 #define DEPCA_WRNICSR(sc, val) (LE_OUTW(sc, DEPCA_REG_NICSR, val))
1240
1241 #define DEPCA_IDSTR_OFFSET 0xC006 /* ID String Offset */
1242
1243 #define DEPCA_REG_EISAID 0x80
1244 #define DEPCA_EISAID_MASK 0xf0ffffff
1245 #define DEPCA_EISAID_DE422 0x2042A310
1246
1247 typedef enum {
1248 DEPCA_CLASSIC,
1249 DEPCA_DE100, DEPCA_DE101,
1250 DEPCA_EE100,
1251 DEPCA_DE200, DEPCA_DE201, DEPCA_DE202,
1252 DEPCA_DE422,
1253 DEPCA_UNKNOWN
1254 } depca_t;
1255
1256 static const char *depca_signatures[] = {
1257 "DEPCA",
1258 "DE100", "DE101",
1259 "EE100",
1260 "DE200", "DE201", "DE202",
1261 "DE422",
1262 NULL
1263 };
1264
1265 static int
1266 depca_probe(
1267 le_softc_t *sc,
1268 const le_board_t *bd,
1269 int *msize)
1270 {
1271 unsigned nicsr, idx, idstr_offset = DEPCA_IDSTR_OFFSET;
1272
1273 /*
1274 * Find out how memory we are dealing with. Adjust
1275 * the ID string offset approriately if we are at
1276 * 32K. Make sure the ROM is enabled.
1277 */
1278 nicsr = DEPCA_RDNICSR(sc);
1279 nicsr &= ~(DEPCA_NICSR_SHE|DEPCA_NICSR_LED|DEPCA_NICSR_ENABINTR);
1280
1281 if (nicsr & DEPCA_NICSR_32KRAM) {
1282 /*
1283 * Make we are going to read the upper
1284 * 32K so we do read the ROM.
1285 */
1286 sc->lance_ramsize = 32 * 1024;
1287 nicsr &= ~DEPCA_NICSR_LOW32K;
1288 sc->lance_ramoffset = 32 * 1024;
1289 idstr_offset -= sc->lance_ramsize;
1290 } else {
1291 sc->lance_ramsize = 64 * 1024;
1292 sc->lance_ramoffset = 0;
1293 }
1294 DEPCA_WRNICSR(sc, nicsr);
1295
1296 sc->le_prodname = NULL;
1297 for (idx = 0; depca_signatures[idx] != NULL; idx++) {
1298 if (bcmp(depca_signatures[idx], sc->le_membase + idstr_offset, 5) == 0) {
1299 sc->le_prodname = depca_signatures[idx];
1300 break;
1301 }
1302 }
1303
1304 if (sc->le_prodname == NULL) {
1305 /*
1306 * Try to get the EISA device if it's a DE422.
1307 */
1308 if (sc->le_iobase > 0x1000 && (sc->le_iobase & 0x0F00) == 0x0C00
1309 && (LE_INL(sc, DEPCA_REG_EISAID) & DEPCA_EISAID_MASK)
1310 == DEPCA_EISAID_DE422) {
1311 sc->le_prodname = "DE422";
1312 } else {
1313 return 0;
1314 }
1315 }
1316 if (idx == DEPCA_CLASSIC)
1317 sc->lance_ramsize -= 16384; /* Can't use the ROM area on a DEPCA */
1318
1319 /*
1320 * Try to read the address ROM.
1321 * Stop the LANCE, reset the Address ROM Counter (AAC),
1322 * read the NICSR to "clock" in the reset, and then
1323 * re-enable the Address ROM Counter. Now read the
1324 * address ROM.
1325 */
1326 sc->lance_rdp = DEPCA_REG_RDP;
1327 sc->lance_rap = DEPCA_REG_RAP;
1328 sc->lance_csr3 = LN_CSR3_ALE;
1329 sc->le_mctbl = sc->lance_initb.ln_multi_mask;
1330 sc->le_mcmask = LN_MC_MASK;
1331 LN_SELCSR(sc, LN_CSR0);
1332 LN_WRCSR(sc, LN_CSR0_STOP);
1333
1334 if (idx < DEPCA_DE200) {
1335 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) & ~DEPCA_NICSR_AAC);
1336 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_AAC);
1337 }
1338
1339 if (le_read_macaddr(sc, DEPCA_REG_ADDRROM, idx == DEPCA_CLASSIC) < 0)
1340 return 0;
1341
1342 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
1343 /*
1344 * Renable shared RAM.
1345 */
1346 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_SHE);
1347
1348 le_intrvec[sc->le_if.if_unit] = depca_intr;
1349 if (!lance_init_adapmem(sc))
1350 return 0;
1351
1352 sc->if_reset = lance_reset;
1353 sc->if_init = lance_init;
1354 sc->le_if.if_start = lance_start;
1355 DEPCA_WRNICSR(sc, DEPCA_NICSR_SHE | DEPCA_NICSR_ENABINTR);
1356 sc->if_reset(sc);
1357
1358 LN_STAT(low_txfree = sc->lance_txinfo.ri_max);
1359 LN_STAT(low_txheapsize = 0xFFFFFFFF);
1360 *msize = sc->lance_ramsize;
1361 return DEPCA_IOSPACE;
1362 }
1363
1364 static void
1365 depca_intr(
1366 le_softc_t *sc)
1367 {
1368 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) ^ DEPCA_NICSR_LED);
1369 lance_intr(sc);
1370 }
1371
1372 /*
1373 * Here's as good a place to describe our paritioning of the
1374 * LANCE shared RAM space. (NOTE: this driver does not yet support
1375 * the concept of a LANCE being able to DMA).
1376 *
1377 * First is the 24 (00:23) bytes for LANCE Initialization Block
1378 * Next are the recieve descriptors. The number is calculated from
1379 * how many LN_BUFSIZE buffers we can allocate (this number must
1380 * be a power of 2). Next are the transmit descriptors. The amount
1381 * of transmit descriptors is derived from the size of the RAM
1382 * divided by 1K. Now come the receive buffers (one for each receive
1383 * descriptor). Finally is the transmit heap. (no fixed buffers are
1384 * allocated so as to make the most use of the limited space).
1385 */
1386 static int
1387 lance_init_adapmem(
1388 le_softc_t *sc)
1389 {
1390 lance_addr_t rxbufoffset;
1391 lance_addr_t rxdescoffset, txdescoffset;
1392 unsigned rxdescs, txdescs;
1393
1394 /*
1395 * First calculate how many descriptors we heap.
1396 * Note this assumes the ramsize is a power of two.
1397 */
1398 sc->lance_rxbufsize = LN_BUFSIZE;
1399 rxdescs = 1;
1400 while (rxdescs * sc->lance_rxbufsize < sc->lance_ramsize)
1401 rxdescs *= 2;
1402 rxdescs /= 2;
1403 if (rxdescs > LN_DESC_MAX) {
1404 sc->lance_rxbufsize *= rxdescs / LN_DESC_MAX;
1405 rxdescs = LN_DESC_MAX;
1406 }
1407 txdescs = sc->lance_ramsize / LN_TXDESC_RATIO;
1408 if (txdescs > LN_DESC_MAX)
1409 txdescs = LN_DESC_MAX;
1410
1411 /*
1412 * Now calculate where everything goes in memory
1413 */
1414 rxdescoffset = sizeof(ln_initb_t);
1415 txdescoffset = rxdescoffset + sizeof(ln_desc_t) * rxdescs;
1416 rxbufoffset = txdescoffset + sizeof(ln_desc_t) * txdescs;
1417
1418 sc->le_mctbl = (le_mcbits_t *) sc->lance_initb.ln_multi_mask;
1419 /*
1420 * Remember these for debugging.
1421 */
1422 sc->lance_raminitb = (ln_initb_t *) sc->le_membase;
1423 sc->lance_ramdesc = (ln_desc_t *) (sc->le_membase + rxdescoffset);
1424
1425 /*
1426 * Initialize the rings.
1427 */
1428 if (!lance_init_ring(sc, &sc->lance_initb.ln_rxring, &sc->lance_rxinfo,
1429 rxdescs, rxbufoffset, rxdescoffset))
1430 return 0;
1431 sc->lance_rxinfo.ri_heap = rxbufoffset;
1432 sc->lance_rxinfo.ri_heapend = rxbufoffset + sc->lance_rxbufsize * rxdescs;
1433
1434 if (!lance_init_ring(sc, &sc->lance_initb.ln_txring, &sc->lance_txinfo,
1435 txdescs, 0, txdescoffset))
1436 return 0;
1437 sc->lance_txinfo.ri_heap = sc->lance_rxinfo.ri_heapend;
1438 sc->lance_txinfo.ri_heapend = sc->lance_ramsize;
1439
1440 /*
1441 * Set CSR1 and CSR2 to the address of the init block (which
1442 * for us is always 0.
1443 */
1444 sc->lance_csr1 = LN_ADDR_LO(0 + sc->lance_ramoffset);
1445 sc->lance_csr2 = LN_ADDR_HI(0 + sc->lance_ramoffset);
1446 return 1;
1447 }
1448
1449 static int
1450 lance_init_ring(
1451 le_softc_t *sc,
1452 ln_ring_t *rp,
1453 lance_ring_t *ri,
1454 unsigned ndescs,
1455 lance_addr_t bufoffset,
1456 lance_addr_t descoffset)
1457 {
1458 lance_descinfo_t *di;
1459
1460 /*
1461 * Initialize the ring pointer in the LANCE InitBlock
1462 */
1463 rp->r_addr_lo = LN_ADDR_LO(descoffset + sc->lance_ramoffset);
1464 rp->r_addr_hi = LN_ADDR_HI(descoffset + sc->lance_ramoffset);
1465 rp->r_log2_size = ffs(ndescs) - 1;
1466
1467 /*
1468 * Allocate the ring entry descriptors and initialize
1469 * our ring information data structure. All these are
1470 * our copies and do not live in the LANCE RAM.
1471 */
1472 ri->ri_first = (lance_descinfo_t *) malloc(ndescs * sizeof(*di), M_DEVBUF, M_NOWAIT);
1473 if (ri->ri_first == NULL) {
1474 printf("lance_init_ring: malloc(%d) failed\n", ndescs * sizeof(*di));
1475 return 0;
1476 }
1477 ri->ri_free = ri->ri_max = ndescs;
1478 ri->ri_last = ri->ri_first + ri->ri_max;
1479 for (di = ri->ri_first; di < ri->ri_last; di++) {
1480 di->di_addr = sc->le_membase + descoffset;
1481 di->di_mbuf = NULL;
1482 if (bufoffset) {
1483 di->di_bufaddr = bufoffset;
1484 di->di_buflen = sc->lance_rxbufsize;
1485 bufoffset += sc->lance_rxbufsize;
1486 }
1487 descoffset += sizeof(ln_desc_t);
1488 }
1489 return 1;
1490 }
1491
1492 static void
1493 lance_dumpcsrs(
1494 le_softc_t *sc,
1495 const char *id)
1496 {
1497 if_printf(&sc->le_if, "%s: nicsr=%04x", id, DEPCA_RDNICSR(sc));
1498 LN_SELCSR(sc, LN_CSR0); printf(" csr0=%04x", LN_RDCSR(sc));
1499 LN_SELCSR(sc, LN_CSR1); printf(" csr1=%04x", LN_RDCSR(sc));
1500 LN_SELCSR(sc, LN_CSR2); printf(" csr2=%04x", LN_RDCSR(sc));
1501 LN_SELCSR(sc, LN_CSR3); printf(" csr3=%04x\n", LN_RDCSR(sc));
1502 LN_SELCSR(sc, LN_CSR0);
1503 }
1504
1505 static void
1506 lance_reset(
1507 le_softc_t *sc)
1508 {
1509 register int cnt, csr;
1510
1511 /* lance_dumpcsrs(sc, "lance_reset: start"); */
1512
1513 LN_WRCSR(sc, LN_RDCSR(sc) & ~LN_CSR0_ENABINTR);
1514 LN_WRCSR(sc, LN_CSR0_STOP);
1515 DELAY(100);
1516
1517 sc->le_flags &= ~IFF_UP;
1518 sc->le_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
1519
1520 le_multi_filter(sc); /* initialize the multicast table */
1521 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
1522 sc->lance_initb.ln_multi_mask[0] = 0xFFFFU;
1523 sc->lance_initb.ln_multi_mask[1] = 0xFFFFU;
1524 sc->lance_initb.ln_multi_mask[2] = 0xFFFFU;
1525 sc->lance_initb.ln_multi_mask[3] = 0xFFFFU;
1526 }
1527 sc->lance_initb.ln_physaddr[0] = ((u_short *) sc->le_ac.ac_enaddr)[0];
1528 sc->lance_initb.ln_physaddr[1] = ((u_short *) sc->le_ac.ac_enaddr)[1];
1529 sc->lance_initb.ln_physaddr[2] = ((u_short *) sc->le_ac.ac_enaddr)[2];
1530 if (sc->le_if.if_flags & IFF_PROMISC) {
1531 sc->lance_initb.ln_mode |= LN_MODE_PROMISC;
1532 } else {
1533 sc->lance_initb.ln_mode &= ~LN_MODE_PROMISC;
1534 }
1535 /*
1536 * We force the init block to be at the start
1537 * of the LANCE's RAM buffer.
1538 */
1539 LN_COPYTO(sc, &sc->lance_initb, sc->le_membase, sizeof(sc->lance_initb));
1540 LN_SELCSR(sc, LN_CSR1); LN_WRCSR(sc, sc->lance_csr1);
1541 LN_SELCSR(sc, LN_CSR2); LN_WRCSR(sc, sc->lance_csr2);
1542 LN_SELCSR(sc, LN_CSR3); LN_WRCSR(sc, sc->lance_csr3);
1543
1544 /* lance_dumpcsrs(sc, "lance_reset: preinit"); */
1545
1546 /*
1547 * clear INITDONE and INIT the chip
1548 */
1549 LN_SELCSR(sc, LN_CSR0);
1550 LN_WRCSR(sc, LN_CSR0_INIT|LN_CSR0_INITDONE);
1551
1552 csr = 0;
1553 cnt = 100;
1554 while (cnt-- > 0) {
1555 if (((csr = LN_RDCSR(sc)) & LN_CSR0_INITDONE) != 0)
1556 break;
1557 DELAY(10000);
1558 }
1559
1560 if ((csr & LN_CSR0_INITDONE) == 0) { /* make sure we got out okay */
1561 lance_dumpcsrs(sc, "lance_reset: reset failure");
1562 } else {
1563 /* lance_dumpcsrs(sc, "lance_reset: end"); */
1564 sc->le_if.if_flags |= IFF_UP;
1565 sc->le_flags |= IFF_UP;
1566 }
1567 }
1568
1569 static void
1570 lance_init(void *xsc)
1571 {
1572 le_softc_t *sc;
1573 lance_ring_t *ri;
1574 lance_descinfo_t *di;
1575 ln_desc_t desc;
1576
1577 sc = (le_softc_t *)xsc;
1578
1579 LN_STAT(inits++);
1580 if (sc->le_if.if_flags & IFF_RUNNING) {
1581 sc->if_reset(sc);
1582 lance_tx_intr(sc);
1583 /*
1584 * If we were running, requeue any pending transmits.
1585 */
1586 ri = &sc->lance_txinfo;
1587 di = ri->ri_nextout;
1588 while (ri->ri_free < ri->ri_max) {
1589 if (--di == ri->ri_first)
1590 di = ri->ri_nextout - 1;
1591 if (di->di_mbuf == NULL)
1592 break;
1593 IF_PREPEND(&sc->le_if.if_snd, di->di_mbuf);
1594 di->di_mbuf = NULL;
1595 ri->ri_free++;
1596 }
1597 } else {
1598 sc->if_reset(sc);
1599 }
1600
1601 /*
1602 * Reset the transmit ring. Make sure we own all the buffers.
1603 * Also reset the transmit heap.
1604 */
1605 sc->le_if.if_flags &= ~IFF_OACTIVE;
1606 ri = &sc->lance_txinfo;
1607 for (di = ri->ri_first; di < ri->ri_last; di++) {
1608 if (di->di_mbuf != NULL) {
1609 m_freem(di->di_mbuf);
1610 di->di_mbuf = NULL;
1611 }
1612 desc.d_flag = 0;
1613 desc.d_addr_lo = LN_ADDR_LO(ri->ri_heap + sc->lance_ramoffset);
1614 desc.d_addr_hi = LN_ADDR_HI(ri->ri_heap + sc->lance_ramoffset);
1615 desc.d_buflen = 0;
1616 LN_PUTDESC(sc, &desc, di->di_addr);
1617 }
1618 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1619 ri->ri_free = ri->ri_max;
1620 ri->ri_outptr = ri->ri_heap;
1621 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1622
1623 ri = &sc->lance_rxinfo;
1624 desc.d_flag = LN_DFLAG_OWNER;
1625 desc.d_buflen = 0 - sc->lance_rxbufsize;
1626 for (di = ri->ri_first; di < ri->ri_last; di++) {
1627 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1628 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1629 LN_PUTDESC(sc, &desc, di->di_addr);
1630 }
1631 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1632 ri->ri_outptr = ri->ri_heap;
1633 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1634 ri->ri_free = 0;
1635
1636 if (sc->le_if.if_flags & IFF_UP) {
1637 sc->le_if.if_flags |= IFF_RUNNING;
1638 LN_WRCSR(sc, LN_CSR0_START|LN_CSR0_INITDONE|LN_CSR0_ENABINTR);
1639 /* lance_dumpcsrs(sc, "lance_init: up"); */
1640 lance_start(&sc->le_if);
1641 } else {
1642 /* lance_dumpcsrs(sc, "lance_init: down"); */
1643 sc->le_if.if_flags &= ~IFF_RUNNING;
1644 }
1645 }
1646
1647 static void
1648 lance_intr(
1649 le_softc_t *sc)
1650 {
1651 unsigned oldcsr;
1652
1653 oldcsr = LN_RDCSR(sc);
1654 oldcsr &= ~LN_CSR0_ENABINTR;
1655 LN_WRCSR(sc, oldcsr);
1656 LN_WRCSR(sc, LN_CSR0_ENABINTR);
1657
1658 if (oldcsr & LN_CSR0_ERRSUM) {
1659 if (oldcsr & LN_CSR0_MISS) {
1660 /*
1661 * LN_CSR0_MISS is signaled when the LANCE receiver
1662 * loses a packet because it doesn't own a receive
1663 * descriptor. Rev. D LANCE chips, which are no
1664 * longer used, require a chip reset as described
1665 * below.
1666 */
1667 LN_STAT(rx_misses++);
1668 }
1669 if (oldcsr & LN_CSR0_MEMERROR) {
1670 LN_STAT(memory_errors++);
1671 if (oldcsr & (LN_CSR0_RXON|LN_CSR0_TXON)) {
1672 lance_init(sc);
1673 return;
1674 }
1675 }
1676 }
1677
1678 if ((oldcsr & LN_CSR0_RXINT) && lance_rx_intr(sc)) {
1679 lance_init(sc);
1680 return;
1681 }
1682
1683 if (oldcsr & LN_CSR0_TXINT) {
1684 if (lance_tx_intr(sc))
1685 lance_start(&sc->le_if);
1686 }
1687
1688 if (oldcsr == (LN_CSR0_PENDINTR|LN_CSR0_RXON|LN_CSR0_TXON))
1689 if_printf(&sc->le_if, "lance_intr: stray interrupt\n");
1690 }
1691
1692 static int
1693 lance_rx_intr(
1694 le_softc_t *sc)
1695 {
1696 lance_ring_t *ri = &sc->lance_rxinfo;
1697 lance_descinfo_t *eop;
1698 ln_desc_t desc;
1699 int ndescs, total_len, rxdescs;
1700
1701 LN_STAT(rx_intrs++);
1702
1703 for (rxdescs = 0;;) {
1704 /*
1705 * Now to try to find the end of this packet chain.
1706 */
1707 for (ndescs = 1, eop = ri->ri_nextin;; ndescs++) {
1708 /*
1709 * If we don't own this descriptor, the packet ain't
1710 * all here so return because we are done.
1711 */
1712 LN_GETDESC(sc, &desc, eop->di_addr);
1713 if (desc.d_flag & LN_DFLAG_OWNER)
1714 return 0;
1715 /*
1716 * In case we have missed a packet and gotten the
1717 * LANCE confused, make sure we are pointing at the
1718 * start of a packet. If we aren't, something is really
1719 * strange so reinit the LANCE.
1720 */
1721 if (desc.d_flag & LN_DFLAG_RxBUFERROR) {
1722 LN_STAT(rx_buferror++);
1723 return 1;
1724 }
1725 if ((desc.d_flag & LN_DFLAG_SOP) && eop != ri->ri_nextin) {
1726 LN_STAT(rx_badsop++);
1727 return 1;
1728 }
1729 if (desc.d_flag & LN_DFLAG_EOP)
1730 break;
1731 if (++eop == ri->ri_last)
1732 eop = ri->ri_first;
1733 }
1734
1735 total_len = (desc.d_status & LN_DSTS_RxLENMASK) - 4;
1736 if ((desc.d_flag & LN_DFLAG_RxERRSUM) == 0) {
1737 /*
1738 * Valid Packet -- If the SOP is less than or equal to the EOP
1739 * or the length is less than the receive buffer size, then the
1740 * packet is contiguous in memory and can be copied in one shot.
1741 * Otherwise we need to copy two segments to get the entire
1742 * packet.
1743 */
1744 if (ri->ri_nextin <= eop || total_len <= ri->ri_heapend - ri->ri_nextin->di_bufaddr) {
1745 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1746 total_len, total_len, NULL);
1747 LN_STAT(rx_contig++);
1748 } else {
1749 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1750 total_len,
1751 ri->ri_heapend - ri->ri_nextin->di_bufaddr,
1752 sc->le_membase + ri->ri_first->di_bufaddr);
1753 LN_STAT(rx_noncontig++);
1754 }
1755 } else {
1756 /*
1757 * If the packet is bad, increment the
1758 * counters.
1759 */
1760 sc->le_if.if_ierrors++;
1761 if (desc.d_flag & LN_DFLAG_RxBADCRC)
1762 LN_STAT(rx_badcrc++);
1763 if (desc.d_flag & LN_DFLAG_RxOVERFLOW)
1764 LN_STAT(rx_badalign++);
1765 if (desc.d_flag & LN_DFLAG_RxFRAMING)
1766 LN_STAT(rx_badframe++);
1767 }
1768 sc->le_if.if_ipackets++;
1769 LN_STAT(rx_ndescs[ndescs-1]++);
1770 rxdescs += ndescs;
1771 while (ndescs-- > 0) {
1772 LN_SETFLAG(sc, ri->ri_nextin->di_addr, LN_DFLAG_OWNER);
1773 if (++ri->ri_nextin == ri->ri_last)
1774 ri->ri_nextin = ri->ri_first;
1775 }
1776 }
1777 /* LN_STAT(rx_intr_descs[rxdescs]++); */
1778 LN_MAXSTAT(rx_intr_hidescs, rxdescs);
1779
1780 return 0;
1781 }
1782
1783 static void
1784 lance_start(
1785 struct ifnet *ifp)
1786 {
1787 le_softc_t *sc = (le_softc_t *) ifp;
1788 struct ifqueue *ifq = &ifp->if_snd;
1789 lance_ring_t *ri = &sc->lance_txinfo;
1790 lance_descinfo_t *di;
1791 ln_desc_t desc;
1792 unsigned len, slop;
1793 struct mbuf *m, *m0;
1794 caddr_t bp;
1795
1796 if ((ifp->if_flags & IFF_RUNNING) == 0)
1797 return;
1798
1799 for (;;) {
1800 IF_DEQUEUE(ifq, m);
1801 if (m == NULL)
1802 break;
1803
1804 /*
1805 * Make the packet meets the minimum size for Ethernet.
1806 * The slop is so that we also use an even number of longwards.
1807 */
1808 len = ETHERMIN + sizeof(struct ether_header);
1809 if (m->m_pkthdr.len > len)
1810 len = m->m_pkthdr.len;
1811
1812 slop = (8 - len) & 3;
1813 /*
1814 * If there are no free ring entries (there must be always
1815 * one owned by the host), or there's not enough space for
1816 * this packet, or this packet would wrap around the end
1817 * of LANCE RAM then wait for the transmits to empty for
1818 * space and ring entries to become available.
1819 */
1820 if (ri->ri_free == 1 || len + slop > ri->ri_outsize) {
1821 /*
1822 * Try to see if we can free up anything off the transit ring.
1823 */
1824 if (lance_tx_intr(sc) > 0) {
1825 LN_STAT(tx_drains[0]++);
1826 IF_PREPEND(ifq, m);
1827 continue;
1828 }
1829 LN_STAT(tx_nospc[0]++);
1830 break;
1831 }
1832
1833 if (len + slop > ri->ri_heapend - ri->ri_outptr) {
1834 /*
1835 * Since the packet won't fit in the end of the transmit
1836 * heap, see if there is space at the beginning of the transmit
1837 * heap. If not, try again when there is space.
1838 */
1839 LN_STAT(tx_orphaned++);
1840 slop += ri->ri_heapend - ri->ri_outptr;
1841 if (len + slop > ri->ri_outsize) {
1842 LN_STAT(tx_nospc[1]++);
1843 break;
1844 }
1845 /*
1846 * Point to the beginning of the heap
1847 */
1848 ri->ri_outptr = ri->ri_heap;
1849 LN_STAT(tx_adoptions++);
1850 }
1851
1852 /*
1853 * Initialize the descriptor (saving the buffer address,
1854 * buffer length, and mbuf) and write the packet out
1855 * to the board.
1856 */
1857 di = ri->ri_nextout;
1858 di->di_bufaddr = ri->ri_outptr;
1859 di->di_buflen = len + slop;
1860 di->di_mbuf = m;
1861 bp = sc->le_membase + di->di_bufaddr;
1862 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1863 LN_COPYTO(sc, mtod(m0, caddr_t), bp, m0->m_len);
1864 bp += m0->m_len;
1865 }
1866 /*
1867 * Zero out the remainder if needed (< ETHERMIN).
1868 */
1869 if (m->m_pkthdr.len < len)
1870 LN_ZERO(sc, bp, len - m->m_pkthdr.len);
1871
1872 /*
1873 * Finally, copy out the descriptor and tell the
1874 * LANCE to transmit!.
1875 */
1876 desc.d_buflen = 0 - len;
1877 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1878 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1879 desc.d_flag = LN_DFLAG_SOP|LN_DFLAG_EOP|LN_DFLAG_OWNER;
1880 LN_PUTDESC(sc, &desc, di->di_addr);
1881 LN_WRCSR(sc, LN_CSR0_TXDEMAND|LN_CSR0_ENABINTR);
1882
1883 /*
1884 * Do our bookkeeping with our transmit heap.
1885 * (if we wrap, point back to the beginning).
1886 */
1887 ri->ri_outptr += di->di_buflen;
1888 ri->ri_outsize -= di->di_buflen;
1889 LN_MAXSTAT(high_txoutptr, ri->ri_outptr);
1890 LN_MINSTAT(low_txheapsize, ri->ri_outsize);
1891
1892 if (ri->ri_outptr == ri->ri_heapend)
1893 ri->ri_outptr = ri->ri_heap;
1894
1895 ri->ri_free--;
1896 if (++ri->ri_nextout == ri->ri_last)
1897 ri->ri_nextout = ri->ri_first;
1898 LN_MINSTAT(low_txfree, ri->ri_free);
1899 }
1900 if (m != NULL) {
1901 ifp->if_flags |= IFF_OACTIVE;
1902 IF_PREPEND(ifq, m);
1903 }
1904 }
1905
1906 static int
1907 lance_tx_intr(
1908 le_softc_t *sc)
1909 {
1910 lance_ring_t *ri = &sc->lance_txinfo;
1911 unsigned xmits;
1912
1913 LN_STAT(tx_intrs++);
1914 for (xmits = 0; ri->ri_free < ri->ri_max; ) {
1915 ln_desc_t desc;
1916
1917 LN_GETDESC(sc, &desc, ri->ri_nextin->di_addr);
1918 if (desc.d_flag & LN_DFLAG_OWNER)
1919 break;
1920
1921 if (desc.d_flag & (LN_DFLAG_TxONECOLL|LN_DFLAG_TxMULTCOLL))
1922 sc->le_if.if_collisions++;
1923 if (desc.d_flag & LN_DFLAG_TxDEFERRED)
1924 LN_STAT(tx_deferred++);
1925 if (desc.d_flag & LN_DFLAG_TxONECOLL)
1926 LN_STAT(tx_single_collisions++);
1927 if (desc.d_flag & LN_DFLAG_TxMULTCOLL)
1928 LN_STAT(tx_multiple_collisions++);
1929
1930 if (desc.d_flag & LN_DFLAG_TxERRSUM) {
1931 if (desc.d_status & (LN_DSTS_TxUNDERFLOW|LN_DSTS_TxBUFERROR|
1932 LN_DSTS_TxEXCCOLL|LN_DSTS_TxLATECOLL)) {
1933 if (desc.d_status & LN_DSTS_TxEXCCOLL) {
1934 unsigned tdr;
1935 LN_STAT(tx_excessive_collisions++);
1936 if ((tdr = (desc.d_status & LN_DSTS_TxTDRMASK)) > 0) {
1937 tdr *= 100;
1938 if_printf(&sc->le_if, "lance: warning: excessive collisions: TDR %dns (%d-%dm)\n",
1939 tdr, (tdr*99)/1000, (tdr*117)/1000);
1940 }
1941 }
1942 if (desc.d_status & LN_DSTS_TxBUFERROR)
1943 LN_STAT(tx_buferror++);
1944 sc->le_if.if_oerrors++;
1945 if ((desc.d_status & LN_DSTS_TxLATECOLL) == 0) {
1946 lance_init(sc);
1947 return 0;
1948 } else {
1949 LN_STAT(tx_late_collisions++);
1950 }
1951 }
1952 }
1953 m_freem(ri->ri_nextin->di_mbuf);
1954 ri->ri_nextin->di_mbuf = NULL;
1955 sc->le_if.if_opackets++;
1956 ri->ri_free++;
1957 ri->ri_outsize += ri->ri_nextin->di_buflen;
1958 if (++ri->ri_nextin == ri->ri_last)
1959 ri->ri_nextin = ri->ri_first;
1960 sc->le_if.if_flags &= ~IFF_OACTIVE;
1961 xmits++;
1962 }
1963 if (ri->ri_free == ri->ri_max)
1964 LN_STAT(tx_emptied++);
1965 /* LN_STAT(tx_intr_descs[xmits]++); */
1966 LN_MAXSTAT(tx_intr_hidescs, xmits);
1967 return xmits;
1968 }
1969 #endif /* !defined(LE_NOLANCE) */
Cache object: 36a93c3c51d2a98cdd20ba42d4586ec3
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