FreeBSD/Linux Kernel Cross Reference
sys/i386/isa/if_le.c
1 /*-
2 * Copyright (c) 1994 Matt Thomas (thomas@lkg.dec.com)
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the author may not be used to endorse or promote products
11 * derived from this software without specific prior written permission
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
18 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
19 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
20 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
21 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
22 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
23 */
24
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD: releng/5.2/sys/i386/isa/if_le.c 122057 2003-11-04 14:02:13Z nyan $");
27
28 /*
29 * DEC EtherWORKS 2 Ethernet Controllers
30 * DEC EtherWORKS 3 Ethernet Controllers
31 *
32 * Written by Matt Thomas
33 * BPF support code stolen directly from if_ec.c
34 *
35 * This driver supports the DEPCA, DE100, DE101, DE200, DE201,
36 * DE2002, DE203, DE204, DE205, and DE422 cards.
37 */
38
39 #include "le.h"
40 #include "opt_inet.h"
41 #include "opt_ipx.h"
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/mbuf.h>
47 #include <sys/socket.h>
48 #include <sys/sockio.h>
49 #include <sys/malloc.h>
50 #include <sys/bus.h>
51
52 #include <net/ethernet.h>
53 #include <net/if.h>
54 #include <net/if_types.h>
55 #include <net/if_dl.h>
56
57 #include <netinet/in.h>
58 #include <netinet/if_ether.h>
59
60 #include <machine/frame.h>
61
62 #include <i386/isa/isa_device.h>
63 #include <i386/isa/icu.h>
64
65 #include <vm/vm.h>
66 #include <vm/pmap.h>
67
68 #include <net/bpf.h>
69
70 #ifndef COMPAT_OLDISA
71 #error "The le device requires the old isa compatibility shims"
72 #endif
73
74 /* Forward declarations */
75 typedef struct le_softc le_softc_t;
76 typedef struct le_board le_board_t;
77
78 typedef u_short le_mcbits_t;
79 #define LE_MC_NBPW_LOG2 4
80 #define LE_MC_NBPW (1 << LE_MC_NBPW_LOG2)
81
82 #if !defined(LE_NOLEMAC)
83 /*
84 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
85 *
86 * Start of DEC EtherWORKS III (LEMAC) dependent structures
87 *
88 */
89 #include <i386/isa/ic/lemac.h> /* Include LEMAC definitions */
90
91 static int lemac_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
92
93 struct le_lemac_info {
94 u_int lemac__lastpage; /* last 2K page */
95 u_int lemac__memmode; /* Are we in 2K, 32K, or 64K mode */
96 u_int lemac__membase; /* Physical address of start of RAM */
97 u_int lemac__txctl; /* Transmit Control Byte */
98 u_int lemac__txmax; /* Maximum # of outstanding transmits */
99 le_mcbits_t lemac__mctbl[LEMAC_MCTBL_SIZE/sizeof(le_mcbits_t)];
100 /* local copy of multicast table */
101 u_char lemac__eeprom[LEMAC_EEP_SIZE]; /* local copy eeprom */
102 char lemac__prodname[LEMAC_EEP_PRDNMSZ+1]; /* prodname name */
103 #define lemac_lastpage le_un.un_lemac.lemac__lastpage
104 #define lemac_memmode le_un.un_lemac.lemac__memmode
105 #define lemac_membase le_un.un_lemac.lemac__membase
106 #define lemac_txctl le_un.un_lemac.lemac__txctl
107 #define lemac_txmax le_un.un_lemac.lemac__txmax
108 #define lemac_mctbl le_un.un_lemac.lemac__mctbl
109 #define lemac_eeprom le_un.un_lemac.lemac__eeprom
110 #define lemac_prodname le_un.un_lemac.lemac__prodname
111 };
112 #endif /* !defined(LE_NOLEMAC) */
113
114 #if !defined(LE_NOLANCE)
115 /*
116 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
117 *
118 * Start of DEC EtherWORKS II (LANCE) dependent structures
119 *
120 */
121
122 #include <i386/isa/ic/am7990.h>
123
124 #ifndef LN_DOSTATS
125 #define LN_DOSTATS 1
126 #endif
127
128 static int depca_probe(le_softc_t *sc, const le_board_t *bd, int *msize);
129
130 typedef struct lance_descinfo lance_descinfo_t;
131 typedef struct lance_ring lance_ring_t;
132
133 typedef unsigned lance_addr_t;
134
135 struct lance_descinfo {
136 caddr_t di_addr; /* address of descriptor */
137 lance_addr_t di_bufaddr; /* LANCE address of buffer owned by descriptor */
138 unsigned di_buflen; /* size of buffer owned by descriptor */
139 struct mbuf *di_mbuf; /* mbuf being transmitted/received */
140 };
141
142 struct lance_ring {
143 lance_descinfo_t *ri_first; /* Pointer to first descriptor in ring */
144 lance_descinfo_t *ri_last; /* Pointer to last + 1 descriptor in ring */
145 lance_descinfo_t *ri_nextin; /* Pointer to next one to be given to HOST */
146 lance_descinfo_t *ri_nextout; /* Pointer to next one to be given to LANCE */
147 unsigned ri_max; /* Size of Ring - 1 */
148 unsigned ri_free; /* Number of free rings entires (owned by HOST) */
149 lance_addr_t ri_heap; /* Start of RAM for this ring */
150 lance_addr_t ri_heapend; /* End + 1 of RAM for this ring */
151 lance_addr_t ri_outptr; /* Pointer to first output byte */
152 unsigned ri_outsize; /* Space remaining for output */
153 };
154
155 struct le_lance_info {
156 unsigned lance__csr1; /* LANCE Address of init block (low 16) */
157 unsigned lance__csr2; /* LANCE Address of init block (high 8) */
158 unsigned lance__csr3; /* Copy of CSR3 */
159 unsigned lance__rap; /* IO Port Offset of RAP */
160 unsigned lance__rdp; /* IO Port Offset of RDP */
161 unsigned lance__ramoffset; /* Offset to valid LANCE RAM */
162 unsigned lance__ramsize; /* Amount of RAM shared by LANCE */
163 unsigned lance__rxbufsize; /* Size of a receive buffer */
164 ln_initb_t lance__initb; /* local copy of LANCE initblock */
165 ln_initb_t *lance__raminitb; /* copy to board's LANCE initblock (debugging) */
166 ln_desc_t *lance__ramdesc; /* copy to board's LANCE descriptors (debugging) */
167 lance_ring_t lance__rxinfo; /* Receive ring information */
168 lance_ring_t lance__txinfo; /* Transmit ring information */
169 #define lance_csr1 le_un.un_lance.lance__csr1
170 #define lance_csr2 le_un.un_lance.lance__csr2
171 #define lance_csr3 le_un.un_lance.lance__csr3
172 #define lance_rap le_un.un_lance.lance__rap
173 #define lance_rdp le_un.un_lance.lance__rdp
174 #define lance_ramoffset le_un.un_lance.lance__ramoffset
175 #define lance_ramsize le_un.un_lance.lance__ramsize
176 #define lance_rxbufsize le_un.un_lance.lance__rxbufsize
177 #define lance_initb le_un.un_lance.lance__initb
178 #define lance_raminitb le_un.un_lance.lance__raminitb
179 #define lance_ramdesc le_un.un_lance.lance__ramdesc
180 #define lance_rxinfo le_un.un_lance.lance__rxinfo
181 #define lance_txinfo le_un.un_lance.lance__txinfo
182 };
183 #endif /* !defined(LE_NOLANCE) */
184
185 /*
186 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
187 *
188 * Start of Common Code
189 *
190 */
191
192 static void (*le_intrvec[NLE])(le_softc_t *sc);
193
194 /*
195 * Ethernet status, per interface.
196 */
197 struct le_softc {
198 struct arpcom le_ac; /* Common Ethernet/ARP Structure */
199 int le_unit; /* Unit number */
200 void (*if_init)(void *);/* Interface init routine */
201 void (*if_reset)(le_softc_t *);/* Interface reset routine */
202 caddr_t le_membase; /* Starting memory address (virtual) */
203 unsigned le_iobase; /* Starting I/O base address */
204 unsigned le_irq; /* Interrupt Request Value */
205 unsigned le_flags; /* local copy of if_flags */
206 #define LE_BRDCSTONLY 0x01000000 /* If only broadcast is enabled */
207 u_int le_mcmask; /* bit mask for CRC-32 for multicast hash */
208 le_mcbits_t *le_mctbl; /* pointer to multicast table */
209 const char *le_prodname; /* product name DE20x-xx */
210 u_char le_hwaddr[6]; /* local copy of hwaddr */
211 union {
212 #if !defined(LE_NOLEMAC)
213 struct le_lemac_info un_lemac; /* LEMAC specific information */
214 #endif
215 #if !defined(LE_NOLANCE)
216 struct le_lance_info un_lance; /* Am7990 specific information */
217 #endif
218 } le_un;
219 };
220 #define le_if le_ac.ac_if
221
222
223 static int le_probe(struct isa_device *dvp);
224 static int le_attach(struct isa_device *dvp);
225 static ointhand2_t le_intr;
226 static int le_ioctl(struct ifnet *ifp, u_long command, caddr_t data);
227 static void le_input(le_softc_t *sc, caddr_t seg1, size_t total_len,
228 size_t len2, caddr_t seg2);
229 static void le_multi_filter(le_softc_t *sc);
230 static void le_multi_op(le_softc_t *sc, const u_char *mca, int oper_flg);
231 static int le_read_macaddr(le_softc_t *sc, int ioreg, int skippat);
232
233 #define LE_CRC32_POLY 0xEDB88320UL /* CRC-32 Poly -- Little Endian */
234
235 struct le_board {
236 int (*bd_probe)(le_softc_t *sc, const le_board_t *bd, int *msize);
237 };
238
239
240 static le_softc_t le_softc[NLE];
241
242 static const le_board_t le_boards[] = {
243 #if !defined(LE_NOLEMAC)
244 { lemac_probe }, /* DE20[345] */
245 #endif
246 #if !defined(LE_NOLANCE)
247 { depca_probe }, /* DE{20[012],422} */
248 #endif
249 { NULL } /* Must Be Last! */
250 };
251
252 /*
253 * This tells the autoconf code how to set us up.
254 */
255 struct isa_driver ledriver = {
256 INTR_TYPE_NET,
257 le_probe,
258 le_attach,
259 "le",
260 };
261 COMPAT_ISA_DRIVER(le, ledriver);
262
263 static unsigned le_intrs[NLE];
264
265 #define LE_ADDREQUAL(a1, a2) \
266 (((u_short *)a1)[0] == ((u_short *)a2)[0] \
267 || ((u_short *)a1)[1] == ((u_short *)a2)[1] \
268 || ((u_short *)a1)[2] == ((u_short *)a2)[2])
269 #define LE_ADDRBRDCST(a1) \
270 (((u_short *)a1)[0] == 0xFFFFU \
271 || ((u_short *)a1)[1] == 0xFFFFU \
272 || ((u_short *)a1)[2] == 0xFFFFU)
273
274 #define LE_INL(sc, reg) \
275 ({ u_int data; \
276 __asm __volatile("inl %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
277 data; })
278
279
280 #define LE_OUTL(sc, reg, data) \
281 ({__asm __volatile("outl %0, %1"::"a" ((u_int)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
282
283 #define LE_INW(sc, reg) \
284 ({ u_short data; \
285 __asm __volatile("inw %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
286 data; })
287
288
289 #define LE_OUTW(sc, reg, data) \
290 ({__asm __volatile("outw %0, %1"::"a" ((u_short)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
291
292 #define LE_INB(sc, reg) \
293 ({ u_char data; \
294 __asm __volatile("inb %1, %0": "=a" (data): "d" ((u_short)((sc)->le_iobase + (reg)))); \
295 data; })
296
297
298 #define LE_OUTB(sc, reg, data) \
299 ({__asm __volatile("outb %0, %1"::"a" ((u_char)(data)), "d" ((u_short)((sc)->le_iobase + (reg))));})
300
301 #define MEMCPY(to, from, len) bcopy(from, to, len)
302 #define MEMSET(where, what, howmuch) bzero(where, howmuch)
303 #define MEMCMP(l, r, len) bcmp(l, r, len)
304
305
306 static int
307 le_probe(
308 struct isa_device *dvp)
309 {
310 le_softc_t *sc = &le_softc[dvp->id_unit];
311 const le_board_t *bd;
312 int iospace;
313
314 if (dvp->id_unit >= NLE) {
315 printf("%s%d not configured -- too many devices\n",
316 ledriver.name, dvp->id_unit);
317 return 0;
318 }
319
320 sc->le_iobase = dvp->id_iobase;
321 sc->le_membase = (u_char *) dvp->id_maddr;
322 sc->le_irq = dvp->id_irq;
323 sc->le_unit = dvp->id_unit;
324
325 /*
326 * Find and Initialize board..
327 */
328
329 sc->le_flags &= ~(IFF_UP|IFF_ALLMULTI);
330
331 for (bd = le_boards; bd->bd_probe != NULL; bd++) {
332 if ((iospace = (*bd->bd_probe)(sc, bd, &dvp->id_msize)) != 0) {
333 return iospace;
334 }
335 }
336
337 return 0;
338 }
339
340 static int
341 le_attach(
342 struct isa_device *dvp)
343 {
344 le_softc_t *sc = &le_softc[dvp->id_unit];
345 struct ifnet *ifp = &sc->le_if;
346
347 dvp->id_ointr = le_intr;
348 ifp->if_softc = sc;
349 if_initname(ifp, ledriver.name, dvp->id_unit);
350 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
351 ifp->if_ioctl = le_ioctl;
352 ifp->if_init = sc->if_init;
353 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN;
354
355 if_printf(ifp, "%s ethernet address %6D\n",
356 sc->le_prodname,
357 sc->le_ac.ac_enaddr, ":");
358
359 ether_ifattach(ifp, sc->le_ac.ac_enaddr);
360
361 return 1;
362 }
363
364 static void
365 le_intr(
366 int unit)
367 {
368 int s = splimp();
369
370 le_intrs[unit]++;
371 (*le_intrvec[unit])(&le_softc[unit]);
372
373 splx(s);
374 }
375
376 #define LE_XTRA 0
377
378 static void
379 le_input(
380 le_softc_t *sc,
381 caddr_t seg1,
382 size_t total_len,
383 size_t len1,
384 caddr_t seg2)
385 {
386 struct ifnet *ifp = &sc->le_if;
387 struct mbuf *m;
388
389 MGETHDR(m, M_DONTWAIT, MT_DATA);
390 if (m == NULL) {
391 ifp->if_ierrors++;
392 return;
393 }
394 m->m_pkthdr.len = total_len;
395 m->m_pkthdr.rcvif = ifp;
396 if (total_len + LE_XTRA > MHLEN /* >= MINCLSIZE */) {
397 MCLGET(m, M_DONTWAIT);
398 if ((m->m_flags & M_EXT) == 0) {
399 m_free(m);
400 ifp->if_ierrors++;
401 return;
402 }
403 } else if (total_len + LE_XTRA > MHLEN && MINCLSIZE == (MHLEN+MLEN)) {
404 MGET(m->m_next, M_DONTWAIT, MT_DATA);
405 if (m->m_next == NULL) {
406 m_free(m);
407 ifp->if_ierrors++;
408 return;
409 }
410 m->m_next->m_len = total_len - MHLEN - LE_XTRA;
411 len1 = total_len = MHLEN - LE_XTRA;
412 MEMCPY(mtod(m->m_next, caddr_t), &seg1[MHLEN-LE_XTRA], m->m_next->m_len);
413 } else if (total_len + LE_XTRA > MHLEN) {
414 panic("le_input: pkt of unknown length");
415 }
416 m->m_data += LE_XTRA;
417 m->m_len = total_len;
418 MEMCPY(mtod(m, caddr_t), seg1, len1);
419 if (seg2 != NULL)
420 MEMCPY(mtod(m, caddr_t) + len1, seg2, total_len - len1);
421
422 (*ifp->if_input)(ifp, m);
423 }
424
425 static int
426 le_ioctl(
427 struct ifnet *ifp,
428 u_long cmd,
429 caddr_t data)
430 {
431 le_softc_t *sc = ifp->if_softc;
432 int s, error = 0;
433
434 if ((sc->le_flags & IFF_UP) == 0)
435 return EIO;
436
437 s = splimp();
438
439 switch (cmd) {
440 case SIOCSIFFLAGS: {
441 sc->if_init(sc);
442 break;
443 }
444
445 case SIOCADDMULTI:
446 case SIOCDELMULTI:
447 /*
448 * Update multicast listeners
449 */
450 sc->if_init(sc);
451 error = 0;
452 break;
453
454 default: {
455 error = ether_ioctl(ifp, cmd, data);
456 break;
457 }
458 }
459
460 splx(s);
461 return error;
462 }
463
464 /*
465 * This is the standard method of reading the DEC Address ROMS.
466 * I don't understand it but it does work.
467 */
468 static int
469 le_read_macaddr(
470 le_softc_t *sc,
471 int ioreg,
472 int skippat)
473 {
474 int cksum, rom_cksum;
475
476 if (!skippat) {
477 int idx, idx2, found, octet;
478 static u_char testpat[] = { 0xFF, 0, 0x55, 0xAA, 0xFF, 0, 0x55, 0xAA };
479 idx2 = found = 0;
480
481 for (idx = 0; idx < 32; idx++) {
482 octet = LE_INB(sc, ioreg);
483
484 if (octet == testpat[idx2]) {
485 if (++idx2 == sizeof testpat) {
486 ++found;
487 break;
488 }
489 } else {
490 idx2 = 0;
491 }
492 }
493
494 if (!found)
495 return -1;
496 }
497
498 cksum = 0;
499 sc->le_hwaddr[0] = LE_INB(sc, ioreg);
500 sc->le_hwaddr[1] = LE_INB(sc, ioreg);
501
502 cksum = *(u_short *) &sc->le_hwaddr[0];
503
504 sc->le_hwaddr[2] = LE_INB(sc, ioreg);
505 sc->le_hwaddr[3] = LE_INB(sc, ioreg);
506 cksum *= 2;
507 if (cksum > 65535) cksum -= 65535;
508 cksum += *(u_short *) &sc->le_hwaddr[2];
509 if (cksum > 65535) cksum -= 65535;
510
511 sc->le_hwaddr[4] = LE_INB(sc, ioreg);
512 sc->le_hwaddr[5] = LE_INB(sc, ioreg);
513 cksum *= 2;
514 if (cksum > 65535) cksum -= 65535;
515 cksum += *(u_short *) &sc->le_hwaddr[4];
516 if (cksum >= 65535) cksum -= 65535;
517
518 rom_cksum = LE_INB(sc, ioreg);
519 rom_cksum |= LE_INB(sc, ioreg) << 8;
520
521 if (cksum != rom_cksum)
522 return -1;
523 return 0;
524 }
525
526 static void
527 le_multi_filter(
528 le_softc_t *sc)
529 {
530 struct ifmultiaddr *ifma;
531
532 MEMSET(sc->le_mctbl, 0, (sc->le_mcmask + 1) / 8);
533
534 if (sc->le_if.if_flags & IFF_ALLMULTI) {
535 sc->le_flags |= IFF_MULTICAST|IFF_ALLMULTI;
536 return;
537 }
538 sc->le_flags &= ~IFF_MULTICAST;
539 /* if (interface has had an address assigned) { */
540 le_multi_op(sc, sc->le_if.if_broadcastaddr, TRUE);
541 sc->le_flags |= LE_BRDCSTONLY|IFF_MULTICAST;
542 /* } */
543
544 sc->le_flags |= IFF_MULTICAST;
545
546 TAILQ_FOREACH(ifma, &sc->le_ac.ac_if.if_multiaddrs, ifma_link) {
547 if (ifma->ifma_addr->sa_family != AF_LINK)
548 continue;
549
550 le_multi_op(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr), 1);
551 sc->le_flags &= ~LE_BRDCSTONLY;
552 }
553 }
554
555 static void
556 le_multi_op(
557 le_softc_t *sc,
558 const u_char *mca,
559 int enable)
560 {
561 u_int idx, bit, data, crc = 0xFFFFFFFFUL;
562
563 #ifdef __alpha
564 for (data = *(__unaligned u_long *) mca, bit = 0; bit < 48; bit++, data >>=
565 1)
566 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
567 #else
568 for (idx = 0; idx < 6; idx++)
569 for (data = *mca++, bit = 0; bit < 8; bit++, data >>= 1)
570 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? LE_CRC32_POLY : 0);
571 #endif
572 /*
573 * The following two line convert the N bit index into a longword index
574 * and a longword mask.
575 */
576 crc &= sc->le_mcmask;
577 bit = 1 << (crc & (LE_MC_NBPW -1));
578 idx = crc >> (LE_MC_NBPW_LOG2);
579
580 /*
581 * Set or clear hash filter bit in our table.
582 */
583 if (enable) {
584 sc->le_mctbl[idx] |= bit; /* Set Bit */
585 } else {
586 sc->le_mctbl[idx] &= ~bit; /* Clear Bit */
587 }
588 }
589
590 #if !defined(LE_NOLEMAC)
591 /*
592 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
593 *
594 * Start of DEC EtherWORKS III (LEMAC) dependent code
595 *
596 */
597
598 #define LEMAC_INTR_ENABLE(sc) \
599 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_ALL)
600
601 #define LEMAC_INTR_DISABLE(sc) \
602 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ~LEMAC_IC_ALL)
603
604 #define LEMAC_64K_MODE(mbase) (((mbase) >= 0x0A) && ((mbase) <= 0x0F))
605 #define LEMAC_32K_MODE(mbase) (((mbase) >= 0x14) && ((mbase) <= 0x1F))
606 #define LEMAC_2K_MODE(mbase) ( (mbase) >= 0x40)
607
608 static void lemac_init(void *);
609 static void lemac_start(struct ifnet *ifp);
610 static void lemac_reset(le_softc_t *sc);
611 static void lemac_intr(le_softc_t *sc);
612 static void lemac_rne_intr(le_softc_t *sc);
613 static void lemac_tne_intr(le_softc_t *sc);
614 static void lemac_txd_intr(le_softc_t *sc, unsigned cs_value);
615 static void lemac_rxd_intr(le_softc_t *sc, unsigned cs_value);
616 static int lemac_read_eeprom(le_softc_t *sc);
617 static void lemac_init_adapmem(le_softc_t *sc);
618
619 #define LE_MCBITS_ALL_1S ((le_mcbits_t)~(le_mcbits_t)0)
620
621 static const le_mcbits_t lemac_allmulti_mctbl[16] = {
622 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
623 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
624 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
625 LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S, LE_MCBITS_ALL_1S,
626 };
627 /*
628 * An IRQ mapping table. Less space than switch statement.
629 */
630 static const int lemac_irqs[] = { IRQ5, IRQ10, IRQ11, IRQ15 };
631
632 /*
633 * Some tuning/monitoring variables.
634 */
635 static unsigned lemac_deftxmax = 16; /* see lemac_max above */
636 static unsigned lemac_txnospc = 0; /* total # of tranmit starvations */
637
638 static unsigned lemac_tne_intrs = 0; /* total # of tranmit done intrs */
639 static unsigned lemac_rne_intrs = 0; /* total # of receive done intrs */
640 static unsigned lemac_txd_intrs = 0; /* total # of tranmit error intrs */
641 static unsigned lemac_rxd_intrs = 0; /* total # of receive error intrs */
642
643
644 static int
645 lemac_probe(
646 le_softc_t *sc,
647 const le_board_t *bd,
648 int *msize)
649 {
650 int irq, portval;
651
652 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
653 DELAY(LEMAC_EEP_DELAY);
654
655 /*
656 * Read Ethernet address if card is present.
657 */
658 if (le_read_macaddr(sc, LEMAC_REG_APD, 0) < 0)
659 return 0;
660
661 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
662 /*
663 * Clear interrupts and set IRQ.
664 */
665
666 portval = LE_INB(sc, LEMAC_REG_IC) & LEMAC_IC_IRQMSK;
667 irq = lemac_irqs[portval >> 5];
668 LE_OUTB(sc, LEMAC_REG_IC, portval);
669
670 /*
671 * Make sure settings match.
672 */
673
674 if (irq != sc->le_irq) {
675 if_printf(&sc->le_if,
676 "lemac configuration error: expected IRQ 0x%x actual 0x%x\n",
677 sc->le_irq, irq);
678 return 0;
679 }
680
681 /*
682 * Try to reset the unit
683 */
684 sc->if_init = lemac_init;
685 sc->le_if.if_start = lemac_start;
686 sc->if_reset = lemac_reset;
687 sc->lemac_memmode = 2;
688 sc->if_reset(sc);
689 if ((sc->le_flags & IFF_UP) == 0)
690 return 0;
691
692 /*
693 * Check for correct memory base configuration.
694 */
695 if (vtophys(sc->le_membase) != sc->lemac_membase) {
696 if_printf(&sc->le_if,
697 "lemac configuration error: expected iomem 0x%x actual 0x%x\n",
698 vtophys(sc->le_membase), sc->lemac_membase);
699 return 0;
700 }
701
702 sc->le_prodname = sc->lemac_prodname;
703 sc->le_mctbl = sc->lemac_mctbl;
704 sc->le_mcmask = (1 << LEMAC_MCTBL_BITS) - 1;
705 sc->lemac_txmax = lemac_deftxmax;
706 *msize = 2048;
707 le_intrvec[sc->le_unit] = lemac_intr;
708
709 return LEMAC_IOSPACE;
710 }
711
712 /*
713 * Do a hard reset of the board;
714 */
715 static void
716 lemac_reset(
717 le_softc_t *sc)
718 {
719 int portval, cksum;
720
721 /*
722 * Initialize board..
723 */
724
725 sc->le_flags &= IFF_UP;
726 sc->le_if.if_flags &= ~IFF_OACTIVE;
727 LEMAC_INTR_DISABLE(sc);
728
729 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEINIT);
730 DELAY(LEMAC_EEP_DELAY);
731
732 /* Disable Interrupts */
733 /* LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) & ICR_IRQ_SEL); */
734
735 /*
736 * Read EEPROM information. NOTE - the placement of this function
737 * is important because functions hereafter may rely on information
738 * read from the EEPROM.
739 */
740 if ((cksum = lemac_read_eeprom(sc)) != LEMAC_EEP_CKSUM) {
741 if_printf(&sc->le_if, "reset: EEPROM checksum failed (0x%x)\n", cksum);
742 return;
743 }
744
745 /*
746 * Force to 2K mode if not already configured.
747 */
748
749 portval = LE_INB(sc, LEMAC_REG_MBR);
750 if (!LEMAC_2K_MODE(portval)) {
751 if (LEMAC_64K_MODE(portval)) {
752 portval = (((portval * 2) & 0xF) << 4);
753 sc->lemac_memmode = 64;
754 } else if (LEMAC_32K_MODE(portval)) {
755 portval = ((portval & 0xF) << 4);
756 sc->lemac_memmode = 32;
757 }
758 LE_OUTB(sc, LEMAC_REG_MBR, portval);
759 }
760 sc->lemac_membase = portval * (2 * 1024) + (512 * 1024);
761
762 /*
763 * Initialize Free Memory Queue, Init mcast table with broadcast.
764 */
765
766 lemac_init_adapmem(sc);
767 sc->le_flags |= IFF_UP;
768 return;
769 }
770
771 static void
772 lemac_init(void *xsc)
773 {
774 le_softc_t *sc;
775 int s;
776
777 sc = (le_softc_t *)xsc;
778
779 if ((sc->le_flags & IFF_UP) == 0)
780 return;
781
782 s = splimp();
783
784 /*
785 * If the interface has the up flag
786 */
787 if (sc->le_if.if_flags & IFF_UP) {
788 int saved_cs = LE_INB(sc, LEMAC_REG_CS);
789 LE_OUTB(sc, LEMAC_REG_CS, saved_cs | (LEMAC_CS_TXD | LEMAC_CS_RXD));
790 LE_OUTB(sc, LEMAC_REG_PA0, sc->le_ac.ac_enaddr[0]);
791 LE_OUTB(sc, LEMAC_REG_PA1, sc->le_ac.ac_enaddr[1]);
792 LE_OUTB(sc, LEMAC_REG_PA2, sc->le_ac.ac_enaddr[2]);
793 LE_OUTB(sc, LEMAC_REG_PA3, sc->le_ac.ac_enaddr[3]);
794 LE_OUTB(sc, LEMAC_REG_PA4, sc->le_ac.ac_enaddr[4]);
795 LE_OUTB(sc, LEMAC_REG_PA5, sc->le_ac.ac_enaddr[5]);
796
797 LE_OUTB(sc, LEMAC_REG_IC, LE_INB(sc, LEMAC_REG_IC) | LEMAC_IC_IE);
798
799 if (sc->le_if.if_flags & IFF_PROMISC) {
800 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE | LEMAC_CS_PME);
801 } else {
802 LEMAC_INTR_DISABLE(sc);
803 le_multi_filter(sc);
804 LE_OUTB(sc, LEMAC_REG_MPN, 0);
805 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
806 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], lemac_allmulti_mctbl, sizeof(lemac_allmulti_mctbl));
807 } else {
808 MEMCPY(&sc->le_membase[LEMAC_MCTBL_OFF], sc->lemac_mctbl, sizeof(sc->lemac_mctbl));
809 }
810 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_MCE);
811 }
812
813 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
814
815 LEMAC_INTR_ENABLE(sc);
816 sc->le_if.if_flags |= IFF_RUNNING;
817 } else {
818 LE_OUTB(sc, LEMAC_REG_CS, LEMAC_CS_RXD|LEMAC_CS_TXD);
819
820 LEMAC_INTR_DISABLE(sc);
821 sc->le_if.if_flags &= ~IFF_RUNNING;
822 }
823 splx(s);
824 }
825
826 /*
827 * What to do upon receipt of an interrupt.
828 */
829 static void
830 lemac_intr(
831 le_softc_t *sc)
832 {
833 int cs_value;
834
835 LEMAC_INTR_DISABLE(sc); /* Mask interrupts */
836
837 /*
838 * Determine cause of interrupt. Receive events take
839 * priority over Transmit.
840 */
841
842 cs_value = LE_INB(sc, LEMAC_REG_CS);
843
844 /*
845 * Check for Receive Queue not being empty.
846 * Check for Transmit Done Queue not being empty.
847 */
848
849 if (cs_value & LEMAC_CS_RNE)
850 lemac_rne_intr(sc);
851 if (cs_value & LEMAC_CS_TNE)
852 lemac_tne_intr(sc);
853
854 /*
855 * Check for Transmitter Disabled.
856 * Check for Receiver Disabled.
857 */
858
859 if (cs_value & LEMAC_CS_TXD)
860 lemac_txd_intr(sc, cs_value);
861 if (cs_value & LEMAC_CS_RXD)
862 lemac_rxd_intr(sc, cs_value);
863
864 /*
865 * Toggle LED and unmask interrupts.
866 */
867
868 LE_OUTB(sc, LEMAC_REG_CTL, LE_INB(sc, LEMAC_REG_CTL) ^ LEMAC_CTL_LED);
869 LEMAC_INTR_ENABLE(sc); /* Unmask interrupts */
870 }
871
872 static void
873 lemac_rne_intr(
874 le_softc_t *sc)
875 {
876 int rxcount, rxlen, rxpg;
877 u_char *rxptr;
878
879 lemac_rne_intrs++;
880 rxcount = LE_INB(sc, LEMAC_REG_RQC);
881 while (rxcount--) {
882 rxpg = LE_INB(sc, LEMAC_REG_RQ);
883 LE_OUTB(sc, LEMAC_REG_MPN, rxpg);
884
885 rxptr = sc->le_membase;
886 sc->le_if.if_ipackets++;
887 if (*rxptr & LEMAC_RX_OK) {
888
889 /*
890 * Get receive length - subtract out checksum.
891 */
892
893 rxlen = ((*(u_int *)rxptr >> 8) & 0x7FF) - 4;
894 le_input(sc, rxptr + sizeof(u_int), rxlen, rxlen, NULL);
895 } else { /* end if (*rxptr & LEMAC_RX_OK) */
896 sc->le_if.if_ierrors++;
897 }
898 LE_OUTB(sc, LEMAC_REG_FMQ, rxpg); /* Return this page to Free Memory Queue */
899 } /* end while (recv_count--) */
900
901 return;
902 }
903
904 static void
905 lemac_rxd_intr(
906 le_softc_t *sc,
907 unsigned cs_value)
908 {
909 /*
910 * Handle CS_RXD (Receiver disabled) here.
911 *
912 * Check Free Memory Queue Count. If not equal to zero
913 * then just turn Receiver back on. If it is equal to
914 * zero then check to see if transmitter is disabled.
915 * Process transmit TXD loop once more. If all else
916 * fails then do software init (0xC0 to EEPROM Init)
917 * and rebuild Free Memory Queue.
918 */
919
920 lemac_rxd_intrs++;
921
922 /*
923 * Re-enable Receiver.
924 */
925
926 cs_value &= ~LEMAC_CS_RXD;
927 LE_OUTB(sc, LEMAC_REG_CS, cs_value);
928
929 if (LE_INB(sc, LEMAC_REG_FMC) > 0)
930 return;
931
932 if (cs_value & LEMAC_CS_TXD)
933 lemac_txd_intr(sc, cs_value);
934
935 if ((LE_INB(sc, LEMAC_REG_CS) & LEMAC_CS_RXD) == 0)
936 return;
937
938 if_printf(&sc->le_if, "fatal RXD error, attempting recovery\n");
939
940 sc->if_reset(sc);
941 if (sc->le_flags & IFF_UP) {
942 lemac_init(sc);
943 return;
944 }
945
946 /*
947 * Error during initializion. Mark card as disabled.
948 */
949 if_printf(&sc->le_if, "recovery failed -- board disabled\n");
950 return;
951 }
952
953 static void
954 lemac_start(
955 struct ifnet *ifp)
956 {
957 le_softc_t *sc = (le_softc_t *) ifp;
958 struct ifqueue *ifq = &ifp->if_snd;
959
960 if ((ifp->if_flags & IFF_RUNNING) == 0)
961 return;
962
963 LEMAC_INTR_DISABLE(sc);
964
965 while (ifq->ifq_head != NULL) {
966 struct mbuf *m;
967 int tx_pg;
968 u_int txhdr, txoff;
969
970 if (LE_INB(sc, LEMAC_REG_TQC) >= sc->lemac_txmax) {
971 ifp->if_flags |= IFF_OACTIVE;
972 break;
973 }
974
975 tx_pg = LE_INB(sc, LEMAC_REG_FMQ); /* get free memory page */
976 /*
977 * Check for good transmit page.
978 */
979 if (tx_pg == 0 || tx_pg > sc->lemac_lastpage) {
980 lemac_txnospc++;
981 ifp->if_flags |= IFF_OACTIVE;
982 break;
983 }
984
985 IF_DEQUEUE(ifq, m);
986 LE_OUTB(sc, LEMAC_REG_MPN, tx_pg); /* Shift 2K window. */
987
988 /*
989 * The first four bytes of each transmit buffer are for
990 * control information. The first byte is the control
991 * byte, then the length (why not word aligned?), then
992 * the off to the buffer.
993 */
994
995 txoff = (mtod(m, u_int) & (sizeof(u_long) - 1)) + LEMAC_TX_HDRSZ;
996 txhdr = sc->lemac_txctl | (m->m_pkthdr.len << 8) | (txoff << 24);
997 *(u_int *) sc->le_membase = txhdr;
998
999 /*
1000 * Copy the packet to the board
1001 */
1002
1003 m_copydata(m, 0, m->m_pkthdr.len, sc->le_membase + txoff);
1004
1005 LE_OUTB(sc, LEMAC_REG_TQ, tx_pg); /* tell chip to transmit this packet */
1006
1007 BPF_MTAP(&sc->le_if, m);
1008
1009 m_freem(m); /* free the mbuf */
1010 }
1011 LEMAC_INTR_ENABLE(sc);
1012 }
1013
1014 static void
1015 lemac_tne_intr(
1016 le_softc_t *sc)
1017 {
1018 int txsts, txcount = LE_INB(sc, LEMAC_REG_TDC);
1019
1020 lemac_tne_intrs++;
1021 while (txcount--) {
1022 txsts = LE_INB(sc, LEMAC_REG_TDQ);
1023 sc->le_if.if_opackets++; /* another one done */
1024 if ((txsts & LEMAC_TDQ_COL) != LEMAC_TDQ_NOCOL)
1025 sc->le_if.if_collisions++;
1026 }
1027 sc->le_if.if_flags &= ~IFF_OACTIVE;
1028 lemac_start(&sc->le_if);
1029 }
1030
1031 static void
1032 lemac_txd_intr(
1033 le_softc_t *sc,
1034 unsigned cs_value)
1035 {
1036 /*
1037 * Read transmit status, remove transmit buffer from
1038 * transmit queue and place on free memory queue,
1039 * then reset transmitter.
1040 * Increment appropriate counters.
1041 */
1042
1043 lemac_txd_intrs++;
1044 sc->le_if.if_oerrors++;
1045 if (LE_INB(sc, LEMAC_REG_TS) & LEMAC_TS_ECL)
1046 sc->le_if.if_collisions++;
1047 sc->le_if.if_flags &= ~IFF_OACTIVE;
1048
1049 LE_OUTB(sc, LEMAC_REG_FMQ, LE_INB(sc, LEMAC_REG_TQ));
1050 /* Get Page number and write it back out */
1051
1052 LE_OUTB(sc, LEMAC_REG_CS, cs_value & ~LEMAC_CS_TXD);
1053 /* Turn back on transmitter */
1054 return;
1055 }
1056
1057 static int
1058 lemac_read_eeprom(
1059 le_softc_t *sc)
1060 {
1061 int word_off, cksum;
1062
1063 u_char *ep;
1064
1065 cksum = 0;
1066 ep = sc->lemac_eeprom;
1067 for (word_off = 0; word_off < LEMAC_EEP_SIZE / 2; word_off++) {
1068 LE_OUTB(sc, LEMAC_REG_PI1, word_off);
1069 LE_OUTB(sc, LEMAC_REG_IOP, LEMAC_IOP_EEREAD);
1070
1071 DELAY(LEMAC_EEP_DELAY);
1072
1073 *ep = LE_INB(sc, LEMAC_REG_EE1); cksum += *ep++;
1074 *ep = LE_INB(sc, LEMAC_REG_EE2); cksum += *ep++;
1075 }
1076
1077 /*
1078 * Set up Transmit Control Byte for use later during transmit.
1079 */
1080
1081 sc->lemac_txctl |= LEMAC_TX_FLAGS;
1082
1083 if ((sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_SQE) == 0)
1084 sc->lemac_txctl &= ~LEMAC_TX_SQE;
1085
1086 if (sc->lemac_eeprom[LEMAC_EEP_SWFLAGS] & LEMAC_EEP_SW_LAB)
1087 sc->lemac_txctl |= LEMAC_TX_LAB;
1088
1089 MEMCPY(sc->lemac_prodname, &sc->lemac_eeprom[LEMAC_EEP_PRDNM], LEMAC_EEP_PRDNMSZ);
1090 sc->lemac_prodname[LEMAC_EEP_PRDNMSZ] = '\0';
1091
1092 return cksum % 256;
1093 }
1094
1095 static void
1096 lemac_init_adapmem(
1097 le_softc_t *sc)
1098 {
1099 int pg, conf;
1100
1101 conf = LE_INB(sc, LEMAC_REG_CNF);
1102
1103 if ((sc->lemac_eeprom[LEMAC_EEP_SETUP] & LEMAC_EEP_ST_DRAM) == 0) {
1104 sc->lemac_lastpage = 63;
1105 conf &= ~LEMAC_CNF_DRAM;
1106 } else {
1107 sc->lemac_lastpage = 127;
1108 conf |= LEMAC_CNF_DRAM;
1109 }
1110
1111 LE_OUTB(sc, LEMAC_REG_CNF, conf);
1112
1113 for (pg = 1; pg <= sc->lemac_lastpage; pg++)
1114 LE_OUTB(sc, LEMAC_REG_FMQ, pg);
1115
1116 return;
1117 }
1118 #endif /* !defined(LE_NOLEMAC) */
1119
1120 #if !defined(LE_NOLANCE)
1121 /*
1122 * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
1123 *
1124 * Start of DEPCA (DE200/DE201/DE202/DE422 etal) support.
1125 *
1126 */
1127 static void depca_intr(le_softc_t *sc);
1128 static int lance_init_adapmem(le_softc_t *sc);
1129 static int lance_init_ring(le_softc_t *sc, ln_ring_t *rp, lance_ring_t *ri,
1130 unsigned ndescs, unsigned bufoffset,
1131 unsigned descoffset);
1132 static void lance_init(void *);
1133 static void lance_reset(le_softc_t *sc);
1134 static void lance_intr(le_softc_t *sc);
1135 static int lance_rx_intr(le_softc_t *sc);
1136 static void lance_start(struct ifnet *ifp);
1137 static int lance_tx_intr(le_softc_t *sc);
1138
1139 #define LN_BUFSIZE /* 380 */ 304 /* 1520 / 4 */
1140 #define LN_TXDESC_RATIO 2048
1141 #define LN_DESC_MAX 128
1142
1143 #if LN_DOSTATS
1144 static struct {
1145 unsigned lance_rx_misses;
1146 unsigned lance_rx_badcrc;
1147 unsigned lance_rx_badalign;
1148 unsigned lance_rx_badframe;
1149 unsigned lance_rx_buferror;
1150 unsigned lance_tx_deferred;
1151 unsigned lance_tx_single_collisions;
1152 unsigned lance_tx_multiple_collisions;
1153 unsigned lance_tx_excessive_collisions;
1154 unsigned lance_tx_late_collisions;
1155
1156 unsigned lance_memory_errors;
1157 unsigned lance_inits;
1158 unsigned lance_tx_intrs;
1159 unsigned lance_tx_nospc[2];
1160 unsigned lance_tx_drains[2];
1161 unsigned lance_tx_orphaned;
1162 unsigned lance_tx_adoptions;
1163 unsigned lance_tx_emptied;
1164 unsigned lance_tx_deftxint;
1165 unsigned lance_tx_buferror;
1166 unsigned lance_high_txoutptr;
1167 unsigned lance_low_txheapsize;
1168 unsigned lance_low_txfree;
1169 unsigned lance_tx_intr_hidescs;
1170 /* unsigned lance_tx_intr_descs[LN_DESC_MAX]; */
1171
1172 unsigned lance_rx_intrs;
1173 unsigned lance_rx_badsop;
1174 unsigned lance_rx_contig;
1175 unsigned lance_rx_noncontig;
1176 unsigned lance_rx_intr_hidescs;
1177 unsigned lance_rx_ndescs[4096 / LN_BUFSIZE];
1178 /* unsigned lance_rx_intr_descs[LN_DESC_MAX]; */
1179 } lance_stats;
1180
1181 #define LN_STAT(stat) (lance_stats.lance_ ## stat)
1182 #define LN_MINSTAT(stat, val) (LN_STAT(stat > (val)) ? LN_STAT(stat = (val)) : 0)
1183 #define LN_MAXSTAT(stat, val) (LN_STAT(stat < (val)) ? LN_STAT(stat = (val)) : 0)
1184
1185 #else
1186 #define LN_STAT(stat) 0
1187 #define LN_MINSTAT(stat, val) 0
1188 #define LN_MAXSTAT(stat, val) 0
1189 #endif
1190
1191 #define LN_SELCSR(sc, csrno) (LE_OUTW(sc, sc->lance_rap, csrno))
1192 #define LN_INQCSR(sc) (LE_INW(sc, sc->lance_rap))
1193
1194 #define LN_WRCSR(sc, val) (LE_OUTW(sc, sc->lance_rdp, val))
1195 #define LN_RDCSR(sc) (LE_INW(sc, sc->lance_rdp))
1196
1197
1198 #define LN_ZERO(sc, vaddr, len) bzero(vaddr, len)
1199 #define LN_COPYTO(sc, from, to, len) bcopy(from, to, len)
1200
1201 #define LN_SETFLAG(sc, vaddr, val) \
1202 (((volatile u_char *) vaddr)[3] = (val))
1203
1204 #define LN_PUTDESC(sc, desc, vaddr) \
1205 (((volatile u_short *) vaddr)[0] = ((u_short *) desc)[0], \
1206 ((volatile u_short *) vaddr)[2] = ((u_short *) desc)[2], \
1207 ((volatile u_short *) vaddr)[1] = ((u_short *) desc)[1])
1208
1209 /*
1210 * Only get the descriptor flags and length/status. All else
1211 * read-only.
1212 */
1213 #define LN_GETDESC(sc, desc, vaddr) \
1214 (((u_short *) desc)[1] = ((volatile u_short *) vaddr)[1], \
1215 ((u_short *) desc)[3] = ((volatile u_short *) vaddr)[3])
1216
1217
1218 /*
1219 * These definitions are specific to the DEC "DEPCA-style" NICs.
1220 * (DEPCA, DE10x, DE20[012], DE422)
1221 *
1222 */
1223 #define DEPCA_REG_NICSR 0 /* (RW;16) NI Control / Status */
1224 #define DEPCA_REG_RDP 4 /* (RW:16) LANCE RDP (data) register */
1225 #define DEPCA_REG_RAP 6 /* (RW:16) LANCE RAP (address) register */
1226 #define DEPCA_REG_ADDRROM 12 /* (R : 8) DEPCA Ethernet Address ROM */
1227 #define DEPCA_IOSPACE 16 /* DEPCAs use 16 bytes of IO space */
1228
1229 #define DEPCA_NICSR_LED 0x0001 /* Light the LED on the back of the DEPCA */
1230 #define DEPCA_NICSR_ENABINTR 0x0002 /* Enable Interrupts */
1231 #define DEPCA_NICSR_MASKINTR 0x0004 /* Mask Interrupts */
1232 #define DEPCA_NICSR_AAC 0x0008 /* Address Counter Clear */
1233 #define DEPCA_NICSR_REMOTEBOOT 0x0010 /* Remote Boot Enabled (ignored) */
1234 #define DEPCA_NICSR_32KRAM 0x0020 /* DEPCA LANCE RAM size 64K (C) / 32K (S) */
1235 #define DEPCA_NICSR_LOW32K 0x0040 /* Bank Select (A15 = !This Bit) */
1236 #define DEPCA_NICSR_SHE 0x0080 /* Shared RAM Enabled (ie hide ROM) */
1237 #define DEPCA_NICSR_BOOTTMO 0x0100 /* Remote Boot Timeout (ignored) */
1238
1239 #define DEPCA_RDNICSR(sc) (LE_INW(sc, DEPCA_REG_NICSR))
1240 #define DEPCA_WRNICSR(sc, val) (LE_OUTW(sc, DEPCA_REG_NICSR, val))
1241
1242 #define DEPCA_IDSTR_OFFSET 0xC006 /* ID String Offset */
1243
1244 #define DEPCA_REG_EISAID 0x80
1245 #define DEPCA_EISAID_MASK 0xf0ffffff
1246 #define DEPCA_EISAID_DE422 0x2042A310
1247
1248 typedef enum {
1249 DEPCA_CLASSIC,
1250 DEPCA_DE100, DEPCA_DE101,
1251 DEPCA_EE100,
1252 DEPCA_DE200, DEPCA_DE201, DEPCA_DE202,
1253 DEPCA_DE422,
1254 DEPCA_UNKNOWN
1255 } depca_t;
1256
1257 static const char *depca_signatures[] = {
1258 "DEPCA",
1259 "DE100", "DE101",
1260 "EE100",
1261 "DE200", "DE201", "DE202",
1262 "DE422",
1263 NULL
1264 };
1265
1266 static int
1267 depca_probe(
1268 le_softc_t *sc,
1269 const le_board_t *bd,
1270 int *msize)
1271 {
1272 unsigned nicsr, idx, idstr_offset = DEPCA_IDSTR_OFFSET;
1273
1274 /*
1275 * Find out how memory we are dealing with. Adjust
1276 * the ID string offset approriately if we are at
1277 * 32K. Make sure the ROM is enabled.
1278 */
1279 nicsr = DEPCA_RDNICSR(sc);
1280 nicsr &= ~(DEPCA_NICSR_SHE|DEPCA_NICSR_LED|DEPCA_NICSR_ENABINTR);
1281
1282 if (nicsr & DEPCA_NICSR_32KRAM) {
1283 /*
1284 * Make we are going to read the upper
1285 * 32K so we do read the ROM.
1286 */
1287 sc->lance_ramsize = 32 * 1024;
1288 nicsr &= ~DEPCA_NICSR_LOW32K;
1289 sc->lance_ramoffset = 32 * 1024;
1290 idstr_offset -= sc->lance_ramsize;
1291 } else {
1292 sc->lance_ramsize = 64 * 1024;
1293 sc->lance_ramoffset = 0;
1294 }
1295 DEPCA_WRNICSR(sc, nicsr);
1296
1297 sc->le_prodname = NULL;
1298 for (idx = 0; depca_signatures[idx] != NULL; idx++) {
1299 if (bcmp(depca_signatures[idx], sc->le_membase + idstr_offset, 5) == 0) {
1300 sc->le_prodname = depca_signatures[idx];
1301 break;
1302 }
1303 }
1304
1305 if (sc->le_prodname == NULL) {
1306 /*
1307 * Try to get the EISA device if it's a DE422.
1308 */
1309 if (sc->le_iobase > 0x1000 && (sc->le_iobase & 0x0F00) == 0x0C00
1310 && (LE_INL(sc, DEPCA_REG_EISAID) & DEPCA_EISAID_MASK)
1311 == DEPCA_EISAID_DE422) {
1312 sc->le_prodname = "DE422";
1313 } else {
1314 return 0;
1315 }
1316 }
1317 if (idx == DEPCA_CLASSIC)
1318 sc->lance_ramsize -= 16384; /* Can't use the ROM area on a DEPCA */
1319
1320 /*
1321 * Try to read the address ROM.
1322 * Stop the LANCE, reset the Address ROM Counter (AAC),
1323 * read the NICSR to "clock" in the reset, and then
1324 * re-enable the Address ROM Counter. Now read the
1325 * address ROM.
1326 */
1327 sc->lance_rdp = DEPCA_REG_RDP;
1328 sc->lance_rap = DEPCA_REG_RAP;
1329 sc->lance_csr3 = LN_CSR3_ALE;
1330 sc->le_mctbl = sc->lance_initb.ln_multi_mask;
1331 sc->le_mcmask = LN_MC_MASK;
1332 LN_SELCSR(sc, LN_CSR0);
1333 LN_WRCSR(sc, LN_CSR0_STOP);
1334
1335 if (idx < DEPCA_DE200) {
1336 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) & ~DEPCA_NICSR_AAC);
1337 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_AAC);
1338 }
1339
1340 if (le_read_macaddr(sc, DEPCA_REG_ADDRROM, idx == DEPCA_CLASSIC) < 0)
1341 return 0;
1342
1343 MEMCPY(sc->le_ac.ac_enaddr, sc->le_hwaddr, 6);
1344 /*
1345 * Renable shared RAM.
1346 */
1347 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) | DEPCA_NICSR_SHE);
1348
1349 le_intrvec[sc->le_unit] = depca_intr;
1350 if (!lance_init_adapmem(sc))
1351 return 0;
1352
1353 sc->if_reset = lance_reset;
1354 sc->if_init = lance_init;
1355 sc->le_if.if_start = lance_start;
1356 DEPCA_WRNICSR(sc, DEPCA_NICSR_SHE | DEPCA_NICSR_ENABINTR);
1357 sc->if_reset(sc);
1358
1359 LN_STAT(low_txfree = sc->lance_txinfo.ri_max);
1360 LN_STAT(low_txheapsize = 0xFFFFFFFF);
1361 *msize = sc->lance_ramsize;
1362 return DEPCA_IOSPACE;
1363 }
1364
1365 static void
1366 depca_intr(
1367 le_softc_t *sc)
1368 {
1369 DEPCA_WRNICSR(sc, DEPCA_RDNICSR(sc) ^ DEPCA_NICSR_LED);
1370 lance_intr(sc);
1371 }
1372
1373 /*
1374 * Here's as good a place to describe our paritioning of the
1375 * LANCE shared RAM space. (NOTE: this driver does not yet support
1376 * the concept of a LANCE being able to DMA).
1377 *
1378 * First is the 24 (00:23) bytes for LANCE Initialization Block
1379 * Next are the recieve descriptors. The number is calculated from
1380 * how many LN_BUFSIZE buffers we can allocate (this number must
1381 * be a power of 2). Next are the transmit descriptors. The amount
1382 * of transmit descriptors is derived from the size of the RAM
1383 * divided by 1K. Now come the receive buffers (one for each receive
1384 * descriptor). Finally is the transmit heap. (no fixed buffers are
1385 * allocated so as to make the most use of the limited space).
1386 */
1387 static int
1388 lance_init_adapmem(
1389 le_softc_t *sc)
1390 {
1391 lance_addr_t rxbufoffset;
1392 lance_addr_t rxdescoffset, txdescoffset;
1393 unsigned rxdescs, txdescs;
1394
1395 /*
1396 * First calculate how many descriptors we heap.
1397 * Note this assumes the ramsize is a power of two.
1398 */
1399 sc->lance_rxbufsize = LN_BUFSIZE;
1400 rxdescs = 1;
1401 while (rxdescs * sc->lance_rxbufsize < sc->lance_ramsize)
1402 rxdescs *= 2;
1403 rxdescs /= 2;
1404 if (rxdescs > LN_DESC_MAX) {
1405 sc->lance_rxbufsize *= rxdescs / LN_DESC_MAX;
1406 rxdescs = LN_DESC_MAX;
1407 }
1408 txdescs = sc->lance_ramsize / LN_TXDESC_RATIO;
1409 if (txdescs > LN_DESC_MAX)
1410 txdescs = LN_DESC_MAX;
1411
1412 /*
1413 * Now calculate where everything goes in memory
1414 */
1415 rxdescoffset = sizeof(ln_initb_t);
1416 txdescoffset = rxdescoffset + sizeof(ln_desc_t) * rxdescs;
1417 rxbufoffset = txdescoffset + sizeof(ln_desc_t) * txdescs;
1418
1419 sc->le_mctbl = (le_mcbits_t *) sc->lance_initb.ln_multi_mask;
1420 /*
1421 * Remember these for debugging.
1422 */
1423 sc->lance_raminitb = (ln_initb_t *) sc->le_membase;
1424 sc->lance_ramdesc = (ln_desc_t *) (sc->le_membase + rxdescoffset);
1425
1426 /*
1427 * Initialize the rings.
1428 */
1429 if (!lance_init_ring(sc, &sc->lance_initb.ln_rxring, &sc->lance_rxinfo,
1430 rxdescs, rxbufoffset, rxdescoffset))
1431 return 0;
1432 sc->lance_rxinfo.ri_heap = rxbufoffset;
1433 sc->lance_rxinfo.ri_heapend = rxbufoffset + sc->lance_rxbufsize * rxdescs;
1434
1435 if (!lance_init_ring(sc, &sc->lance_initb.ln_txring, &sc->lance_txinfo,
1436 txdescs, 0, txdescoffset))
1437 return 0;
1438 sc->lance_txinfo.ri_heap = sc->lance_rxinfo.ri_heapend;
1439 sc->lance_txinfo.ri_heapend = sc->lance_ramsize;
1440
1441 /*
1442 * Set CSR1 and CSR2 to the address of the init block (which
1443 * for us is always 0.
1444 */
1445 sc->lance_csr1 = LN_ADDR_LO(0 + sc->lance_ramoffset);
1446 sc->lance_csr2 = LN_ADDR_HI(0 + sc->lance_ramoffset);
1447 return 1;
1448 }
1449
1450 static int
1451 lance_init_ring(
1452 le_softc_t *sc,
1453 ln_ring_t *rp,
1454 lance_ring_t *ri,
1455 unsigned ndescs,
1456 lance_addr_t bufoffset,
1457 lance_addr_t descoffset)
1458 {
1459 lance_descinfo_t *di;
1460
1461 /*
1462 * Initialize the ring pointer in the LANCE InitBlock
1463 */
1464 rp->r_addr_lo = LN_ADDR_LO(descoffset + sc->lance_ramoffset);
1465 rp->r_addr_hi = LN_ADDR_HI(descoffset + sc->lance_ramoffset);
1466 rp->r_log2_size = ffs(ndescs) - 1;
1467
1468 /*
1469 * Allocate the ring entry descriptors and initialize
1470 * our ring information data structure. All these are
1471 * our copies and do not live in the LANCE RAM.
1472 */
1473 ri->ri_first = (lance_descinfo_t *) malloc(ndescs * sizeof(*di), M_DEVBUF, M_NOWAIT);
1474 if (ri->ri_first == NULL) {
1475 printf("lance_init_ring: malloc(%d) failed\n", ndescs * sizeof(*di));
1476 return 0;
1477 }
1478 ri->ri_free = ri->ri_max = ndescs;
1479 ri->ri_last = ri->ri_first + ri->ri_max;
1480 for (di = ri->ri_first; di < ri->ri_last; di++) {
1481 di->di_addr = sc->le_membase + descoffset;
1482 di->di_mbuf = NULL;
1483 if (bufoffset) {
1484 di->di_bufaddr = bufoffset;
1485 di->di_buflen = sc->lance_rxbufsize;
1486 bufoffset += sc->lance_rxbufsize;
1487 }
1488 descoffset += sizeof(ln_desc_t);
1489 }
1490 return 1;
1491 }
1492
1493 static void
1494 lance_dumpcsrs(
1495 le_softc_t *sc,
1496 const char *id)
1497 {
1498 if_printf(&sc->le_if, "%s: nicsr=%04x", id, DEPCA_RDNICSR(sc));
1499 LN_SELCSR(sc, LN_CSR0); printf(" csr0=%04x", LN_RDCSR(sc));
1500 LN_SELCSR(sc, LN_CSR1); printf(" csr1=%04x", LN_RDCSR(sc));
1501 LN_SELCSR(sc, LN_CSR2); printf(" csr2=%04x", LN_RDCSR(sc));
1502 LN_SELCSR(sc, LN_CSR3); printf(" csr3=%04x\n", LN_RDCSR(sc));
1503 LN_SELCSR(sc, LN_CSR0);
1504 }
1505
1506 static void
1507 lance_reset(
1508 le_softc_t *sc)
1509 {
1510 register int cnt, csr;
1511
1512 /* lance_dumpcsrs(sc, "lance_reset: start"); */
1513
1514 LN_WRCSR(sc, LN_RDCSR(sc) & ~LN_CSR0_ENABINTR);
1515 LN_WRCSR(sc, LN_CSR0_STOP);
1516 DELAY(100);
1517
1518 sc->le_flags &= ~IFF_UP;
1519 sc->le_if.if_flags &= ~(IFF_UP|IFF_RUNNING);
1520
1521 le_multi_filter(sc); /* initialize the multicast table */
1522 if ((sc->le_flags | sc->le_if.if_flags) & IFF_ALLMULTI) {
1523 sc->lance_initb.ln_multi_mask[0] = 0xFFFFU;
1524 sc->lance_initb.ln_multi_mask[1] = 0xFFFFU;
1525 sc->lance_initb.ln_multi_mask[2] = 0xFFFFU;
1526 sc->lance_initb.ln_multi_mask[3] = 0xFFFFU;
1527 }
1528 sc->lance_initb.ln_physaddr[0] = ((u_short *) sc->le_ac.ac_enaddr)[0];
1529 sc->lance_initb.ln_physaddr[1] = ((u_short *) sc->le_ac.ac_enaddr)[1];
1530 sc->lance_initb.ln_physaddr[2] = ((u_short *) sc->le_ac.ac_enaddr)[2];
1531 if (sc->le_if.if_flags & IFF_PROMISC) {
1532 sc->lance_initb.ln_mode |= LN_MODE_PROMISC;
1533 } else {
1534 sc->lance_initb.ln_mode &= ~LN_MODE_PROMISC;
1535 }
1536 /*
1537 * We force the init block to be at the start
1538 * of the LANCE's RAM buffer.
1539 */
1540 LN_COPYTO(sc, &sc->lance_initb, sc->le_membase, sizeof(sc->lance_initb));
1541 LN_SELCSR(sc, LN_CSR1); LN_WRCSR(sc, sc->lance_csr1);
1542 LN_SELCSR(sc, LN_CSR2); LN_WRCSR(sc, sc->lance_csr2);
1543 LN_SELCSR(sc, LN_CSR3); LN_WRCSR(sc, sc->lance_csr3);
1544
1545 /* lance_dumpcsrs(sc, "lance_reset: preinit"); */
1546
1547 /*
1548 * clear INITDONE and INIT the chip
1549 */
1550 LN_SELCSR(sc, LN_CSR0);
1551 LN_WRCSR(sc, LN_CSR0_INIT|LN_CSR0_INITDONE);
1552
1553 csr = 0;
1554 cnt = 100;
1555 while (cnt-- > 0) {
1556 if (((csr = LN_RDCSR(sc)) & LN_CSR0_INITDONE) != 0)
1557 break;
1558 DELAY(10000);
1559 }
1560
1561 if ((csr & LN_CSR0_INITDONE) == 0) { /* make sure we got out okay */
1562 lance_dumpcsrs(sc, "lance_reset: reset failure");
1563 } else {
1564 /* lance_dumpcsrs(sc, "lance_reset: end"); */
1565 sc->le_if.if_flags |= IFF_UP;
1566 sc->le_flags |= IFF_UP;
1567 }
1568 }
1569
1570 static void
1571 lance_init(void *xsc)
1572 {
1573 le_softc_t *sc;
1574 lance_ring_t *ri;
1575 lance_descinfo_t *di;
1576 ln_desc_t desc;
1577
1578 sc = (le_softc_t *)xsc;
1579
1580 LN_STAT(inits++);
1581 if (sc->le_if.if_flags & IFF_RUNNING) {
1582 sc->if_reset(sc);
1583 lance_tx_intr(sc);
1584 /*
1585 * If we were running, requeue any pending transmits.
1586 */
1587 ri = &sc->lance_txinfo;
1588 di = ri->ri_nextout;
1589 while (ri->ri_free < ri->ri_max) {
1590 if (--di == ri->ri_first)
1591 di = ri->ri_nextout - 1;
1592 if (di->di_mbuf == NULL)
1593 break;
1594 IF_PREPEND(&sc->le_if.if_snd, di->di_mbuf);
1595 di->di_mbuf = NULL;
1596 ri->ri_free++;
1597 }
1598 } else {
1599 sc->if_reset(sc);
1600 }
1601
1602 /*
1603 * Reset the transmit ring. Make sure we own all the buffers.
1604 * Also reset the transmit heap.
1605 */
1606 sc->le_if.if_flags &= ~IFF_OACTIVE;
1607 ri = &sc->lance_txinfo;
1608 for (di = ri->ri_first; di < ri->ri_last; di++) {
1609 if (di->di_mbuf != NULL) {
1610 m_freem(di->di_mbuf);
1611 di->di_mbuf = NULL;
1612 }
1613 desc.d_flag = 0;
1614 desc.d_addr_lo = LN_ADDR_LO(ri->ri_heap + sc->lance_ramoffset);
1615 desc.d_addr_hi = LN_ADDR_HI(ri->ri_heap + sc->lance_ramoffset);
1616 desc.d_buflen = 0;
1617 LN_PUTDESC(sc, &desc, di->di_addr);
1618 }
1619 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1620 ri->ri_free = ri->ri_max;
1621 ri->ri_outptr = ri->ri_heap;
1622 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1623
1624 ri = &sc->lance_rxinfo;
1625 desc.d_flag = LN_DFLAG_OWNER;
1626 desc.d_buflen = 0 - sc->lance_rxbufsize;
1627 for (di = ri->ri_first; di < ri->ri_last; di++) {
1628 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1629 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1630 LN_PUTDESC(sc, &desc, di->di_addr);
1631 }
1632 ri->ri_nextin = ri->ri_nextout = ri->ri_first;
1633 ri->ri_outptr = ri->ri_heap;
1634 ri->ri_outsize = ri->ri_heapend - ri->ri_heap;
1635 ri->ri_free = 0;
1636
1637 if (sc->le_if.if_flags & IFF_UP) {
1638 sc->le_if.if_flags |= IFF_RUNNING;
1639 LN_WRCSR(sc, LN_CSR0_START|LN_CSR0_INITDONE|LN_CSR0_ENABINTR);
1640 /* lance_dumpcsrs(sc, "lance_init: up"); */
1641 lance_start(&sc->le_if);
1642 } else {
1643 /* lance_dumpcsrs(sc, "lance_init: down"); */
1644 sc->le_if.if_flags &= ~IFF_RUNNING;
1645 }
1646 }
1647
1648 static void
1649 lance_intr(
1650 le_softc_t *sc)
1651 {
1652 unsigned oldcsr;
1653
1654 oldcsr = LN_RDCSR(sc);
1655 oldcsr &= ~LN_CSR0_ENABINTR;
1656 LN_WRCSR(sc, oldcsr);
1657 LN_WRCSR(sc, LN_CSR0_ENABINTR);
1658
1659 if (oldcsr & LN_CSR0_ERRSUM) {
1660 if (oldcsr & LN_CSR0_MISS) {
1661 /*
1662 * LN_CSR0_MISS is signaled when the LANCE receiver
1663 * loses a packet because it doesn't own a receive
1664 * descriptor. Rev. D LANCE chips, which are no
1665 * longer used, require a chip reset as described
1666 * below.
1667 */
1668 LN_STAT(rx_misses++);
1669 }
1670 if (oldcsr & LN_CSR0_MEMERROR) {
1671 LN_STAT(memory_errors++);
1672 if (oldcsr & (LN_CSR0_RXON|LN_CSR0_TXON)) {
1673 lance_init(sc);
1674 return;
1675 }
1676 }
1677 }
1678
1679 if ((oldcsr & LN_CSR0_RXINT) && lance_rx_intr(sc)) {
1680 lance_init(sc);
1681 return;
1682 }
1683
1684 if (oldcsr & LN_CSR0_TXINT) {
1685 if (lance_tx_intr(sc))
1686 lance_start(&sc->le_if);
1687 }
1688
1689 if (oldcsr == (LN_CSR0_PENDINTR|LN_CSR0_RXON|LN_CSR0_TXON))
1690 if_printf(&sc->le_if, "lance_intr: stray interrupt\n");
1691 }
1692
1693 static int
1694 lance_rx_intr(
1695 le_softc_t *sc)
1696 {
1697 lance_ring_t *ri = &sc->lance_rxinfo;
1698 lance_descinfo_t *eop;
1699 ln_desc_t desc;
1700 int ndescs, total_len, rxdescs;
1701
1702 LN_STAT(rx_intrs++);
1703
1704 for (rxdescs = 0;;) {
1705 /*
1706 * Now to try to find the end of this packet chain.
1707 */
1708 for (ndescs = 1, eop = ri->ri_nextin;; ndescs++) {
1709 /*
1710 * If we don't own this descriptor, the packet ain't
1711 * all here so return because we are done.
1712 */
1713 LN_GETDESC(sc, &desc, eop->di_addr);
1714 if (desc.d_flag & LN_DFLAG_OWNER)
1715 return 0;
1716 /*
1717 * In case we have missed a packet and gotten the
1718 * LANCE confused, make sure we are pointing at the
1719 * start of a packet. If we aren't, something is really
1720 * strange so reinit the LANCE.
1721 */
1722 if (desc.d_flag & LN_DFLAG_RxBUFERROR) {
1723 LN_STAT(rx_buferror++);
1724 return 1;
1725 }
1726 if ((desc.d_flag & LN_DFLAG_SOP) && eop != ri->ri_nextin) {
1727 LN_STAT(rx_badsop++);
1728 return 1;
1729 }
1730 if (desc.d_flag & LN_DFLAG_EOP)
1731 break;
1732 if (++eop == ri->ri_last)
1733 eop = ri->ri_first;
1734 }
1735
1736 total_len = (desc.d_status & LN_DSTS_RxLENMASK) - 4;
1737 if ((desc.d_flag & LN_DFLAG_RxERRSUM) == 0) {
1738 /*
1739 * Valid Packet -- If the SOP is less than or equal to the EOP
1740 * or the length is less than the receive buffer size, then the
1741 * packet is contiguous in memory and can be copied in one shot.
1742 * Otherwise we need to copy two segments to get the entire
1743 * packet.
1744 */
1745 if (ri->ri_nextin <= eop || total_len <= ri->ri_heapend - ri->ri_nextin->di_bufaddr) {
1746 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1747 total_len, total_len, NULL);
1748 LN_STAT(rx_contig++);
1749 } else {
1750 le_input(sc, sc->le_membase + ri->ri_nextin->di_bufaddr,
1751 total_len,
1752 ri->ri_heapend - ri->ri_nextin->di_bufaddr,
1753 sc->le_membase + ri->ri_first->di_bufaddr);
1754 LN_STAT(rx_noncontig++);
1755 }
1756 } else {
1757 /*
1758 * If the packet is bad, increment the
1759 * counters.
1760 */
1761 sc->le_if.if_ierrors++;
1762 if (desc.d_flag & LN_DFLAG_RxBADCRC)
1763 LN_STAT(rx_badcrc++);
1764 if (desc.d_flag & LN_DFLAG_RxOVERFLOW)
1765 LN_STAT(rx_badalign++);
1766 if (desc.d_flag & LN_DFLAG_RxFRAMING)
1767 LN_STAT(rx_badframe++);
1768 }
1769 sc->le_if.if_ipackets++;
1770 LN_STAT(rx_ndescs[ndescs-1]++);
1771 rxdescs += ndescs;
1772 while (ndescs-- > 0) {
1773 LN_SETFLAG(sc, ri->ri_nextin->di_addr, LN_DFLAG_OWNER);
1774 if (++ri->ri_nextin == ri->ri_last)
1775 ri->ri_nextin = ri->ri_first;
1776 }
1777 }
1778 /* LN_STAT(rx_intr_descs[rxdescs]++); */
1779 LN_MAXSTAT(rx_intr_hidescs, rxdescs);
1780
1781 return 0;
1782 }
1783
1784 static void
1785 lance_start(
1786 struct ifnet *ifp)
1787 {
1788 le_softc_t *sc = (le_softc_t *) ifp;
1789 struct ifqueue *ifq = &ifp->if_snd;
1790 lance_ring_t *ri = &sc->lance_txinfo;
1791 lance_descinfo_t *di;
1792 ln_desc_t desc;
1793 unsigned len, slop;
1794 struct mbuf *m, *m0;
1795 caddr_t bp;
1796
1797 if ((ifp->if_flags & IFF_RUNNING) == 0)
1798 return;
1799
1800 for (;;) {
1801 IF_DEQUEUE(ifq, m);
1802 if (m == NULL)
1803 break;
1804
1805 /*
1806 * Make the packet meets the minimum size for Ethernet.
1807 * The slop is so that we also use an even number of longwards.
1808 */
1809 len = ETHERMIN + sizeof(struct ether_header);
1810 if (m->m_pkthdr.len > len)
1811 len = m->m_pkthdr.len;
1812
1813 slop = (8 - len) & 3;
1814 /*
1815 * If there are no free ring entries (there must be always
1816 * one owned by the host), or there's not enough space for
1817 * this packet, or this packet would wrap around the end
1818 * of LANCE RAM then wait for the transmits to empty for
1819 * space and ring entries to become available.
1820 */
1821 if (ri->ri_free == 1 || len + slop > ri->ri_outsize) {
1822 /*
1823 * Try to see if we can free up anything off the transit ring.
1824 */
1825 if (lance_tx_intr(sc) > 0) {
1826 LN_STAT(tx_drains[0]++);
1827 IF_PREPEND(ifq, m);
1828 continue;
1829 }
1830 LN_STAT(tx_nospc[0]++);
1831 break;
1832 }
1833
1834 if (len + slop > ri->ri_heapend - ri->ri_outptr) {
1835 /*
1836 * Since the packet won't fit in the end of the transmit
1837 * heap, see if there is space at the beginning of the transmit
1838 * heap. If not, try again when there is space.
1839 */
1840 LN_STAT(tx_orphaned++);
1841 slop += ri->ri_heapend - ri->ri_outptr;
1842 if (len + slop > ri->ri_outsize) {
1843 LN_STAT(tx_nospc[1]++);
1844 break;
1845 }
1846 /*
1847 * Point to the beginning of the heap
1848 */
1849 ri->ri_outptr = ri->ri_heap;
1850 LN_STAT(tx_adoptions++);
1851 }
1852
1853 /*
1854 * Initialize the descriptor (saving the buffer address,
1855 * buffer length, and mbuf) and write the packet out
1856 * to the board.
1857 */
1858 di = ri->ri_nextout;
1859 di->di_bufaddr = ri->ri_outptr;
1860 di->di_buflen = len + slop;
1861 di->di_mbuf = m;
1862 bp = sc->le_membase + di->di_bufaddr;
1863 for (m0 = m; m0 != NULL; m0 = m0->m_next) {
1864 LN_COPYTO(sc, mtod(m0, caddr_t), bp, m0->m_len);
1865 bp += m0->m_len;
1866 }
1867 /*
1868 * Zero out the remainder if needed (< ETHERMIN).
1869 */
1870 if (m->m_pkthdr.len < len)
1871 LN_ZERO(sc, bp, len - m->m_pkthdr.len);
1872
1873 /*
1874 * Finally, copy out the descriptor and tell the
1875 * LANCE to transmit!.
1876 */
1877 desc.d_buflen = 0 - len;
1878 desc.d_addr_lo = LN_ADDR_LO(di->di_bufaddr + sc->lance_ramoffset);
1879 desc.d_addr_hi = LN_ADDR_HI(di->di_bufaddr + sc->lance_ramoffset);
1880 desc.d_flag = LN_DFLAG_SOP|LN_DFLAG_EOP|LN_DFLAG_OWNER;
1881 LN_PUTDESC(sc, &desc, di->di_addr);
1882 LN_WRCSR(sc, LN_CSR0_TXDEMAND|LN_CSR0_ENABINTR);
1883
1884 /*
1885 * Do our bookkeeping with our transmit heap.
1886 * (if we wrap, point back to the beginning).
1887 */
1888 ri->ri_outptr += di->di_buflen;
1889 ri->ri_outsize -= di->di_buflen;
1890 LN_MAXSTAT(high_txoutptr, ri->ri_outptr);
1891 LN_MINSTAT(low_txheapsize, ri->ri_outsize);
1892
1893 if (ri->ri_outptr == ri->ri_heapend)
1894 ri->ri_outptr = ri->ri_heap;
1895
1896 ri->ri_free--;
1897 if (++ri->ri_nextout == ri->ri_last)
1898 ri->ri_nextout = ri->ri_first;
1899 LN_MINSTAT(low_txfree, ri->ri_free);
1900 }
1901 if (m != NULL) {
1902 ifp->if_flags |= IFF_OACTIVE;
1903 IF_PREPEND(ifq, m);
1904 }
1905 }
1906
1907 static int
1908 lance_tx_intr(
1909 le_softc_t *sc)
1910 {
1911 lance_ring_t *ri = &sc->lance_txinfo;
1912 unsigned xmits;
1913
1914 LN_STAT(tx_intrs++);
1915 for (xmits = 0; ri->ri_free < ri->ri_max; ) {
1916 ln_desc_t desc;
1917
1918 LN_GETDESC(sc, &desc, ri->ri_nextin->di_addr);
1919 if (desc.d_flag & LN_DFLAG_OWNER)
1920 break;
1921
1922 if (desc.d_flag & (LN_DFLAG_TxONECOLL|LN_DFLAG_TxMULTCOLL))
1923 sc->le_if.if_collisions++;
1924 if (desc.d_flag & LN_DFLAG_TxDEFERRED)
1925 LN_STAT(tx_deferred++);
1926 if (desc.d_flag & LN_DFLAG_TxONECOLL)
1927 LN_STAT(tx_single_collisions++);
1928 if (desc.d_flag & LN_DFLAG_TxMULTCOLL)
1929 LN_STAT(tx_multiple_collisions++);
1930
1931 if (desc.d_flag & LN_DFLAG_TxERRSUM) {
1932 if (desc.d_status & (LN_DSTS_TxUNDERFLOW|LN_DSTS_TxBUFERROR|
1933 LN_DSTS_TxEXCCOLL|LN_DSTS_TxLATECOLL)) {
1934 if (desc.d_status & LN_DSTS_TxEXCCOLL) {
1935 unsigned tdr;
1936 LN_STAT(tx_excessive_collisions++);
1937 if ((tdr = (desc.d_status & LN_DSTS_TxTDRMASK)) > 0) {
1938 tdr *= 100;
1939 if_printf(&sc->le_if, "lance: warning: excessive collisions: TDR %dns (%d-%dm)\n",
1940 tdr, (tdr*99)/1000, (tdr*117)/1000);
1941 }
1942 }
1943 if (desc.d_status & LN_DSTS_TxBUFERROR)
1944 LN_STAT(tx_buferror++);
1945 sc->le_if.if_oerrors++;
1946 if ((desc.d_status & LN_DSTS_TxLATECOLL) == 0) {
1947 lance_init(sc);
1948 return 0;
1949 } else {
1950 LN_STAT(tx_late_collisions++);
1951 }
1952 }
1953 }
1954 m_freem(ri->ri_nextin->di_mbuf);
1955 ri->ri_nextin->di_mbuf = NULL;
1956 sc->le_if.if_opackets++;
1957 ri->ri_free++;
1958 ri->ri_outsize += ri->ri_nextin->di_buflen;
1959 if (++ri->ri_nextin == ri->ri_last)
1960 ri->ri_nextin = ri->ri_first;
1961 sc->le_if.if_flags &= ~IFF_OACTIVE;
1962 xmits++;
1963 }
1964 if (ri->ri_free == ri->ri_max)
1965 LN_STAT(tx_emptied++);
1966 /* LN_STAT(tx_intr_descs[xmits]++); */
1967 LN_MAXSTAT(tx_intr_hidescs, xmits);
1968 return xmits;
1969 }
1970 #endif /* !defined(LE_NOLANCE) */
Cache object: 969119429eea676e207d642782bfe56e
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