1 #ifndef IF_RDPREG_H
2 #define IF_RDPREG_H 1
3 /*
4 * Copyright (c) 1998 Joerg Wunsch
5 *
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE DEVELOPERS ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE DEVELOPERS BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * $FreeBSD: releng/5.1/sys/i386/isa/if_rdpreg.h 50477 1999-08-28 01:08:13Z peter $
29 */
30
31 /*
32 * Part of the definitions here has been copied over from the REDP
33 * packet driver's REDPPD.INC file. This provides us with the same
34 * set of acronyms as the packet driver is using.
35 *
36 * The packet driver had no copyright, and is believed to be in the
37 * public domain. The author seems to be someone who calls himself
38 * "Chiu", so that's the only acknowledgment i can give here.
39 * Supposedly the author was someone from RealTek.
40 */
41
42 /*
43 * We're hanging upon an LPT port, thus suck in the lpt defs as well.
44 */
45 #include <i386/isa/lptreg.h>
46
47 struct rdphdr {
48 /* RTL8002 header that is prepended to the actual packet */
49 u_char unused2[2];
50 u_short pktlen;
51 u_char status; /* copy of RSR for this packet */
52 u_char unused3[3];
53 };
54
55 /*
56 *
57 * 8 Data Modes are provided:
58 *
59 * +--------+---------------+-------------+
60 * | Mode | Read | Write |
61 * +--------+---------------+-------------+
62 * | 0 | LptCtrl | LptData |
63 * +--------+---------------+-------------+
64 * | 1 | LptCtrl | LptCtrl |
65 * +--------+---------------+-------------+
66 * | 2 | LptCtrl*2 | LptData |
67 * +--------+---------------+-------------+
68 * | 3 | LptCtrl*2 | LptCtrl |
69 * +--------+---------------+-------------+
70 * | 4 | LptData | LptData |
71 * +--------+---------------+-------------+
72 * | 5 | LptData | LptCtrl |
73 * +--------+---------------+-------------+
74 * | 6 | LptData*2 | LptData |
75 * +--------+---------------+-------------+
76 * | 7 | LptData*2 | LptCtrl |
77 * +--------+---------------+-------------+
78 *
79 * Right now, this driver only implements mode 0 (which ought to work
80 * on any standard parallel interface).
81 *
82 */
83
84 /*
85 * Page 0 of EPLC registers
86 */
87 #define IDR0 0x00 /* Ethernet ID register (R/W) */
88 #define IDR1 0x01
89 #define IDR2 0x02
90 #define IDR3 0x03
91 #define IDR4 0x04
92 #define IDR5 0x05
93 #define TBCR0 0x06 /* transmit byte count (W), 11 bits valid */
94 #define TBCR1 0x07
95 #define TSR 0x08 /* transmit status (R), cleared upon next tx */
96 # define TSR_TOK 1 /* transmit OK */
97 # define TSR_TABT 2 /* transmit aborted (excessive collisions) */
98 # define TSR_COL 4 /* collision detected */
99 # define TSR_CDH 8 /* CD heartbeat detected */
100 #define RSR 0x09 /*
101 * receiver status (R), cleared upon next
102 * received packet (but stored in rx buffer
103 * header anyway)
104 */
105 # define RSR_ROK 1 /* receive OK */
106 # define RSR_CRC 2 /* CRC error */
107 # define RSR_FA 4 /* frame alignment error (not multiple of 8) */
108 # define RSR_BUFO 0x10 /* rx buffer overflow, packet discarded */
109 # define RSR_PUN 0x20 /* packet count underflow (jump command issued
110 * but rx buffer was empty) */
111 # define RSR_POV 0x40 /* packet count overflow (more than 254 (?)
112 * packets still in buffer) */
113 #define ISR 0x0A /* interrupt status register (R), writing
114 * clears the written bits */
115 # define ISR_TOK 1 /* transmission OK (~ TSR_TOK) */
116 # define ISR_TER 2 /* transmitter error (~ TSR_TABT) */
117 # define ISR_ROK 4 /* receive OK (~ RSR_ROK) */
118 # define ISR_RER 8 /* receiver error (~ RSR_CRC|RSR_FA) */
119 # define ISR_RBER 0x10 /* rx buffer overflow (POV|PUN|BUFO) */
120 #define IMR 0x0B /* interrupt mask register (R/W), bit as ISR */
121 #define CMR1 0x0C /* command register 1 (R/W) */
122 # define CMR1_BUFE 1 /* (R) rx buffer empty */
123 # define CMR1_IRQ 2 /* (R) interrupt request */
124 # define CMR1_TRA 4 /* (R) transmission in progress */
125 /* (W) transmit start */
126 # define CMR1_TE 0x10 /* (R/W) transmitter enable */
127 # define CMR1_RE 0x20 /* (R/W) receiver enable */
128 # define CMR1_RST 0x40 /* (R/W) reset; sticks until reset completed */
129 # define CMR1_RDPAC 1 /* (W) `rx jump packet', prepare for reading
130 * next packet from ring buffer */
131 # define CMR1_WRPAC 2 /* (W) `tx jump packet', packet in tx buffer
132 * is complete and can be sent */
133 # define CMR1_RETX 8 /* (W) retransmit (must be accomp'ed by TRA) */
134 # define CMR1_MUX 0x80 /* (W) RTL8012: tell the printer MUX to
135 * connect the output pins to the host */
136 #define CMR2 0x0D /* command register 2 (R/W) */
137 # define CMR2_IRQOUT 1 /* interrupt signal output enabled */
138 # define CMR2_RAMTST 2 /* enable RAM test */
139 # define CMR2_PAGE 4 /* select register page #1 */
140 # define CMR2_IRQINV 8 /* make active IRQ `low' */
141 # define CMR2_AMbits 0x30 /* address mode bits: */
142 # define CMR2_AM_NONE 0x00 /* 0: accept nothing */
143 # define CMR2_AM_PHYS 0x10 /* 1: only physical addr */
144 # define CMR2_AM_PB 0x20 /* 2: phys + broadcast */
145 # define CMR2_AM_ALL 0x30 /* 3: promiscuous */
146 # define CMR2_LBK 0x40 /* enable loopback */
147 # define CMR2_SER 0x80 /* save error packet */
148 #define MAR 0x0E /* memory access register (?), used for
149 * remote DMA to the 8002's buffer */
150 #define PNR TBCR0 /* received packet number (R) */
151 #define COLR TBCR1 /* collision count (R) (4 bit valid) */
152
153 /*
154 * Page 1 of EPLC registers -- EEPROM control
155 */
156 #define PCMR TBCR0 /* port command register */
157 /* bits for 93C46 control -- add HNib */
158 #define PCMR_SK 0x04 /* serial clock for EEPROM */
159 #define PCMR_CS 0x02 /* chip select for EEPROM */
160 #define PCMR_DO 0x01 /* DI to EEPROM */
161
162 /* EEPROM data, nibbles for 74S288, bits for 93C46 */
163 #define PDR TBCR1 /* DO from EEPROM, only bit 0 valid for
164 * serial EEPROM */
165
166 /*
167 * The following definitionss define remote DMA command through LptCtrl
168 */
169 #define ATFD 3 /* ATFD bit in Lpt's Control register */
170 /* -> ATFD bit is added for Xircom's MUX */
171 #define Ctrl_LNibRead (0x08+ATFD) /* specify low nibble */
172 #define Ctrl_HNibRead (0+ATFD) /* specify high nibble */
173 #define Ctrl_SelData (0x04+ATFD) /* not through LptCtrl but through */
174 /* LptData */
175 #define Ctrl_IRQEN 0x10 /* set IRQEN of lpt control register */
176
177 /* Here define constants to construct the required read/write commands */
178 #define WrAddr 0x40 /* set address of EPLC write register */
179 #define RdAddr 0x0C0 /* set address of EPLC read register */
180 #define EOR 0x20 /* ORed to make 'end of read',set CSB=1 */
181 #define EOW 0x0E0 /* end of write, R/WB=A/DB=CSB=1 */
182 #define EOC 0x0E0 /* End Of r/w Command, R/WB=A/DB=CSB=1 */
183 #define HNib 0x10
184
185 #define MkHi(value) (((value) >> 4) | HNib)
186
187 #endif /* IF_RDPREG_H */
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