Now available: The Design and Implementation of the FreeBSD Operating System (Second Edition)
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sys/i386/isa/if_sr.c
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1 /* 2 * Copyright (c) 1996 John Hay. 3 * Copyright (c) 1996 SDL Communications, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * Programming assumptions and other issues. 35 * 36 * Only a 16K window will be used. 37 * 38 * The descriptors of a DMA channel will fit in a 16K memory window. 39 * 40 * The buffers of a transmit DMA channel will fit in a 16K memory window. 41 * 42 * When interface is going up, handshaking is set and it is only cleared 43 * when the interface is down'ed. 44 * 45 * There should be a way to set/reset Raw HDLC/PPP, Loopback, DCE/DTE, 46 * internal/external clock, etc..... 47 * 48 */ 49 50 #include "sr.h" 51 #include "opt_netgraph.h" 52 #ifdef NETGRAPH 53 #include <i386/isa/if_sr.h> 54 #else /* NETGRAPH */ 55 #ifdef notyet 56 #include "fr.h" 57 #else 58 #define NFR 0 59 #endif 60 #include "bpfilter.h" 61 #endif /* NETGRAPH */ 62 63 #ifndef NETGRAPH 64 #include "sppp.h" 65 #if NSPPP <= 0 66 #error Device 'sr' requires sppp. 67 #endif 68 #endif /* NETGRAPH */ 69 70 #include <sys/param.h> 71 #include <sys/systm.h> 72 #include <sys/kernel.h> 73 #include <sys/malloc.h> 74 #include <sys/mbuf.h> 75 #include <sys/sockio.h> 76 #include <sys/socket.h> 77 78 #include <net/if.h> 79 #ifdef NETGRAPH 80 #include <sys/syslog.h> 81 #else /* NETGRAPH */ 82 #include <net/if_sppp.h> 83 84 #if NBPFILTER > 0 85 #include <net/bpf.h> 86 #endif /* NBPFILTER > 0 */ 87 #endif /* NETGRAPH */ 88 89 #include <machine/md_var.h> 90 91 #include <i386/isa/if_srregs.h> 92 #include <i386/isa/ic/hd64570.h> 93 #include <i386/isa/isa_device.h> 94 95 #ifdef NETGRAPH 96 #include <netgraph/ng_message.h> 97 #include <netgraph/netgraph.h> 98 #endif /* NETGRAPH */ 99 /* #define USE_MODEMCK */ 100 101 #ifndef BUGGY 102 #define BUGGY 0 103 #endif 104 105 #ifndef NETGRAPH 106 #define PPP_HEADER_LEN 4 107 #endif /* NETGRAPH */ 108 109 /* 110 * These macros are used to hide the difference between the way the 111 * ISA N2 cards and the PCI N2 cards access the Hitachi 64570 SCA. 112 */ 113 #define SRC_GET8(base,off) (*hc->src_get8)(base,(u_int)&off) 114 #define SRC_GET16(base,off) (*hc->src_get16)(base,(u_int)&off) 115 #define SRC_PUT8(base,off,d) (*hc->src_put8)(base,(u_int)&off,d) 116 #define SRC_PUT16(base,off,d) (*hc->src_put16)(base,(u_int)&off,d) 117 118 /* 119 * These macros enable/disable the DPRAM and select the correct 120 * DPRAM page. 121 */ 122 #define SRC_GET_WIN(addr) ((addr >> SRC_WIN_SHFT) & SR_PG_MSK) 123 124 #define SRC_SET_ON(iobase) outb(iobase+SR_PCR, \ 125 SR_PCR_MEM_WIN | inb(iobase+SR_PCR)) 126 #define SRC_SET_MEM(iobase,win) outb(iobase+SR_PSR, SRC_GET_WIN(win) | \ 127 (inb(iobase+SR_PSR) & ~SR_PG_MSK)) 128 #define SRC_SET_OFF(iobase) outb(iobase+SR_PCR, \ 129 ~SR_PCR_MEM_WIN & inb(iobase+SR_PCR)) 130 131 /* 132 * Define the hardware (card information) structure needed to keep 133 * track of the device itself... There is only one per card. 134 */ 135 struct sr_hardc { 136 struct sr_hardc *next; /* PCI card linkage */ 137 struct sr_softc *sc; /* software channels */ 138 int cunit; /* card w/in system */ 139 140 u_short iobase; /* I/O Base Address */ 141 int cardtype; 142 int numports; /* # of ports on cd */ 143 int mempages; 144 u_int memsize; /* DPRAM size: bytes */ 145 u_int winmsk; 146 vm_offset_t sca_base; 147 vm_offset_t mem_pstart; /* start of buffer */ 148 caddr_t mem_start; /* start of DP RAM */ 149 caddr_t mem_end; /* end of DP RAM */ 150 caddr_t plx_base; 151 152 sca_regs *sca; /* register array */ 153 154 /* 155 * We vectorize the following functions to allow re-use between the 156 * ISA card's needs and those of the PCI card. 157 */ 158 void (*src_put8)(u_int base, u_int off, u_int val); 159 void (*src_put16)(u_int base, u_int off, u_int val); 160 u_int (*src_get8)(u_int base, u_int off); 161 u_int (*src_get16)(u_int base, u_int off); 162 }; 163 164 static int next_sc_unit = 0; 165 #ifndef NETGRAPH 166 static int sr_watcher = 0; 167 #endif /* NETGRAPH */ 168 static struct sr_hardc sr_hardc[NSR]; 169 static struct sr_hardc *sr_hardc_pci; 170 171 /* 172 * Define the software interface for the card... There is one for 173 * every channel (port). 174 */ 175 struct sr_softc { 176 #ifndef NETGRAPH 177 struct sppp ifsppp; /* PPP service w/in system */ 178 #endif /* NETGRAPH */ 179 struct sr_hardc *hc; /* card-level information */ 180 181 int unit; /* With regard to all sr devices */ 182 int subunit; /* With regard to this card */ 183 184 #ifndef NETGRAPH 185 int attached; /* attached to FR or PPP */ 186 int protocol; /* FR or PPP */ 187 #define N2_USE_FRP 2 /* Frame Relay Protocol */ 188 #define N2_USE_PPP 1 /* Point-to-Point Protocol */ 189 #endif /* NETGRAPH */ 190 struct buf_block { 191 u_int txdesc; /* DPRAM offset */ 192 u_int txstart;/* DPRAM offset */ 193 u_int txend; /* DPRAM offset */ 194 u_int txtail; /* # of 1st free gran */ 195 u_int txmax; /* # of free grans */ 196 u_int txeda; /* err descr addr */ 197 } block[SR_TX_BLOCKS]; 198 199 char xmit_busy; /* Transmitter is busy */ 200 char txb_inuse; /* # of tx grans in use */ 201 u_int txb_new; /* ndx to new buffer */ 202 u_int txb_next_tx; /* ndx to next gran rdy tx */ 203 204 u_int rxdesc; /* DPRAM offset */ 205 u_int rxstart; /* DPRAM offset */ 206 u_int rxend; /* DPRAM offset */ 207 u_int rxhind; /* ndx to the hd of rx bufrs */ 208 u_int rxmax; /* # of avail grans */ 209 210 u_int clk_cfg; /* Clock configuration */ 211 212 int scachan; /* channel # on card */ 213 #ifdef NETGRAPH 214 int running; /* something is attached so we are running */ 215 int dcd; /* do we have dcd? */ 216 /* ---netgraph bits --- */ 217 char nodename[NG_NODELEN + 1]; /* store our node name */ 218 int datahooks; /* number of data hooks attached */ 219 node_p node; /* netgraph node */ 220 hook_p hook; /* data hook */ 221 hook_p debug_hook; 222 struct ifqueue xmitq_hipri; /* hi-priority transmit queue */ 223 struct ifqueue xmitq; /* transmit queue */ 224 int flags; /* state */ 225 #define SCF_RUNNING 0x01 /* board is active */ 226 #define SCF_OACTIVE 0x02 /* output is active */ 227 int out_dog; /* watchdog cycles output count-down */ 228 #if ( __FreeBSD__ >= 3 ) 229 struct callout_handle handle; /* timeout(9) handle */ 230 #endif 231 u_long inbytes, outbytes; /* stats */ 232 u_long lastinbytes, lastoutbytes; /* a second ago */ 233 u_long inrate, outrate; /* highest rate seen */ 234 u_long inlast; /* last input N secs ago */ 235 u_long out_deficit; /* output since last input */ 236 u_long oerrors, ierrors[6]; 237 u_long opackets, ipackets; 238 #endif /* NETGRAPH */ 239 }; 240 241 #ifdef NETGRAPH 242 #define DOG_HOLDOFF 6 /* dog holds off for 6 secs */ 243 #define QUITE_A_WHILE 300 /* 5 MINUTES */ 244 #define LOTS_OF_PACKETS 100 245 #endif /* NETGRAPH */ 246 247 /* 248 * List of valid interrupt numbers for the N2 ISA card. 249 */ 250 static int sr_irqtable[16] = { 251 0, /* 0 */ 252 0, /* 1 */ 253 0, /* 2 */ 254 1, /* 3 */ 255 1, /* 4 */ 256 1, /* 5 */ 257 0, /* 6 */ 258 1, /* 7 */ 259 0, /* 8 */ 260 0, /* 9 */ 261 1, /* 10 */ 262 1, /* 11 */ 263 1, /* 12 */ 264 0, /* 13 */ 265 0, /* 14 */ 266 1 /* 15 */ 267 }; 268 269 static int srprobe(struct isa_device *id); 270 static int srattach_isa(struct isa_device *id); 271 272 struct isa_driver srdriver = {srprobe, srattach_isa, "src"}; 273 274 /* 275 * Baud Rate table for Sync Mode. 276 * Each entry consists of 3 elements: 277 * Baud Rate (x100) , TMC, BR 278 * 279 * Baud Rate = FCLK / TMC / 2^BR 280 * Baud table for Crystal freq. of 9.8304 Mhz 281 */ 282 #ifdef N2_TEST_SPEED 283 struct rate_line { 284 int target; /* target rate/100 */ 285 int tmc_reg; /* TMC register value */ 286 int br_reg; /* BR (BaudRateClk) selector */ 287 } n2_rates[] = { 288 /* Baudx100 TMC BR */ 289 { 3, 128, 8 }, 290 { 6, 128, 7 }, 291 { 12, 128, 6 }, 292 { 24, 128, 5 }, 293 { 48, 128, 4 }, 294 { 96, 128, 3 }, 295 { 192, 128, 2 }, 296 { 384, 128, 1 }, 297 { 560, 88, 1 }, 298 { 640, 77, 1 }, 299 { 1280, 38, 1 }, 300 { 2560, 19, 1 }, 301 { 5120, 10, 1 }, 302 { 10000, 5, 1 }, 303 { 15000, 3, 1 }, 304 { 25000, 2, 1 }, 305 { 50000, 1, 1 }, 306 { 0, 0, 0 } 307 }; 308 309 int sr_test_speed[] = { 310 N2_TEST_SPEED, 311 N2_TEST_SPEED 312 }; 313 314 int etc0vals[] = { 315 SR_MCR_ETC0, /* ISA channel 0 */ 316 SR_MCR_ETC1, /* ISA channel 1 */ 317 SR_FECR_ETC0, /* PCI channel 0 */ 318 SR_FECR_ETC1 /* PCI channel 1 */ 319 }; 320 #endif 321 322 struct sr_hardc *srattach_pci(int unit, vm_offset_t plx_vaddr, 323 vm_offset_t sca_vaddr); 324 void srintr_hc(struct sr_hardc *hc); 325 326 static ointhand2_t srintr; 327 328 static int srattach(struct sr_hardc *hc); 329 static void sr_xmit(struct sr_softc *sc); 330 #ifndef NETGRAPH 331 static void srstart(struct ifnet *ifp); 332 static int srioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 333 static void srwatchdog(struct ifnet *ifp); 334 #else 335 static void srstart(struct sr_softc *sc); 336 static void srwatchdog(struct sr_softc *sc); 337 #endif /* NETGRAPH */ 338 static int sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat); 339 static void sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len); 340 static void sr_eat_packet(struct sr_softc *sc, int single); 341 static void sr_get_packets(struct sr_softc *sc); 342 343 static void sr_up(struct sr_softc *sc); 344 static void sr_down(struct sr_softc *sc); 345 static void src_init(struct sr_hardc *hc); 346 static void sr_init_sca(struct sr_hardc *hc); 347 static void sr_init_msci(struct sr_softc *sc); 348 static void sr_init_rx_dmac(struct sr_softc *sc); 349 static void sr_init_tx_dmac(struct sr_softc *sc); 350 static void sr_dmac_intr(struct sr_hardc *hc, u_char isr); 351 static void sr_msci_intr(struct sr_hardc *hc, u_char isr); 352 static void sr_timer_intr(struct sr_hardc *hc, u_char isr); 353 #ifndef NETGRAPH 354 static void sr_modemck(void *x); 355 #else 356 static void sr_modemck(struct sr_softc *x); 357 #endif /* NETGRAPH */ 358 359 static u_int src_get8_io(u_int base, u_int off); 360 static u_int src_get16_io(u_int base, u_int off); 361 static void src_put8_io(u_int base, u_int off, u_int val); 362 static void src_put16_io(u_int base, u_int off, u_int val); 363 static u_int src_get8_mem(u_int base, u_int off); 364 static u_int src_get16_mem(u_int base, u_int off); 365 static void src_put8_mem(u_int base, u_int off, u_int val); 366 static void src_put16_mem(u_int base, u_int off, u_int val); 367 368 #ifndef NETGRAPH 369 #if NFR > 0 370 extern void fr_detach(struct ifnet *); 371 extern int fr_attach(struct ifnet *); 372 extern int fr_ioctl(struct ifnet *, int, caddr_t); 373 extern void fr_flush(struct ifnet *); 374 extern int fr_input(struct ifnet *, struct mbuf *); 375 extern struct mbuf *fr_dequeue(struct ifnet *); 376 #endif 377 #else 378 static void ngsr_watchdog_frame(void * arg); 379 static void ngsr_init(void* ignored); 380 381 static ng_constructor_t ngsr_constructor; 382 static ng_rcvmsg_t ngsr_rcvmsg; 383 static ng_shutdown_t ngsr_rmnode; 384 static ng_newhook_t ngsr_newhook; 385 /*static ng_findhook_t ngsr_findhook; */ 386 static ng_connect_t ngsr_connect; 387 static ng_rcvdata_t ngsr_rcvdata; 388 static ng_disconnect_t ngsr_disconnect; 389 390 static struct ng_type typestruct = { 391 NG_VERSION, 392 NG_SR_NODE_TYPE, 393 NULL, 394 ngsr_constructor, 395 ngsr_rcvmsg, 396 ngsr_rmnode, 397 ngsr_newhook, 398 NULL, 399 ngsr_connect, 400 ngsr_rcvdata, 401 ngsr_rcvdata, 402 ngsr_disconnect, 403 NULL 404 }; 405 406 static int ngsr_done_init = 0; 407 #endif /* NETGRAPH */ 408 409 /* 410 * I/O for ISA N2 card(s) 411 */ 412 #define SRC_REG(iobase,y) ((((y) & 0xf) + (((y) & 0xf0) << 6) + \ 413 (iobase)) | 0x8000) 414 415 static u_int 416 src_get8_io(u_int base, u_int off) 417 { 418 return inb(SRC_REG(base, off)); 419 } 420 421 static u_int 422 src_get16_io(u_int base, u_int off) 423 { 424 return inw(SRC_REG(base, off)); 425 } 426 427 static void 428 src_put8_io(u_int base, u_int off, u_int val) 429 { 430 outb(SRC_REG(base, off), val); 431 } 432 433 static void 434 src_put16_io(u_int base, u_int off, u_int val) 435 { 436 outw(SRC_REG(base, off), val); 437 } 438 439 /* 440 * I/O for PCI N2 card(s) 441 */ 442 #define SRC_PCI_SCA_REG(y) ((y & 2) ? ((y & 0xfd) + 0x100) : y) 443 444 static u_int 445 src_get8_mem(u_int base, u_int off) 446 { 447 return *((u_char *)(base + SRC_PCI_SCA_REG(off))); 448 } 449 450 static u_int 451 src_get16_mem(u_int base, u_int off) 452 { 453 return *((u_short *)(base + SRC_PCI_SCA_REG(off))); 454 } 455 456 static void 457 src_put8_mem(u_int base, u_int off, u_int val) 458 { 459 *((u_char *)(base + SRC_PCI_SCA_REG(off))) = (u_char)val; 460 } 461 462 static void 463 src_put16_mem(u_int base, u_int off, u_int val) 464 { 465 *((u_short *)(base + SRC_PCI_SCA_REG(off))) = (u_short)val; 466 } 467 468 /* 469 * Probe for an ISA card. If it is there, size its memory. Then get the 470 * rest of its information and fill it in. 471 */ 472 static int 473 srprobe(struct isa_device *id) 474 { 475 struct sr_hardc *hc = &sr_hardc[id->id_unit]; 476 u_int pgs, i, tmp; 477 u_short port; 478 u_short *smem; 479 u_char mar; 480 sca_regs *sca = 0; 481 482 /* 483 * Now see if the card is realy there. 484 */ 485 hc->cardtype = SR_CRD_N2; 486 487 /* 488 * We have to fill these in early because the SRC_PUT* and SRC_GET* 489 * macros use them. 490 */ 491 hc->src_get8 = src_get8_io; 492 hc->src_get16 = src_get16_io; 493 hc->src_put8 = src_put8_io; 494 hc->src_put16 = src_put16_io; 495 496 hc->sca = 0; 497 port = id->id_iobase; 498 hc->numports = NCHAN; /* assumed # of channels on the card */ 499 500 if (id->id_flags & SR_FLAGS_NCHAN_MSK) 501 hc->numports = id->id_flags & SR_FLAGS_NCHAN_MSK; 502 503 outb(port + SR_PCR, 0); /* turn off the card */ 504 505 /* 506 * Next, we'll test the Base Address Register to retension of 507 * data... ... seeing if we're *really* talking to an N2. 508 */ 509 for (i = 0; i < 0x100; i++) { 510 outb(port + SR_BAR, i); 511 inb(port + SR_PCR); 512 tmp = inb(port + SR_BAR); 513 if (tmp != i) { 514 printf("sr%d: probe failed BAR %x, %x.\n", 515 id->id_unit, i, tmp); 516 return 0; 517 } 518 } 519 520 /* 521 * Now see if we can see the SCA. 522 */ 523 outb(port + SR_PCR, SR_PCR_SCARUN | inb(port + SR_PCR)); 524 SRC_PUT8(port, sca->wcrl, 0); 525 SRC_PUT8(port, sca->wcrm, 0); 526 SRC_PUT8(port, sca->wcrh, 0); 527 SRC_PUT8(port, sca->pcr, 0); 528 SRC_PUT8(port, sca->msci[0].tmc, 0); 529 inb(port); 530 531 tmp = SRC_GET8(port, sca->msci[0].tmc); 532 if (tmp != 0) { 533 printf("sr%d: Error reading SCA 0, %x\n", id->id_unit, tmp); 534 return 0; 535 } 536 SRC_PUT8(port, sca->msci[0].tmc, 0x5A); 537 inb(port); 538 539 tmp = SRC_GET8(port, sca->msci[0].tmc); 540 if (tmp != 0x5A) { 541 printf("sr%d: Error reading SCA 0x5A, %x\n", id->id_unit, tmp); 542 return 0; 543 } 544 SRC_PUT16(port, sca->dmac[0].cda, 0); 545 inb(port); 546 547 tmp = SRC_GET16(port, sca->dmac[0].cda); 548 if (tmp != 0) { 549 printf("sr%d: Error reading SCA 0, %x\n", id->id_unit, tmp); 550 return 0; 551 } 552 SRC_PUT16(port, sca->dmac[0].cda, 0x55AA); 553 inb(port); 554 555 tmp = SRC_GET16(port, sca->dmac[0].cda); 556 if (tmp != 0x55AA) { 557 printf("sr%d: Error reading SCA 0x55AA, %x\n", 558 id->id_unit, tmp); 559 return 0; 560 } 561 /* 562 * OK, the board's interface registers seem to work. Now we'll see 563 * if the Dual-Ported RAM is fully accessible... 564 */ 565 outb(port + SR_PCR, SR_PCR_EN_VPM | SR_PCR_ISA16); 566 outb(port + SR_PSR, SR_PSR_WIN_16K); 567 568 /* 569 * Take the kernel "virtual" address supplied to us and convert 570 * it to a "real" address. Then program the card to use that. 571 */ 572 mar = (kvtop(id->id_maddr) >> 16) & SR_PCR_16M_SEL; 573 outb(port + SR_PCR, mar | inb(port + SR_PCR)); 574 mar = kvtop(id->id_maddr) >> 12; 575 outb(port + SR_BAR, mar); 576 outb(port + SR_PCR, inb(port + SR_PCR) | SR_PCR_MEM_WIN); 577 smem = (u_short *)id->id_maddr; /* DP RAM Address */ 578 579 /* 580 * Here we will perform the memory scan to size the device. 581 * 582 * This is done by marking each potential page with a magic number. 583 * We then loop through the pages looking for that magic number. As 584 * soon as we no longer see that magic number, we'll quit the scan, 585 * knowing that no more memory is present. This provides the number 586 * of pages present on the card. 587 * 588 * Note: We're sizing 16K memory granules. 589 */ 590 for (i = 0; i <= SR_PSR_PG_SEL; i++) { 591 outb(port + SR_PSR, 592 (inb(port + SR_PSR) & ~SR_PSR_PG_SEL) | i); 593 594 *smem = 0xAA55; 595 } 596 597 for (i = 0; i <= SR_PSR_PG_SEL; i++) { 598 outb(port + SR_PSR, 599 (inb(port + SR_PSR) & ~SR_PSR_PG_SEL) | i); 600 601 if (*smem != 0xAA55) { 602 /* 603 * If we have less than 64k of memory, give up. That 604 * is 4 x 16k pages. 605 */ 606 if (i < 4) { 607 printf("sr%d: Bad mem page %d, mem %x, %x.\n", 608 id->id_unit, i, 0xAA55, *smem); 609 return 0; 610 } 611 break; 612 } 613 *smem = i; 614 } 615 616 hc->mempages = i; 617 hc->memsize = i * SRC_WIN_SIZ; 618 hc->winmsk = SRC_WIN_MSK; 619 pgs = i; /* final count of 16K pages */ 620 621 /* 622 * This next loop erases the contents of that page in DPRAM 623 */ 624 for (i = 0; i <= pgs; i++) { 625 outb(port + SR_PSR, 626 (inb(port + SR_PSR) & ~SR_PSR_PG_SEL) | i); 627 bzero(smem, SRC_WIN_SIZ); 628 } 629 630 SRC_SET_OFF(port); 631 632 /* 633 * We have a card here, fill in what we can. 634 */ 635 id->id_msize = SRC_WIN_SIZ; 636 hc->iobase = id->id_iobase; 637 hc->sca_base = id->id_iobase; 638 hc->mem_start = id->id_maddr; 639 hc->mem_end = (id->id_maddr + id->id_msize) - 1; 640 hc->mem_pstart = 0; 641 hc->cunit = id->id_unit; 642 643 /* 644 * Do a little sanity check. 645 */ 646 if (sr_irqtable[ffs(id->id_irq) - 1] == 0) 647 printf("sr%d: Warning: illegal interrupt %d chosen.\n", 648 id->id_unit, ffs(id->id_irq) - 1); 649 650 /* 651 * Bogus card configuration 652 */ 653 if ((hc->numports > NCHAN) /* only 2 ports/card */ 654 ||(hc->memsize > (512 * 1024))) /* no more than 256K */ 655 return 0; 656 657 return SRC_IO_SIZ; /* return the amount of IO addresses used. */ 658 } 659 660 /* 661 * srattach_isa and srattach_pci allocate memory for hardc, softc and 662 * data buffers. It also does any initialization that is bus specific. 663 * At the end they call the common srattach() function. 664 */ 665 static int 666 srattach_isa(struct isa_device *id) 667 { 668 u_char mar; 669 struct sr_hardc *hc = &sr_hardc[id->id_unit]; 670 671 /* 672 * Allocate the software interface table(s) 673 */ 674 MALLOC(hc->sc, struct sr_softc *, 675 hc->numports * sizeof(struct sr_softc), M_DEVBUF, M_WAITOK); 676 if (hc->sc == NULL) 677 return(0); 678 bzero(hc->sc, hc->numports * sizeof(struct sr_softc)); 679 680 id->id_ointr = srintr; 681 682 outb(hc->iobase + SR_PCR, inb(hc->iobase + SR_PCR) | SR_PCR_SCARUN); 683 outb(hc->iobase + SR_PSR, inb(hc->iobase + SR_PSR) | SR_PSR_EN_SCA_DMA); 684 outb(hc->iobase + SR_MCR, 685 SR_MCR_DTR0 | SR_MCR_DTR1 | SR_MCR_TE0 | SR_MCR_TE1); 686 687 SRC_SET_ON(hc->iobase); 688 689 /* 690 * Configure the card. Mem address, irq, 691 */ 692 mar = (kvtop(id->id_maddr) >> 16) & SR_PCR_16M_SEL; 693 outb(hc->iobase + SR_PCR, 694 mar | (inb(hc->iobase + SR_PCR) & ~SR_PCR_16M_SEL)); 695 mar = kvtop(id->id_maddr) >> 12; 696 outb(hc->iobase + SR_BAR, mar); 697 698 /* 699 * Get the TX clock direction and configuration. The default is a 700 * single external clock which is used by RX and TX. 701 */ 702 #ifdef N2_TEST_SPEED 703 if (sr_test_speed[0] > 0) 704 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK; 705 else if (id->id_flags & SR_FLAGS_0_CLK_MSK) 706 hc->sc[0].clk_cfg = 707 (id->id_flags & SR_FLAGS_0_CLK_MSK) 708 >> SR_FLAGS_CLK_SHFT; 709 #else 710 if (id->id_flags & SR_FLAGS_0_CLK_MSK) 711 hc->sc[0].clk_cfg = 712 (id->id_flags & SR_FLAGS_0_CLK_MSK) 713 >> SR_FLAGS_CLK_SHFT; 714 #endif 715 716 if (hc->numports == 2) 717 #ifdef N2_TEST_SPEED 718 if (sr_test_speed[1] > 0) 719 hc->sc[0].clk_cfg = SR_FLAGS_INT_CLK; 720 else 721 #endif 722 if (id->id_flags & SR_FLAGS_1_CLK_MSK) 723 hc->sc[1].clk_cfg = (id->id_flags & SR_FLAGS_1_CLK_MSK) 724 >> (SR_FLAGS_CLK_SHFT + SR_FLAGS_CLK_CHAN_SHFT); 725 726 return srattach(hc); 727 } 728 729 struct sr_hardc * 730 srattach_pci(int unit, vm_offset_t plx_vaddr, vm_offset_t sca_vaddr) 731 { 732 int numports, pndx; 733 u_int fecr, *fecrp = (u_int *)(sca_vaddr + SR_FECR); 734 struct sr_hardc *hc, **hcp; 735 736 /* 737 * Configure the PLX. This is magic. I'm doing it just like I'm told 738 * to. :-) 739 * 740 * offset 741 * 0x00 - Map Range - Mem-mapped to locate anywhere 742 * 0x04 - Re-Map - PCI address decode enable 743 * 0x18 - Bus Region - 32-bit bus, ready enable 744 * 0x1c - Master Range - include all 16 MB 745 * 0x20 - Master RAM - Map SCA Base at 0 746 * 0x28 - Master Remap - direct master memory enable 747 * 0x68 - Interrupt - Enable interrupt (0 to disable) 748 * 749 * Note: This is "cargo cult" stuff. - jrc 750 */ 751 *((u_int *)(plx_vaddr + 0x00)) = 0xfffff000; 752 *((u_int *)(plx_vaddr + 0x04)) = 1; 753 *((u_int *)(plx_vaddr + 0x18)) = 0x40030043; 754 *((u_int *)(plx_vaddr + 0x1c)) = 0xff000000; 755 *((u_int *)(plx_vaddr + 0x20)) = 0; 756 *((u_int *)(plx_vaddr + 0x28)) = 0xe9; 757 *((u_int *)(plx_vaddr + 0x68)) = 0x10900; 758 759 /* 760 * Get info from card. 761 * 762 * Only look for the second port if the first exists. Too many things 763 * will break if we have only a second port. 764 */ 765 fecr = *fecrp; 766 numports = 0; 767 768 if (((fecr & SR_FECR_ID0) >> SR_FE_ID0_SHFT) != SR_FE_ID_NONE) { 769 numports++; 770 if (((fecr & SR_FECR_ID1) >> SR_FE_ID1_SHFT) != SR_FE_ID_NONE) 771 numports++; 772 } 773 if (numports == 0) 774 return NULL; 775 776 hc = sr_hardc_pci; 777 hcp = &sr_hardc_pci; 778 779 while (hc) { 780 hcp = &hc->next; 781 hc = hc->next; 782 } 783 784 MALLOC(hc, struct sr_hardc *, sizeof(*hc), M_DEVBUF, M_WAITOK); 785 if (hc == NULL) 786 return NULL; 787 bzero(hc, sizeof(*hc)); 788 789 MALLOC(hc->sc, struct sr_softc *, 790 numports * sizeof(struct sr_softc), M_DEVBUF, M_WAITOK); 791 if (hc->sc == NULL) { 792 FREE(hc, M_DEVBUF); 793 return NULL; 794 } 795 bzero(hc->sc, numports * sizeof(struct sr_softc)); 796 *hcp = hc; 797 798 hc->numports = numports; 799 hc->cunit = unit; 800 hc->cardtype = SR_CRD_N2PCI; 801 hc->plx_base = (caddr_t)plx_vaddr; 802 hc->sca_base = sca_vaddr; 803 804 hc->src_put8 = src_put8_mem; 805 hc->src_put16 = src_put16_mem; 806 hc->src_get8 = src_get8_mem; 807 hc->src_get16 = src_get16_mem; 808 809 /* 810 * Malloc area for tx and rx buffers. For now allocate SRC_WIN_SIZ 811 * (16k) for each buffer. 812 * 813 * Allocate the block below 16M because the N2pci card can only access 814 * 16M memory at a time. 815 * 816 * (We could actually allocate a contiguous block above the 16MB limit, 817 * but this would complicate card programming more than we want to 818 * right now -jrc) 819 */ 820 hc->memsize = 2 * hc->numports * SRC_WIN_SIZ; 821 hc->mem_start = contigmalloc(hc->memsize, 822 M_DEVBUF, 823 M_NOWAIT, 824 0ul, 825 0xfffffful, 826 0x10000, 827 0x1000000); 828 829 if (hc->mem_start == NULL) { 830 printf("src%d: pci: failed to allocate buffer space.\n", unit); 831 return NULL; 832 } 833 hc->winmsk = 0xffffffff; 834 hc->mem_end = (caddr_t)((u_int)hc->mem_start + hc->memsize); 835 hc->mem_pstart = kvtop(hc->mem_start); 836 bzero(hc->mem_start, hc->memsize); 837 838 for (pndx = 0; pndx < numports; pndx++) { 839 int intf_sw; 840 struct sr_softc *sc; 841 842 sc = &hc->sc[pndx]; 843 844 switch (pndx) { 845 case 1: 846 intf_sw = fecr & SR_FECR_ID1 >> SR_FE_ID1_SHFT; 847 break; 848 case 0: 849 default: 850 intf_sw = fecr & SR_FECR_ID0 >> SR_FE_ID0_SHFT; 851 } 852 853 #ifdef N2_TEST_SPEED 854 if (sr_test_speed[pndx] > 0) 855 sc->clk_cfg = SR_FLAGS_INT_CLK; 856 else 857 #endif 858 switch (intf_sw) { 859 default: 860 case SR_FE_ID_RS232: 861 case SR_FE_ID_HSSI: 862 case SR_FE_ID_RS422: 863 case SR_FE_ID_TEST: 864 break; 865 866 case SR_FE_ID_V35: 867 sc->clk_cfg = SR_FLAGS_EXT_SEP_CLK; 868 break; 869 870 case SR_FE_ID_X21: 871 sc->clk_cfg = SR_FLAGS_EXT_CLK; 872 break; 873 } 874 } 875 876 *fecrp = SR_FECR_DTR0 877 | SR_FECR_DTR1 878 | SR_FECR_TE0 879 | SR_FECR_TE1; 880 881 srattach(hc); 882 883 return hc; 884 } 885 886 /* 887 * Register the ports on the adapter. 888 * Fill in the info for each port. 889 #ifndef NETGRAPH 890 * Attach each port to sppp and bpf. 891 #endif 892 */ 893 static int 894 srattach(struct sr_hardc *hc) 895 { 896 struct sr_softc *sc = hc->sc; 897 #ifndef NETGRAPH 898 struct ifnet *ifp; 899 #endif /* NETGRAPH */ 900 int unit; /* index: channel w/in card */ 901 902 /* 903 * Report Card configuration information before we start configuring 904 * each channel on the card... 905 */ 906 printf("src%d: %uK RAM (%d mempages) @ %08x-%08x, %u ports.\n", 907 hc->cunit, hc->memsize / 1024, hc->mempages, 908 (u_int)hc->mem_start, (u_int)hc->mem_end, hc->numports); 909 910 src_init(hc); 911 sr_init_sca(hc); 912 913 /* 914 * Now configure each port on the card. 915 */ 916 for (unit = 0; unit < hc->numports; sc++, unit++) { 917 sc->hc = hc; 918 sc->subunit = unit; 919 sc->unit = next_sc_unit; 920 next_sc_unit++; 921 sc->scachan = unit % NCHAN; 922 923 sr_init_rx_dmac(sc); 924 sr_init_tx_dmac(sc); 925 sr_init_msci(sc); 926 927 printf("sr%d: Adapter %d, port %d.\n", 928 sc->unit, hc->cunit, sc->subunit); 929 930 #ifndef NETGRAPH 931 ifp = &sc->ifsppp.pp_if; 932 ifp->if_softc = sc; 933 ifp->if_unit = sc->unit; 934 ifp->if_name = "sr"; 935 ifp->if_mtu = PP_MTU; 936 ifp->if_flags = IFF_POINTOPOINT | IFF_MULTICAST; 937 ifp->if_ioctl = srioctl; 938 ifp->if_start = srstart; 939 ifp->if_watchdog = srwatchdog; 940 941 /* 942 * Despite the fact that we want to allow both PPP *and* 943 * Frame Relay access to a channel, due to the architecture 944 * of the system, we'll have to do the attach here. 945 * 946 * At some point I'll defer the attach to the "up" call and 947 * have the attach/detach performed when the interface is 948 * up/downed... 949 */ 950 sc->attached = 0; 951 sc->protocol = N2_USE_PPP; /* default protocol */ 952 953 #if 0 954 sc->ifsppp.pp_flags = PP_KEEPALIVE; 955 sppp_attach((struct ifnet *)&sc->ifsppp); 956 #endif 957 958 if_attach(ifp); 959 960 #if NBPFILTER > 0 961 bpfattach(ifp, DLT_PPP, PPP_HEADER_LEN); 962 #endif /* NBPFILTER > 0 */ 963 #else /* NETGRAPH */ 964 /* 965 * we have found a node, make sure our 'type' is availabe. 966 */ 967 if (ngsr_done_init == 0) ngsr_init(NULL); 968 if (ng_make_node_common(&typestruct, &sc->node) != 0) 969 return (0); 970 sc->node->private = sc; 971 callout_handle_init(&sc->handle); 972 sc->xmitq.ifq_maxlen = IFQ_MAXLEN; 973 sc->xmitq_hipri.ifq_maxlen = IFQ_MAXLEN; 974 sprintf(sc->nodename, "%s%d", NG_SR_NODE_TYPE, sc->unit); 975 if (ng_name_node(sc->node, sc->nodename)) { 976 ng_rmnode(sc->node); 977 ng_unref(sc->node); 978 return (0); 979 } 980 sc->running = 0; 981 #endif /* NETGRAPH */ 982 } 983 984 if (hc->mempages) 985 SRC_SET_OFF(hc->iobase); 986 987 return 1; 988 } 989 990 /* 991 * N2 Interrupt Service Routine 992 * 993 * First figure out which SCA gave the interrupt. 994 * Process it. 995 * See if there is other interrupts pending. 996 * Repeat until there no interrupts remain. 997 */ 998 static void 999 srintr(int unit) 1000 { 1001 struct sr_hardc *hc; 1002 1003 hc = &sr_hardc[unit]; 1004 srintr_hc(hc); 1005 1006 return; 1007 } 1008 1009 void 1010 srintr_hc(struct sr_hardc *hc) 1011 { 1012 sca_regs *sca = hc->sca; /* MSCI register tree */ 1013 u_char isr0, isr1, isr2; /* interrupt statii captured */ 1014 1015 #if BUGGY > 1 1016 printf("sr: srintr_hc(hc=%08x)\n", hc); 1017 #endif 1018 1019 /* 1020 * Since multiple interfaces may share this interrupt, we must loop 1021 * until no interrupts are still pending service. 1022 */ 1023 while (1) { 1024 /* 1025 * Read all three interrupt status registers from the N2 1026 * card... 1027 */ 1028 isr0 = SRC_GET8(hc->sca_base, sca->isr0); 1029 isr1 = SRC_GET8(hc->sca_base, sca->isr1); 1030 isr2 = SRC_GET8(hc->sca_base, sca->isr2); 1031 1032 /* 1033 * If all three registers returned 0, we've finished 1034 * processing interrupts from this device, so we can quit 1035 * this loop... 1036 */ 1037 if ((isr0 | isr1 | isr2) == 0) 1038 break; 1039 1040 #if BUGGY > 2 1041 printf("src%d: srintr_hc isr0 %x, isr1 %x, isr2 %x\n", 1042 #ifndef NETGRAPH 1043 unit, isr0, isr1, isr2); 1044 #else 1045 hc->cunit, isr0, isr1, isr2); 1046 #endif /* NETGRAPH */ 1047 #endif 1048 1049 /* 1050 * Now we can dispatch the interrupts. Since we don't expect 1051 * either MSCI or timer interrupts, we'll test for DMA 1052 * interrupts first... 1053 */ 1054 if (isr1) /* DMA-initiated interrupt */ 1055 sr_dmac_intr(hc, isr1); 1056 1057 if (isr0) /* serial part IRQ? */ 1058 sr_msci_intr(hc, isr0); 1059 1060 if (isr2) /* timer-initiated interrupt */ 1061 sr_timer_intr(hc, isr2); 1062 } 1063 } 1064 1065 /* 1066 * This will only start the transmitter. It is assumed that the data 1067 * is already there. 1068 * It is normally called from srstart() or sr_dmac_intr(). 1069 */ 1070 static void 1071 sr_xmit(struct sr_softc *sc) 1072 { 1073 u_short cda_value; /* starting descriptor */ 1074 u_short eda_value; /* ending descriptor */ 1075 struct sr_hardc *hc; 1076 #ifndef NETGRAPH 1077 struct ifnet *ifp; /* O/S Network Services */ 1078 #endif /* NETGRAPH */ 1079 dmac_channel *dmac; /* DMA channel registers */ 1080 1081 #if BUGGY > 0 1082 printf("sr: sr_xmit( sc=%08x)\n", sc); 1083 #endif 1084 1085 hc = sc->hc; 1086 #ifndef NETGRAPH 1087 ifp = &sc->ifsppp.pp_if; 1088 #endif /* NETGRAPH */ 1089 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)]; 1090 1091 /* 1092 * Get the starting and ending addresses of the chain to be 1093 * transmitted and pass these on to the DMA engine on-chip. 1094 */ 1095 cda_value = sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart; 1096 cda_value &= 0x00ffff; 1097 eda_value = sc->block[sc->txb_next_tx].txeda + hc->mem_pstart; 1098 eda_value &= 0x00ffff; 1099 1100 SRC_PUT16(hc->sca_base, dmac->cda, cda_value); 1101 SRC_PUT16(hc->sca_base, dmac->eda, eda_value); 1102 1103 /* 1104 * Now we'll let the DMA status register know about this change 1105 */ 1106 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); 1107 1108 sc->xmit_busy = 1; /* mark transmitter busy */ 1109 1110 #if BUGGY > 2 1111 printf("sr%d: XMIT cda=%04x, eda=%4x, rcda=%08lx\n", 1112 sc->unit, cda_value, eda_value, 1113 sc->block[sc->txb_next_tx].txdesc + hc->mem_pstart); 1114 #endif 1115 1116 sc->txb_next_tx++; /* update next transmit seq# */ 1117 1118 if (sc->txb_next_tx == SR_TX_BLOCKS) /* handle wrap... */ 1119 sc->txb_next_tx = 0; 1120 1121 #ifndef NETGRAPH 1122 /* 1123 * Finally, we'll set a timout (which will start srwatchdog()) 1124 * within the O/S network services layer... 1125 */ 1126 ifp->if_timer = 2; /* Value in seconds. */ 1127 #else 1128 /* 1129 * Don't time out for a while. 1130 */ 1131 sc->out_dog = DOG_HOLDOFF; /* give ourself some breathing space*/ 1132 #endif /* NETGRAPH */ 1133 } 1134 1135 /* 1136 * This function will be called from the upper level when a user add a 1137 * packet to be send, and from the interrupt handler after a finished 1138 * transmit. 1139 * 1140 * NOTE: it should run at spl_imp(). 1141 * 1142 * This function only place the data in the oncard buffers. It does not 1143 * start the transmition. sr_xmit() does that. 1144 * 1145 * Transmitter idle state is indicated by the IFF_OACTIVE flag. 1146 * The function that clears that should ensure that the transmitter 1147 * and its DMA is in a "good" idle state. 1148 */ 1149 #ifndef NETGRAPH 1150 static void 1151 srstart(struct ifnet *ifp) 1152 { 1153 struct sr_softc *sc; /* channel control structure */ 1154 #else 1155 static void 1156 srstart(struct sr_softc *sc) 1157 { 1158 #endif /* NETGRAPH */ 1159 struct sr_hardc *hc; /* card control/config block */ 1160 int len; /* total length of a packet */ 1161 int pkts; /* packets placed in DPRAM */ 1162 int tlen; /* working length of pkt */ 1163 u_int i; 1164 struct mbuf *mtx; /* message buffer from O/S */ 1165 u_char *txdata; /* buffer address in DPRAM */ 1166 sca_descriptor *txdesc; /* working descriptor pointr */ 1167 struct buf_block *blkp; 1168 1169 #ifndef NETGRAPH 1170 #if BUGGY > 0 1171 printf("sr: srstart( ifp=%08x)\n", ifp); 1172 #endif 1173 sc = ifp->if_softc; 1174 if ((ifp->if_flags & IFF_RUNNING) == 0) 1175 return; 1176 #endif /* NETGRAPH */ 1177 hc = sc->hc; 1178 /* 1179 * It is OK to set the memory window outside the loop because all tx 1180 * buffers and descriptors are assumed to be in the same 16K window. 1181 */ 1182 if (hc->mempages) { 1183 SRC_SET_ON(hc->iobase); 1184 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc); 1185 } 1186 1187 /* 1188 * Loop to place packets into DPRAM. 1189 * 1190 * We stay in this loop until there is nothing in 1191 * the TX queue left or the tx buffers are full. 1192 */ 1193 top_srstart: 1194 1195 /* 1196 * See if we have space for more packets. 1197 */ 1198 if (sc->txb_inuse == SR_TX_BLOCKS) { /* out of space? */ 1199 #ifndef NETGRAPH 1200 ifp->if_flags |= IFF_OACTIVE; /* yes, mark active */ 1201 #else 1202 /*ifp->if_flags |= IFF_OACTIVE;*/ /* yes, mark active */ 1203 #endif /* NETGRAPH */ 1204 1205 if (hc->mempages) 1206 SRC_SET_OFF(hc->iobase); 1207 1208 #if BUGGY > 9 1209 printf("sr%d.srstart: sc->txb_inuse=%d; DPRAM full...\n", 1210 sc->unit, sc->txb_inuse); 1211 #endif 1212 return; 1213 } 1214 /* 1215 * OK, the card can take more traffic. Let's see if there's any 1216 * pending from the system... 1217 * 1218 * NOTE: 1219 * The architecture of the networking interface doesn't 1220 * actually call us like 'write()', providing an address. We get 1221 * started, a lot like a disk strategy routine, and we actually call 1222 * back out to the system to get traffic to send... 1223 * 1224 * NOTE: 1225 * If we were gonna run through another layer, we would use a 1226 * dispatch table to select the service we're getting a packet 1227 * from... 1228 */ 1229 #ifndef NETGRAPH 1230 switch (sc->protocol) { 1231 #if NFR > 0 1232 case N2_USE_FRP: 1233 mtx = fr_dequeue(ifp); 1234 break; 1235 #endif 1236 case N2_USE_PPP: 1237 default: 1238 mtx = sppp_dequeue(ifp); 1239 } 1240 #else /* NETGRAPH */ 1241 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 1242 if (mtx == NULL) { 1243 IF_DEQUEUE(&sc->xmitq, mtx); 1244 } 1245 #endif /* NETGRAPH */ 1246 if (!mtx) { 1247 if (hc->mempages) 1248 SRC_SET_OFF(hc->iobase); 1249 return; 1250 } 1251 /* 1252 * OK, we got a packet from the network services of the O/S. Now we 1253 * can move it into the DPRAM (under control of the descriptors) and 1254 * fire it off... 1255 */ 1256 pkts = 0; 1257 i = 0; /* counts # of granules used */ 1258 1259 blkp = &sc->block[sc->txb_new]; /* address of free granule */ 1260 txdesc = (sca_descriptor *) 1261 (hc->mem_start + (blkp->txdesc & hc->winmsk)); 1262 1263 txdata = (u_char *)(hc->mem_start 1264 + (blkp->txstart & hc->winmsk)); 1265 1266 /* 1267 * Now we'll try to install as many packets as possible into the 1268 * card's DP RAM buffers. 1269 */ 1270 for (;;) { /* perform actual copy of packet */ 1271 len = mtx->m_pkthdr.len; /* length of message */ 1272 1273 #if BUGGY > 1 1274 printf("sr%d.srstart: mbuf @ %08lx, %d bytes\n", 1275 sc->unit, mtx, len); 1276 #endif 1277 1278 #ifndef NETGRAPH 1279 #if NBPFILTER > 0 1280 if (ifp->if_bpf) 1281 bpf_mtap(ifp, mtx); 1282 #endif /* NBPFILTER > 0 */ 1283 #else /* NETGRAPH */ 1284 sc->outbytes += len; 1285 #endif /* NETGRAPH */ 1286 1287 /* 1288 * We can perform a straight copy because the tranmit 1289 * buffers won't wrap. 1290 */ 1291 m_copydata(mtx, 0, len, txdata); 1292 1293 /* 1294 * Now we know how big the message is gonna be. We must now 1295 * construct the descriptors to drive this message out... 1296 */ 1297 tlen = len; 1298 while (tlen > SR_BUF_SIZ) { /* loop for full granules */ 1299 txdesc->stat = 0; /* reset bits */ 1300 txdesc->len = SR_BUF_SIZ; /* size of granule */ 1301 tlen -= SR_BUF_SIZ; 1302 1303 txdesc++; /* move to next dscr */ 1304 txdata += SR_BUF_SIZ; /* adjust data addr */ 1305 i++; 1306 } 1307 1308 /* 1309 * This section handles the setting of the final piece of a 1310 * message. 1311 */ 1312 txdesc->stat = SCA_DESC_EOM; 1313 txdesc->len = tlen; 1314 pkts++; 1315 1316 /* 1317 * prepare for subsequent packets (if any) 1318 */ 1319 txdesc++; 1320 txdata += SR_BUF_SIZ; /* next mem granule */ 1321 i++; /* count of granules */ 1322 1323 /* 1324 * OK, we've now placed the message into the DPRAM where it 1325 * can be transmitted. We'll now release the message memory 1326 * and update the statistics... 1327 */ 1328 m_freem(mtx); 1329 #ifndef NETGRAPH 1330 ++sc->ifsppp.pp_if.if_opackets; 1331 #else /* NETGRAPH */ 1332 sc->opackets++; 1333 #endif /* NETGRAPH */ 1334 1335 /* 1336 * Check if we have space for another packet. XXX This is 1337 * hardcoded. A packet can't be larger than 3 buffers (3 x 1338 * 512). 1339 */ 1340 if ((i + 3) >= blkp->txmax) { /* enough remains? */ 1341 #if BUGGY > 9 1342 printf("sr%d.srstart: i=%d (%d pkts); card full.\n", 1343 sc->unit, i, pkts); 1344 #endif 1345 break; 1346 } 1347 /* 1348 * We'll pull the next message to be sent (if any) 1349 */ 1350 #ifndef NETGRAPH 1351 switch (sc->protocol) { 1352 #if NFR > 0 1353 case N2_USE_FRP: 1354 mtx = fr_dequeue(ifp); 1355 break; 1356 #endif 1357 case N2_USE_PPP: 1358 default: 1359 mtx = sppp_dequeue(ifp); 1360 } 1361 #else /* NETGRAPH */ 1362 IF_DEQUEUE(&sc->xmitq_hipri, mtx); 1363 if (mtx == NULL) { 1364 IF_DEQUEUE(&sc->xmitq, mtx); 1365 } 1366 #endif /* NETGRAPH */ 1367 if (!mtx) { /* no message? We're done! */ 1368 #if BUGGY > 9 1369 printf("sr%d.srstart: pending=0, pkts=%d\n", 1370 sc->unit, pkts); 1371 #endif 1372 break; 1373 } 1374 } 1375 1376 blkp->txtail = i; /* record next free granule */ 1377 1378 /* 1379 * Mark the last descriptor, so that the SCA know where to stop. 1380 */ 1381 txdesc--; /* back up to last descriptor in list */ 1382 txdesc->stat |= SCA_DESC_EOT; /* mark as end of list */ 1383 1384 /* 1385 * Now we'll reset the transmit granule's descriptor address so we 1386 * can record this in the structure and fire it off w/ the DMA 1387 * processor of the serial chip... 1388 */ 1389 txdesc = (sca_descriptor *)blkp->txdesc; 1390 blkp->txeda = (u_short)((u_int)&txdesc[i]); 1391 1392 sc->txb_inuse++; /* update inuse status */ 1393 sc->txb_new++; /* new traffic wuz added */ 1394 1395 if (sc->txb_new == SR_TX_BLOCKS) 1396 sc->txb_new = 0; 1397 1398 /* 1399 * If the tranmitter wasn't marked as "busy" we will force it to be 1400 * started... 1401 */ 1402 if (sc->xmit_busy == 0) { 1403 sr_xmit(sc); 1404 #if BUGGY > 9 1405 printf("sr%d.srstart: called sr_xmit()\n", sc->unit); 1406 #endif 1407 } 1408 goto top_srstart; 1409 } 1410 1411 #ifndef NETGRAPH 1412 /* 1413 * Handle ioctl's at the device level, though we *will* call up 1414 * a layer... 1415 */ 1416 #if BUGGY > 2 1417 static int bug_splats[] = {0, 0, 0, 0, 0, 0, 0, 0}; 1418 #endif 1419 1420 static int 1421 srioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1422 { 1423 int s, error, was_up, should_be_up; 1424 struct sppp *sp = (struct sppp *)ifp; 1425 struct sr_softc *sc = ifp->if_softc; 1426 1427 #if BUGGY > 0 1428 printf("sr%d: srioctl(ifp=%08x, cmd=%08x, data=%08x)\n", 1429 ifp->if_unit, ifp, cmd, data); 1430 #endif 1431 1432 was_up = ifp->if_flags & IFF_RUNNING; 1433 1434 if (cmd == SIOCSIFFLAGS) { 1435 /* 1436 * First, handle an apparent protocol switch 1437 */ 1438 #if NFR > 0 1439 if (was_up == 0)/* can only happen if DOWN */ 1440 if (ifp->if_flags & IFF_LINK1) 1441 sc->protocol = N2_USE_FRP; 1442 else 1443 sc->protocol = N2_USE_PPP; 1444 #else 1445 sc->protocol = N2_USE_PPP; 1446 ifp->if_flags &= ~IFF_LINK1; 1447 #endif 1448 1449 /* 1450 * Next we can handle minor protocol point(s) 1451 */ 1452 if (ifp->if_flags & IFF_LINK2) 1453 sp->pp_flags |= PP_CISCO; 1454 else 1455 sp->pp_flags &= ~PP_CISCO; 1456 } 1457 /* 1458 * Next, we'll allow the network service layer we've called process 1459 * the ioctl... 1460 */ 1461 if ((sc->attached != 0) 1462 && (sc->attached != sc->protocol)) { 1463 switch (sc->attached) { 1464 #if NFR > 0 1465 case N2_USE_FRP: 1466 fr_detach(ifp); 1467 break; 1468 #endif 1469 case N2_USE_PPP: 1470 default: 1471 sppp_detach(ifp); 1472 sc->ifsppp.pp_flags &= ~PP_KEEPALIVE; 1473 } 1474 1475 sc->attached = 0; 1476 } 1477 if (sc->attached == 0) { 1478 switch (sc->protocol) { 1479 #if NFR > 0 1480 case N2_USE_FRP: 1481 fr_attach(&sc->ifsppp.pp_if); 1482 break; 1483 #endif 1484 case N2_USE_PPP: 1485 default: 1486 sc->ifsppp.pp_flags |= PP_KEEPALIVE; 1487 sppp_attach(&sc->ifsppp.pp_if); 1488 1489 } 1490 1491 sc->attached = sc->protocol; 1492 } 1493 switch (sc->protocol) { 1494 #if NFR > 0 1495 case N2_USE_FRP: 1496 error = fr_ioctl(ifp, cmd, data); 1497 break; 1498 #endif 1499 case N2_USE_PPP: 1500 default: 1501 error = sppp_ioctl(ifp, cmd, data); 1502 } 1503 1504 #if BUGGY > 1 1505 printf("sr%d: ioctl: ifsppp.pp_flags = %08x, if_flags %08x.\n", 1506 ifp->if_unit, ((struct sppp *)ifp)->pp_flags, ifp->if_flags); 1507 #endif 1508 1509 if (error) 1510 return error; 1511 1512 if ((cmd != SIOCSIFFLAGS) && (cmd != SIOCSIFADDR)) { 1513 #if BUGGY > 2 1514 if (bug_splats[sc->unit]++ < 2) { 1515 printf("sr(%d).if_addrlist = %08x\n", 1516 sc->unit, ifp->if_addrlist); 1517 printf("sr(%d).if_bpf = %08x\n", 1518 sc->unit, ifp->if_bpf); 1519 printf("sr(%d).if_init = %08x\n", 1520 sc->unit, ifp->if_init); 1521 printf("sr(%d).if_output = %08x\n", 1522 sc->unit, ifp->if_output); 1523 printf("sr(%d).if_start = %08x\n", 1524 sc->unit, ifp->if_start); 1525 printf("sr(%d).if_done = %08x\n", 1526 sc->unit, ifp->if_done); 1527 printf("sr(%d).if_ioctl = %08x\n", 1528 sc->unit, ifp->if_ioctl); 1529 printf("sr(%d).if_reset = %08x\n", 1530 sc->unit, ifp->if_reset); 1531 printf("sr(%d).if_watchdog = %08x\n", 1532 sc->unit, ifp->if_watchdog); 1533 } 1534 #endif 1535 return 0; 1536 } 1537 1538 s = splimp(); 1539 should_be_up = ifp->if_flags & IFF_RUNNING; 1540 1541 if (!was_up && should_be_up) { 1542 /* 1543 * Interface should be up -- start it. 1544 */ 1545 sr_up(sc); 1546 srstart(ifp); 1547 1548 /* 1549 * XXX Clear the IFF_UP flag so that the link will only go 1550 * up after sppp lcp and ipcp negotiation. 1551 */ 1552 ifp->if_flags &= ~IFF_UP; 1553 } else if (was_up && !should_be_up) { 1554 /* 1555 * Interface should be down -- stop it. 1556 */ 1557 sr_down(sc); 1558 switch (sc->protocol) { 1559 #if NFR > 0 1560 case N2_USE_FRP: 1561 fr_flush(ifp); 1562 break; 1563 #endif 1564 case N2_USE_PPP: 1565 default: 1566 sppp_flush(ifp); 1567 } 1568 } 1569 splx(s); 1570 1571 #if BUGGY > 2 1572 if (bug_splats[sc->unit]++ < 2) { 1573 printf("sr(%d).if_addrlist = %08x\n", 1574 sc->unit, ifp->if_addrlist); 1575 printf("sr(%d).if_bpf = %08x\n", 1576 sc->unit, ifp->if_bpf); 1577 printf("sr(%d).if_init = %08x\n", 1578 sc->unit, ifp->if_init); 1579 printf("sr(%d).if_output = %08x\n", 1580 sc->unit, ifp->if_output); 1581 printf("sr(%d).if_start = %08x\n", 1582 sc->unit, ifp->if_start); 1583 printf("sr(%d).if_done = %08x\n", 1584 sc->unit, ifp->if_done); 1585 printf("sr(%d).if_ioctl = %08x\n", 1586 sc->unit, ifp->if_ioctl); 1587 printf("sr(%d).if_reset = %08x\n", 1588 sc->unit, ifp->if_reset); 1589 printf("sr(%d).if_watchdog = %08x\n", 1590 sc->unit, ifp->if_watchdog); 1591 } 1592 #endif 1593 1594 return 0; 1595 } 1596 #endif /* NETGRAPH */ 1597 1598 /* 1599 * This is to catch lost tx interrupts. 1600 */ 1601 static void 1602 #ifndef NETGRAPH 1603 srwatchdog(struct ifnet *ifp) 1604 #else 1605 srwatchdog(struct sr_softc *sc) 1606 #endif /* NETGRAPH */ 1607 { 1608 int got_st0, got_st1, got_st3, got_dsr; 1609 #ifndef NETGRAPH 1610 struct sr_softc *sc = ifp->if_softc; 1611 #endif /* NETGRAPH */ 1612 struct sr_hardc *hc = sc->hc; 1613 msci_channel *msci = &hc->sca->msci[sc->scachan]; 1614 dmac_channel *dmac = &sc->hc->sca->dmac[sc->scachan]; 1615 1616 #if BUGGY > 0 1617 #ifndef NETGRAPH 1618 printf("srwatchdog(unit=%d)\n", unit); 1619 #else 1620 printf("srwatchdog(unit=%d)\n", sc->unit); 1621 #endif /* NETGRAPH */ 1622 #endif 1623 1624 #ifndef NETGRAPH 1625 if (!(ifp->if_flags & IFF_RUNNING)) 1626 return; 1627 1628 ifp->if_oerrors++; /* update output error count */ 1629 #else /* NETGRAPH */ 1630 sc->oerrors++; /* update output error count */ 1631 #endif /* NETGRAPH */ 1632 1633 got_st0 = SRC_GET8(hc->sca_base, msci->st0); 1634 got_st1 = SRC_GET8(hc->sca_base, msci->st1); 1635 got_st3 = SRC_GET8(hc->sca_base, msci->st3); 1636 got_dsr = SRC_GET8(hc->sca_base, dmac->dsr); 1637 1638 #ifndef NETGRAPH 1639 #if 0 1640 if (ifp->if_flags & IFF_DEBUG) 1641 #endif 1642 printf("sr%d: transmit failed, " 1643 #else /* NETGRAPH */ 1644 printf("sr%d: transmit failed, " 1645 #endif /* NETGRAPH */ 1646 "ST0 %02x, ST1 %02x, ST3 %02x, DSR %02x.\n", 1647 sc->unit, 1648 got_st0, got_st1, got_st3, got_dsr); 1649 1650 if (SRC_GET8(hc->sca_base, msci->st1) & SCA_ST1_UDRN) { 1651 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXABORT); 1652 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE); 1653 SRC_PUT8(hc->sca_base, msci->st1, SCA_ST1_UDRN); 1654 } 1655 sc->xmit_busy = 0; 1656 #ifndef NETGRAPH 1657 ifp->if_flags &= ~IFF_OACTIVE; 1658 #else 1659 /*ifp->if_flags &= ~IFF_OACTIVE; */ 1660 #endif /* NETGRAPH */ 1661 1662 if (sc->txb_inuse && --sc->txb_inuse) 1663 sr_xmit(sc); 1664 1665 #ifndef NETGRAPH 1666 srstart(ifp); /* restart transmitter */ 1667 #else 1668 srstart(sc); /* restart transmitter */ 1669 #endif /* NETGRAPH */ 1670 } 1671 1672 static void 1673 sr_up(struct sr_softc *sc) 1674 { 1675 u_int *fecrp; 1676 struct sr_hardc *hc = sc->hc; 1677 sca_regs *sca = hc->sca; 1678 msci_channel *msci = &sca->msci[sc->scachan]; 1679 1680 #if BUGGY > 0 1681 printf("sr_up(sc=%08x)\n", sc); 1682 #endif 1683 1684 #ifndef NETGRAPH 1685 /* 1686 * This section should really do the attach to the appropriate 1687 * system service, be it frame relay or PPP... 1688 */ 1689 if (sc->attached == 0) { 1690 switch (sc->protocol) { 1691 #if NFR > 0 1692 case N2_USE_FRP: 1693 fr_attach(&sc->ifsppp.pp_if); 1694 break; 1695 #endif 1696 case N2_USE_PPP: 1697 default: 1698 sc->ifsppp.pp_flags |= PP_KEEPALIVE; 1699 sppp_attach(&sc->ifsppp.pp_if); 1700 1701 } 1702 1703 sc->attached = sc->protocol; 1704 } 1705 1706 #endif /* NETGRAPH */ 1707 /* 1708 * Enable transmitter and receiver. Raise DTR and RTS. Enable 1709 * interrupts. 1710 * 1711 * XXX What about using AUTO mode in msci->md0 ??? 1712 */ 1713 SRC_PUT8(hc->sca_base, msci->ctl, 1714 SRC_GET8(hc->sca_base, msci->ctl) & ~SCA_CTL_RTS); 1715 1716 if (sc->scachan == 0) 1717 switch (hc->cardtype) { 1718 case SR_CRD_N2: 1719 outb(hc->iobase + SR_MCR, 1720 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR0)); 1721 break; 1722 case SR_CRD_N2PCI: 1723 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1724 *fecrp &= ~SR_FECR_DTR0; 1725 break; 1726 } 1727 else 1728 switch (hc->cardtype) { 1729 case SR_CRD_N2: 1730 outb(hc->iobase + SR_MCR, 1731 (inb(hc->iobase + SR_MCR) & ~SR_MCR_DTR1)); 1732 break; 1733 case SR_CRD_N2PCI: 1734 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1735 *fecrp &= ~SR_FECR_DTR1; 1736 break; 1737 } 1738 1739 if (sc->scachan == 0) { 1740 SRC_PUT8(hc->sca_base, sca->ier0, 1741 SRC_GET8(hc->sca_base, sca->ier0) | 0x000F); 1742 SRC_PUT8(hc->sca_base, sca->ier1, 1743 SRC_GET8(hc->sca_base, sca->ier1) | 0x000F); 1744 } else { 1745 SRC_PUT8(hc->sca_base, sca->ier0, 1746 SRC_GET8(hc->sca_base, sca->ier0) | 0x00F0); 1747 SRC_PUT8(hc->sca_base, sca->ier1, 1748 SRC_GET8(hc->sca_base, sca->ier1) | 0x00F0); 1749 } 1750 1751 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXENABLE); 1752 inb(hc->iobase); /* XXX slow it down a bit. */ 1753 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXENABLE); 1754 1755 #ifndef NETGRAPH 1756 #ifdef USE_MODEMCK 1757 if (sr_watcher == 0) 1758 sr_modemck(NULL); 1759 #endif 1760 #else /* NETGRAPH */ 1761 untimeout(ngsr_watchdog_frame, sc, sc->handle); 1762 sc->handle = timeout(ngsr_watchdog_frame, sc, hz); 1763 sc->running = 1; 1764 #endif /* NETGRAPH */ 1765 } 1766 1767 static void 1768 sr_down(struct sr_softc *sc) 1769 { 1770 u_int *fecrp; 1771 struct sr_hardc *hc = sc->hc; 1772 sca_regs *sca = hc->sca; 1773 msci_channel *msci = &sca->msci[sc->scachan]; 1774 1775 #if BUGGY > 0 1776 printf("sr_down(sc=%08x)\n", sc); 1777 #endif 1778 #ifdef NETGRAPH 1779 untimeout(ngsr_watchdog_frame, sc, sc->handle); 1780 sc->running = 0; 1781 #endif /* NETGRAPH */ 1782 1783 /* 1784 * Disable transmitter and receiver. Lower DTR and RTS. Disable 1785 * interrupts. 1786 */ 1787 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXDISABLE); 1788 inb(hc->iobase); /* XXX slow it down a bit. */ 1789 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_TXDISABLE); 1790 1791 SRC_PUT8(hc->sca_base, msci->ctl, 1792 SRC_GET8(hc->sca_base, msci->ctl) | SCA_CTL_RTS); 1793 1794 if (sc->scachan == 0) 1795 switch (hc->cardtype) { 1796 case SR_CRD_N2: 1797 outb(hc->iobase + SR_MCR, 1798 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR0)); 1799 break; 1800 case SR_CRD_N2PCI: 1801 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1802 *fecrp |= SR_FECR_DTR0; 1803 break; 1804 } 1805 else 1806 switch (hc->cardtype) { 1807 case SR_CRD_N2: 1808 outb(hc->iobase + SR_MCR, 1809 (inb(hc->iobase + SR_MCR) | SR_MCR_DTR1)); 1810 break; 1811 case SR_CRD_N2PCI: 1812 fecrp = (u_int *)(hc->sca_base + SR_FECR); 1813 *fecrp |= SR_FECR_DTR1; 1814 break; 1815 } 1816 1817 if (sc->scachan == 0) { 1818 SRC_PUT8(hc->sca_base, sca->ier0, 1819 SRC_GET8(hc->sca_base, sca->ier0) & ~0x0F); 1820 SRC_PUT8(hc->sca_base, sca->ier1, 1821 SRC_GET8(hc->sca_base, sca->ier1) & ~0x0F); 1822 } else { 1823 SRC_PUT8(hc->sca_base, sca->ier0, 1824 SRC_GET8(hc->sca_base, sca->ier0) & ~0xF0); 1825 SRC_PUT8(hc->sca_base, sca->ier1, 1826 SRC_GET8(hc->sca_base, sca->ier1) & ~0xF0); 1827 } 1828 1829 #ifndef NETGRAPH 1830 /* 1831 * This section does the detach from the currently configured net 1832 * service, be it frame relay or PPP... 1833 */ 1834 switch (sc->protocol) { 1835 #if NFR > 0 1836 case N2_USE_FRP: 1837 fr_detach(&sc->ifsppp.pp_if); 1838 break; 1839 #endif 1840 case N2_USE_PPP: 1841 default: 1842 sppp_detach(&sc->ifsppp.pp_if); 1843 } 1844 1845 sc->attached = 0; 1846 #endif /* NETGRAPH */ 1847 } 1848 1849 /* 1850 * Initialize the card, allocate memory for the sr_softc structures 1851 * and fill in the pointers. 1852 */ 1853 static void 1854 src_init(struct sr_hardc *hc) 1855 { 1856 struct sr_softc *sc = hc->sc; 1857 int x; 1858 u_int chanmem; 1859 u_int bufmem; 1860 u_int next; 1861 u_int descneeded; 1862 1863 #if BUGGY > 0 1864 printf("src_init(hc=%08x)\n", hc); 1865 #endif 1866 1867 chanmem = hc->memsize / hc->numports; 1868 next = 0; 1869 1870 for (x = 0; x < hc->numports; x++, sc++) { 1871 int blk; 1872 1873 for (blk = 0; blk < SR_TX_BLOCKS; blk++) { 1874 sc->block[blk].txdesc = next; 1875 bufmem = (16 * 1024) / SR_TX_BLOCKS; 1876 descneeded = bufmem / SR_BUF_SIZ; 1877 1878 sc->block[blk].txstart = sc->block[blk].txdesc 1879 + ((((descneeded * sizeof(sca_descriptor)) 1880 / SR_BUF_SIZ) + 1) 1881 * SR_BUF_SIZ); 1882 1883 sc->block[blk].txend = next + bufmem; 1884 sc->block[blk].txmax = 1885 (sc->block[blk].txend - sc->block[blk].txstart) 1886 / SR_BUF_SIZ; 1887 next += bufmem; 1888 1889 #if BUGGY > 2 1890 printf("sr%d: blk %d: txdesc %08x, txstart %08x\n", 1891 sc->unit, blk, 1892 sc->block[blk].txdesc, sc->block[blk].txstart); 1893 #endif 1894 } 1895 1896 sc->rxdesc = next; 1897 bufmem = chanmem - (bufmem * SR_TX_BLOCKS); 1898 descneeded = bufmem / SR_BUF_SIZ; 1899 sc->rxstart = sc->rxdesc + 1900 ((((descneeded * sizeof(sca_descriptor)) / 1901 SR_BUF_SIZ) + 1) * SR_BUF_SIZ); 1902 sc->rxend = next + bufmem; 1903 sc->rxmax = (sc->rxend - sc->rxstart) / SR_BUF_SIZ; 1904 next += bufmem; 1905 } 1906 } 1907 1908 /* 1909 * The things done here are channel independent. 1910 * 1911 * Configure the sca waitstates. 1912 * Configure the global interrupt registers. 1913 * Enable master dma enable. 1914 */ 1915 static void 1916 sr_init_sca(struct sr_hardc *hc) 1917 { 1918 sca_regs *sca = hc->sca; 1919 1920 #if BUGGY > 0 1921 printf("sr_init_sca(hc=%08x)\n", hc); 1922 #endif 1923 1924 /* 1925 * Do the wait registers. Set everything to 0 wait states. 1926 */ 1927 SRC_PUT8(hc->sca_base, sca->pabr0, 0); 1928 SRC_PUT8(hc->sca_base, sca->pabr1, 0); 1929 SRC_PUT8(hc->sca_base, sca->wcrl, 0); 1930 SRC_PUT8(hc->sca_base, sca->wcrm, 0); 1931 SRC_PUT8(hc->sca_base, sca->wcrh, 0); 1932 1933 /* 1934 * Configure the interrupt registers. Most are cleared until the 1935 * interface is configured. 1936 */ 1937 SRC_PUT8(hc->sca_base, sca->ier0, 0x00); /* MSCI interrupts. */ 1938 SRC_PUT8(hc->sca_base, sca->ier1, 0x00); /* DMAC interrupts */ 1939 SRC_PUT8(hc->sca_base, sca->ier2, 0x00); /* TIMER interrupts. */ 1940 SRC_PUT8(hc->sca_base, sca->itcr, 0x00); /* Use ivr and no intr 1941 * ack */ 1942 SRC_PUT8(hc->sca_base, sca->ivr, 0x40); /* Interrupt vector. */ 1943 SRC_PUT8(hc->sca_base, sca->imvr, 0x40); 1944 1945 /* 1946 * Configure the timers. XXX Later 1947 */ 1948 1949 /* 1950 * Set the DMA channel priority to rotate between all four channels. 1951 * 1952 * Enable all dma channels. 1953 */ 1954 SRC_PUT8(hc->sca_base, sca->pcr, SCA_PCR_PR2); 1955 SRC_PUT8(hc->sca_base, sca->dmer, SCA_DMER_EN); 1956 } 1957 1958 /* 1959 * Configure the msci 1960 * 1961 * NOTE: The serial port configuration is hardcoded at the moment. 1962 */ 1963 static void 1964 sr_init_msci(struct sr_softc *sc) 1965 { 1966 int portndx; /* on-board port number */ 1967 u_int mcr_v; /* contents of modem control */ 1968 u_int *fecrp; /* pointer for PCI's MCR i/o */ 1969 struct sr_hardc *hc = sc->hc; 1970 msci_channel *msci = &hc->sca->msci[sc->scachan]; 1971 #ifdef N2_TEST_SPEED 1972 int br_v; /* contents for BR divisor */ 1973 int etcndx; /* index into ETC table */ 1974 int fifo_v, gotspeed; /* final tabled speed found */ 1975 int tmc_v; /* timer control register */ 1976 int wanted; /* speed (bitrate) wanted... */ 1977 struct rate_line *rtp; 1978 #endif 1979 1980 portndx = sc->scachan; 1981 1982 #if BUGGY > 0 1983 printf("sr: sr_init_msci( sc=%08x)\n", sc); 1984 #endif 1985 1986 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RESET); 1987 SRC_PUT8(hc->sca_base, msci->md0, SCA_MD0_CRC_1 | 1988 SCA_MD0_CRC_CCITT | 1989 SCA_MD0_CRC_ENABLE | 1990 SCA_MD0_MODE_HDLC); 1991 SRC_PUT8(hc->sca_base, msci->md1, SCA_MD1_NOADDRCHK); 1992 SRC_PUT8(hc->sca_base, msci->md2, SCA_MD2_DUPLEX | SCA_MD2_NRZ); 1993 1994 /* 1995 * According to the manual I should give a reset after changing the 1996 * mode registers. 1997 */ 1998 SRC_PUT8(hc->sca_base, msci->cmd, SCA_CMD_RXRESET); 1999 SRC_PUT8(hc->sca_base, msci->ctl, SCA_CTL_IDLPAT | 2000 SCA_CTL_UDRNC | 2001 SCA_CTL_RTS); 2002 2003 /* 2004 * XXX Later we will have to support different clock settings. 2005 */ 2006 switch (sc->clk_cfg) { 2007 default: 2008 #if BUGGY > 0 2009 printf("sr%: clk_cfg=%08x, selected default clock.\n", 2010 portndx, sc->clk_cfg); 2011 #endif 2012 /* FALLTHROUGH */ 2013 case SR_FLAGS_EXT_CLK: 2014 /* 2015 * For now all interfaces are programmed to use the RX clock 2016 * for the TX clock. 2017 */ 2018 2019 #if BUGGY > 0 2020 printf("sr%d: External Clock Selected.\n", portndx); 2021 #endif 2022 2023 SRC_PUT8(hc->sca_base, msci->rxs, 0); 2024 SRC_PUT8(hc->sca_base, msci->txs, 0); 2025 break; 2026 2027 case SR_FLAGS_EXT_SEP_CLK: 2028 #if BUGGY > 0 2029 printf("sr%d: Split Clocking Selected.\n", portndx); 2030 #endif 2031 2032 #if 1 2033 SRC_PUT8(hc->sca_base, msci->rxs, 0); 2034 SRC_PUT8(hc->sca_base, msci->txs, 0); 2035 #else 2036 SRC_PUT8(hc->sca_base, msci->rxs, 2037 SCA_RXS_CLK_RXC0 | SCA_RXS_DIV1); 2038 2039 /* 2040 * We need to configure the internal bit clock for the 2041 * transmitter's channel... 2042 */ 2043 SRC_PUT8(hc->sca_base, msci->txs, 2044 SCA_TXS_CLK_RX | SCA_TXS_DIV1); 2045 #endif 2046 break; 2047 2048 case SR_FLAGS_INT_CLK: 2049 #if BUGGY > 0 2050 printf("sr%d: Internal Clocking selected.\n", portndx); 2051 #endif 2052 2053 /* 2054 * XXX I do need some code to set the baud rate here! 2055 */ 2056 #ifdef N2_TEST_SPEED 2057 switch (hc->cardtype) { 2058 case SR_CRD_N2PCI: 2059 fecrp = (u_int *)(hc->sca_base + SR_FECR); 2060 mcr_v = *fecrp; 2061 etcndx = 2; 2062 break; 2063 case SR_CRD_N2: 2064 default: 2065 mcr_v = inb(hc->iobase + SR_MCR); 2066 etcndx = 0; 2067 } 2068 2069 fifo_v = 0x10; /* stolen from Linux version */ 2070 2071 /* 2072 * search for appropriate speed in table, don't calc it: 2073 */ 2074 wanted = sr_test_speed[portndx]; 2075 rtp = &n2_rates[0]; /* point to first table item */ 2076 2077 while ((rtp->target > 0) /* search table for speed */ 2078 &&(rtp->target != wanted)) 2079 rtp++; 2080 2081 /* 2082 * We've searched the table for a matching speed. If we've 2083 * found the correct rate line, we'll get the pre-calc'd 2084 * values for the TMC and baud rate divisor for subsequent 2085 * use... 2086 */ 2087 if (rtp->target > 0) { /* use table-provided values */ 2088 gotspeed = wanted; 2089 tmc_v = rtp->tmc_reg; 2090 br_v = rtp->br_reg; 2091 } else { /* otherwise assume 1MBit comm rate */ 2092 gotspeed = 10000; 2093 tmc_v = 5; 2094 br_v = 1; 2095 } 2096 2097 /* 2098 * Now we mask in the enable clock output for the MCR: 2099 */ 2100 mcr_v |= etc0vals[etcndx + portndx]; 2101 2102 /* 2103 * Now we'll program the registers with these speed- related 2104 * contents... 2105 */ 2106 SRC_PUT8(hc->sca_base, msci->tmc, tmc_v); 2107 SRC_PUT8(hc->sca_base, msci->trc0, fifo_v); 2108 SRC_PUT8(hc->sca_base, msci->rxs, SCA_RXS_CLK_INT + br_v); 2109 SRC_PUT8(hc->sca_base, msci->txs, SCA_TXS_CLK_INT + br_v); 2110 2111 switch (hc->cardtype) { 2112 case SR_CRD_N2PCI: 2113 *fecrp = mcr_v; 2114 break; 2115 case SR_CRD_N2: 2116 default: 2117 outb(hc->iobase + SR_MCR, mcr_v); 2118 } 2119 2120 #if BUGGY > 0 2121 if (wanted != gotspeed) 2122 printf("sr%d: Speed wanted=%d, found=%d\n", 2123 wanted, gotspeed); 2124 2125 printf("sr%d: Internal Clock %dx100 BPS, tmc=%d, div=%d\n", 2126 portndx, gotspeed, tmc_v, br_v); 2127 #endif 2128 #else 2129 SRC_PUT8(hc->sca_base, msci->rxs, 2130 SCA_RXS_CLK_INT | SCA_RXS_DIV1); 2131 SRC_PUT8(hc->sca_base, msci->txs, 2132 SCA_TXS_CLK_INT | SCA_TXS_DIV1); 2133 2134 SRC_PUT8(hc->sca_base, msci->tmc, 5); 2135 2136 if (portndx == 0) 2137 switch (hc->cardtype) { 2138 case SR_CRD_N2PCI: 2139 fecrp = (u_int *)(hc->sca_base + SR_FECR); 2140 *fecrp |= SR_FECR_ETC0; 2141 break; 2142 case SR_CRD_N2: 2143 default: 2144 mcr_v = inb(hc->iobase + SR_MCR); 2145 mcr_v |= SR_MCR_ETC0; 2146 outb(hc->iobase + SR_MCR, mcr_v); 2147 } 2148 else 2149 switch (hc->cardtype) { 2150 case SR_CRD_N2: 2151 mcr_v = inb(hc->iobase + SR_MCR); 2152 mcr_v |= SR_MCR_ETC1; 2153 outb(hc->iobase + SR_MCR, mcr_v); 2154 break; 2155 case SR_CRD_N2PCI: 2156 fecrp = (u_int *)(hc->sca_base + SR_FECR); 2157 *fecrp |= SR_FECR_ETC1; 2158 break; 2159 } 2160 #endif 2161 } 2162 2163 /* 2164 * XXX Disable all interrupts for now. I think if you are using the 2165 * dmac you don't use these interrupts. 2166 */ 2167 SRC_PUT8(hc->sca_base, msci->ie0, 0); 2168 SRC_PUT8(hc->sca_base, msci->ie1, 0x0C); 2169 SRC_PUT8(hc->sca_base, msci->ie2, 0); 2170 SRC_PUT8(hc->sca_base, msci->fie, 0); 2171 2172 SRC_PUT8(hc->sca_base, msci->sa0, 0); 2173 SRC_PUT8(hc->sca_base, msci->sa1, 0); 2174 2175 SRC_PUT8(hc->sca_base, msci->idl, 0x7E); /* set flags value */ 2176 2177 SRC_PUT8(hc->sca_base, msci->rrc, 0x0E); 2178 SRC_PUT8(hc->sca_base, msci->trc0, 0x10); 2179 SRC_PUT8(hc->sca_base, msci->trc1, 0x1F); 2180 } 2181 2182 /* 2183 * Configure the rx dma controller. 2184 */ 2185 static void 2186 sr_init_rx_dmac(struct sr_softc *sc) 2187 { 2188 struct sr_hardc *hc; 2189 dmac_channel *dmac; 2190 sca_descriptor *rxd; 2191 u_int cda_v, sarb_v, rxbuf, rxda, rxda_d; 2192 2193 #if BUGGY > 0 2194 printf("sr_init_rx_dmac(sc=%08x)\n", sc); 2195 #endif 2196 2197 hc = sc->hc; 2198 dmac = &hc->sca->dmac[DMAC_RXCH(sc->scachan)]; 2199 2200 if (hc->mempages) 2201 SRC_SET_MEM(hc->iobase, sc->rxdesc); 2202 2203 /* 2204 * This phase initializes the contents of the descriptor table 2205 * needed to construct a circular buffer... 2206 */ 2207 rxd = (sca_descriptor *)(hc->mem_start + (sc->rxdesc & hc->winmsk)); 2208 rxda_d = (u_int) hc->mem_start - (sc->rxdesc & ~hc->winmsk); 2209 2210 for (rxbuf = sc->rxstart; 2211 rxbuf < sc->rxend; 2212 rxbuf += SR_BUF_SIZ, rxd++) { 2213 /* 2214 * construct the circular chain... 2215 */ 2216 rxda = (u_int) & rxd[1] - rxda_d + hc->mem_pstart; 2217 rxd->cp = (u_short)(rxda & 0xffff); 2218 2219 /* 2220 * set the on-card buffer address... 2221 */ 2222 rxd->bp = (u_short)((rxbuf + hc->mem_pstart) & 0xffff); 2223 rxd->bpb = (u_char)(((rxbuf + hc->mem_pstart) >> 16) & 0xff); 2224 2225 rxd->len = 0; /* bytes resident w/in granule */ 2226 rxd->stat = 0xff; /* The sca write here when finished */ 2227 } 2228 2229 /* 2230 * heal the chain so that the last entry points to the first... 2231 */ 2232 rxd--; 2233 rxd->cp = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff); 2234 2235 /* 2236 * reset the reception handler's index... 2237 */ 2238 sc->rxhind = 0; 2239 2240 /* 2241 * We'll now configure the receiver's DMA logic... 2242 */ 2243 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA transfer */ 2244 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT); 2245 2246 /* XXX maybe also SCA_DMR_CNTE */ 2247 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF); 2248 SRC_PUT16(hc->sca_base, dmac->bfl, SR_BUF_SIZ); 2249 2250 cda_v = (u_short)((sc->rxdesc + hc->mem_pstart) & 0xffff); 2251 sarb_v = (u_char)(((sc->rxdesc + hc->mem_pstart) >> 16) & 0xff); 2252 2253 SRC_PUT16(hc->sca_base, dmac->cda, cda_v); 2254 SRC_PUT8(hc->sca_base, dmac->sarb, sarb_v); 2255 2256 rxd = (sca_descriptor *)sc->rxstart; 2257 2258 SRC_PUT16(hc->sca_base, dmac->eda, 2259 (u_short)((u_int) & rxd[sc->rxmax - 1] & 0xffff)); 2260 2261 SRC_PUT8(hc->sca_base, dmac->dir, 0xF0); 2262 2263 2264 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); /* Enable DMA */ 2265 } 2266 2267 /* 2268 * Configure the TX DMA descriptors. 2269 * Initialize the needed values and chain the descriptors. 2270 */ 2271 static void 2272 sr_init_tx_dmac(struct sr_softc *sc) 2273 { 2274 int blk; 2275 u_int txbuf, txda, txda_d; 2276 struct sr_hardc *hc; 2277 sca_descriptor *txd; 2278 dmac_channel *dmac; 2279 struct buf_block *blkp; 2280 u_int x; 2281 u_int sarb_v; 2282 2283 #if BUGGY > 0 2284 printf("sr_init_tx_dmac(sc=%08x)\n", sc); 2285 #endif 2286 2287 hc = sc->hc; 2288 dmac = &hc->sca->dmac[DMAC_TXCH(sc->scachan)]; 2289 2290 if (hc->mempages) 2291 SRC_SET_MEM(hc->iobase, sc->block[0].txdesc); 2292 2293 /* 2294 * Initialize the array of descriptors for transmission 2295 */ 2296 for (blk = 0; blk < SR_TX_BLOCKS; blk++) { 2297 blkp = &sc->block[blk]; 2298 txd = (sca_descriptor *)(hc->mem_start 2299 + (blkp->txdesc & hc->winmsk)); 2300 txda_d = (u_int) hc->mem_start 2301 - (blkp->txdesc & ~hc->winmsk); 2302 2303 x = 0; 2304 txbuf = blkp->txstart; 2305 for (; txbuf < blkp->txend; txbuf += SR_BUF_SIZ, txd++) { 2306 txda = (u_int) & txd[1] - txda_d + hc->mem_pstart; 2307 txd->cp = (u_short)(txda & 0xffff); 2308 2309 txd->bp = (u_short)((txbuf + hc->mem_pstart) 2310 & 0xffff); 2311 txd->bpb = (u_char)(((txbuf + hc->mem_pstart) >> 16) 2312 & 0xff); 2313 txd->len = 0; 2314 txd->stat = 0; 2315 x++; 2316 } 2317 2318 txd--; 2319 txd->cp = (u_short)((blkp->txdesc + hc->mem_pstart) 2320 & 0xffff); 2321 2322 blkp->txtail = (u_int)txd - (u_int)hc->mem_start; 2323 } 2324 2325 SRC_PUT8(hc->sca_base, dmac->dsr, 0); /* Disable DMA */ 2326 SRC_PUT8(hc->sca_base, dmac->dcr, SCA_DCR_ABRT); 2327 SRC_PUT8(hc->sca_base, dmac->dmr, SCA_DMR_TMOD | SCA_DMR_NF); 2328 SRC_PUT8(hc->sca_base, dmac->dir, 2329 SCA_DIR_EOT | SCA_DIR_BOF | SCA_DIR_COF); 2330 2331 sarb_v = (sc->block[0].txdesc + hc->mem_pstart) >> 16; 2332 sarb_v &= 0x00ff; 2333 2334 SRC_PUT8(hc->sca_base, dmac->sarb, (u_char) sarb_v); 2335 } 2336 2337 /* 2338 * Look through the descriptors to see if there is a complete packet 2339 * available. Stop if we get to where the sca is busy. 2340 * 2341 * Return the length and status of the packet. 2342 * Return nonzero if there is a packet available. 2343 * 2344 * NOTE: 2345 * It seems that we get the interrupt a bit early. The updateing of 2346 * descriptor values is not always completed when this is called. 2347 */ 2348 static int 2349 sr_packet_avail(struct sr_softc *sc, int *len, u_char *rxstat) 2350 { 2351 int granules; /* count of granules in pkt */ 2352 int wki, wko; 2353 struct sr_hardc *hc; 2354 sca_descriptor *rxdesc; /* current descriptor */ 2355 sca_descriptor *endp; /* ending descriptor */ 2356 sca_descriptor *cda; /* starting descriptor */ 2357 2358 hc = sc->hc; /* get card's information */ 2359 2360 /* 2361 * set up starting descriptor by pulling that info from the DMA half 2362 * of the HD chip... 2363 */ 2364 wki = DMAC_RXCH(sc->scachan); 2365 wko = SRC_GET16(hc->sca_base, hc->sca->dmac[wki].cda); 2366 2367 cda = (sca_descriptor *)(hc->mem_start + (wko & hc->winmsk)); 2368 2369 #if BUGGY > 1 2370 printf("sr_packet_avail(): wki=%d, wko=%04x, cda=%08x\n", 2371 wki, wko, cda); 2372 #endif 2373 2374 /* 2375 * open the appropriate memory window and set our expectations... 2376 */ 2377 if (hc->mempages) { 2378 SRC_SET_MEM(hc->iobase, sc->rxdesc); 2379 SRC_SET_ON(hc->iobase); 2380 } 2381 rxdesc = (sca_descriptor *) 2382 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 2383 endp = rxdesc; 2384 rxdesc = &rxdesc[sc->rxhind]; 2385 endp = &endp[sc->rxmax]; 2386 2387 *len = 0; /* reset result total length */ 2388 granules = 0; /* reset count of granules */ 2389 2390 /* 2391 * This loop will scan descriptors, but it *will* puke up if we wrap 2392 * around to our starting point... 2393 */ 2394 while (rxdesc != cda) { 2395 *len += rxdesc->len; /* increment result length */ 2396 granules++; 2397 2398 /* 2399 * If we hit a valid packet's completion we'll know we've 2400 * got a live one, and that we can deliver the packet. 2401 * Since we're only allowed to report a packet available, 2402 * somebody else does that... 2403 */ 2404 if (rxdesc->stat & SCA_DESC_EOM) { /* End Of Message */ 2405 *rxstat = rxdesc->stat; /* return closing */ 2406 #if BUGGY > 0 2407 printf("sr%d: PKT AVAIL len %d, %x, bufs %u.\n", 2408 sc->unit, *len, *rxstat, granules); 2409 #endif 2410 return 1; /* indicate success */ 2411 } 2412 /* 2413 * OK, this packet take up multiple granules. Move on to 2414 * the next descriptor so we can consider it... 2415 */ 2416 rxdesc++; 2417 2418 if (rxdesc == endp) /* recognize & act on wrap point */ 2419 rxdesc = (sca_descriptor *) 2420 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 2421 } 2422 2423 /* 2424 * Nothing found in the DPRAM. Let the caller know... 2425 */ 2426 *len = 0; 2427 *rxstat = 0; 2428 2429 return 0; 2430 } 2431 2432 /* 2433 * Copy a packet from the on card memory into a provided mbuf. 2434 * Take into account that buffers wrap and that a packet may 2435 * be larger than a buffer. 2436 */ 2437 static void 2438 sr_copy_rxbuf(struct mbuf *m, struct sr_softc *sc, int len) 2439 { 2440 struct sr_hardc *hc; 2441 sca_descriptor *rxdesc; 2442 u_int rxdata; 2443 u_int rxmax; 2444 u_int off = 0; 2445 u_int tlen; 2446 2447 #if BUGGY > 0 2448 printf("sr_copy_rxbuf(m=%08x,sc=%08x,len=%d)\n", 2449 m, sc, len); 2450 #endif 2451 2452 hc = sc->hc; 2453 2454 rxdata = sc->rxstart + (sc->rxhind * SR_BUF_SIZ); 2455 rxmax = sc->rxstart + (sc->rxmax * SR_BUF_SIZ); 2456 2457 rxdesc = (sca_descriptor *) 2458 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 2459 rxdesc = &rxdesc[sc->rxhind]; 2460 2461 /* 2462 * Using the count of bytes in the received packet, we decrement it 2463 * for each granule (controller by an SCA descriptor) to control the 2464 * looping... 2465 */ 2466 while (len) { 2467 /* 2468 * tlen gets the length of *this* granule... ...which is 2469 * then copied to the target buffer. 2470 */ 2471 tlen = (len < SR_BUF_SIZ) ? len : SR_BUF_SIZ; 2472 2473 if (hc->mempages) 2474 SRC_SET_MEM(hc->iobase, rxdata); 2475 2476 bcopy(hc->mem_start + (rxdata & hc->winmsk), 2477 mtod(m, caddr_t) +off, 2478 tlen); 2479 2480 off += tlen; 2481 len -= tlen; 2482 2483 /* 2484 * now, return to the descriptor's window in DPRAM and reset 2485 * the descriptor we've just suctioned... 2486 */ 2487 if (hc->mempages) 2488 SRC_SET_MEM(hc->iobase, sc->rxdesc); 2489 2490 rxdesc->len = 0; 2491 rxdesc->stat = 0xff; 2492 2493 /* 2494 * Move on to the next granule. If we've any remaining 2495 * bytes to process we'll just continue in our loop... 2496 */ 2497 rxdata += SR_BUF_SIZ; 2498 rxdesc++; 2499 2500 if (rxdata == rxmax) { /* handle the wrap point */ 2501 rxdata = sc->rxstart; 2502 rxdesc = (sca_descriptor *) 2503 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 2504 } 2505 } 2506 } 2507 2508 /* 2509 * If single is set, just eat a packet. Otherwise eat everything up to 2510 * where cda points. Update pointers to point to the next packet. 2511 * 2512 * This handles "flushing" of a packet as received... 2513 * 2514 * If the "single" parameter is zero, all pending reeceive traffic will 2515 * be flushed out of existence. A non-zero value will only drop the 2516 * *next* (currently) pending packet... 2517 */ 2518 static void 2519 sr_eat_packet(struct sr_softc *sc, int single) 2520 { 2521 struct sr_hardc *hc; 2522 sca_descriptor *rxdesc; /* current descriptor being eval'd */ 2523 sca_descriptor *endp; /* last descriptor in chain */ 2524 sca_descriptor *cda; /* current start point */ 2525 u_int loopcnt = 0; /* count of packets flushed ??? */ 2526 u_char stat; /* captured status byte from descr */ 2527 2528 hc = sc->hc; 2529 cda = (sca_descriptor *)(hc->mem_start + 2530 (SRC_GET16(hc->sca_base, 2531 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda) & 2532 hc->winmsk)); 2533 2534 /* 2535 * loop until desc->stat == (0xff || EOM) Clear the status and 2536 * length in the descriptor. Increment the descriptor. 2537 */ 2538 if (hc->mempages) 2539 SRC_SET_MEM(hc->iobase, sc->rxdesc); 2540 2541 rxdesc = (sca_descriptor *) 2542 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 2543 endp = rxdesc; 2544 rxdesc = &rxdesc[sc->rxhind]; 2545 endp = &endp[sc->rxmax]; 2546 2547 /* 2548 * allow loop, but abort it if we wrap completely... 2549 */ 2550 while (rxdesc != cda) { 2551 loopcnt++; 2552 2553 if (loopcnt > sc->rxmax) { 2554 printf("sr%d: eat pkt %d loop, cda %x, " 2555 "rxdesc %x, stat %x.\n", 2556 sc->unit, loopcnt, (u_int) cda, (u_int) rxdesc, 2557 rxdesc->stat); 2558 break; 2559 } 2560 stat = rxdesc->stat; 2561 2562 rxdesc->len = 0; 2563 rxdesc->stat = 0xff; 2564 2565 rxdesc++; 2566 sc->rxhind++; 2567 2568 if (rxdesc == endp) { 2569 rxdesc = (sca_descriptor *) 2570 (hc->mem_start + (sc->rxdesc & hc->winmsk)); 2571 sc->rxhind = 0; 2572 } 2573 if (single && (stat == SCA_DESC_EOM)) 2574 break; 2575 } 2576 2577 /* 2578 * Update the eda to the previous descriptor. 2579 */ 2580 rxdesc = (sca_descriptor *)sc->rxdesc; 2581 rxdesc = &rxdesc[(sc->rxhind + sc->rxmax - 2) % sc->rxmax]; 2582 2583 SRC_PUT16(hc->sca_base, 2584 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda, 2585 (u_short)((u_int)(rxdesc + hc->mem_pstart) & 0xffff)); 2586 } 2587 2588 /* 2589 * While there is packets available in the rx buffer, read them out 2590 * into mbufs and ship them off. 2591 */ 2592 static void 2593 sr_get_packets(struct sr_softc *sc) 2594 { 2595 u_char rxstat; /* acquired status byte */ 2596 int i; 2597 int pkts; /* count of packets found */ 2598 int rxndx; /* rcv buffer index */ 2599 int tries; /* settling time counter */ 2600 u_int len; /* length of pending packet */ 2601 struct sr_hardc *hc; /* card-level information */ 2602 sca_descriptor *rxdesc; /* descriptor in memory */ 2603 #ifndef NETGRAPH 2604 struct ifnet *ifp; /* network intf ctl table */ 2605 #endif /* NETGRAPH */ 2606 struct mbuf *m = NULL; /* message buffer */ 2607 2608 #if BUGGY > 0 2609 printf("sr_get_packets(sc=%08x)\n", sc); 2610 #endif 2611 2612 hc = sc->hc; 2613 #ifndef NETGRAPH 2614 ifp = &sc->ifsppp.pp_if; 2615 #endif /* NETGRAPH */ 2616 2617 if (hc->mempages) { 2618 SRC_SET_MEM(hc->iobase, sc->rxdesc); 2619 SRC_SET_ON(hc->iobase); /* enable shared memory */ 2620 } 2621 pkts = 0; /* reset count of found packets */ 2622 2623 /* 2624 * for each complete packet in the receiving pool, process each 2625 * packet... 2626 */ 2627 while (sr_packet_avail(sc, &len, &rxstat)) { /* packet pending? */ 2628 /* 2629 * I have seen situations where we got the interrupt but the 2630 * status value wasn't deposited. This code should allow 2631 * the status byte's value to settle... 2632 */ 2633 2634 tries = 5; 2635 2636 while ((rxstat == 0x00ff) 2637 && --tries) 2638 sr_packet_avail(sc, &len, &rxstat); 2639 2640 #if BUGGY > 1 2641 printf("sr_packet_avail() returned len=%d, rxstat=%02ux\n", 2642 len, rxstat); 2643 #endif 2644 2645 pkts++; 2646 #ifdef NETGRAPH 2647 sc->inbytes += len; 2648 sc->inlast = 0; 2649 #endif /* NETGRAPH */ 2650 2651 /* 2652 * OK, we've settled the incoming message status. We can now 2653 * process it... 2654 */ 2655 if (((rxstat & SCA_DESC_ERRORS) == 0) && (len < MCLBYTES)) { 2656 #if BUGGY > 1 2657 printf("sr%d: sr_get_packet() rxstat=%02x, len=%d\n", 2658 sc->unit, rxstat, len); 2659 #endif 2660 2661 MGETHDR(m, M_DONTWAIT, MT_DATA); 2662 if (m == NULL) { 2663 /* 2664 * eat (flush) packet if get mbuf fail!! 2665 */ 2666 sr_eat_packet(sc, 1); 2667 continue; 2668 } 2669 /* 2670 * construct control information for pass-off 2671 */ 2672 #ifndef NETGRAPH 2673 m->m_pkthdr.rcvif = ifp; 2674 #else 2675 m->m_pkthdr.rcvif = NULL; 2676 #endif /* NETGRAPH */ 2677 m->m_pkthdr.len = m->m_len = len; 2678 if (len > MHLEN) { 2679 MCLGET(m, M_DONTWAIT); 2680 if ((m->m_flags & M_EXT) == 0) { 2681 /* 2682 * We couldn't get a big enough 2683 * message packet, so we'll send the 2684 * packet to /dev/null... 2685 */ 2686 m_freem(m); 2687 sr_eat_packet(sc, 1); 2688 continue; 2689 } 2690 } 2691 /* 2692 * OK, we've got a good message buffer. Now we can 2693 * copy the received message into it 2694 */ 2695 sr_copy_rxbuf(m, sc, len); /* copy from DPRAM */ 2696 2697 #ifndef NETGRAPH 2698 #if NBPFILTER > 0 2699 if (ifp->if_bpf) 2700 bpf_mtap(ifp, m); 2701 #endif 2702 2703 #if BUGGY > 3 2704 { 2705 u_char *bp; 2706 2707 bp = (u_char *)m; 2708 printf("sr%d: rcvd=%02x%02x%02x%02x%02x%02x\n", 2709 sc->unit, 2710 bp[0], bp[1], bp[2], 2711 bp[4], bp[5], bp[6]); 2712 } 2713 #endif 2714 /* 2715 * Pass off the message to PPP, connecting it it to 2716 * the system... 2717 */ 2718 switch (sc->protocol) { 2719 #if NFR > 0 2720 case N2_USE_FRP: 2721 fr_input(ifp, m); 2722 break; 2723 #endif 2724 case N2_USE_PPP: 2725 default: 2726 sppp_input(ifp, m); 2727 } 2728 2729 ifp->if_ipackets++; 2730 2731 #else /* NETGRAPH */ 2732 #if BUGGY > 3 2733 { 2734 u_char *bp; 2735 2736 bp = mtod(m,u_char *); 2737 printf("sr%d: rd=%02x:%02x:%02x:%02x:%02x:%02x", 2738 sc->unit, 2739 bp[0], bp[1], bp[2], 2740 bp[4], bp[5], bp[6]); 2741 printf(":%02x:%02x:%02x:%02x:%02x:%02x\n", 2742 bp[6], bp[7], bp[8], 2743 bp[9], bp[10], bp[11]); 2744 } 2745 #endif 2746 ng_queue_data(sc->hook, m, NULL); 2747 sc->ipackets++; 2748 #endif /* NETGRAPH */ 2749 /* 2750 * Update the eda to the previous descriptor. 2751 */ 2752 i = (len + SR_BUF_SIZ - 1) / SR_BUF_SIZ; 2753 sc->rxhind = (sc->rxhind + i) % sc->rxmax; 2754 2755 rxdesc = (sca_descriptor *)sc->rxdesc; 2756 rxndx = (sc->rxhind + sc->rxmax - 2) % sc->rxmax; 2757 rxdesc = &rxdesc[rxndx]; 2758 2759 SRC_PUT16(hc->sca_base, 2760 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda, 2761 (u_short)((u_int)(rxdesc + hc->mem_pstart) 2762 & 0xffff)); 2763 2764 } else { 2765 int got_st3, got_cda, got_eda; 2766 int tries = 5; 2767 2768 while((rxstat == 0xff) && --tries) 2769 sr_packet_avail(sc, &len, &rxstat); 2770 2771 /* 2772 * It look like we get an interrupt early 2773 * sometimes and then the status is not 2774 * filled in yet. 2775 */ 2776 if(tries && (tries != 5)) 2777 continue; 2778 2779 /* 2780 * This chunk of code handles the error packets. 2781 * We'll log them for posterity... 2782 */ 2783 sr_eat_packet(sc, 1); 2784 2785 #ifndef NETGRAPH 2786 ifp->if_ierrors++; 2787 #else 2788 sc->ierrors[0]++; 2789 #endif /* NETGRAPH */ 2790 2791 got_st3 = SRC_GET8(hc->sca_base, 2792 hc->sca->msci[sc->scachan].st3); 2793 got_cda = SRC_GET16(hc->sca_base, 2794 hc->sca->dmac[DMAC_RXCH(sc->scachan)].cda); 2795 got_eda = SRC_GET16(hc->sca_base, 2796 hc->sca->dmac[DMAC_RXCH(sc->scachan)].eda); 2797 2798 #if BUGGY > 0 2799 printf("sr%d: Receive error chan %d, " 2800 "stat %02x, msci st3 %02x," 2801 "rxhind %d, cda %04x, eda %04x.\n", 2802 sc->unit, sc->scachan, rxstat, 2803 got_st3, sc->rxhind, got_cda, got_eda); 2804 #endif 2805 } 2806 } 2807 2808 #if BUGGY > 0 2809 printf("sr%d: sr_get_packets() found %d packet(s)\n", 2810 sc->unit, pkts); 2811 #endif 2812 2813 if (hc->mempages) 2814 SRC_SET_OFF(hc->iobase); 2815 } 2816 2817 /* 2818 * All DMA interrupts come here. 2819 * 2820 * Each channel has two interrupts. 2821 * Interrupt A for errors and Interrupt B for normal stuff like end 2822 * of transmit or receive dmas. 2823 */ 2824 static void 2825 sr_dmac_intr(struct sr_hardc *hc, u_char isr1) 2826 { 2827 u_char dsr; /* contents of DMA Stat Reg */ 2828 u_char dotxstart; /* enables for tranmit part */ 2829 int mch; /* channel being processed */ 2830 struct sr_softc *sc; /* channel's softc structure */ 2831 sca_regs *sca = hc->sca; 2832 dmac_channel *dmac; /* dma structure of chip */ 2833 2834 #if BUGGY > 0 2835 printf("sr_dmac_intr(hc=%08x,isr1=%04x)\n", hc, isr1); 2836 #endif 2837 2838 mch = 0; /* assume chan0 on card */ 2839 dotxstart = isr1; /* copy for xmitter starts */ 2840 2841 /* 2842 * Shortcut if there is no interrupts for dma channel 0 or 1. 2843 * Skip processing for channel 0 if no incoming hit 2844 */ 2845 if ((isr1 & 0x0F) == 0) { 2846 mch = 1; 2847 isr1 >>= 4; 2848 } 2849 do { 2850 sc = &hc->sc[mch]; 2851 2852 /* 2853 * Transmit channel - DMA Status Register Evaluation 2854 */ 2855 if (isr1 & 0x0C) { 2856 dmac = &sca->dmac[DMAC_TXCH(mch)]; 2857 2858 /* 2859 * get the DMA Status Register contents and write 2860 * back to reset interrupt... 2861 */ 2862 dsr = SRC_GET8(hc->sca_base, dmac->dsr); 2863 SRC_PUT8(hc->sca_base, dmac->dsr, dsr); 2864 2865 /* 2866 * Check for (& process) a Counter overflow 2867 */ 2868 if (dsr & SCA_DSR_COF) { 2869 printf("sr%d: TX DMA Counter overflow, " 2870 "txpacket no %lu.\n", 2871 #ifndef NETGRAPH 2872 sc->unit, sc->ifsppp.pp_if.if_opackets); 2873 sc->ifsppp.pp_if.if_oerrors++; 2874 #else 2875 sc->unit, sc->opackets); 2876 sc->oerrors++; 2877 #endif /* NETGRAPH */ 2878 } 2879 /* 2880 * Check for (& process) a Buffer overflow 2881 */ 2882 if (dsr & SCA_DSR_BOF) { 2883 printf("sr%d: TX DMA Buffer overflow, " 2884 "txpacket no %lu, dsr %02x, " 2885 "cda %04x, eda %04x.\n", 2886 #ifndef NETGRAPH 2887 sc->unit, sc->ifsppp.pp_if.if_opackets, 2888 #else 2889 sc->unit, sc->opackets, 2890 #endif /* NETGRAPH */ 2891 dsr, 2892 SRC_GET16(hc->sca_base, dmac->cda), 2893 SRC_GET16(hc->sca_base, dmac->eda)); 2894 #ifndef NETGRAPH 2895 sc->ifsppp.pp_if.if_oerrors++; 2896 #else 2897 sc->oerrors++; 2898 #endif /* NETGRAPH */ 2899 } 2900 /* 2901 * Check for (& process) an End of Transfer (OK) 2902 */ 2903 if (dsr & SCA_DSR_EOT) { 2904 /* 2905 * This should be the most common case. 2906 * 2907 * Clear the IFF_OACTIVE flag. 2908 * 2909 * Call srstart to start a new transmit if 2910 * there is data to transmit. 2911 */ 2912 #if BUGGY > 0 2913 printf("sr%d: TX Completed OK\n", sc->unit); 2914 #endif 2915 sc->xmit_busy = 0; 2916 #ifndef NETGRAPH 2917 sc->ifsppp.pp_if.if_flags &= ~IFF_OACTIVE; 2918 sc->ifsppp.pp_if.if_timer = 0; 2919 #else 2920 /* XXX may need to mark tx inactive? */ 2921 sc->out_deficit++; 2922 sc->out_dog = DOG_HOLDOFF; 2923 #endif /* NETGRAPH */ 2924 2925 if (sc->txb_inuse && --sc->txb_inuse) 2926 sr_xmit(sc); 2927 } 2928 } 2929 /* 2930 * Receive channel processing of DMA Status Register 2931 */ 2932 if (isr1 & 0x03) { 2933 dmac = &sca->dmac[DMAC_RXCH(mch)]; 2934 2935 dsr = SRC_GET8(hc->sca_base, dmac->dsr); 2936 SRC_PUT8(hc->sca_base, dmac->dsr, dsr); 2937 2938 /* 2939 * End of frame processing (MSG OK?) 2940 */ 2941 if (dsr & SCA_DSR_EOM) { 2942 #if BUGGY > 0 2943 int tt, ind; 2944 2945 #ifndef NETGRAPH 2946 tt = sc->ifsppp.pp_if.if_ipackets; 2947 #else /* NETGRAPH */ 2948 tt = sc->ipackets; 2949 #endif /* NETGRAPH */ 2950 ind = sc->rxhind; 2951 #endif 2952 2953 sr_get_packets(sc); 2954 #if BUGGY > 0 2955 #ifndef NETGRAPH 2956 if (tt == sc->ifsppp.pp_if.if_ipackets) 2957 #else /* NETGRAPH */ 2958 if (tt == sc->ipackets) 2959 #endif /* NETGRAPH */ 2960 { 2961 sca_descriptor *rxdesc; 2962 int i; 2963 2964 printf("SR: RXINTR isr1 %x, dsr %x, " 2965 "no data %d pkts, orxind %d.\n", 2966 dotxstart, dsr, tt, ind); 2967 printf("SR: rxdesc %x, rxstart %x, " 2968 "rxend %x, rxhind %d, " 2969 "rxmax %d.\n", 2970 sc->rxdesc, sc->rxstart, 2971 sc->rxend, sc->rxhind, 2972 sc->rxmax); 2973 printf("SR: cda %x, eda %x.\n", 2974 SRC_GET16(hc->sca_base, dmac->cda), 2975 SRC_GET16(hc->sca_base, dmac->eda)); 2976 2977 if (hc->mempages) { 2978 SRC_SET_ON(hc->iobase); 2979 SRC_SET_MEM(hc->iobase, sc->rxdesc); 2980 } 2981 rxdesc = (sca_descriptor *) 2982 (hc->mem_start + 2983 (sc->rxdesc & hc->winmsk)); 2984 rxdesc = &rxdesc[sc->rxhind]; 2985 2986 for (i = 0; i < 3; i++, rxdesc++) 2987 printf("SR: rxdesc->stat %x, " 2988 "len %d.\n", 2989 rxdesc->stat, 2990 rxdesc->len); 2991 2992 if (hc->mempages) 2993 SRC_SET_OFF(hc->iobase); 2994 } 2995 #endif /* BUGGY */ 2996 } 2997 /* 2998 * Check for Counter overflow 2999 */ 3000 if (dsr & SCA_DSR_COF) { 3001 printf("sr%d: RX DMA Counter overflow, " 3002 "rxpkts %lu.\n", 3003 #ifndef NETGRAPH 3004 sc->unit, sc->ifsppp.pp_if.if_ipackets); 3005 sc->ifsppp.pp_if.if_ierrors++; 3006 #else /* NETGRAPH */ 3007 sc->unit, sc->ipackets); 3008 sc->ierrors[1]++; 3009 #endif /* NETGRAPH */ 3010 } 3011 /* 3012 * Check for Buffer overflow 3013 */ 3014 if (dsr & SCA_DSR_BOF) { 3015 printf("sr%d: RX DMA Buffer overflow, " 3016 "rxpkts %lu, rxind %d, " 3017 "cda %x, eda %x, dsr %x.\n", 3018 #ifndef NETGRAPH 3019 sc->unit, sc->ifsppp.pp_if.if_ipackets, 3020 #else /* NETGRAPH */ 3021 sc->unit, sc->ipackets, 3022 #endif /* NETGRAPH */ 3023 sc->rxhind, 3024 SRC_GET16(hc->sca_base, dmac->cda), 3025 SRC_GET16(hc->sca_base, dmac->eda), 3026 dsr); 3027 3028 /* 3029 * Make sure we eat as many as possible. 3030 * Then get the system running again. 3031 */ 3032 if (hc->mempages) 3033 SRC_SET_ON(hc->iobase); 3034 3035 sr_eat_packet(sc, 0); 3036 #ifndef NETGRAPH 3037 sc->ifsppp.pp_if.if_ierrors++; 3038 #else /* NETGRAPH */ 3039 sc->ierrors[2]++; 3040 #endif /* NETGRAPH */ 3041 3042 SRC_PUT8(hc->sca_base, 3043 sca->msci[mch].cmd, 3044 SCA_CMD_RXMSGREJ); 3045 3046 SRC_PUT8(hc->sca_base, dmac->dsr, SCA_DSR_DE); 3047 3048 #if BUGGY > 0 3049 printf("sr%d: RX DMA Buffer overflow, " 3050 "rxpkts %lu, rxind %d, " 3051 "cda %x, eda %x, dsr %x. After\n", 3052 sc->unit, 3053 #ifndef NETGRAPH 3054 sc->ipackets, 3055 #else /* NETGRAPH */ 3056 sc->ifsppp.pp_if.if_ipackets, 3057 #endif /* NETGRAPH */ 3058 sc->rxhind, 3059 SRC_GET16(hc->sca_base, dmac->cda), 3060 SRC_GET16(hc->sca_base, dmac->eda), 3061 SRC_GET8(hc->sca_base, dmac->dsr)); 3062 #endif 3063 3064 if (hc->mempages) 3065 SRC_SET_OFF(hc->iobase); 3066 } 3067 /* 3068 * End of Transfer 3069 */ 3070 if (dsr & SCA_DSR_EOT) { 3071 /* 3072 * If this happen, it means that we are 3073 * receiving faster than what the processor 3074 * can handle. 3075 * 3076 * XXX We should enable the dma again. 3077 */ 3078 printf("sr%d: RX End of xfer, rxpkts %lu.\n", 3079 sc->unit, 3080 #ifndef NETGRAPH 3081 sc->ifsppp.pp_if.if_ipackets); 3082 sc->ifsppp.pp_if.if_ierrors++; 3083 #else 3084 sc->ipackets); 3085 sc->ierrors[3]++; 3086 #endif /* NETGRAPH */ 3087 } 3088 } 3089 isr1 >>= 4; /* process next half of ISR */ 3090 mch++; /* and move to next channel */ 3091 } while ((mch < NCHAN) && isr1); /* loop for each chn */ 3092 3093 /* 3094 * Now that we have done all the urgent things, see if we can fill 3095 * the transmit buffers. 3096 */ 3097 for (mch = 0; mch < NCHAN; mch++) { 3098 if (dotxstart & 0x0C) { /* TX initiation enabled? */ 3099 sc = &hc->sc[mch]; 3100 #ifndef NETGRAPH 3101 srstart(&sc->ifsppp.pp_if); 3102 #else 3103 srstart(sc); 3104 #endif /* NETGRAPH */ 3105 } 3106 dotxstart >>= 4;/* shift for next channel */ 3107 } 3108 } 3109 #ifndef NETGRAPH 3110 /* 3111 * Perform timeout on an FR channel 3112 * 3113 * Establish a periodic check of open N2 ports; If 3114 * a port is open/active, its DCD state is checked 3115 * and a loss of DCD is recognized (and eventually 3116 * processed). 3117 */ 3118 static void 3119 sr_modemck(void *arg) 3120 { 3121 u_int s; 3122 int card; /* card index in table */ 3123 int cards; /* card list index */ 3124 int mch; /* channel on card */ 3125 u_char dcd_v; /* Data Carrier Detect */ 3126 u_char got_st0; /* contents of ST0 */ 3127 u_char got_st1; /* contents of ST1 */ 3128 u_char got_st2; /* contents of ST2 */ 3129 u_char got_st3; /* contents of ST3 */ 3130 struct sr_hardc *hc; /* card's configuration */ 3131 struct sr_hardc *Card[16];/* up to 16 cards in system */ 3132 struct sr_softc *sc; /* channel's softc structure */ 3133 struct ifnet *ifp; /* interface control table */ 3134 msci_channel *msci; /* regs specific to channel */ 3135 3136 s = splimp(); 3137 3138 #if 0 3139 if (sr_opens == 0) { /* count of "up" channels */ 3140 sr_watcher = 0; /* indicate no watcher */ 3141 splx(s); 3142 return; 3143 } 3144 #endif 3145 3146 sr_watcher = 1; /* mark that we're online */ 3147 3148 /* 3149 * Now we'll need a list of cards to process. Since we can handle 3150 * both ISA and PCI cards (and I didn't think of making this logic 3151 * global YET) we'll generate a single table of card table 3152 * addresses. 3153 */ 3154 cards = 0; 3155 3156 for (card = 0; card < NSR; card++) { 3157 hc = &sr_hardc[card]; 3158 3159 if (hc->sc == (void *)0) 3160 continue; 3161 3162 Card[cards++] = hc; 3163 } 3164 3165 hc = sr_hardc_pci; 3166 3167 while (hc) { 3168 Card[cards++] = hc; 3169 hc = hc->next; 3170 } 3171 3172 /* 3173 * OK, we've got work we can do. Let's do it... (Please note that 3174 * this code _only_ deals w/ ISA cards) 3175 */ 3176 for (card = 0; card < cards; card++) { 3177 hc = Card[card];/* get card table */ 3178 3179 for (mch = 0; mch < hc->numports; mch++) { 3180 sc = &hc->sc[mch]; 3181 3182 if (sc->attached == 0) 3183 continue; 3184 3185 ifp = &sc->ifsppp.pp_if; 3186 3187 /* 3188 * if this channel isn't "up", skip it 3189 */ 3190 if ((ifp->if_flags & IFF_UP) == 0) 3191 continue; 3192 3193 /* 3194 * OK, now we can go looking at this channel's 3195 * actual register contents... 3196 */ 3197 msci = &hc->sca->msci[sc->scachan]; 3198 3199 /* 3200 * OK, now we'll look into the actual status of this 3201 * channel... 3202 * 3203 * I suck in more registers than strictly needed 3204 */ 3205 got_st0 = SRC_GET8(hc->sca_base, msci->st0); 3206 got_st1 = SRC_GET8(hc->sca_base, msci->st1); 3207 got_st2 = SRC_GET8(hc->sca_base, msci->st2); 3208 got_st3 = SRC_GET8(hc->sca_base, msci->st3); 3209 3210 /* 3211 * We want to see if the DCD signal is up (DCD is 3212 * true if zero) 3213 */ 3214 dcd_v = (got_st3 & SCA_ST3_DCD) == 0; 3215 3216 if (dcd_v == 0) 3217 printf("sr%d: DCD lost\n", sc->unit); 3218 } 3219 } 3220 3221 /* 3222 * OK, now set up for the next modem signal checking pass... 3223 */ 3224 timeout(sr_modemck, NULL, hz); 3225 3226 splx(s); 3227 } 3228 3229 #else /* NETGRAPH */ 3230 /* 3231 * If a port is open/active, it's DCD state is checked 3232 * and a loss of DCD is recognized (and eventually processed?). 3233 */ 3234 static void 3235 sr_modemck(struct sr_softc *sc ) 3236 { 3237 u_int s; 3238 u_char got_st3; /* contents of ST3 */ 3239 struct sr_hardc *hc = sc->hc; /* card's configuration */ 3240 msci_channel *msci; /* regs specific to channel */ 3241 3242 s = splimp(); 3243 3244 3245 if (sc->running == 0) 3246 return; 3247 /* 3248 * OK, now we can go looking at this channel's register contents... 3249 */ 3250 msci = &hc->sca->msci[sc->scachan]; 3251 got_st3 = SRC_GET8(hc->sca_base, msci->st3); 3252 3253 /* 3254 * We want to see if the DCD signal is up (DCD is true if zero) 3255 */ 3256 sc->dcd = (got_st3 & SCA_ST3_DCD) == 0; 3257 splx(s); 3258 } 3259 3260 #endif /* NETGRAPH */ 3261 static void 3262 sr_msci_intr(struct sr_hardc *hc, u_char isr0) 3263 { 3264 printf("src%d: SRINTR: MSCI\n", hc->cunit); 3265 } 3266 3267 static void 3268 sr_timer_intr(struct sr_hardc *hc, u_char isr2) 3269 { 3270 printf("src%d: SRINTR: TIMER\n", hc->cunit); 3271 } 3272 3273 #ifdef NETGRAPH 3274 /***************************************** 3275 * Device timeout/watchdog routine. 3276 * called once per second. 3277 * checks to see that if activity was expected, that it hapenned. 3278 * At present we only look to see if expected output was completed. 3279 */ 3280 static void 3281 ngsr_watchdog_frame(void * arg) 3282 { 3283 struct sr_softc * sc = arg; 3284 int s; 3285 int speed; 3286 3287 if(sc->running == 0) 3288 return; /* if we are not running let timeouts die */ 3289 /* 3290 * calculate the apparent throughputs 3291 * XXX a real hack 3292 */ 3293 s = splimp(); 3294 speed = sc->inbytes - sc->lastinbytes; 3295 sc->lastinbytes = sc->inbytes; 3296 if ( sc->inrate < speed ) 3297 sc->inrate = speed; 3298 speed = sc->outbytes - sc->lastoutbytes; 3299 sc->lastoutbytes = sc->outbytes; 3300 if ( sc->outrate < speed ) 3301 sc->outrate = speed; 3302 sc->inlast++; 3303 splx(s); 3304 3305 if ((sc->inlast > QUITE_A_WHILE) 3306 && (sc->out_deficit > LOTS_OF_PACKETS)) { 3307 log(LOG_ERR, "sr%d: No response from remote end\n", sc->unit); 3308 s = splimp(); 3309 sr_down(sc); 3310 sr_up(sc); 3311 sc->inlast = sc->out_deficit = 0; 3312 splx(s); 3313 } else if ( sc->xmit_busy ) { /* no TX -> no TX timeouts */ 3314 if (sc->out_dog == 0) { 3315 log(LOG_ERR, "sr%d: Transmit failure.. no clock?\n", 3316 sc->unit); 3317 s = splimp(); 3318 srwatchdog(sc); 3319 #if 0 3320 sr_down(sc); 3321 sr_up(sc); 3322 #endif 3323 splx(s); 3324 sc->inlast = sc->out_deficit = 0; 3325 } else { 3326 sc->out_dog--; 3327 } 3328 } 3329 sr_modemck(sc); /* update the DCD status */ 3330 sc->handle = timeout(ngsr_watchdog_frame, sc, hz); 3331 } 3332 3333 /*********************************************************************** 3334 * This section contains the methods for the Netgraph interface 3335 ***********************************************************************/ 3336 /* 3337 * It is not possible or allowable to create a node of this type. 3338 * If the hardware exists, it will already have created it. 3339 */ 3340 static int 3341 ngsr_constructor(node_p *nodep) 3342 { 3343 return (EINVAL); 3344 } 3345 3346 /* 3347 * give our ok for a hook to be added... 3348 * If we are not running this should kick the device into life. 3349 * The hook's private info points to our stash of info about that 3350 * channel. 3351 */ 3352 static int 3353 ngsr_newhook(node_p node, hook_p hook, const char *name) 3354 { 3355 struct sr_softc * sc = node->private; 3356 3357 /* 3358 * check if it's our friend the debug hook 3359 */ 3360 if (strcmp(name, NG_SR_HOOK_DEBUG) == 0) { 3361 hook->private = NULL; /* paranoid */ 3362 sc->debug_hook = hook; 3363 return (0); 3364 } 3365 3366 /* 3367 * Check for raw mode hook. 3368 */ 3369 if (strcmp(name, NG_SR_HOOK_RAW) != 0) { 3370 return (EINVAL); 3371 } 3372 hook->private = sc; 3373 sc->hook = hook; 3374 sc->datahooks++; 3375 sr_up(sc); 3376 return (0); 3377 } 3378 3379 /* 3380 * incoming messages. 3381 * Just respond to the generic TEXT_STATUS message 3382 */ 3383 static int 3384 ngsr_rcvmsg(node_p node, 3385 struct ng_mesg *msg, const char *retaddr, struct ng_mesg **resp) 3386 { 3387 struct sr_softc * sc; 3388 int error = 0; 3389 3390 sc = node->private; 3391 switch (msg->header.typecookie) { 3392 case NG_SR_COOKIE: 3393 error = EINVAL; 3394 break; 3395 case NGM_GENERIC_COOKIE: 3396 switch(msg->header.cmd) { 3397 case NGM_TEXT_STATUS: { 3398 char *arg; 3399 int pos = 0; 3400 int resplen = sizeof(struct ng_mesg) + 512; 3401 MALLOC(*resp, struct ng_mesg *, resplen, 3402 M_NETGRAPH, M_NOWAIT); 3403 if (*resp == NULL) { 3404 error = ENOMEM; 3405 break; 3406 } 3407 bzero(*resp, resplen); 3408 arg = (*resp)->data; 3409 3410 /* 3411 * Put in the throughput information. 3412 */ 3413 pos = sprintf(arg, "%ld bytes in, %ld bytes out\n" 3414 "highest rate seen: %ld B/S in, %ld B/S out\n", 3415 sc->inbytes, sc->outbytes, 3416 sc->inrate, sc->outrate); 3417 pos += sprintf(arg + pos, 3418 "%ld output errors\n", 3419 sc->oerrors); 3420 pos += sprintf(arg + pos, 3421 "ierrors = %ld, %ld, %ld, %ld, %ld, %ld\n", 3422 sc->ierrors[0], 3423 sc->ierrors[1], 3424 sc->ierrors[2], 3425 sc->ierrors[3], 3426 sc->ierrors[4], 3427 sc->ierrors[5]); 3428 3429 (*resp)->header.version = NG_VERSION; 3430 (*resp)->header.arglen = strlen(arg) + 1; 3431 (*resp)->header.token = msg->header.token; 3432 (*resp)->header.typecookie = NG_SR_COOKIE; 3433 (*resp)->header.cmd = msg->header.cmd; 3434 strncpy((*resp)->header.cmdstr, "status", 3435 NG_CMDSTRLEN); 3436 } 3437 break; 3438 default: 3439 error = EINVAL; 3440 break; 3441 } 3442 break; 3443 default: 3444 error = EINVAL; 3445 break; 3446 } 3447 free(msg, M_NETGRAPH); 3448 return (error); 3449 } 3450 3451 /* 3452 * get data from another node and transmit it to the correct channel 3453 */ 3454 static int 3455 ngsr_rcvdata(hook_p hook, struct mbuf *m, meta_p meta) 3456 { 3457 int s; 3458 int error = 0; 3459 struct sr_softc * sc = hook->node->private; 3460 struct ifqueue *xmitq_p; 3461 3462 /* 3463 * data doesn't come in from just anywhere (e.g control hook) 3464 */ 3465 if ( hook->private == NULL) { 3466 error = ENETDOWN; 3467 goto bad; 3468 } 3469 3470 /* 3471 * Now queue the data for when it can be sent 3472 */ 3473 if (meta && meta->priority > 0) { 3474 xmitq_p = (&sc->xmitq_hipri); 3475 } else { 3476 xmitq_p = (&sc->xmitq); 3477 } 3478 s = splimp(); 3479 if (IF_QFULL(xmitq_p)) { 3480 IF_DROP(xmitq_p); 3481 splx(s); 3482 error = ENOBUFS; 3483 goto bad; 3484 } 3485 IF_ENQUEUE(xmitq_p, m); 3486 srstart(sc); 3487 splx(s); 3488 return (0); 3489 3490 bad: 3491 /* 3492 * It was an error case. 3493 * check if we need to free the mbuf, and then return the error 3494 */ 3495 NG_FREE_DATA(m, meta); 3496 return (error); 3497 } 3498 3499 /* 3500 * do local shutdown processing.. 3501 * this node will refuse to go away, unless the hardware says to.. 3502 * don't unref the node, or remove our name. just clear our links up. 3503 */ 3504 static int 3505 ngsr_rmnode(node_p node) 3506 { 3507 struct sr_softc * sc = node->private; 3508 3509 sr_down(sc); 3510 ng_cutlinks(node); 3511 node->flags &= ~NG_INVALID; /* bounce back to life */ 3512 return (0); 3513 } 3514 3515 /* already linked */ 3516 static int 3517 ngsr_connect(hook_p hook) 3518 { 3519 /* be really amiable and just say "YUP that's OK by me! " */ 3520 return (0); 3521 } 3522 3523 /* 3524 * notify on hook disconnection (destruction) 3525 * 3526 * Invalidate the private data associated with this dlci. 3527 * For this type, removal of the last link resets tries to destroy the node. 3528 * As the device still exists, the shutdown method will not actually 3529 * destroy the node, but reset the device and leave it 'fresh' :) 3530 * 3531 * The node removal code will remove all references except that owned by the 3532 * driver. 3533 */ 3534 static int 3535 ngsr_disconnect(hook_p hook) 3536 { 3537 struct sr_softc * sc = hook->node->private; 3538 int s; 3539 /* 3540 * If it's the data hook, then free resources etc. 3541 */ 3542 if (hook->private) { 3543 s = splimp(); 3544 sc->datahooks--; 3545 if (sc->datahooks == 0) 3546 sr_down(sc); 3547 splx(s); 3548 } else { 3549 sc->debug_hook = NULL; 3550 } 3551 return (0); 3552 } 3553 3554 /* 3555 * called during bootup 3556 * or LKM loading to put this type into the list of known modules 3557 */ 3558 static void 3559 ngsr_init(void *ignored) 3560 { 3561 if (ng_newtype(&typestruct)) 3562 printf("ngsr install failed\n"); 3563 ngsr_done_init = 1; 3564 } 3565 #endif /* NETGRAPH */ 3566 3567 /* 3568 ********************************* END ************************************ 3569 */
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